Sony CXD3500R Datasheet

Timing Generator for LCD Panels

Description

The CXD3500R is a timing signal generator for driving the LCD panels of Sony data projectors. This chip has a built-in serial interface circuit which supports various SXGA (skip scan display), XGA, SVGA and VGA signals, and (double speed) NTSC and PAL signals through external control from a microcomputer, etc.

Direct drive of LCD panels is possible using 5V drive.

Features

• Generates the drive pulses for the LCD panels of

Sony high-temperature polycrystalline silicon TFT

data projectors.

•

Supports various SXGA, XGA, SVGA and VGA signals.

• Programmable output signals allow the optimal

pulse output settings for each panel.

• Programmable skip scan display allows skip scan

display of various signals (SXGA → XGA, XGA →

SVGA, Macintosh16 → SVGA, etc.)

• Supports NTSC and PAL signals with line double-

speed display using a built-in double-speed

controller. (clock frequency: 36MHz or less)

(Line memory: µPD485505: NEC)

• Allows control of sample-and-hold position of

CXA2112R sample-and-hold driver.

• Supports up/down inversion and/or right/left

inversion.

• Supports line inversion and field inversion.

• AC drive of LCD panels during no signal

Applications

LCD projectors, etc.

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25°C, Vss = 0V)

• Supply voltage VDD Vss – 0.5 to +7.0 V

• Input voltage VI Vss – 0.5 to VDD + 0.5 V

• Output voltage VO Vss – 0.5 to VDD + 0.5 V

• Operating temperature

Topr –20 to +75 °C

• Storage temperature Tstg –55 to +150 °C

Recommended Operating Conditions

• Supply voltage VDD 4.5 to 5.5 V

• Operating temperature

Topr –20 to +75 °C

– 1 –

E99112-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXD3500R

64 pin LQFP (Plastic)

Note) "Macintosh" is a registered trademark of Apple Computer Inc.

"PC98" is a registered trademark of NEC Corp. "VGA" is a registered trademark of IBM Corp. Other company names and product names, etc. contained in these materials are trademarks or registered trademarks of the respective companies.

– 2 –

CXD3500R

Block Diagram

31 52 54 57 58 59 63

27 28 29 30 32 36 38 39 42

10 11

20 21 22 25 26 37 45 46 47 48 49

17644319

SYSTEM CLEAR

IRACT

RSTR

RCK

RSTW

WCK

HDN

HST HCK1 HCK2

BLK

ENB1

PCG

ENB2

CLP

PRG

60 61 62

SCTR

SCLK

SDAT

RGTCNT

FRPCNT

MODE3

MODE2

MODE1

RGT

XRGT

DWN

SHP1A

SHP1B

SHP2A

SHP2B

7 9 12 13 14 15 16 18 35 41

INV

XCLR

CKI2

CKLIM

CKI1

CKI3

HSYNC VSYNC

XVS XHS ORACT

VSS

VD FLD VCK VST FRP XFRP

TEST

SERIAL DATA I/F

PLL COUNTER & DECODER

H-POSITION COUNTER & DECODER

AUX. PLL COUNTER & DECODER

MASTER CLOCK

V-POSITION COUNTER & DECODER

SYNC DETECTOR

PULSE ELIMINATOR

H-TIMING PULSE GENERATOR

V-TIMING PULSE GENERATOR

– 3 –

CXD3500R

Pin Description

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

HSYNC VSYNC CKI2 CKLIM VD FLD TEST0 VSS0 TEST1 RGTCNT FRPCNT TEST2 TEST3 TEST4 TEST5 TEST6 CKI3 TEST7 XCLR MODE3 MODE2 MODE1 VSS1 VDD0 RGT XRGT HST HCK1 HCK2 BLK HD ENB1 VCK

I I

I/O

— — —

I — — — — —

I —

O O

O — —

Horizontal sync signal input Vertical sync signal input Clock 2 input (Small signal: Vth = VDD/2, min. Vp-p = 0.5V) Clock input selector (CKI1 selected when open.) VD pulse output FLD pulse I/O Test (Not connected.) GND Test (Not connected.) Right/left inversion external control FRP pulse inversion external control Test (Not connected.) Test (Not connected.) Test (Not connected.) Test (Not connected.) Test (Connect to GND.) Clock 3 input (for LAP) Test (Not connected.) System clear (L: set to SVGA 60Hz) Parallel Out 3 output (Panel mode switching 3 output) Parallel Out 2 output (Panel mode switching 2 output) Parallel Out 1 output (Panel mode switching 1 output) GND VDD Right/left inversion discrimination signal output (H: Normal, L: Reverse) Right/left inversion discrimination signal output (reverse polarity of RGT) Horizontal display start pulse output Horizontal display clock pulse output Horizontal display clock pulse output BLK pulse output HD pulse output ENB1 pulse output Vertical display clock pulse output

— — —

H — — — — — —

H — — — — — — — — — — — — — —

Symbol I/O Description

∗

H: Pull up

Input pin for

open status

– 4 –

CXD3500R

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

VST TEST8 PCG DWN ENB2 CLP VSS2 TEST9 PRG FRP XFRP SHP1A SHP1B SHP2A SHP2B INV XVS XHS IRACT ORACT RSTR VSS3 VDD1 RCK RSTW WCK SCTR SCLK SDAT HDN CKI1

—

O O O

O — —

I I I

Vertical display start pulse output Test (Not connected.) Precharge timing pulse output Up/down inversion discrimination signal output (H: Down, L: Up) ENB2 pulse output Pedestal clamp pulse output for CXA2112R GND Test (Not connected.) Precharge signal pulse output AC drive inversion timing output AC drive inversion timing output (reverse polarity of FRP) External sample-and-hold driver control signal (for CXA2112R) External sample-and-hold driver control signal (for CXA2112R) External sample-and-hold driver control signal (for CXA2112R) External sample-and-hold driver control signal (for CXA2112R) External sample-and-hold driver control signal (for CXA2112R) Vertical auxiliary pulse output Horizontal auxiliary pulse output LAP control pulse output LAP control pulse output Reset read output (for high-speed line buffer) GND VDD Read clock output (for high-speed line buffer) Reset write output (for high-speed line buffer) Write clock output (for high-speed line buffer) Chip select input (serial transfer block) Serial clock input (serial transfer block) Serial data input (serial transfer block) Phase comparator pulse output Clock 1 input (TTL)

— — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —

∗

H: Pull up

No.

Symbol I/O Description

Input pin for open status

– 5 –

CXD3500R

Electrical Characteristics

1. DC characteristics

(VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C)

Item

VDD VI, VO VIH VIL Vth VIH VIL VIN RFB VIH VIL VT+ VT– VT+ – VT– VOH VOL VOH VOL VOH VOL II IIL II

IOZ IDD

4.5

VSS

2.2

0.7VDD

0.5

250k

0.7VDD

2.2

VDD – 0.8

–10 –40 –40

–40

5.0

VDD/2

0.4

–100

5.5

VDD

0.8

0.3VDD

2.5M

0.3VDD

0.8

0.4

0.4 10

–240

40 40

IOH = –2mA IOL = 4mA IOH = –6mA IOL = 4mA IOH = –8mA IOL = 8mA

∗5 ∗7

∗9 ∗10 ∗11

Symbol Conditions Min. Typ. Max. Unit Supply voltage Input, output voltages

Input voltage 1

Logical threshold value

Input voltage 2

Input amplitude Feedback resistor

Input voltage 3

Input voltage 4

Output voltage 1

Output voltage 2

Output voltage 3

Input leak current

Output leak current

Current consumption

Applicable pins

∗1

CKLIM, RGTCNT, FRPCNT, CKI3, TEST7, XCLR

∗2

MODE1, MODE2, MODE3, RGT, XRGT, DWN, SHP1B, SHP2B, INV

∗3

VD, BLK, HD, ENB1, ENB2, VCK, VST, PCG, CLP, PRG, FRP, XFRP, XVS, XHS, IRACT, ORACT, HDN

∗4

HST, HCK1, HCK2, RSTR, RCK, RSTW, WCK

∗5

Normal input pins (VIN = Vss or VDD)

∗6

HSYNC, VSYNC, RGTCNT, CKI3, SCTR, SCLK, SDAT, CKI1

∗7

Pins with pull-up resistors (VIN = Vss)

∗8

CKLIM, FRPCNT, TEST7, XCLR

∗9

Bidirectional pins (VIN = Vss or VDD)

∗10

Tri-state (at high impedance, VIN = Vss or VDD)

∗11

VDD = 5.0V, 55MHz input (actual measurement)

V V

Vp-p

Ω

µA

CKI1

CKI2

∗1

HSYNC, VSYNC, SCTR, SCLK, SDAT

TTL input

Small amplitude input

50MHz sine wave VIN = Vss or VDD

CMOS input

TTL Schmitt trigger input

∗2

∗3

∗4

∗6 ∗8

FLD SHP1A,

SHP2A At a 30pF load

– 6 –

CXD3500R

2. AC characteristics (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C)

3. Serial transfer AC characteristics (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C)

Item

Clock input cycle

CKI1 CKI2 All outputs All outputs HCK1, 2 HCK1 HCK2

tr tf

∆t

tH/(tH + tL) tL/(tH + tL)

Output rise time Output fall time Cross-point time difference HCK1 Duty HCK2 Duty

18.2

–10

48 48

20 20 10 52 52

CL = 30pF

Applicable pinsSymbol ConditionsMin. Typ. Max.

Unit

Note) The minimum value for the clock input cycle (CKI1) when using the built-in double-speed controller is 27ns.

Item SCTR setup time with respect to rise of SCLK SDAT setup time with respect to rise of SCLK SCTR hold time with respect to rise of SCLK SDAT hold time with respect to rise of SCLK SCLK L level pulse width SCLK H level pulse width

4Tns 2Tns 4Tns 2Tns 2Tns 2Tns 5Tns 5Tns

Min. Typ. Max.

ts0 ts1 th0

th1 tW1L tW1H

tW2 tW3

Symbol

T: Input clock cycle

Note) Consider the frequency at free running (no signal). When the above characteristic specification is not

satisfied at free running, IC operation including serial transfer is not guaranteed.

4. External clock input AC characteristics (VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C) Item

HSYNC setup time with respect to rise of CKI1 HSYNC hold time with respect to rise of CKI1 HSYNC setup time with respect to rise of CKI2 HSYNC hold time with respect to rise of CKI2 CKI1,2 L/H level pulse width HSYNC setup time with respect to rise of CKI1 HSYNC hold time with respect to rise of CKI1 HSYNC setup time with respect to rise of CKI2 HSYNC hold time with respect to rise of CKI2 CKI1,2 L/H level pulse width

4 7 2 9 6 0 6 0 8

40 60

Min.

T/2

Typ. Max. Unit

ts0

th0

ts0

th0

tWL/tWH

ts0

th0

ts0

th0

tWL/tWH

Symbol

SLCK∗1: H CKPOL∗2: H SLRS∗3: L

SLCK∗1: L CKPOL∗2: H

Conditions

∗1, 2, 3

: Serial data Add. 0A

T: Input clock cycle

Note) During external clock input, set serial data HR to L. The pulse synchronized to the horizontal sync signal is

generated by detecting the front edge of the horizontal sync signal and then resetting the internal PLL counter.

– 7 –

CXD3500R

5. Timing definitions

AC characteristics

90%

CKI1/2

HCK1

HCK2

HCK1

Output

Note) HCK2 is the reverse phase of HCK1.

10%

tpr

100%

90%

10%

50%

∆t

tpf

tH tL

50%50% 50%

50%

∆t

Serial transfer AC characteristics

SCTR

SCLK

SDAT

ts0

tw2tw1L tw1H

ts1 th1 ts1 th1

th0 tw3

50%

D15D7D9D14

Note) See "Serial transfer timing" on page 11 for the timing relationship between D15 to D0 and each pulse.

D0D8D15

External clock input AC characteristics

HSYNC (negative polarity)

CKI1, 2

50%

th0 ts0

twL twH

50% 50%

50%

th0 ts0

50%

– 8 –

CXD3500R

(4) NTSC

ODD FIELD

EVEN FIELD

HSYNC

VSYNC

H/2

Sync signal phase reference

Input Signal Protocol

1. Horizontal sync signal

a) A standard signal (HSYNC) should be input for each mode.

However, since the CXD3500R requires a double-speed signal as input during NTSC/PAL double-speed display when not using the built-in double-speed controller, the input specifications at that time are similar to those for normal data type sync signals, and there should not be a 1/2 offset with respect to the vertical sync signal.

b) The input sync signal polarity is not fixed, and is set by the serial data (HPOL).

2. Vertical sync signal

a) A sync-separated, normal-speed VSYNC should be input as the vertical sync signal. b) The input sync signal polarity is not fixed, and is set by the serial data (VPOL). c) The phase relationship between HSYNC and VSYNC is specified as follows for the CXD3500R.

(1) XGA, Macintosh16, SVGA, VGA, PC-98

HSYNC

VSYNC Sync signal

phase reference

(2) Double-speed NTSC

Double-speed HSYNC

VSYNC

Sync signal phase reference

(3) Double-speed PAL

VSYNC

Double-speed HSYNC

Sync signal phase reference

– 9 –

CXD3500R

(5) PAL

ODD FIELD

EVEN FIELD

HSYNC

VSYNC

H/2

Sync signal phase reference

Notes) (2) and (3) show the timing when supporting input of double-speed signals.

(4) and (5) show the timing when using the built-in double-speed controller (CXD3500R) and a line memory (µPD485505: NEC)

– 10 –

CXD3500R

Description of Operation

Sync signal input

The HSYNC and VSYNC input pins support separate SYNC only. When using a composite SYNC input, perform sync separation using a separate sync separation IC, etc.

Clock input (1) CKI1 and 2 pins

CKI1 and 2 are the clock input pins from an external PLL IC. CKI1 is TTL level input, and CKI2 is small amplitude clock input. Internal operation is performed at 1/2 clock, so the CXD3500R has a built-in frequency divider which halves the input master clock, and can select this halved clock or a 1/2 clock input from an external source by the serial interface setting. However, the input clock should be 55MHz or less, so when using a master clock of more than 55MHz, input the 1/2 clock. The 1/N frequency divider output for the PLL IC is output from the HDN pin. The HDN polarity at this time is set by serial data HDNPOL.

(2) CKI3 pin

CKI3 is the clock input pin when using a scan converter that operates with the input sync signals and an asynchronous clock in the system. Since two types of clock are input in this case, the circuits that basically operate with the respective clocks of CKI1 and CKI2 are asynchronous. The input clock should be 55MHz or less. For details, see the explanation of pulse setting for the scan converter in this data sheet (starting on page 34).

AC driving of LCD panels for no signal

The following measures have been adopted to allow AC driving of LCD panels even when there is no signal. However, master clock CKI1 or CKI2 must be input even during free running. Note that the recommended PLL IC CXA3106(A)Q does not output the clock when there is no HSYNC input.

Horizontal direction pulse

The PLL is set to free running status. Therefore, the frequency of the horizontal direction pulse is dependent on the PLL free-running frequency.

Vertical direction pulse

The number of lines is counted by an internal counter and the vertical direction pulses (VST, FRP) are output at a specified cycle. For the CXD3500R, no signal (free running) status is judged if there is no VSYNC input for longer than the following periods (free running detection timing).

PLSSL2, 1, 0

L L L or L L H

L H L to H L L

H L H to H H H

V cycle for no signal

701H 1001H 1301H

Free running detection

700H 1000H 1300H

– 11 –

CXD3500R

XCLR pin

The CXD3500R should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits. At this time, the serial interface circuit is reset to the initial status (preset status). See page 38 for the preset settings.

Serial transfer operation

1. Control method

The CXD3500R operation timing is controlled by serial data. The control data is comprised of an 8-bit address and 8-bit data, and the individual data is loaded at the rise of SCLK. This loading operation starts from the fall of SCTR and is completed at the next rise of SCTR.

SCTR

SCLK

SDAT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

DataAddress

D3 D2 D1 D0

Serial transfer timing

– 12 –

CXD3500R

2. Control data

When using the CXD3500R, set the control data corresponding to each LCD panel and video signal according to the formats in the table below.

Note) PLLP0, HP0, VP0, HSTW0, HSTP0, PCGU0, PCGD0, PRGD0, FRPP0, SHP0, MBKA0, MBKB0,

MBKZ0, IRD0, IRU0, ORRS0, ORP0, ORD0, ORU0, HAXD0, HAXU0, VAXD0, VAXU0: LSB. Shaded bits (PLLP0, IRU0, ORPU, ORU0 and HAXU0) are indicated for reference, and actual data setting to these bits is invalid.

D15

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Address Data

D14

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D13

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

D12

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

D11

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

D10

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

PLLP11

PLLP3

HP7 VP7

HSTW1

PCGU2

—

set 0

VSTFX

VSTPOL

SLCNT BLKON MBKZ3

VGAV XGBK

—

SLLAP

IRD11

IRD3 IRU7

VRSP3

ORP7

ORD11

ORD3 ORU7

HAXD11

HAXD3 HAXU7

VAXD11

VAXD3

VAXU7

PLLP10

PLLP2

HP6

VP6 HSTW0 PCGU1

—

PCG

HCKFX

HCKPOL

SLFLD

BLKPOL

MBKZ2

HDON

—

LPCK

IRD10

IRD2 IRU6

VRSP2

ORP6

ORD10

ORD2 ORU6

HAXD10

HAXD2 HAXU6

VAXD10

VAXD2 VAXU6

D5 PLLP9 PLLP1

HP5 VP5

HSTP5

PCGU0

—

FRP1

HCKM

VPOL SLRS

FMBK

MBKZ1

DWN

HAXON

—

SLCKL

IRD9 IRD1 IRU5

VRSP1

ORP5 ORD9 ORD1

ORU5 HAXD9 HAXD1 HAXU5

VAXD9 VAXD1 VAXU5

D4 PLLP8 PLLP0

HP4 VP4

HSTP4 PCGD4 PRGD4

FRP0

INV

HPOL CKPOL MBKA4 MBKZ0

RGT

VAXON

—

ORRS4

IRD8 IRD0 IRU4

VRSP0

ORP4

ORD8 ORD0

ORU4 HAXD8 HAXD0 HAXU4

VAXD8 VAXD0 VAXU4

PLLP7

HP11

HP3 VP3

HSTP3 PCGD3 PRGD3

FRPP3

SHP3

HDNPOL

SLCK MBKA3 MBKB3

DSP

set 0

—

ORRS3

IRD7

IRU11

IRU3

ORP11

ORP3 ORD7

ORU11

ORU3

HAXD7

HAXU11

HAXU3

VAXD7

VAXU11

VAXU3

PLLP6

HP10

HP2

VP2

HSTP2 PCGD2 PRGD2

FRPP2

SHP2

CLPPOL

PLSSL2

MBKA2 MBKB2

PO/MODE3

set 0

—

ORRS2

IRD6

IRU10

IRU2

ORP10

ORP2 ORD6

ORU10

ORU2

HAXD6

HAXU10

HAXU2 VAXD6

VAXU10

VAXU2

PLLP5

HP9 HP1 VP1

HSTP1 PCGD1 PRGD1

FRPP1

SHP1

CLPW

PLSSL1

MBKA1 MBKB1

PO/MODE2

set 0 set 0

ORRS1

IRD5 IRU9

IRU1 ORP9 ORP1

ORD5 ORU9

ORU1 HAXD5 HAXU9 HAXU1

VAXD5 VAXU9 VAXU1

PLLP4

HP8 HP0 VP0

HSTP0 PCGD0 PRGD0

FRPP0

SHP0 CLPP

PLSSL0

MBKA0 MBKB0

PO/MODE1

SPON

set 0

ORRS0

IRD4 IRU8

IRU0 ORP8 ORP0 ORD4 ORU8 ORU0

HAXD4 HAXU8 HAXU0

VAXD4 VAXU8 VAXU0

— or : Setting invalid.

– 13 –

CXD3500R

Each control data is described in detail below.

The following descriptions define the width of one dot clock as "clk".

PLLP11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0

These bits set the frequency division ratio (master clock) of the internal 1/N frequency divider for the PLL. The data is 12 bits and the frequency division ratio can be set up to 4096. However, the internal logic circuits of this TG operate at 1/2 clock, so the PLLP0 setting is invalid. When N is an odd number, use an external frequency divider. The actual frequency division ratio should be set as follows.

Number of clk for the horizontal period – 2 = Actual number of dots set

Examples of settings for major modes are shown below.

Note) When using an external frequency divider (serial data HR is L), these settings are not necessary. (They

can also be set to all L.)

1) Macintosh16 (832 × 624) PLLP setting value = 1152 (horizontal period) – 2 → 1150 (LHLLLHHHHHHL: LSB)

PLLP

Setting data11L10H9L8L7L6H5H4H3H2H1H0L

2) SVGA (800 × 600) PLLP setting value = 1056 (horizontal period) – 2 → 1054 (LHLLLLLHHHHL: LSB)

PLLP

Setting data11L10H9L8L7L6L5L4L3H2H1H0L

3) VGA (640 × 480) PLLP setting value = 800 (horizontal period) – 2 → 798 (LLHHLLLHHHHL: LSB)

PLLP

Setting data11L10L9H8H7L6L5L4H3H2H1H0L

4) PC98 (640 × 400) PLLP setting value = 848 (horizontal period) – 2 → 846 (LLHHLHLLHHHL: LSB)

PLLP

Setting data11L10L9H8H7L6H5L4L3H2H1H0L

5) NTSC double speed (640 × 480) PLLP setting value = 1560 (horizontal period) – 2 → 1558 (LHHLLLLHLHHL: LSB)

PLLP

Setting data11L10H9H8L7L6L5L4H3L2H1H0L

6) PAL double speed (762 × 572) PLLP setting value = 1880 (horizontal period) – 2 → 1878 (LHHHLHLHLHHL: LSB)

PLLP

Setting data11L10H9H8H7L6H5L4H3L2H1H0L

∗

VESA SVGA60

∗

VGA60

– 14 –

CXD3500R

HP11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0

These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of with 12 bits is possible using the front edge of HSYNC as the reference. The HP setting range is from 0 to (N – 1). However, do not set HP to the number of frequency divisions N or higher, as the various pulses will not be output.

The horizontal direction timing is interlinked using the falling edges of ENB1 and 2 as the reference. The following pulses are interlinked according to the HP11 to 0 setting.

HST, HCK1, HCK2, ENB1, ENB2, PCG, PRG, CLP, BLK, VD, VCK transition point, FRP transition point, XFRP transition point, BLK transition point and VD transition point

HSYNC

Thp Image display period

Thp: Timing from the front edge of HSYNC to the HST pulse HSTP5 to 0: LLLLL, HDNPOL: H

HST

HDN

Minimum Thp setting values for each mode

PLSSL2, 1, 0

L L L L L H L H L

L H H

H L L H L H H H L

H H H

Thp 72 clk 92 clk

118 clk 146 clk 178 clk 188 clk 204 clk 232 clk

∗

HSTP5, 4, 3, 2, 1, 0: All L

Note) The time from HST until image display starts differs for each panel and its display area switching mode.

In modes which apply a reset at the front edge of HSYNC (HR: L), the HDN pulse transition point is delayed by several dots relative to HSYNC. In these modes, Thp in the table above indicates the value using the HDN pulse transition point as the reference.

HSYNC

6 to 10 clk

Reference: HDN transition point

HDN

HDNPOL: H

– 15 –

CXD3500R

VP7, 6, 5, 4, 3, 2, 1, 0

These bits set the vertical display start position. The minimum adjustment width is 1H of the output signal, and adjustment of up to 256H with 8 bits is possible using the front edge of VSYNC as the reference. In interlace signal double-speed mode, the vertical display start position can be set within a width of 1H relative to the double-speed converted signal.

a) Non-interlace

VSYNC

Tvp

HSYNC

Minimum adjustment width

VST

VCK

VSYNC

ODD field

Tvp

HSYNC

Minimum adjustment width

VST

VCK

VSYNC

EVEN field

Tvp

HSYNC

VST

VCK

Note) The time from VST until image display starts differs for each panel.

Also see the data sheets of the used panels.

b) When using an interlace double-speed controller

Minimum and maximum Tvp setting values

Min.

Max.

7 L

6 L

5 L

4 L

3 L

2 L

1 L

0 L

259H

– 16 –

CXD3500R

The vertical display start position setting VP sets the value used to decode the internal counter. This internal counter is reset at the ENB1 and 2 pulse fall position when VSYNC is input, and counts up at each ENB1 and 2 pulse fall position thereafter. Therefore, when VSYNC is delayed relative to HSYNC and serial data HP is all L or a similar value, or when the HP11 to 0 setting is large and the ENB pulses fall near the end of the horizontal period, the vertical display start position is offset by 1H.

VSYNC

HSYNC

ENB1, 2

The counter is reset at this timing.

When the HP11 to 0 setting is large.

– 17 –

CXD3500R

Horizontal direction pulses

The horizontal direction timing pulses for driving LCD panels are advanced and delayed interlinked with serial data HP11 to 0. The reference at this time is the falling edge of the ENB1 and 2 pulses. Except for during skip scan, the ENB1 and 2 pulse width is fixed by serial data PLSSL, and the pulse position is determined by serial data HP11 to 0. (See the Timing Charts.) The horizontal direction pulse position for other panels is generated by the internal counter that is reset at the ENB1 and 2 pulse fall position.

HSTW1, 0

These bits set the HST pulse width. Normally set HSTW1 and 0 to LL for 6-dot simultaneous sampling panels (VGA, SVGA), and to HL for 12-dot simultaneous sampling panels (XGA).

HSTW1, 0

L L L H H L

H H

HST pulse width

12 clk 18 clk 24 clk 48 clk

ENB1, 2

Thst

HST

HSTP5, 4

This sets the HST pulse rise position. The HST pulse rise position from the falling edge of the ENB1 and 2 pulses is as shown in the table below according to the PLSSL2, 1, 0 setting. However, note that the HSTP5 setting is invalid when PLSSL2 to 0 (described hereafter) is set from LLL to HLL.

Thst rise position

L L L L L H L H L

L H H

H L L

H L H H H L

H H H

L L 70 clk 90 clk

116 clk 144 clk 176 clk 186 clk 202 clk 230 clk

L H

82 clk 102 clk 128 clk 156 clk 188 clk 198 clk 214 clk 242 clk

H L 70 clk 90 clk

116 clk 144 clk 176 clk 210 clk 226 clk 254 clk

H H

82 clk 102 clk 128 clk 156 clk 188 clk 222 clk 238 clk 266 clk

Note) HST3, 2, 1, 0: LLLL

PLSSL2, 1, 0

HSTP5, 4

– 18 –

CXD3500R

HSTP3, 2, 1, 0

These bits adjust the HST pulse start phase relative to HCK in 1-dot units. Set these bits as follows using HSTP5 to 0: LLLLLL (LSB) as the reference.

Serial setting HCKM: L (6-dot simultaneous sampling)

HST

HCK1

Reference

HSTP5 to 0: LLLLLL (LSB)

Reference

HSTP5 to 0: LLLLHH (LSB)

3 clk

HST

HCK1

Reference

HSTP5 to 0: LLLHHL (LSB)

Reference

HSTP5 to 0: LLHLHH (LSB) to LLHHHH (LSB)

11 clk

6 clk

HST

HCK1

Reference Same hereafter using this point as the reference.

HSTP5 to 0: LHLLLL (LSB)

Note) HCK2 is the reverse polarity of HCK1. The timings shown above are for RGT: H, HCKPOL: H and

HCKFX: L.

Serial setting HCKM: H (12-dot simultaneous sampling)

12 clk

HST

HCK1

Reference

HSTP5 to 0: LLLLLL (LSB)

6 clk

Reference

HSTP5 to 0: LLLHHL (LSB)

11 clk

HST

HCK1

Reference

HSTP5 to 0: LLHLHH (LSB) to LLHHHH (LSB)

Reference Same hereafter using this point as the reference.

HSTP5 to 0: LHLLLL (LSB)

Note) HCK2 is the reverse polarity of HCK1. The timings shown above are for RGT: H, HCKPOL: H and

HCKFX: L.

– 19 –

CXD3500R

PCGU2, 1, 0

These bits adjust the PCG pulse rise position in 2-dot units. (However, serial data PCG: H) When serial data PCG is L, the PCGU2 to 0 setting is invalid and the PCG pulse rises at the same position as the FRP pulse transition point regardless of this setting. (interlinked with FRPP3, 2, 1, 0)

PCGD4, 3, 2, 1, 0

These bits adjust the PCG pulse fall position in 2-dot units. However, the PCGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL.

The PCGU2, 1, 0 and PCGD4, 3, 2, 1, 0 setting ranges are shown in the table below.

L L L L L H L H L

L H H

H L L

H L H H H L

H H H

L L L 12 clk 18 clk 26 clk 36 clk 46 clk 48 clk 52 clk 58 clk

H H H 28 clk 32 clk 40 clk 50 clk 60 clk 62 clk 66 clk 72 clk

L L L L L

56 clk 74 clk

98 clk 124 clk 152 clk 150 clk 164 clk 190 clk

H H H H H

86 clk 104 clk 128 clk 154 clk 182 clk 212 clk 226 clk 252 clk

∗

: The PCGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL.

PLSSL2, 1, 0

Tpcu Tpcd

PCGU2, 1, 0

PCGD4∗, 3, 2, 1, 0

ENB1, 2

Tpcu

Tpcd

PCG

PCG: H

Adjust the PCG pulse width to match the specifications for each LCD panel with the PCGU2 to 0 and PCGD4 to 0 settings. See the data sheets of the used panel for the PCG pulse width.

– 20 –

CXD3500R

PRGD4, 3, 2, 1, 0

These bits adjust the PRG pulse fall position in 2-dot units. However, the PRGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL. The PRG pulse rise position is the same as the FRP pulse transition point. (interlinked with FRPP3, 2, 1, 0)

The PRGD4, 3, 2, 1, 0 setting range is shown in the table below.

PCG

This bit selects the new and old PCG pulse timing. When PCG is H, the PCGU2 to 0 setting shown on the previous page is selected. (new timing) When PCG is L, the PCG pulse rise position is interlinked with the FRP pulse transition point. (old timing) Set to match the timing specifications of the LCD panel. Set PCG to H for SVGA panels that support two-step precharge, and to L for other panels.

L L L L L H L H L

L H H

H L L

H L H H H L

H H H

L L L L L

62 clk

82 clk 108 clk 136 clk 168 clk 136 clk 142 clk 162 clk

L H H H H

92 clk 112 clk 138 clk 166 clk 198 clk 166 clk 172 clk 192 clk

H L L L L

62 clk

82 clk 108 clk 136 clk 168 clk 182 clk 196 clk 222 clk

H H H H H

92 clk 112 clk 138 clk 166 clk 198 clk 212 clk 226 clk 252 clk

∗

: The PRGD4 setting is invalid when PLSSL2, 1, 0 is set from LLL to HLL.

PLSSL2, 1, 0

PCGD4∗, 3, 2, 1, 0 PCGD4∗, 3, 2, 1, 0

ENB1, 2

Tprd

PRG

FRP

PCG: H

FRP

PCG: L

Tpru setting range

– 21 –

CXD3500R

FRP1, 0

These bits are the data for switching the LCD AC conversion signal FRP pulse cycle. Normally set FRP1, 0 to LL. FRP0 can also be controlled externally. → See SLCNT.

FRP1, 0: LL (1F/1H inversion)

FRP1, 0: HL (2F/1H inversion)

FRP1, 0: LH (1F inversion)

FRP1, 0: HH (2F inversion)

FRPP3, 2, 1, 0

These bits adjust the FRP pulse transition point in 2-dot units. The PRG pulse rise position is the same as the FRP pulse transition point, and is interlinked with FRPP3 to 0.

ENB1, 2

FRP

Tfrp

PCG

L L L L L H L H L L H H H L L H L H H H L

H H H

L L L L

16 clk 24 clk 36 clk 52 clk 68 clk 58 clk 62 clk 72 clk

H H H H

46 clk 54 clk 66 clk 82 clk 98 clk 88 clk 92 clk

102 clk

PLSSL2, 1, 0

FRPP3, 2, 1, 0

Tfrp setting range

– 22 –

CXD3500R

VSTFX, VSTPOL

These bits set the VST pulse polarity. When VSTFX is H, the polarity of the VST pulse is positive regardless of other settings. Normally set VSTPOL to H. See the table below for details.

Panel VSTFX

XGA

SVGA

—

VSTPOL DWN VST pulse polarity

∗

—: don't care

HCKFX, HCKPOL

These bits set the HCK1 and 2 pulse polarity. When HCKFX is H, the HCK1 and 2 pulse polarity is fixed regardless of the right/left inversion control setting RGT. However, the polarity is inverted by HCKPOL. See the table and figures below for details.

HCKFX

H H

L L L L

— —

L H H

RGT HCKPOL

B A A B B A

HCK polarity

∗

—: don't care

HST

HCK1

HCK2

HST

HCK1

HCK2

HCKM

This bit sets the HCK1 and 2 pulse width. When HCKM is L, the HCK1 and 2 pulse for 6-dot simultaneous sampling is output. When HCKM is H, the HCK1 and 2 pulse for 12-dot simultaneous sampling is output. Set the width to match the panel specifications.

SVGA panel → 6-dot simultaneous sampling → HCKM: L XGA panel → 12-dot simultaneous sampling → HCKM: H

HSTW1, 0: LL, HSTP5 to 0: LLLLHH, HCKM: L

A in the table above B in the table above

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