Sony CXD3408GA Datasheet

CXD3408GA

Timing Generator and Signal Processor for Frame Readout CCD Image Sensor

Description

The CXD3408GA is a timing generator and CCD

signal processor IC for the ICX406 CCD image sensor.

Features

• Timing generator functions

• Horizontal drive frequency 18MHz

(base oscillation frequency 36MHz)

• Supports frame readout/draft (quadruple speed) /AF (auto-focus)

• High-speed/low-speed shutter function

• Horizontal and vertical drivers for CCD image

sensor

• CCD signal processor functions

• Correlated double sampling

• Programmable gain amplifier (PGA) allows gain

adjustment over a wide range (–6 to +42dB)

• 10-bit A/D converter

• Chip Scale Package (CSP):

CSP allows vast reduction in the CCD camera block footprint

Applications

Digital still cameras

Structure

Silicon gate CMOS IC

Applicable CCD Image Sensors

ICX406 (1/1.8", 3980K pixels)

Absolute Maximum Ratings

• Supply voltage

V

DDa, VDDb, VDDc, VDDdVSS – 0.3 to +7.0 V

VDDe, VDDf, VDDgVSS – 0.3 to +4.0 V

VL –10.0 to VSS V VH VL – 0.3 to +26.0 V

• Input voltage (analog) V

IN VSS – 0.3 to VDD + 0.3 V

• Input voltage (digital) VI VSS – 0.3 to VDD + 0.3 V

• Output voltage VO1 VSS – 0.3 to VDD + 0.3 V VO2 VL – 0.3 to VSS + 0.3 V V

O3 VL – 0.3 to VH + 0.3 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –55 to +125 °C

Recommended Operating Conditions

• Supply voltage

V

DDb 3.0 to 5.25 V

VDDa, VDDc, VDDd, VDDe, VDDf, VDDg

3.0 to 3.6 V VM 0.0 V VH 14.5 to 15.5 V VL –7.0 to –8.0 V

• Operating temperature Topr –20 to +75 °C

– 1 –

E01341A26

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

96 pin LFLGA (Plastic)

– 2 –

CXD3408GA

Block Diagram

C7

C3

A1NCA2

NC

D8C2D7C1B8

AVDD3B6AVDD4B9AVSS3A6AVSS4C5AVSS5A3SCK2A4SSI2B4SEN2A5TEST3C4TEST4B5TEST5E2DVDD1F2DVSS3F3DVDD2E3DVSS1

F1

B3

DVSS2

D0 (LSB)

Latch

Serial Port

Register

DAC

PGACDS ADC

Preblanking

Dummy Pixel

Auto Zero

Pulse Generator

V Driver

Serial Port

Register

SSG

Black Level

Auto Zero

B2

D1

B1

D2

C3

D3

C2

D4

C1

D5

D3

D6

D2

D7

D1

D8

E1

D9 (MSB)

G1

ADCLKI

G2

CLPOBI

G3

CLPDMI

L3

V

SS4

H1

ADCLK

H2

CLPOB

H3

CLPDM

J3

V

SS5

L1

OSCI

K1

OSCO

J1

CKI

J2

CKO

K2

MCKO

N8

SNCSL

L2

SSI1

M6

VL

L4

VM

M5

VH

M9

WEN

N9

ID/EXP

J7

V

SS3

J9

H2

J8

H1

H9

V

DD3

K9

V

SS2

K8

RG

K7

V

DD2

H8

V

DD4

H7

XRS

G7

PBLK

G8

XSHD

G9

XSHP

F7

PBLKI

F8

XSHDI

E7

AV

SS2

F9

XSHPI

D9

AV

SS1

E8

AV

DD2

E9

AV

DD1

C9

CCDIN

C6

C9

A7

C8

B7

C7

A8

AV

SS6

A9

AV

DD5

C8

C4

M1

SCK1

N1

SEN1

N3

VSS6

L7

VSS1

K3

VDD5

L9

VDD1

M2

VD

N2

HD

N7

SUB

N4

V4

N6

V3B

V3A

L6

V2

M4N5

V1B

M7

TEST2

M3

TEST1

M8

RST

L8

SSGSL

L5

V1A

Selector

Latch

Selector

1/2

– 3 –

CXD3408GA

Pin Configuration (Top View)

NC

D2

D5

D8

D9

DV

SS2

ADCLKI

ADCLK

CKI

OSCO

OSCI

SCK1

SEN1

A

B

C

D

E

F

G

H

J

K

L

M

N

NC

D1

D4

D7

DV

DD1

DVSS3

CLPOBI

CLPOB

CKO

MCKO

SSI1

VD

HD

SCK2

D0

D3

D6

DV

SS1

DVDD2

CLPDMI

CLPDM

VSS5

VDD5

VSS4

TEST1

V

SS6

SSI2

SEN2

TEST4

VM

V2

V4

TEST3

TEST5

AVSS5

V1A

VH

V1B

AV

SS4

AVDD4

C9

V3A

VL

V3B

C8

C7

C3

C1

AV

SS2

PBLKI

PBLK

XRS

VSS3

VDD2

VSS1

TEST2

SUB

AVSS6

AVDD3

C4

C2

AV

DD2

XSHDI

XSHD

V

DD4

H1

RG

SSGSL

RST

SNCSL

AV

DD5

AVSS3

CCDIN

AV

SS1

AV

DD1

XSHPI

XSHP

V

DD3

H2

V

SS2

VDD1

WEN

ID/EXP

123456789

– 4 –

CXD3408GA

Pin Description

No connected. (Open) No connected. (Open) CCD signal processor block serial interface clock input. (Schmitt trigger) CCD signal processor block serial interface data input. (Schmitt trigger) CCD signal processor block test input 3. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. CCD signal processor block analog GND. CCD signal processor block analog power supply. ADC output. ADC output. ADC output (LSB). CCD signal processor block serial interface enable input. (Schmitt trigger) CCD signal processor block test input 5. Connect to DVDD. CCD signal processor block analog power supply. Capacitor connection. CCD signal processor block analog power supply. CCD signal processor block analog GND. ADC output. ADC output. ADC output. CCD signal processor block test input 4. Connect to DVSS. CCD signal processor block analog GND. Capacitor connection. Capacitor connection. Capacitor connection. CCD output signal input. ADC output. ADC output. ADC output. Capacitor connection. Capacitor connection. CCD signal processor block analog GND. ADC output (MSB). CCD signal processor block digital power supply. (Power supply for ADC)

A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8

B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D7 D8 D9 E1 E2

NC NC SCK2 SSI2 TEST3 AVSS4 C8 AVSS6 AVDD5 D2 D1 D0 SEN2 TEST5 AVDD4 C7 AVDD3 AVSS3 D5 D4 D3 TEST4 AVSS5 C9 C3 C4 CCDIN D8 D7 D6 C1 C2 AVSS1 D9 DVDD1

— —

I I I

— — — —

O O O

I I

— — — —

O O O

I

— — — —

I O O O

— — —

O

—

No.

Symbol I/O Description

– 5 –

CXD3408GA

CCD signal processor block digital GND. CCD signal processor block analog GND. CCD signal processor block analog power supply. CCD signal processor block analog power supply. CCD signal processor block digital GND. CCD signal processor block digital GND. CCD signal processor block digital power supply. Pulse input for horizontal and vertical blanking period pulse cleaning. (Schmitt trigger) CCD data level sample-and-hold pulse input. (Schmitt trigger) CCD precharge level sample-and-hold pulse input. (Schmitt trigger) Clock input for analog/digital conversion. (Schmitt trigger) CCD optical black signal clamp pulse input. (Schmitt trigger) CCD dummy signal clamp pulse input. (Schmitt trigger) Pulse output for horizontal and vertical blanking period pulse cleaning. CCD data level sample-and-hold pulse output. CCD precharge level sample-and-hold pulse output. Clock output for analog/digital conversion. CCD optical black signal clamp pulse output. CCD dummy signal clamp pulse output. Sample-and-hold pulse output for analog/digital conversion phase alignment. Timing generator block digital power supply. (Power supply for CDS block) Timing generator block 3.0 to 5.0V power supply. (Power supply for H1/H2) Inverter input. Inverter output. Timing generator block digital GND. Timing generator block digital GND. CCD horizontal register clock output. CCD horizontal register clock output. Inverter output for oscillation. When not used, leave open or connect a capacitor. System clock output for signal processor IC. Timing generator block digital power supply. (Power supply for common logic block) Timing generator block digital power supply. (Power supply for RG) CCD reset gate pulse output. Timing generator block digital GND. Inverter input for oscillation. When not used, fix to low.

E3 E7 E8 E9

F1 F2 F3 F7 F8

F9 G1 G2 G3 G7 G8 G9 H1 H2 H3 H7 H8 H9

J1

J2

J3

J7

J8

J9 K1 K2 K3 K7 K8 K9

L1

DVSS1 AVSS2 AVDD2 AVDD1 DVSS2 DVSS3 DVDD2 PBLKI XSHDI XSHPI ADCLKI CLPOBI CLPDMI PBLK XSHD XSHP ADCLK CLPOB CLPDM XRS VDD4 VDD3 CKI CKO VSS5 VSS3 H1 H2 OSCO MCKO VDD5 VDD2 RG VSS2 OSCI

— — — — — — —

I I I I I

I O O O O O O O

— —

I O

— —

O O O O

— —

O

—

I

No.

Symbol I/O Description

– 6 –

CXD3408GA

Timing generator block serial interface data input. Schmitt trigger input/No protective diode on power supply side.

Timing generator block digital GND. Timing generator block digital GND. (GND for vertical driver) CCD vertical register clock output. CCD vertical register clock output. Timing generator block digital GND. Internal SSG enable.

High: Internal SSG valid, Low: External sync valid (With pull-down resistor) Timing generator block digital power supply. (Power supply for common logic block) Timing generator block serial interface clock input.

Schmitt trigger input/No protective diode on power supply side. Vertical sync signal input. Timing generator block test input 1.

Normally fix to GND. (With pull-down resistor) CCD vertical register clock output. Timing generator block 15.0V power supply. (Power supply for vertical driver) Timing generator block –7.5V power supply. (Power supply for vertical driver) Timing generator block test input 2.

Normally fix to GND. (With pull-down resistor) Timing generator block reset input.

High: Normal operation, Low: Reset control Normally apply reset during power-on. Schmitt trigger input/No protective diode on power supply side

Memory write timing pulse output. Timing generator block serial interface strobe input.

Schmitt trigger input/No protective diode on power supply side Horizontal sync signal input. Timing generator block digital GND. CCD vertical register clock output. CCD vertical register clock output. CCD vertical register clock output. CCD electronic shutter pulse output. Control input used to switch sync system.

High: CKI sync, Low: MCKO sync (With pull-down resistor) Vertical direction line identification pulse output/exposure time identification pulse

output. Switching possible using the serial interface data. (Default: ID)

L2 L3

L4 L5 L6 L7

L8

L9 M1 M2 M3 M4

M5 M6

M7

M8

M9

N1 N2

N3 N4 N5 N6 N7

N8

N9

SSI1 VSS4

VM V1A V3A VSS1

SSGSL VDD1 SCK1 VD TEST1 V2

VH VL

TEST2

RST

WEN SEN1 HD

VSS6 V4 V1B V3B SUB

SNCSL

ID/EXP

I

— —

O O

—

I

—

I I I

O

— —

I

O

I I

—

O O O O

I

O

Pin No.

Symbol I/O Description

– 7 –

CXD3408GA

Electrical Characteristics

Timing Generator Block Electrical Characteristics DC Characteristics (Within the recommended operating conditions)

VDD2 VDD3 VDD4 VDD1, VDD5

RST, SCK1, SSI1, SEN1

TEST1, TEST2 SNCSL, SSGSL

VD, HD

H1, H2

RG

XSHP, XSHD, XRS, PBLK, CLPOB, CLPDM, ADCLK

CKO

MCKO

ID/EXP, WEN

V1A, V1B, V3A, V3B, V2, V4

SUB

V

DDa

VDDb VDDc VDDd

VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3

VOH5 VOL5 VOH6 VOL6 VOH7 VOL7 IOL IOM1 IOM2 IOH IOSL IOSH

3.0

0.7VDDd

0.8VDDd

VDDd – 0.8

VDDb – 0.8

VDDa – 0.8

VDDd – 0.8

10.0

5.0

5.4

3.3

3.6

5.25

3.6

0.3VDDd

0.2VDDd

0.4

–5.0

–7.2

–4.0

V V V V

V V V V V V V V V V

V V V V V

V mA mA mA mA mA mA

Feed current where I

OH = –1.2mA

Pull-in current where IOL = 2.4mA Feed current where IOH = –22.0mA Pull-in current where IOL = 14.4mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA

Feed current where IOH = –6.9mA Pull-in current where IOL = 4.8mA Feed current where IOH = –3.3mA Pull-in current where IOL = 2.4mA Feed current where IOH = –2.4mA Pull-in current where IOL = 4.8mA V1A/B, V2, V3A/B, V4 = –8.25V V1A/B, V2, V3A/B, V4 = –0.25V V1A/B, V3A/B = 0.25V V1A/B, V3A/B = 14.75V SUB = –8.25V SUB = 14.75V

Supply voltage 1 Supply voltage 2 Supply voltage 3 Supply voltage 4

Input voltage 1

∗1

Input voltage 2

∗2

Input/Output voltage

Output voltage 1

Output voltage 2

Output voltage 3

Output voltage 4

Output voltage 5

Output voltage 6

Output current 1

Output current 2

Item Pins Symbol Conditions Min. Typ. Max. Unit

V

0.8V

DD

d

V

I+

VI –

0.2VDDd

∗1

This input pin is a schmitt trigger input and it does not have protective diode of the power supply side in the IC.

∗

2

These input pins are with pull-down resistor in the IC.

Note) This table indicates conditions at 3.3V drive.

V

OH4

Feed current where IOH = –3.3mA

V

DDc – 0.8

V

OL4

Pull-in current where IOL = 2.4mA

0.4

V

– 8 –

CXD3408GA

Inverter I/O Characteristics for Oscillation (Within the recommended operating conditions)

Item

Logical Vth Input

voltage Output

voltage Feedback

resistor Oscillation

frequency

Pins

OSCI

OSCO

OSCI, OSCO

Symbol

LVth V

IH

VIL VOH VOL

RFB

f

Conditions

Feed current where IOH = –3.6mA Pull-in current where IOL = 2.4mA

VIN = VDDd or VSS

Min.

0.7V

DDd

V

DDd – 0.8

500k

20

Typ.

V

DDd/2

2M

Max.

0.3VDDd

0.4 5M

50

Unit

V V V V V

Ω

MHz

Item

Logical Vth Input

voltage Input

amplitude

Pins

CKI

Symbol

LVth V

IH

V

IL

VIN

Conditions

fmax 50MHz sine wave

Min.

0.7V

DDd

0.3

Typ.

VDDd/2

Max.

0.3VDDd

Unit

V V V

Vp-p

Item

Rise time

Fall time

Output noise voltage

Symbol

TTLM TTMH TTLH TTML TTHM TTHL VCLH VCLL VCMH VCML

Conditions

VL to VM VM to VH VL to VH VM to VL VH to VM VH to VL

Min.

200 200

30 200 200

30

Typ.

350 350

60 350 350

60

Max.

500 500

90 500 500

90

1.0

Unit

ns ns ns ns ns ns

V V V V

Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment

(Within the recommended operating conditions)

Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude

is the input amplitude characteristics in the case of input through a capacitor.

Switching Characteristics (VH = 15.0V, VM = GND, VL = –7.5V)

Notes)

1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for measures to prevent electrostatic discharge.

2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between each power supply pin (VH, VL) and GND.

3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.

– 9 –

CXD3408GA

Switching Waveforms

V1A (V1B, V3A, V3B)

V2 (V4)

SUB

TTMH TTHM

VH

VM

VL

VM

VL

VH

VL

90%

10%

90%

10%

TTLM

90%

10%

90%

10%

TTLH TTHL

90%90%

10% 10%

TTML

90%

10%

TTML

90%

10%

Waveform Noise

VCMH

VCML

VM

VL

VCLH

VCLL

– 10 –

CXD3408GA

Measurement Circuit

N1

N2

L4

L5

L6N7L7

N8

N9

M1M2M3

N4N5N6

M4

N3 L2 K2 K9 K8 K7 K1 L1 K3 J9 J8 J7 J3 J2 J1 H9 H8 H7 H3 H2 L3 G9 G8 G7

A2 A1 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B9 B8 C1 C2 C3 C4 C5 C6

M5

M6

E1

L8

L9

M7M8M9

E8

D8

D7

D3D2D1C9C8

C7

F3

F2

G1

E9D9E7

G3

G2

H1

F9F8F7

F1

E3

E2

VD

CXD3408GA

V2VHVLD9SSGSL

V

DD1

SCK1VDTEST1V4V1B

V3B

TEST2

RST

WEN

SEN1HDVM

V1A

V3A

SUB

V

SS1

SNCSL

ID/EXP

CLPDMI

CLPOBI

ADCLK

XSHPI

XSHDI

PBLKI

DV

DD2

DVSS3

ADCLKI

AV

DD1

AVSS1

AVSS2

DVSS2

DVSS1

DVDD1

AVDD2

C2C1D6D7D8

CCDIN

C4

C3

VSS6

SSI1

MCKO

V

SS2

RG

V

DD2

OSCO

OSCI

V

DD5

H2

H1

V

SS3

VSS5

CKO

CKI

V

DD3

VDD4

XRS

CLPDM

CLPOB

V

SS4

XSHP

XSHD

PBLK

NC

SCK2

SSI2

TEST3

AV

SS4

C8

AV

SS6

AVDD5

D2

D1

D0

SEN2

TEST5

AV

DD4

C7

AV

SS3

AVDD3

D5

D4

D3

TEST4

AV

SS5

C9

Serial interface data

HD

+3.3V

+15.0V

–7.5V

C2

C2 C2

C2

R1

R2

R1

R1 R1

C2

C1

C2

C3

CKI

C6 C4 C5 C5 C6 C6

C1 3300pF C2 560pF C3 820pF C4 8pF C5 180pF C6 10pF

R1 30Ω R2 10Ω

– 11 –

CXD3408GA

AC Characteristics

AC characteristics between the serial interface clocks

SSI1

0.2V

DDd

0.2VDDd

0.8V

DDd

ts2

th1ts1

ts3

0.8V

DDd

0.8V

DDd

SCK1

SEN1

Symbol

ts1 th1 ts2 ts3

Definition SSI1 setup time, activated by the rising edge of SCK1 SSI1 hold time, activated by the rising edge of SCK1 SCK1 setup time, activated by the rising edge of SEN1 SEN1 setup time, activated by the rising edge of SCK1

Min. Typ. Max.

20 20 20 20

Unit

ns ns ns ns

Serial interface clock internal loading characteristics (1)

(Within the recommended operating conditions)

th1

Enlarged view

Example: During frame mode

0.2V

DDd

ts1

0.2V

DDd

V1A

VD

HD

V1A

SEN1

0.8V

DDd

Symbol

t

s1

t

h1

Definition SEN1 setup time, activated by the falling edge of HD SEN1 hold time, activated by the falling edge of HD

Min. Typ. Max.

0

110

Unit

ns

µs

∗

Be sure to maintain a constantly high SEN1 logic level near the falling edge of the HD in the horizontal period during which V1A/B and V3A/B values take the ternary value and during that horizontal period.

(Within the recommended operating conditions)

– 12 –

CXD3408GA

Serial interface clock output variation characteristics

Normally, the serial interface data is loaded to the CXD3408GA at the timing shown in "Serial interface clock internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is loaded to the CXD3408GA and controlled at the rising edge of SEN1. See "Description of Operation".

0.8VDDd

SEN1

Output signal

tpdPULSE

Symbol

tpdPULSE

Definition

Output signal delay, activated by the rising edge of SEN1

Min. Typ. Max.

1005

Unit

ns

(Within the recommended operating conditions)

Serial interface clock internal loading characteristics (2)

th1

0.2VDDd

ts1

0.2V

DDd

VD

HD

VD

HD

SEN1

0.8V

DDd

Enlarged view

Example: During frame mode

Symbol

ts1 th1

Definition

SEN1 setup time, activated by the falling edge of VD SEN1 hold time, activated by the falling edge of VD

Min. Typ. Max.

0

200

Unit

ns ns

∗

Be sure to maintain a constantly high SEN1 logic level near the falling edge of VD.

(Within the recommended operating conditions)

– 13 –

CXD3408GA

RST

0.2VDDd tw1

0.8VDDd

VD

HD

ts1

th1

0.2V

DDd

0.2V

DDd

0.2V

DDd

RST loading characteristics

Symbol

tw1

Definition

RST pulse width

Min. Typ. Max.25Unit

ns

(Within the recommended operating conditions)

VD and HD phase characteristics

Symbol

t

s1

t

h1

Definition VD setup time, activated by the falling edge of HD VD hold time, activated by the falling edge of HD

Min. Typ. Max.

20

100

Unit

ns ns

(Within the recommended operating conditions)

HD

MCKO

ts1

th1

0.2VDDd

0.8V

DDd

0.2VDDd

HD loading characteristics

Symbol

ts1 th1

Definition HD setup time, activated by the rising edge of MCKO

HD hold time, activated by the rising edge of MCKO

Min. Typ. Max.

20

5

Unit

ns ns

MCKO load capacitance = 10pF

(Within the recommended operating conditions)

– 14 –

CXD3408GA

0.8VDDd

MCKO

WEN, ID/EXP

tpd1

WEN and ID/EXP load capacitance = 10pF

(Within the recommended operating conditions)

Symbol

tpd1

Definition

Time until the above outputs change after the rise of MCKO

Min. Typ. Max.

6020

Unit

ns

Output variation characteristics

– 15 –

CXD3408GA

CCD Signal Processor Block Electrical Characteristics

DC Characteristics (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)

Item Supply voltage 1 Supply voltage 2

Supply voltage 3

Analog input capacitance

Input voltage

A/D clock duty

Output voltage

Pins DVDD1 DVDD2 AVDD1,

AVDD2, AVDD3, AVDD4, AVDD5

CCDIN SCK2, SSI2,

SEN2, TEST3, TEST4, XSHDI, XSHPI, ADCLKI, CLPOBI, CLPDMI, PBLKI

ADCLKI

D0 to D9

Symbol

VDDe VDDf

VDDg

CIN VI +

VI –

VOH VOL

Conditions

Feed current where I

OH = –2.0mA

Pull-in current where IOL = 2.0mA

Min.

3.0

VDDe – 0.9

Typ.

3.3

15

1.8

1.1

50

Max.

3.6

0.4

Unit

V V

V

pF

V

%

V V

Analog Characteristics (Fc = 18MSPS, DVDD1, 2 = AVDD1, 2, 3, 4, 5 = 3.3V, Ta = 25°C)

Item CCDIN input voltage amplitude PGA maximum gain PGA minimum gain ADC resolution ADC maximum conversion rate ADC integral non-linearity error ADC differential non-linearity error

Signal-to-noise ratio

CCDIN input voltage clamp level CCD optical black signal clamp

level

Symbol

V

IN

Gmax Gmin

Fc max EL ED

SNR

∗1

CLP OB

Conditions PGA gain = 0dB, output full scale PGA gain setting data = "3FFh" PGA gain setting data = "000h"

PGA gain = 0dB PGA gain = 0dB CCDIN input connected to GND

via a coupling capacitor PGA gain = 0dB

OBLVL = "8h" PGA gain = 0dB

Min.

900

18

Typ.

42 –6 10

±1.0 ±0.5

62

1.5 32

Max. 1100

±5.0 ±1.0

Unit

mV

dB dB bit

MHz

LSB LSB

dB

V

LSB

∗

1

SNR = 20 log (full-scale voltage/rms noise)