Sony CXD3027R Datasheet
CXD3027R
Description
The CXD3027R is a digital signal processor LSI for CD
players. This LSI incorporates a digital servo, high & bass
boost, shock-proof memory controller, 1-bit DAC and
analog low-pass filter.
Features
• All digital signal processing during playback is performed
with a single chip
• Highly integrated mounting possible due to a built-in RAM
Digital Signal Processor (DSP) Block
• Supports CAV (Constant Angular Velocity) playback
• Frame jitter free
• 0.5
× to 4× speed continuous playback possible
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 4× speed playback
• Supports variable pitch playback
• The bit clock, which strobes the EFM signal, is generated
by the digital PLL.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error correction
C1: double correction, C2: quadruple correction
Supported during 4× speed playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and subcode-Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a new
CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• CD TEXT data demodulation
• Digital Out can be generated from the audio serial input.
(also supported after shock-proof and digital bass boost
processing, subcode-Q addition function)
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
• Tracking filter: 6 stages
Focus filter: 5 stages
Shock-Proof Memory Controller Block
• Supports an external 4M-bit/16M-bit DRAM
• Time axis-based data linking
• ADPCM compression method (uncompressed/4 bits/
6 bits/8 bits)
Digital Filter, DAC and Analog Low-pass Filter Blocks
• Digital dynamic bass boost and high boost
Bass Boost:4th-order IIR 24dB/Oct
+10dB/+14dB/+18dB/+22dB
High Boost: Second-order IIR 12dB/Oct
+4dB/+6dB/+8dB/+10dB
• Independent turnover frequency selection possible
Bass Boost: 125Hz/160Hz/200Hz
High Boost: 5kHz/7kHz
• Digital dynamics (compressor)
Volume increased by +5dB at low level
• 8× oversampling digital filter
(attenuation: 61dB, ripple within band: ±0.0075dB)
• Digital signal output possible after boost
• Serial data format selectable from (output) 20 bits/
18 bits/16 bits (rearward truncation, MSB first)
• Digital attenuation: –∞, –60 to +6dB, 2048 steps (linear)
• Soft mute
• Digital de-emphasis
• High-cut filter
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage V
DD, AVDD –0.3 to +4.6 V
• Input voltage V
I –0.3 to +4.6 V
(V
SS – 0.3V to VDD + 0.3V)
• Output voltage V
O –0.3 to +4.6 V
•
Storage temperature
Tstg –40 to +125 °C
• Supply voltage difference
AV
SS – VSS –0.3 to +0.3 V
AV
DD – VDD –0.3 to +0.3V(AVDD < 2.2V)
AV
DD – VDD –0.3 to +1.4V(AVDD = 2.2 to 3.6V)
Recommended Operating Conditions
• Supply voltage VDD , AVDD0, 3 2.2 to 3.6 V
AV
DD1, 2, DVDD VDD to 3.6 V
•
Operating temperature
Topr –20 to +75 °C
I/O Pin Capacitance
• Input capacitance CI 12 (max.) pF
• Output capacitance C
O 12 (max.) pF
Note) Measurement conditions V
DD = VI = 0V
f
M = 1MHz
– 1 –
E99431B04-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
120 pin LQFP (Plastic)
CD Digital Signal Processor with Built-in Digital Servo +
Shock-Proof Memory Controller + Digital High & Bass Boost
– 2 –
CXD3027R
A0 to A11
D0 to D4
XEMP
XWIH
XQOK
BCK
LRCK
DOUT
PCMD
XRST
TEST
TES1
D/A
Interface
EFM
demodulator
Error
Corrector
32K
RAM
Sub Code
Processor
Clock
Generator
Asymmetry
Corrector
Digital
PLL
CPU
Interface
Signal
Processor
Block
C2PO
WFCK
EMPH
GFS
XUGF
XTAI
RFAC
ASYI
ASYO
BIAS
FILO
FILI
PCO
CLTV
MDP
PWMI
SENS
DATA
XLAT
CLOK
SCOR
SBSO
EXCK
WDCK
XTAO
VPCO
VCTL
XPCK
SQSO
SQCK
Digital
CLV
SCSY
Servo Block
SERVO
Interface
ATSK
SCLK
SSTP
MIRR
DFCT
FOK
MIRR
DFCT
FOK
SERVO DSP
FOCUS SERVO
TRACKING
SERVO
SLED SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING PWM
GENERATOR
SLED PWM
GENERATOR
FFDR
FRDR
TFDR
TRDR
SFDR
SRDR
RFDC
CE
TE
SE
FE
VC
IGEN
OPAmp
Analog SW
A/D
Converter
COUT
XRAS
LOCK
XWE
XCAS
XOE
XWRE
XRDE
Selecter
Digital
OUT
Memory Controller,
Bass Boost Block
XTSL
Servo
Auto
Sequencer
XSOE
SYSM
LRMU
LRCKI
BCKI
PCMDI
LPF
AOUT1
AIN1
LOUT1
LPF
AOUT2
AIN2
LOUT2
DAC
Shock-Proof
Memory
Controller +
Compression/
Expansion
Block Diagram
– 3 –
CXD3027R
Pin Configuration
36
35
34
31
32
33
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27 28
29
30
1
40
39
38
37
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68
67
63
64
65
66
61
62
71
72
97
96
95
94
91
92
93
100
99
98
101
102
103
104
105
106
107
108
73
74
81
82
83
84
75
76
77
78
88
87
86
85
79
80
89
90
111
109
110
112
113
114
115
116
117
118
119
120
BCK
PCMDI
V
DD
2
WFCK
C2PO
GFS
XUGF
WDCK
V
SS
2
XTSL
AV
DD
3
ASYO
ASYI
BIAS
CLTV
PCO
FILI
FILO
VCTL
VPCO
VC
FE
DOUT
XPCK
AV
SS
3
SE
A9
A8
A7
A4
XWRE
XRDE
XEMP
XWIH
XQOK
LRMU
SQSO
SQCK
SCSY
SCOR
V
SS
0
SBSO
EXCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
XSOE
R4M
A6
A5
DV
SS
ATSK
MDP
C176
V
DD1
TEST3
TEST2
TEST1
LOCK
FOK
DFCT
MIRR
COUT
V
DD0
AV
DD0
TES1
TEST
V
SS1
FRDR
FFDR
TRDR
TFDR
SRDR
SFDR
SSTP
MDS
RFDC
AV
SS0
IGEN
PWMI
CE
TE
RFAC
LRCKI
LRCK
PCMD
A1
A0
DV
DD
A10
A11
XRAS
XWE
D0
D3
D2
XCAS
XOE
AV
DD1
LOUT1
AIN1
AOUT1
AV
SS1
AV
SS2
AOUT2
AIN2
LOUT2
AV
DD2
A2
XTAI
XTAO
XV
SS
D1
XV
DD
BCKI
A3
– 4 –
CXD3027R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
O
O
O
—
O
O
O
I
I
O
O
I
O
O
I
I
O
—
O
I
I
I
I
I
I
O
I
I
I/O
O
—
1, 0
1, 0
1, 0
—
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
—
1, 0
1, 0
1, 0
—
4M-bit/16M-bit DRAM address bus 9.
4M-bit/16M-bit DRAM address bus 8.
4M-bit/16M-bit DRAM address bus 7.
DRAM interface GND
4M-bit/16M-bit DRAM address bus 6.
4M-bit/16M-bit DRAM address bus 5.
4M-bit/16M-bit DRAM address bus 4.
DRAM write enable signal.
DRAM readout enable signal.
DRAM readout prohibited signal.
DRAM write prohibited signal.
Subcode-Q OK input.
Lch, Rch "0" detection flag (AND output)
Subcode-Q 80-bit, PCM peak and level data output.
CD TEXT data output, DRAM data output.
SQSO readout clock input.
GRSCOR resynchronization input. High during track jump.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Digital GND.
Subcode P to W serial output.
SBSO readout clock input.
System reset. Reset when low.
Mute input. Muted when high.
Serial data input from CPU.
Latch input from CPU.
Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
SQSO or SENS readout clock is input by switching with the command.
SENS output to CPU.
SQSO data is output by switching with the command.
SENS serial data readout clock input.
CPU serial data output enable signal.
Anti-shock I/O.
Microcomputer clock output.
C4M is output by switching with the command.
Digital power supply.
A9
A8
A7
DVSS
A6
A5
A4
XWRE
XRDE
XEMP
XWIH
XQOK
LRMU
SQSO
SQCK
SCSY
SCOR
VSS0
SBSO
EXCK
XRST
SYSM
DATA
XLAT
CLOK
SENS
SCLK
XSOE
ATSK
R4M
VDD0
Symbol I/O Description
– 5 –
CXD3027R
Pin
No.
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
I/O
I/O
I/O
I/O
I
I/O
O
O
O
—
O
O
O
I
O
O
O
O
O
O
—
I
I
—
I
—
I
I
I
I
I
I
O
I
1, 0
1, 0
1, 0
1, 0
1, 0
—
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
—
—
—
1, Z, 0
Track count signal I/O.
Mirror signal I/O.
Defect signal I/O.
Focus OK signal I/O.
Spindle motor external control input.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low.
Or input when LKIN = 1.
Test pin.
Test pin.
Test pin.
Digital power supply.
176.4kHz output.
Spindle motor servo control output.
Spindle motor servo control output.
Disc innermost track detection signal input.
Sled drive output.
Sled drive output.
Tracking drive output.
Tracking drive output.
Focus drive output.
Focus drive output.
Digital GND.
Test pin. Normally, GND.
Test pin. Normally, GND.
Analog power supply.
Operational amplifier constant current input.
Analog GND.
RF signal input.
Center servo analog input or E input.
Tracking error signal input or F input.
Sled error signal input or B input.
Focus error signal input or A output.
Center voltage input.
Wide-band EFM PLL charge pump output.
Wide-band EFM PLL VCO2 control voltage input.
COUT
MIRR
DFCT
FOK
PWMI
LOCK
TEST1
TEST2
TEST3
VDD1
C176
MDP
MDS
SSTP
SFDR
SRDR
TFDR
TRDR
FFDR
FRDR
VSS1
TEST
TES1
AVDD0
IGEN
AVSS0
RFDC
CE
TE
SE
FE
VC
VPCO
VCTL
Symbol I/O Description
– 6 –
CXD3027R
Pin
No.
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
O
I
O
I
—
I
I
I
O
—
I
—
O
O
O
O
O
O
—
O
O
I
O
I
O
I
—
I
O
Analog
1, Z, 0
—
1, 0
—
—
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
—
1, 0
1, 0
1, 0
1, 0
—
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Multiplier VCO1 control voltage input.
Analog GND.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM full-swing output (low = VSS, high = VDD).
Analog power supply.
Crystal selection input.
Low when the crystal is 16.9344MHz; high when the crystal is 33.8688MHz.
Digital GND.
Word clock output f = 2Fs.
GRSCOR is output by switching with the command.
XUGF output.
MNT0, RFCK or SOUT is output by switching with the command.
XPCK output.
MNT1 or SOCK is output by switching with the command.
GFS output.
MNT2, XROF or XOLT is output by switching with the command.
C2PO output.
MNT3 or GTOP is output by switching with the command.
WFCK output.
Digital power supply.
Digital Out output.
D/A interface. LR clock output f = Fs.
D/A interface. LR clock input.
D/A interface. Serial data output.
(two's complement, MSB first)
D/A interface. Serial data input.
(two's complement, MSB first)
D/A interface. Bit clock output.
D/A interface. Bit clock input.
Master clock power supply.
Crystal oscillation circuit input.
The master clock is externally input from this pin.
Crystal oscillation circuit output.
FILO
FILI
PCO
CLTV
AVSS3
RFAC
BIAS
ASYI
ASYO
AVDD3
XTSL
VSS2
WDCK
XUGF
XPCK
GFS
C2PO
WFCK
VDD2
DOUT
LRCK
LRCKI
PCMD
PDMDI
BCK
BCKI
XVDD
XTAI
XTAO
Symbol I/O Description
– 7 –
CXD3027R
Pin
No.
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
—
—
O
I
O
—
—
O
I
O
—
O
O
O
O
—
O
O
O
O
I/O
I/O
I/O
I/O
O
O
—
—
—
—
—
1, 0
1, 0
1, 0
1, 0
—
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Master clock GND.
Analog power supply.
Lch LINE output.
Lch operational amplifier input.
Lch analog output.
Analog GND.
Analog GND.
Rch analog output.
Rch operational amplifier input.
Rch LINE output.
Analog power supply.
4M-bit/16M-bit DRAM address bus 3.
4M-bit/16M-bit DRAM address bus 2.
4M-bit/16M-bit DRAM address bus 1.
4M-bit/16M-bit DRAM address bus 0.
DRAM interface power supply.
16M DRAM address bus 10.
16M DRAM address bus 11.
DRAM row address strobe signal.
DRAM data input enable signal.
DRAM data bus 1.
DRAM data bus 0.
DRAM data bus 3.
DRAM data bus 2.
DRAM column address strobe signal.
DRAM data output enable signal.
XVSS
AVDD1
LOUT1
AIN1
AOUT1
AVSS1
AVSS2
AOUT2
AIN2
LOUT2
AVDD2
A3
A2
A1
A0
DVDD
A10
A11
XRAS
XWE
D1
D0
D3
D2
XCAS
XOE
Symbol I/O Description
Notes) • PCMD is a MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before
sync protection.
• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM
signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XROF is generated when the 32K RAM exceeds the ±28F jitter margin.
• C4M is a 4.2336MHz output that changes in CAV-W mode and variable pitch mode.
• FSTO is the 2/3 frequency-division output of the XTAI pin.
• SOUT is the serial data output inside the servo block.
• SOCK is the serial data readout clock output inside the servo block.
• XOLT is the serial data latch output inside the servo block.
– 8 –
CXD3027R
Monitor Pin Output Combinations
Command bit
Output data
SRO1
MTSL1
MTSL0
XUGF
XPCK
GFS
C2PO
MNT0
MNT1
MNT2
MNT3
RFCK
XPCK
XROF
GTOP
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
C4M
FSTO
GFS
C2PO
SOUT
SOCK
XOLT
C2PO
– 9 –
CXD3027R
Electrical Characteristics
1. DC Characteristics (VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Input voltage
(1)
Input voltage
(2)
Input voltage
(3)
Output voltage
(1)
Output voltage
(2)
∗1, ∗2
,
∗3, ∗4, ∗12
∗
5
∗6, ∗7
∗2, ∗4, ∗8
,
∗9, ∗11, ∗12
Input leak current (1)
Input leak current (2)
Tri-state output leak current
∗3, ∗4, ∗5
,
∗6
∗7
∗9
∗10
Schmitt input
Analog input
IOH = –4mA
IOL = 4mA
IOH = –0.28mA
IOL = 0.36mA
VIN = 0 to VDD
VIN = 0.25VDD
to 0.75VDD
VO = 0 to 3.6V
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
Input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
VIH (1)
VIL (1)
VIH (2)
VIL (2)
VIN (3)
VOH (1)
VOL (1)
VOH (2)
VOL(2)
ILI (1)
ILI (2)
ILO
0.7VDD
0.8VDD
Vss
VDD – 0.4
0
VDD – 0.5
0
–10
–40
–5
0.2VDD
0.2VDD
VDD
VDD
0.4
VDD
0.4
10
40
5
V
V
V
V
V
V
V
V
V
µA
µA
µA
Conditions Min.
Typ.
Max.
Unit
Applicable
pins
Applicable pins
∗1
TEST, TES1
∗2
COUT, MIRR, DFCT, FOK, LOCK
∗3
XQOK, SCSY, SYSM, DATA, PCMDI, XWRE, XSOE, XRDE, XTSL, SSTP
∗4
ATSK, PWMI, SSTP
∗5
SQCK, EXCK, XRST, CLOK, SCLK, BCKI, LRCKI, XLAT
∗6
VCTL, FILI, CLTV, ASYI, IGEN, BIAS
∗7
CE, TE, SE, FE, VC
∗8
XEMP, XWIH, SQSO, SBSO, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, WDCK, SFDR, SRDR, TFDR,
TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, R4M, C176
∗9
SENS, MDP, VPCO, PCO, MDS
∗10
FILO
∗11
A0, A11, XRAS, XWE, XCAS, XOE
∗12
D0 to D3
– 10 –
CXD3027R
2. AC Characteristics
(1) XTAI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)
(b) When inputting pulses to XTAI pin
(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)
(c) When inputting sine waves to XTAI pin via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)
Oscillation
frequency
fMAX 7 34
MHz
Item Symbol Min. Typ. Max. Unit
High level pulse
width
tWHX
13 500
ns
Low level pulse
width
tWLX
13 500
ns
Pulse cycle
tCX
26 1000
ns
Input high level VIHX 0.7VDD
V
Input low level VILX 0.2VDD
V
Rise time,
fall time
tR, tF
10
ns
Item
Symbol Min. Typ. Max. Unit
Input amplitude
VI 0.5VDD VDD + 0.3 Vp-p
Item Symbol Min. Typ. Max. Unit
tR tF
tWHX
tWLX
tCX
VILX
VIHX × 0.1
V
IHX × 0.9
V
IHX
XTAI
V
DD/2
– 11 –
CXD3027R
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width
COUT frequency (during input)
∗
COUT pulse width (during input)
∗
fCK
tWCK
tSU
tH
tD
tWL
fT
tWT
fT
tWT
750
300
300
300
750
750
7.5
0.65
0.65
65
MHz
ns
ns
ns
ns
ns
MHz
ns
kHz
µs
Item
Symbol Min.
Typ. Max. Unit
tWCK tWCK
1/fCK
tH
tSU
tWL
tD
1/fT
tWT
tWT
tH
tSU
CLOK
DATA
XLAT
EXCK
SQCK
COUT
SBSO
SQSO
∗
Only when $44 and $45 are executed.
– 12 –
CXD3027R
(3) SCLK pin
SCLK frequency
SCLK pulse width
Delay time
fSCLK
tSPW
tDLS
31.3
15
16 MHz
ns
µs
Item
Symbol
Min. Typ.
Max. Unit
tSPWtDLS
1/fSCLK
MSB LSB
...
...
XLAT
SCLK
Serial Read Out Data
(SENS)
(4) COUT, MIRR and DFCT pins
Operating frequency (VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)
COUT maximum
operating frequency
MIRR maximum
operating frequency
DFCT maximum
operating frequency
fCOUT
fMIRR
fDFCTH
40
40
5
kHz
kHz
kHz
∗1
∗2
∗3
Signal
Symbol Min. Typ. Max.
Unit
Conditions
∗1
When using a high-speed traverse TZC.
∗2
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.11VDD to 0.23VDD
• ≤ 25%
∗3
During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
A
B
B
A + B
Fs = 44.1kHz in all cases.
The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.
– 13 –
CXD3027R
1-bit DAC and LPF Block Analog Characteristics (VDD = AVDD = 3.3V, VSS = AVSS = 0V, Ta = 25°C)
Item
Total harmonic
distortion
Signal-to-noise
ratio
Symbol
THD
S/N
Conditions
1kHz, 0dB data
Crystal
1kHz, 0dB data, AMUT ON
(Using A-weighting filter)
384Fs
768Fs
384Fs
768Fs
96
96
0.0120
0.0120
100
100
0.0140
0.0140
Min.
Typ.
Max.
Unit
%
dB
Audio Analyzer
SHIBASOKU (AM51A)
100k
22µF
330pF
27k
27k
27k
68pF
AOUT1 (2)
AIN1 (2)
LOUT1 (2)
Audio Analyzer
CXD3027R
Rch A
Lch B
DATA RF
TEST DISC
768Fs/384Fs
(VDD = AVDD = 3.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)
VOUT
RL
∗1
∗1
Vrms
kΩ
Symbol
20
Min.
Max.
0.64
Typ.
Applicable pinsUnit
Output voltage
Load resistance
Item
∗
Measurement is conducted for the above circuit diagrams with the sine wave output of 1kHz and 0dB.
Applicable pins
∗1
LOUT1, LOUT2
Block diagram of analog characteristics measurement
LPF external circuit diagram
– 14 –
CXD3027R
Contents
[1] CPU Interface
§1-1. CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
§1-2. CPU Interface Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
§1-3. CPU Command Presets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
§1-4. Description of SENS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
§1-5. Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
[2] Subcode Interface
§2-1. P to W Subcode Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
§2-2. 80-bit Subcode-Q Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
[3] Description of Modes
§3-1. CLV-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
§3-2. CLV-W Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
§3-3. CAV-W Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
§3-4. VCO-C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
[4] Description of Other Functions
§4-1. Channel Clock Recovery by Digital PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
§4-2. Frame Sync Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
§4-3. Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
§4-4. DA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
§4-5. Digital Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
§4-6. Servo Auto Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
§4-7. Digital CLV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
§4-8. CD-DSP Block Playback Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
§4-9. Description of DAC Block and Shock-Proof Memory Controller Block Circuits . . . . . . . . . . . . . . 121
§4-10. DAC Block Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
§4-11. Description of DAC Block Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
§4-12. LPF Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
§4-13. Description of Shock-Proof Memory Controller Block Functions . . . . . . . . . . . . . . . . . . . . . . . . . 129
§4-14. CPU to DRAM Access Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
§4-15. Asymmetry Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
§4-16. CD TEXT Data Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
[5] Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of Servo Signal Processing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
§5-2. Digital Servo Block Master Clock (MCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
§5-3. DC Offset Cancel [AVRG Measurement and Compensation] . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
§5-4. E:F Balance Adjustment Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
§5-5. FCS Bias Adjustment Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
§5-6. AGCNTL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
§5-7. FCS Servo and FCS Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
§5-8. TRK and SLD Servo Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
§5-9. MIRR and DFCT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
§5-10. DFCT Countermeasure Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
§5-11. Anti-Shock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
§5-12. Brake Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
§5-13. COUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
§5-14. Serial Readout Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
§5-15. Writing to Coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
§5-16. PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
§5-17. Servo Status Changes Produced by LOCK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
§5-18. Description of Commands and Data Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
§5-19. List of Servo Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
§5-20. Filter Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
§5-21. TRACKING and FOCUS Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
[6] Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Explanation of abbreviations
AVRG: Average
AGCNTL: Auto gain control
FCS: Focus
TRK: Tracking
SLD: Sled
DFCT: Defect
– 15 –
CXD3027R
[1] CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
• The internal registers are initialized by a reset when XRST = 0.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
8
9
A
B
C
D
E
8 bits
8 to 24 bits
16 bits
20 bits
32 bits
32 bits
28 bits
28 bits
28 bits
28 bits
20 bits
Total bit length
750ns or more
D18 D19 D20 D21 D22 D23
750ns or more
Valid
CLOK
DATA
XLAT
Registers
D0 D1
– 16 –
CXD3027R
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SEACH
VOLTAGE UP
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN
NORMAL
TRACKING GAIN UP
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
FILTER SELECT 2
1
1
0
0
0
0
1
0
—
—
—
—
—
—
0
1
—
—
—
—
0
—
1
0
—
—
—
—
—
—
0
1
1
1
—
—
—
—
0
1
—
—
—
—
—
—
0
1
—
—
—
—
—
—
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0 0 0 0
0 0 0 1
FOCUS
CONTROL
TRACKING
CONTROL
Regis-
ter
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Command Table ($0X to 1X)
—: don’t care
– 17 –
CXD3027R
TRACKING SERVO OFF
TRACKING SERVO ON
FORWARD TRACK JUMP
REVERSE TRACK JUMP
SLED SERVO OFF
SLED SERVO ON
FORWARD SLED MOVE
REVERSE SLED MOVE
SLED KICK LEVEL
(±1 × basic value) (default)
SLED KICK LEVEL
(±2 × basic value)
SLED KICK LEVEL
(±3 × basic value)
SLED KICK LEVEL
(±4 × basic value)
0
0
1
1
—
—
—
—
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
0
0
1
1
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
0 0 1 0
0 0 1 1
TRACKING
MODE
SELECT
Regis-
ter
Command
Address
D23 to D20
Regis-
ter
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
—: don’t care
Command Table ($2X to 3X)
– 18 –
CXD3027R
KRAM DATA (K00)
SLED INPUT GAIN
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 0SELECT
Regis-
ter
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($340X)
– 19 –
CXD3027R
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K18)
FIX
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 1SELECT
Regis-
ter
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($341X)
– 20 –
CXD3027R
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 0SELECT
Regis-
ter
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($342X)
– 21 –
CXD3027R
KRAM DATA (K30)
SLED INPUT GAIN (when TGup2 is accessed with
SFSK = 1)
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K32)
NOT USED
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 1SELECT
Regis-
ter
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($343X)
– 22 –
CXD3027R
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K46)
TRACKING HOLD INPUT GAIN (when TGup2 is
accessed with THSK = 1)
KRAM DATA (K47)
NOT USED
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1
0 1 0 0 0 1 0 0
SELECT
Regis-
ter
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
Command Table ($344X)
– 23 –
CXD3027R
PGFS, PFOK, RFAC
DOUT
Booster Surf Brake
Booster
DFCT
FCS Bias Limit
FCS Bias Data
Traverse Center Data
3
1
1
1
1
1
1
0
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
0
1
PGFS1
A/D
SEL
SFBK1
THBON
IDFS3
1
0
0
PGFS0
COPY
EN
SFBK2
FHBON
IDFS2
0
1
0
PFOK1
EMPH
D
0
TLB10N
IDFS1
FBL9
FB9
TV9
PFOK0
CAT
b8
0
FLB1ON
IDFS0
FBL8
FB8
TV8
0
DOUT
EN1
0
TLB2ON
0
FBL7
FB7
TV7
0
DOUT
DMUT
0
0
0
FBL6
FB6
TV6
0
DOUT
WOD
0
HBST1
IDFT1
FBL5
FB5
TV5
MRS
WIN
EN
0
HBST0
IDFT0
FBL4
FB4
TV4
MRT1
DOUT
EN2
0
LB1S1
0
FBL3
FB3
TV3
MRT0
0
0
LB1S0
0
FBL2
FB2
TV2
0
0
0
LB2S1
0
FBL1
FB1
TV1
0
0
0
LB2S0
INVRFDC
—
—
TV0
SELECT
Regis-
ter
Command
Address 1 Address 2
D23 to D20
Address 3
D15
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0
D3 D2
Data 3Data 2Data 1Address 3
D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
Command Table ($348X to 3FX)
0 0 1 1
D19 to D16
0 1 0 0
– 24 –
CXD3027R
FCS search, AGF
TRK jump, AGT
FZC, AGC, SLD move
DC measure, cancel
Serial data read out
FCS Bias, Gain,
Surf jump/brake
Mirr, DFCT, FOK
TZC, COUT, Bottom,
MIRR
SLD filter
Filter
Clock, others
3
FT1
0
FZSH
VCLM
DAC
0
SFO2
COSS
SFID
F1NM
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
FT0
DTZC
FZSL
VCLC
SD6
FBON
SFO1
COTS
SFSK
F1DM
AGG4
FS5
TJ5
SM5
FLM
SD5
FBSS
SDF2
CETZ
THID
F3NM
XT4D
FS4
TJ4
SM4
FLC0
SD4
FBUP
SDF1
CETF
THSK
F3UM
XT2D
FS3
TJ3
SM3
RFLM
SD3
FBV1
MAX2
COT2
ABEF
TINM
0
FS2
TJ2
SM2
RFLC
SD2
FBV0
MAX1
COT1
TLD2
TIUM
DRR2
FS1
TJ1
SM1
AGF
SD1FIFZC
SFOX
MOT2
TLD1
T3NM
DRR1
FS0
TJ0
SM0
AGT
SD0
TJD0
BTF
0
TLD0
T3DM
DRR0
FTZ
SFJP
AGS
DFSW
0
FPS1
D2V2
BTS1
0
DFIS
0
FG6
TG6
AGJ
LKSW
0
FPS0
D2V1
BTS0
0
TLCD
ASFG
FG5
TG5
AGGF
TBLM
0
TPS1
D1V2
MRC1
0
0
FTQ
FG4
TG4
AGGT
TCLM
0
TPS0
D1V1
MRC0
0
LKIN
LPAS
FG3
TG3
AGV1
FLC1
0
SVDA
RINT
0
0
COIN
SRO1
FG2
TG2
AGV2
TLC2
0
SJHD
0
0
0
MDFI
0
FG1
TG1
AGHS
TLC1
0
INBK
0
0
0
MIRI
AGHF
FG0
TG0
AGHT
TLC0
0
MTI0
0
0
0
XT1D
ASOT
SELECT
Regis-
ter
Command
Address 1 Address 2
D23 to D20
D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
0 0 1 1
Command Table ($34FX to 3FX) cont.
Address 2
D19
1
1 1 1
1
1
1
1
0
0
0
1
0
0
1
0
0
1
1
0
SYG3
0
0
0
SYG2
0
0
0
SYG1
0
0
0
SYG1
1
0
1
FI
FZB3
0
0
0
FI
FZB2
0
0
0
FI
FZB1
0
0
0
FI
FZB0
0
0
0
FI
FZA3
0
0
1
FI
FZA2
0
0
0
FI
FZA1
0
0
0
FI
FZA0
0
0
0
System GAIN
D18 D17 D16
Address 3
D15 D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
– 25 –
CXD3027R
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence (N)
track jump count
setting
MODE
specification
Function
specification
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
AS3
TR3
SD3
32768
CD-
ROM
1
AS2
TR2
SD2
16384
DOUT
Mute
DSPB
AS1
TR1
SD1
8192
DOUT
Mute-F
ASEQ
AS0
TR0
SD0
4096
WSEL
1
MT3
0
KF3
2048
VCO
SEL1
BiliGL
MAIN
MT2
0
KF2
1024
ASHS
BiliGL
SUB
MT1
0
KF1
512
SOCT0
FLFC
MT0
0
KF0
256
VCO
SEL2
0
LSSL
0
0
128
KSL3
0
0
0
0
64
KSL2
0
0
0
0
32
KSL1
SYCOF
0
0
0
16
KSL0
0
—
—
—
8
VCO1
CS1
1
—
—
—
4
VCO1
CS0
0
—
—
—
2
0
0
—
—
—
1
VCO2
CS
1
4
5
6
7
8
9
Regis-
ter
Command
Address
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Data 1 Data 2 Data 3 Data 4
Command Table ($4X to EX)
—: don’t care
– 26 –
CXD3027R
Audio CTRL
Signal select
Bass boost
Shock-proof
memory setting
Shock-proof
memory control
DOUT subcode-Q
setting
DRAM I/F
Compression
setting
EFM playability
enhancement settin
g
Sync expansion
specification
Sleep setting
Variable pitch
setting
Spindle servo
setting
1 0 1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
1
Mute
0
0
1
1
0
0
1
1
0
0
1
1
ATT
0
1
0
1
0
1
0
1
0
1
0
1
PCT1
RSL1
0
0
1
1
0
SL
XQOK
XQOK
SubQA3
1
1
ADPON
ARDTEN
AVW
ADCPS
VARI
ON
SYG3
EA
PCT2
RSL0
0
1
0
1
0
SL
XWRE
XWRE
SubQA2
1
1
BITSL1
1
0
DSP
SLEEP
VARI
USE
SYG2
EA
0
0
1
PWDN
BBON1
COMP
ON
0
GTOP
CHECK
XRDE
SubQA1
1
1
BITSL0
1
SFP5
DSSP
SLEEP
0
SYG1
EA
SOC2
0
ZMUTA
ZDPL
BBON0
0
1
NOLIM
WDCK
XSOEO
SubQA0
0
1
0
1
SFP4
ASYM
SLEEP
0
SYG0
EA
0
DTSL1
SMUT
XWOC
HBON1
0
0
SPSL
COM
XSOEO2
0
1
DADR19
0
1
SFP3
ESP
SLEEP
MDP
OUTSL1
0
DTSL0
AD10
DAC
EMPH
HBON0
0
0
READ2
0
0
DRWR
DADR18
0
0
SFP2
LPF
SLEEP
MDP
OUTSL0
0
MCSL1
AD9
HiCut
FILTER
BBSL1
0
0
REFSEL
0
0
DRADR
DADR17
0
1
SFP1
DSUB
SLEEP
LPWR2
0
MCSL0
AD8
BST
CL
BBSL0
0
0
REFON
SDTO
OUT
0
0
DADR16
0
0
SFP0
0
0
0
0
AD7
1
HBSL1
0
0
0
SubQD7
DRD15
DADR15
0
0
0
MDS
CTL
1
SDSL2
AD6
0
HBSL0
0
0
MSL2
SubQD6
DRD14
DADR14
GRSEL
0
0
MDP
UP
0
SDSL1
AD5
OBIT1
BBST
Vdwn1
1
0
MSL1
SubQD5
DRD13
DADR13
0
1
0
0
0
SDSL0
AD4
OBIT0
BBST
Vdwn0
0
0
MSL0
SubQD4
DRD12
DADR12
0
0
0
MDP
CTL4
A
Regis-
ter
Command
Address
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Data 1 Data 2 Data 3 Data 4
Command Table ($4X to EX) cont.
– 27 –
CXD3027R
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
0
32768
Gain
MDP1
0
CM3
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
16384
Gain
MDP0
TB
CM2
8192
Gain
MDS1
TP
CM1
4096
Gain
MDS0
CLVS
Gain
CM0
2048
Gain
DCLV1
VP7
EPWM
1024
Gain
DCLV0
VP6
SPD
512
PCC1
VP5
ICAP
256
PCC0
VP4
SFSL
128
SFP3
VP3
VC2C
64
SFP2
VP2
HIFC
32
SFP1
VP1
LPWR
16
SFP0
VP0
VPON
8
SRP3
VP
CTL1
Gain
CAV1
4
SRP2
VP
CTL0
Gain
CAV0
2
SPR1
0
0
1
SRP0
0
INV
VPCO
B
C
D
E
Regis-
ter
Command
Address
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Data 1 Data 2 Data 3 Data 4
Command Table ($4X to EX) cont.
– 28 –
CXD3027R
—: don’t care
MODE
specification
Function
specification
AUDIO CTRL
Signal select
Bass boost
DOUT subcode-Q
setting
DRAM I/F
EFM playability
enhancement setting
Spindle servo
setting
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
8
9
A
B
C
D
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 0
0 0 ∗ ∗
0 1 0 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 1
1 1 1 1
0 0 0 0
0 1 ∗ ∗
1 0 ∗ ∗
1 1 ∗ ∗
∗ ∗ ∗ ∗
1 1 1 0
1 1 1 1
0 0 0 0
ERC4
0
0
EN
XSOE
AD3
0
BBST
Vup1
0
0
SubQD3
DRD11
DADR11
1
MDP
CTL3
0
EDC7
0
SCOR
SEL
0
0
CKOUT
SL2
AD2
1
BBST
Vup0
0
0
SubQD2
DRD10
DADR10
0
MDP
CTL2
0
EDC6
0
SCSY
0
0
CKOUT
SL1
AD1
0
BBST
Uth
0
0
SubQD1
DRD9
DADR9
0
MDP
CTL1
MTSL1
EDC5
0
SOCT1
0
0
SLD
BBIN
AD0
0
BBST
Lth
PDM
INV
0
SubQD0
DRD8
DADR8
0
MDP
CTL0
MTSL0
EDC4
0
TXON
0
0
0
DRD7
DADR7
0
ASYE
EDC3
0
TXOUT
0
0
0
DRD6
DADR6
0
MD2
EDC2
0
OUTL1
0
0
0
DRD5
DADR5
0
0
EDC1
0
OUTL0
0
0
0
DRD4
DADR4
0
0
EDC0
0
0
DIV4
—
DRD3
DADR3
1
—
—
0
0
—
DRD2
DADR2
0
—
—
OUTL2
0
—
DRD1
DADR1
0
—
—
0
0
—
DRD0
DADR0
0
—
—
Regis-
ter
Command
Address Data 1 Data 2 Data 3 Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1
D0
Data 5 Data 6 Data 7
Command Table ($4X to EX) cont.
– 29 –
CXD3027R
FOCUS SERVO OFF,
0V OUT
TRACKING GAIN UP
FILTER SELECT 1
TRACKING SERVO OFF
SLED SERVO OFF
SLED KICK LEVEL
(±1 × basic value) (default)
KRAM DATA
($3400XX to $344fXX)
0
0
0
0
0
0
0
0
0
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
2
0 0 0 0
0 0 0 1
0 0 1 0
FOCUS
CONTROL
TRACKING
CONTROL
TRACKING
MODE
Regis-
ter
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Regis-
ter
Command
3 SELECT
Address
D23 to D20
0 0 1 1
0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table".
0 0 0 0 — — — — — — — — — — — — — — — —
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D0 D0
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Address 3
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D0 D0
§1-3. CPU Command Presets
Command Preset Table ($0X to 34X)
—: don’t care
– 30 –
CXD3027R
Command Preset Table ($348X to 34FX)
PGFS, PFOK, RFAC
CAV control
DOUT
Booster Surf Brake
Booster
Servo DAC output
DFCT
FCS Bias Limit
FCS Bias Data
Traverse Center Data
3
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
0
SELECT
Regis-
ter
Command
Address 1
Address 2
D23 to D20
Address 3
D15
D15 D14 D13 D12
D11
D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2
Data 3Data 2Data 1Address 3
D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
0 0 1 1
D19 to D16
0 1 0 0
—: don’t care
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