Sony CXD3021R Datasheet
CD Digital Signal Processor with Built-in Digital Servo and DAC
Description
The CXD3021R is a digital signal processor LSI for
CD players. This LSI incorporates a digital servo,
digital filter and 1-bit DAC.
Features
• All digital signal processing during playback is
performed with a single chip
• Highly integrated mounting possible due to a built-
in RAM
Digital Signal Processor (DSP) Block
• Playback mode supporting CAV (Constant Angular
Velocity)
• Frame jitter free
• 0.5× to 32× continuous playback possible with a
low external clock
• Allows relative rotational velocity readout
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports 1× to 32× playback by switching the
built-in VCO
• The bit clock, which strobes the EFM signal, is
generated by the digital PLL.
• Digital PLL master clock can be set to 2/3 the
conventional one.
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• Refined super strategy-based powerful error
correction
C1: double correction, C2: quadruple correction
Supported during 32× playback
• Noise reduction during track jumps
• Auto zero-cross mute
• Subcode demodulation and Sub-Q data error
detection
• Digital CLV spindle servo (built-in oversampling filter)
• 16-bit traverse counter
• Asymmetry correction circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Fine search performs track jumps with high
accuracy
• Digital audio interface outputs
• Digital level meter, peak meter
• Bilingual compatible
• VCO control mode
• Digital Out can be generated from the audio serial
inputs.
• Supports three types of DA interface
(48 bits/64 bits/32 bits)
• DSP, servo and DAC blocks support sleep mode.
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment function
• Surf jump and surf brake functions supporting micro
two-axis
• Tracking filter: 6 stages
Focus filter: 5 stages
• Servo drive DAC output possible
Digital Filter and DAC Blocks
• Digital de-emphasis
• Digital attenuation
• 8fs oversampling filter
• Adoption of a tertiary ∆∑ noise shaper
• Supports double-speed playback
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD –0.3 to +4.4 V
• Input voltage VI –0.3 to +4.4 V
(VSS – 0.3 to VDD + 0.3) V
• Output voltage VO –0.3 to +4.4 V
• Storage temperature Tstg –40 to +125 °C
•
Supply voltage difference VSS – AVSS
–0.3 to +0.3 V
VDD – AVDD
–0.3 to +0.3 V
Recommended Operating Conditions
• Supply voltage VDD
∗
3.0 to 4.0 V
• Operating temperature Topr –20 to +75 °C
∗
The VDD (min.) for the CXD3021R varies according
to the playback speed and built-in VCO selection.
The VDD (min.) for the CXD3021R under various
conditions are as shown on the following page.
– 1 –
E98209A9Z-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXD3021R
120 pin LQFP (Plastic)
For the availability of this product, please contact the sales office.
– 2 –
CXD3021R
The Maximum Operating Speed graph shows the playback speed VDD (min.) at various temperatures.
The playback conditions are that the high-speed VCO1 selects No.4 and VCO2 selects high speed in CAV-W
mode with DSPB = 1.
Maximum Operating Speed
+25°C
+55°C
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0
27
28
29
30
31
32
33
34
35
36
[V]
[Multiple]
+75°C
– 3 –
CXD3021R
Block Diagram
Noise
Shaper
Peak
detector
32K RAM
Serial/parallel
processor
Digital PLL
Vari-Pitch
double
speed
18-times
oversampling
filter
Subcode
P to W
processor
Timing
Generator1
Subcode Q
processor
Servo
auto
sequencer
CPU interface
8Fs Digital Filter
+
1 bit DAC
EFM
Demodulator
Sync
protector
Priority
encoder
D/A data
processor
Digital out
Register
Address
generator
8
XTLO
XTLI
VPCO1
RMUTO
VPCO2
XTSL
DAC Block
Signal Processor Block
MCKO
V16M
FSTIO
C4M
C16M
VCTL
PDO
VCOI
VCOO
PCO
FILI
FILO
CLTV
RFAC
ASYI
ASYO
ASYE
WFCK
SCOR
MON
FSW
MDP
MDS
SQCK
SQSO
PWMI
VCKI
OSC
TEST
PWMLN
PWMRP
PSSL
DA011
to DA1
MUTE
PWMLP
PWMRN
31 to 35,
37 to 42
SENS
DATA
CLOK
XLAT
DOUT
MD2
DA16 (48PCM)
DA15 (48BCK)
DA14 (64PCM)
DA13 (64BCK)
DA12 (64LRCK)
Servo Block
AV
DD
6
AV
DD
1
AV
DD
2
AV
DD
3
AV
DD
4
AV
DD
5
DV
SS
5
AV
SS
1
AV
SS
2
AV
SS
3
AV
SS
4
BSSD
DV
DD
5
AV
SS
5
AV
SS
6
MIRR
Servo
Interface
DFCT
FOK
DV
SS
4
DV
SS
3
DV
SS
2
DV
SS
1
DV
DD
4
DV
DD
3
DV
DD
2
DV
DD
1
DAC
FOCUS
TRACKING
SLED
OpAmp
FAO
TAO
SAO
SERVO DSP
FOCUS SERVO
TRACKING SERVO
SLED SERVO
COUT
MIRR
DFCT
FOK
OpAmp
AnaSw
A/D
CONVERTER
RFDC
TE
SE
FE
VC
CE
ADIO
TES2
TES3
XRST
PCMDI
BCKI
LRCKI
EXCK
SBSO
LMUTO
DTS0
XWO
MUX
∗
Error
corrector
Error Rate
counter
Clock
Generator
∗ : Asymmetry Correction
36
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
60
70
69
68
67
63
64
65
66
61
62
71
72
97
96
95
94
91
92
93
99
98
102
103
104
105
106
107
108
73
74
81
82
83
84
75
7677
78
88
87
86
85
90
111
109
110
112
113
114
116
117
118
119
120
Timing
Generator2
CLV processor
– 4 –
CXD3021R
Pin Configuration
36
35
34
31
32
33
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17
18
19
20
21
22
23
24
25
26
27 28
29
30
1
40
39
38
37
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
69
68 67
63
64
65
66
61
62
71
72
97
96
95
94
91
92
93
100
99
98
101
102
103
104
105
106
107
108
73
74
81
82
83
84
75
76
77
78
88
87
86
85
79
80
89
90
111
109
110
112
113
114
115
116
117
118
119
120
C16M
C4M
FSTIO
MCKO
XTSL
DV
SS2
DA01
DA03
DA04
DA05
DA06
DV
DD2
DA07
DA08
DA09
DA10
DA11
EXCK
SBSO
SCOR
WFCK
MUTE
DOUT
MD2
DV
DD3
XRST
SCSY
SQCK
SQSO
DA02
FSW
FOK
DFCT
MIRR
COUT
CLOK
XLAT
LMUTO
DATA
ATSK
SCLK
SENS
DV
DD
4
AV
DD
3
AV
SS
3
AV
SS
5
XTLI
XTLO
AV
DD
5
AV
DD
4
PWMRN
AV
SS
4
DV
SS
3
XWO
TESO
DV
SS
4
PWMRP
BSSD
AV
DD6
MON
MDP
MDS
LOCK
SSTP
DV
SS5
TES2
TES3
DV
DD5
VCOO
VCOI
TEST
PDO
VCKI
V16M
AV
DD2
IGEN
AV
SS2
ADIO
RFDC
CE
TE
FAO
SE
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AV
SS
1
RFAC
BIAS
ASYI
ASYO
AV
DD
1
DV
DD
1
DV
SS
1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
DA13
DA12
VC
VPCO1
FE
DA14
BCKI
TAO
SAO
AV
SS6
RMUTO
DTS0
PWMI
PWMLN
PWMLP
– 5 –
CXD3021R
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I
I
I
O
O
I
O
I
O
I
I
I
I
O
I
I
O
O
I
O
I
O
I
O
O
O
O
O
O
1, Z, 0
1, Z, 0
Analog
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
Sled error signal input.
Focus error signal input.
Center voltage input.
Wide-band EFM PLL VCO2 charge pump output.
Wide-band EFM PLL VCO2 charge pump output 2. Turned on and off by $EX
command FCSW.
Wide-band EFM PLL VCO2 control voltage input.
Master PLL filter output (slave = digital PLL).
Master PLL filter input.
Master PLL charge pump output.
Multiplier VCO control voltage input.
Analog GND.
EFM signal input.
Asymmetry circuit constant current input.
Asymmetry comparator voltage input.
EFM full-swing output (low = VSS, high = VDD).
Analog power supply.
Digital power supply.
Digital GND.
Asymmetry circuit on/off (low = off, high = on).
Audio data output mode switching input (low: serial, high: parallel).
D/A interface for 48-bit slot. Word clock f = 2Fs.
D/A interface for 48-bit slot. LR clock f = Fs.
LR clock input to DAC (48-bit slot).
DA16 (MSB) output when PSSL = 1, 48-bit slot serial data output (two's
complement, MSB first) when PSSL = 0.
Audio data input to DAC (48-bit slot).
DA15 output when PSSL = 1, 48-bit slot bit clock output when PSSL = 0.
Bit clock input to DAC (48-bit slot).
DA14 output when PSSL = 1, 32-bit/64-bit slot serial data output (two'
complement, LSB first) when PSSL = 0.
DA13 output when PSSL = 1, 32-bit/64-bit slot bit clock output when PSSL = 0.
DA12 output when PSSL = 1, 32-bit/64-bit slot LR clock output when PSSL = 0.
DA11 output when PSSL = 1, GTOP output when PSSL = 0.
DA10 output when PSSL = 1, XUGF output when PSSL = 0.
DA09 output when PSSL = 1, XPLCK output when PSSL = 0.
SE
FE
VC
VPCO1
VPCO2
VCTL
FILO
FILI
PCO
CLTV
AVSS1
RFAC
BIAS
ASYI
ASYO
AVDD1
DVDD1
DVSS1
ASYE
PSSL
WDCK
LRCK
LRCKI
DA16
PCMDI
DA15
BCKI
DA14
DA13
DA12
DA11
DA10
DA09
Symbol I/O
Description
– 6 –
CXD3021R
Pin
No.
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
O
O
O
O
O
O
O
O
I
O
I/O
O
O
I
O
I
O
O
O
I
O
I
I
I
I
O
O
O
O
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, Z, 0
DA08 output when PSSL = 1, GFS output when PSSL = 0.
DA07 output when PSSL = 1, RFCK output when PSSL = 0.
Digital power supply.
DA06 output when PSSL = 1, C2PO output when PSSL = 0.
DA05 output when PSSL = 1, XRAOF output when PSSL = 0.
DA04 output when PSSL = 1, MNT3 output when PSSL = 0.
DA03 output when PSSL = 1, MNT2 output when PSSL = 0.
DA02 output when PSSL = 1, MNT1 output when PSSL = 0.
DA01 output when PSSL = 1, MNT0 output when PSSL = 0.
Digital GND.
Crystal selection input.
Clock output. Inverted output of XTLI.
Digital servo clock input/output.
(2/3 frequency division for XTLI pin is internally connected.)
1/4 frequency division output for XTLI pin. Changes with variable pitch.
16.9344MHz output. Changes simultaneously with variable pitch.
Digital power supply.
Digital Out on/off control (low = off, high = on).
Digital Out output.
Mute (low: off, high: on).
WFCK (Write Frame Clock) output.
Outputs a high signal when either subcode sync S0 or S1 is detected.
Sub P to W serial output.
SBSO readout clock input.
Sub-Q 80-bit, PCM peak and level data 16-bit outputs.
SQSO readout clock input.
GRSCOR resynchronization input. Normally low, resynchronization is
executed when high.
System reset. Reset when low.
Audio DAC sync window open input. Normally high, window open when low.
Audio DAC right channel zero detection flag.
Audio DAC left channel zero detection flag.
Digital GND.
Analog GND.
Audio DAC PWM output. Right channel, reversed phase.
Audio DAC PWM output. Right channel, forward phase.
DA08
DA07
DVDD2
DA06
DA05
DA04
DA03
DA02
DA01
DVSS2
XTSL
MCKO
FSTIO
C4M
C16M
DVDD3
MD2
DOUT
MUTE
WFCK
SCOR
SBSO
EXCK
SQSO
SQCK
SCSY
XRST
XWO
RMUTO
LMUTO
DVSS3
AVSS4
PWMRN
PWMRP
Symbol
I/O
Description
– 7 –
CXD3021R
Pin
No.
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
O
I
O
O
O
I
I
I
I
I
I/O
I/O
I/O
I/O
O
O
O
O
O
I
O
O
O
I/O
1, 0
1, Z, 0
1, Z, 0
1, Z, 0
1, 0
1, 0
1, 0
1, 0
1, Z, 0
1, 0
1, Z, 0
1, Z, 0
1, 0
Analog power supply.
Master clock power supply.
Master clock crystal oscillation circuit output.
Master clock crystal oscillation circuit input.
Master clock GND.
Analog GND.
Audio DAC PWM output. Left channel, forward phase.
Audio DAC PWM output. Left channel, reversed phase.
Analog power supply.
Digital power supply.
SENS output to CPU.
SENS serial data readout clock input. Set to high when not used.
Anti-shock pin. Set to low when not used.
Serial data input from CPU.
Latch input from CPU. Serial data is latched at the falling edge.
Serial data transfer clock input from CPU.
Digital GND.
Track count signal I/O.
Mirror signal I/O.
Defect signal I/O.
Focus OK signal I/O.
Test pin. Leave this open.
Spindle motor output filter switching output.
GRSCOR output when $8 command SCOR SEL = high.
Analog GND.
Sled filter DAC analog output.
Tracking filter DAC analog output.
Focus filter DAC analog output.
Constant current input for servo filter DAC analog output.
Analog power supply.
Spindle motor on/off control output.
Spindle motor servo control output.
Spindle motor servo control output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal.
If GFS is low eight consecutive samples, this pin outputs low. Input when
LKIN = high. (See $3E.)
AVDD4
AVDD5
XTLO
XTLI
AVSS5
AVSS3
PWMLP
PWMLN
AVDD3
DVDD4
SENS
SCLK
ATSK
DATA
XLAT
CLOK
DVSS4
COUT
MIRR
DFCT
FOK
TESO
FSW
AVSS6
SAO
TAO
FAO
BSSD
AVDD6
MON
MDP
MDS
LOCK
Symbol
I/O
Description
– 8 –
CXD3021R
Notes) • The 32-bit/64-bit slot is a LSB first, two's complement output. The 48-bit slot is a MSB first, two's
complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync
protection.
• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion protection timing match. (See $348.)
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)
• C2PO represents the data error status.
• XRAOF is generated when the 32K RAM exceeds the ±28F jitter margin.
Pin
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
I
I
I
I
I
O
I
I
O
I
O
I
O
I
I
I
1, 0
1, Z, 0
1, 0
Disc innermost track detection signal input.
Digital GND.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Test pin. Normally fixed to low.
Spindle motor external pin input.
Digital power supply.
Analog EFM PLL oscillation circuit output.
Analog EFM PLL oscillation circuit input. flock = 8.6436MHz.
Test pin. Normally fixed to low.
Analog EFM PLL charge pump output.
Variable pitch clock input from the external VCO. fcenter = 16.9344MHz.
Set VCKI to low when the external clock is not input to this pin.
Wide-band EFM PLL VCO2 oscillation output.
Analog power supply.
Connects the operational amplifier current source reference resistance.
Analog GND.
Operational amplifier output.
RF signal input.
Center servo analog input.
Tracking error signal input.
SSTP
DVSS5
DTS0
TES2
TES3
PWMI
DVDD5
VCOO
VCOI
TEST
PDO
VCKI
V16M
AVDD2
IGEN
AVSS2
ADIO
RFDC
CE
TE
Symbol I/O
Description
– 9 –
CXD3021R
Electrical Characteristics
1. DC Characteristics (VDD = AVDD = 3.3V ± 10%, Vss = AVss = 0V, Topr = –20 to +75°C)
Item
Input leak current (1)
Input leak current (2)
Tri-state pin output leak current
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
High level input voltage
Low level input voltage
Input voltage
Input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input voltage (1)
Input voltage (2)
Input voltage (3)
Input voltage (4)
Input voltage (5)
Input voltage (6)
Output voltage (1)
Output voltage (2)
Output voltage (3)
Output voltage (4)
Output voltage (5)
VIH (1)
VIL (1)
VIH (2)
VIL (2)
VIH (3)
VIL (3)
VIH (4)
VIL (4)
VIN (5)
VIN (6)
VOH (1)
VOL (1)
VOH (2)
VOL (2)
VOH (3)
VOL (3)
VOL (4)
VOH (5)
VOL (5)
ILI (1)
ILI (2)
ILO
0.7VDD
0.7VDD
0.7VDD
0.7VDD
VSS
VSS
VDD – 0.4
0
VDD – 0.4
0
VDD – 0.2
0
0
VDD – 0.5
0
–10
–20
–5
0.2VDD
0.2VDD
0.2VDD
0.2VDD
VDD
VDD
VDD
0.4
VDD
0.4
VDD
0.4
0.4
VDD
0.4
10
20
5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
Conditions Min.
Typ. Max.
Unit
Applicable
pins
Applicable pins
∗1
DTS0, TES2, TES3, TEST, PSSL
∗2
ASYE, VCKI
∗3
ATSK, DATA, MD2, PWMI, SSTP, XLAT, XTSL, PCMDI, XWO
∗4
CLOK, EXCK, MUTE, SCLK, SCSY, SQCK, XRST, BCKI, LRCKI
∗5
ASYI, BIAS, CLTV, FILI, IGEN, BSSD, RFAC, VCTL
∗6
CE, FE, SE, TE, VC, RFDC
∗7
ASYO, C16M, C4M, DA01 to DA16, DOUT, LRCK, MON, SBSO, SCOR, SQSO, WDCK, WFCK, PWMLP,
PWMLN, PWMRP, PWMRN, RMUTO, LMUTO
∗8
FSW
∗9
MCKO
∗10
MDP, MDS, PCO, PDO, SENS, V16M, VPCO1, VPCO2
∗11
FILO
∗12
COUT, DFCT, FOK, LOCK, MIRR, FSTIO
Schmitt input
VI ≤ 5.5V
VI ≤ 5.5V
Schmitt input
Analog input
Analog input
IOH = –8mA
IOL = 8mA
IOH = –4mA
IOL = 4mA
IOH = –2mA
IOL = 4mA
IOL = 4mA
IOH = –0.28mA
IOH = 0.36mA
VI = 0 to 5.5V
VI = 0.25VDD
to 0.75VDD
VO = 0 to 3.6V
∗1, ∗12
∗2
∗3
∗4
∗5
∗6
∗9
∗7, ∗10
∗12
∗7, ∗10
∗12
∗8
∗11
∗3, ∗4, ∗
5
∗6
∗10
– 10 –
CXD3021R
2. AC Characteristics
(1) XTLI pin, VCOI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 10%)
(b) When inputting pulses to XTLI and VCOI pins
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 10%)
(c) When inputting sine waves to XTLI and VCOI pins via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 10%)
Oscillation
frequency
fMAX 7
34 MHz
Item Symbol
Min. Typ. Max. Unit
High level pulse
width
tWHX 13 500
ns
Low level pulse
width
tWLX 13 500
ns
Pulse cycle tCX 26
1000
ns
Input high level
VIHX
VDD – 1.0
V
Input low level
VILX 0.8 V
Rise time,
fall time
tR, tF 10
ns
Item Symbol Min. Typ. Max. Unit
Input amplitude VI 2.0 VDD + 0.3
Vp-p
Item Symbol Min.
Typ. Max. Unit
tR tF
tWHX
tWLX
tCX
VILX
VIHX × 0.1
V
IHX × 0.9
V
IHX
XTLI
V
DD/2
– 11 –
CXD3021R
(2) CLOK, DATA, XLAT, SQCK and EXCK pins
(VDD = AVDD = 3.3V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Clock frequency
Clock pulse width
Setup time
Hold time
Delay time
Latch pulse width
EXCK SQCK frequency
EXCK SQCK pulse width
CNIN frequency
∗
CNIN pulse width
∗
fCK
tWCK
tSU
tH
tD
tWL
fT
tWT
fT
tWT
30
30
30
30
750
750
7.5
16
0.65
65
MHz
ns
ns
ns
ns
ns
MHz
ns
kHz
µs
Item Symbol Min. Typ. Max. Unit
tWCK tWCK
1/fCK
tH
tSU
tWL
tD
1/fT
tWT tWT
tH
tSU
CLOK
DATA
XLAT
EXCK
SQCK
CNIN
SBSO
SQSO
∗
Only when $44 and $45 are executed.
– 12 –
CXD3021R
(4) COUT, MIRR and DFCT pins
Operating frequency (VDD = AVDD = 3.3V ± 10%, VSS = AVSS = 0V, Topr = –20 to +75°C)
COUT maximum operating frequency
MIRR maximum operating frequency
DFCT maximum operating frequency
fCOUT
fMIRR
fDFCTH
40
40
5
kHz
kHz
kHz
∗1
∗2
∗3
Signal
Symbol Min. Typ.
Max. Unit
Conditions
∗1
When using a high-speed traverse TZC.
∗2
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.11VDD to 0.23VDD
• ≤ 25%
∗3
During complete RF signal omission.
When settings related to DFCT signal generation are Typ.
(3) SCLK pin
SCLK frequency
SCLK pulse width
Delay time
fSCLK
tSPW
tDLS
31.3
15
16 MHz
ns
µs
Item
Symbol Min. Typ. Max.
Unit
tSPWtDLS
1/fSCLK
MSB
LSB
…
…
XLAT
SCLK
Serial Readout Data
(SENS)
A
B
B
A + B
– 13 –
CXD3021R
(5) BCKI, LRCKI and PCMDI pins (VDD = 3.3V ± 10%, Topr = –20 to +75°C)
Input BCKI frequency
Input BCKI pulse width
Input data setup time
Input data hold time
Input LRCK setup time
Input LRCK hold time
tBCK
tWIB
tIDS
tIDH
tILRH
tILRS
100
10
15
10
15
4.5
MHz
ns
Item Symbol Min. Typ.
Max.
Unit
tILRH
tWIB tWIB
tIDHtIDS
tILRS
50%
BCKI
PCMDI
LRCKI
– 14 –
CXD3021R
DAC Analog Characteristics
Measurement conditions
(Ta = 25°C, VDD = 3.3V, Fs = 44.1kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, master clock = 384fs)
S/N ratio
THD + N
Dynamic range
Channel separation
Output level
Difference in gain between channels
93
0.007
91
91
0.81
0.1
dB
%
dB
dB
V (rms)
dB
Item
Typ.
Unit
(EIAJ)
∗
1
(EIAJ)
(EIAJ)
∗
1, ∗2
(EIAJ)
Remarks
PWMLP
(PWMRP)
100k
100
10µ
1000p
220p
8.2k
8.2k
0.1µ
33k 33k
33k 33k
100p
100p
39k
100p
47k
8.2k
PWMLN
(PWMRN)
15k
15k
15k
15k
∗
1
Using "A" weighting filter
∗
2
–60dB, 1kHz input
The analog characteristics measurement circuit is shown below.
PWMLN
PWMRP
PWMRN
PWMLP
TEST DISC
DATA
Audio Circuit
Analog
1ch
2ch
Audio Analyzer
SHIBASOKU (AM51A)768fs
CXD3021R
Block diagram of analog characteristics measurement
– 15 –
CXD3021R
Servo Drive Analog Characteristics
(VDD = AVDD = 3.0 to 4.0V, VSS = AVSS = 0V, Topr = –20 to +75°C,
BSSD pin is connected to AVDD via a 33kΩ resistor.)
When the load resistance is 200kΩ or more
When the load resistance is 60kΩ
Maximum output voltage
Minimum output voltage
0.9VDD
VSS
0.97VDD
0.03VDD
VDD
0.1VDD
V
V
Item
Min. Typ.
Max. Unit
FAO, TAO, SAO
FAO, TAO, SAO
Applicable pins
Maximum output voltage
Minimum output voltage
VSS
0.90VDD
0.03VDD
0.1VDD
V
V
Item
Min. Typ.
Max. Unit
FAO, TAO, SAO
FAO, TAO, SAO
Applicable pins
– 16 –
CXD3021R
Contents
[1] CPU Interface
§ 1-1. CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
§ 1-2. CPU Interface Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
§ 1-3. CPU Command Presets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
§ 1-4. Description of SENS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
[2] Subcode Interface
§ 2-1. P to W Subcode Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
§ 2-2. 80-bit Sub-Q Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
[3] Description of Modes
§ 3-1. CLV-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
§ 3-2. CLV-W Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
§ 3-3. CAV-W Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
§ 3-4. VCO-C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
[4] Description of Other Functions
§ 4-1. Channel Clock Recovery by Digital PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
§ 4-2. Frame Sync Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
§ 4-3. Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
§ 4-4. DA Interface Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
§ 4-5. Digital Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
§ 4-6. Servo Auto Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
§ 4-7. Digital CLV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
§ 4-8. Playback Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
§ 4-9. DAC Block Playback Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
§ 4-10. DAC Block Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
§ 4-11. Asymmetry Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
§ 4-12. Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
[5] Description of Servo Signal Processing System Functions and Commands
§ 5-1. General Description of Servo Signal Processing System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
§ 5-2. Digital Servo Block Master Clock (MCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
§ 5-3. DC Offset Cancel [AVRG Measurement and Compensation] . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
§ 5-4. E:F Balance Adjustment Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
§ 5-5. FCS Bias Adjustment Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
§ 5-6. AGCNTL Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
§ 5-7. FCS Servo and FCS Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
§ 5-8. TRK and SLD Servo Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
§ 5-9. MIRR and DFCT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
§ 5-10. DFCT Countermeasure Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
§ 5-11. Anti-Shock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
§ 5-12. Brake Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
§ 5-13. COUT Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
§ 5-14. Serial Readout Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
§ 5-15. Writing to Coefficient RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
§ 5-16. DAC Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
§ 5-17. Servo Status Changes Produced by LOCK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
§ 5-18. Description of Commands and Data Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
§ 5-19. List of Servo Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
§ 5-20. Filter Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
§ 5-21. TRACKING and FOCUS Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
[6] Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
Explanation of abbreviations AVRG: Average
AGCNTL: Auto gain control
FCS: Focus
TRK: Tracking
SLD: Sled
DFCT: Defect
– 17 –
CXD3021R
[1] CPU Interface
§ 1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
• The internal registers are initialized by a reset when XRST = 0.
§ 1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
4 to 6
7
8
9
A
B
C
D
E
8 bits
8 to 24 bits
16 bits
20 bits
32 bits
32 bits
28 bits
20 bits
28 bits
20 bits
20 bits
Total bit length
30ns or more
D18 D19 D20 D21 D22 D23
750ns or more
Valid
CLOK
DATA
XLAT
Registers
D0 D1
– 18 –
CXD3021R
Command Table ($0X to 1X)
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SEACH
VOLTAGE UP
ANTI SHOCK ON
ANTI SHOCK OFF
BRAKE ON
BRAKE OFF
TRACKING GAIN
NORMAL
TRACKING GAIN UP
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
FILTER SELECT 2
1
1
0
0
0
0
1
0
—
—
—
—
—
—
0
1
—
—
—
—
0
—
1
0
—
—
—
—
—
—
0
1
1
1
—
—
—
—
0
1
—
—
—
—
—
—
0
1
—
—
—
—
—
—
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0 0 0 0
0 0 0 1
FOCUS
CONTROL
TRACKING
CONTROL
Reg-
ister
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
—: Don't care
– 19 –
CXD3021R
Command Table ($2X to 3X)
TRACKING SERVO OFF
TRACKING SERVO ON
FORWARD TRACK JUMP
REVERSE TRACK JUMP
SLED SERVO OFF
SLED SERVO ON
FORWARD SLED MOVE
REVERSE SLED MOVE
SLED KICK LEVEL
(±1 × basic value) (Default)
SLED KICK LEVEL
(±2 × basic value)
SLED KICK LEVEL
(±3 × basic value)
SLED KICK LEVEL
(±4 × basic value)
0
0
1
1
—
—
—
—
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
0
0
1
1
—
—
—
—
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
3
0 0 1 0
0 0 1 1
TRACKING
MODE
SELECT
Reg-
ister
Command
Address
D23 to D20
Reg-
ister
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
—: Don't care
– 20 –
CXD3021R
Command Table ($340X)
KRAM DATA (K00)
SLED INPUT GAIN
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 0SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 21 –
CXD3021R
Command Table ($341X)
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K18)
FIX
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 0 1SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 22 –
CXD3021R
Command Table ($342X)
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 0SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 23 –
CXD3021R
Command Table ($343X)
KRAM DATA (K30)
SLED INPUT GAIN
(when TGup2 is accessed with SFSK = 1)
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K32)
NOT USED
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 0 1 1SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 24 –
CXD3021R
Command Table ($344X)
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K46)
TRACKING HOLD INPUT GAIN
(when TGup2 is accessed with THSK = 1)
KRAM DATA (K47)
NOT USED
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4F)
NOT USED
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD7
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD6
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD5
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD4
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD3
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD2
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD1
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
KD0
3 0 0 1 1 0 1 0 0 0 1 0 0SELECT
Reg-
ister
Command
Address 1
D23 to D20
Address 2
D19 to D16
Address 3
D15 to D12
Address 4
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D1 D0
– 25 –
CXD3021R
Command Table ($348X to 34FX)
FCS Bias Limit
FCS Bias Data
Traverse Center Data
3
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
FBL9
FB9
TV9
FBL8
FB8
TV8
FBL7
FB7
TV7
FBL6
FB6
TV6
FBL5
FB5
TV5
FBL4
FB4
TV4
FBL3
FB3
TV3
FBL2
FB2
TV2
FBL1
FB1
TV1
—
—
TV0
SELECT
Reg-
ister
Command
Address 1
Address 2
D23 to D20
Address 3
D15
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2
Data 3Data 2Data 1Address 3
D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
—: Don't care
0 0 1 1
D19 to D16
0 1 0 0
PGFS1
0
A/D
SEL
SFBK1
THBON
FAON
PGFS0
0
COPY
EN
SFBK2
FHBON
TAON
PFOK1
0
EMPH
D
0
TLB1ON
SAON
PFOK0
0
CAT
b8
0
FLB1ON
0
PGFS, PFOK, MIRR
DOUT
Booster Surf Brake
Booster
Servo DAC output
0
0
DOUT
EN
0
TLB2ON
FAOZ
0
0
DOUT
DMUT
0
0
TAOZ
0
0
DOUT
WOD
0
HBST1
SAOZ
0
0
WIN
EN
0
HBST0
0
MRT1
0
DOUT
EN2
0
LB1S1
0
MRT0
0
0
0
LB1S0
0
0
0
0
0
LB2S1
0
0
0
0
0
LB2S0
0
– 26 –
CXD3021R
Command Table ($35X to 3FX)
FCS search, AGF
TRK jump, AGT
FZC, AGC, SLD move
DC measure, cancel
Serial data read out
FCS Bias, Gain,
Surf jump/brake
Mirr, DFCT, FOK
TZC, Cout, Bottom, Mirr
SLD filter
Filter
Clock, others
3
FT1
TDZC
FZSH
VCLM
DAC
0
SFO2
COSS
SFID
F1NM
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
FT0
DTZC
FZSL
VCLC
SD6
FBON
SFO1
COTS
SFSK
F1DM
AGC4
FS5
TJ5
SM5
FLM
SD5
FBSS
SDF2
CETZ
THID
F3NM
XT4D
FS4
TJ4
SM4
FLC0
SD4
FBUP
SDF1
CETF
THSK
F3DM
XT2D
FS3
TJ3
SM3
RFLM
SD3
FBV1
MAX2
COT2
0
TINM
0
FS2
TJ2
SM2
RFLC
SD2
FBV0
MAX1
COT1
TLD2
TIUM
DRR2
FS1
TJ1
SM1
AGF
SD1
0
SFOX
MOT2
TLD1
T3NM
DRR1
FS0
TJ0
SM0
AGT
SD0
TJD0
BTF
0
TLD0
T3UM
DRR0
FTZ
SFJP
AGS
DFSW
0
FPS1
D2V2
BTS1
0
DF1S
0
FG6
TG6
AGJ
LKSW
0
FPS0
D2V1
BTS0
0
TLCD
ASFG
FG5
TG5
AGGF
TBLM
0
TPS1
D1V2
MRC1
0
0
FTQ
FG4
TG4
AGGT
TCLM
0
TPS0
D1V1
MRC0
0
LKIN
LPAS
FG3
TG3
AGV1
FLC1
0
0
RINT
0
0
COIN
SRO1
FG2
TG2
AGV2
TLC2
0
SJHD
0
0
0
MDFI
SRO0
FG1
TG1
AGHS
TLC1
0
INBK
0
0
0
MIRI
AGHF
FG0
TG0
AGHT
TLC0
0
MTI0
0
0
0
XT1D
0
SELECT
Reg-
ister
Command
Address 1 Address 2
D23 to D20 D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
0 0 1 1
– 27 –
CXD3021R
Command Table ($4X to EX)
Auto sequence
Blind (A, E),
Brake (B),
Overflow (C, G)
Sled KICK,
BRAKE (D),
KICK (F)
Auto sequence (N)
track jump count
setting
MODE
specification
Function
specification
Audio CTRL
Traverse monitor
counter setting
Spindle servo
coefficient setting
CLV CTRL
SPD mode
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
AS3
TR3
SD3
32768
CD-
ROM
DCLV
ON/OFF
0
32768
Gain
MDP1
DCLV
PWM MD
CM3
AS2
TR2
SD2
16384
DOUT
Mute
DSPB
ON/OFF
0
16384
Gain
MDP0
TB
CM2
AS1
TR1
SD1
8192
DOUT
Mute-F
ASEQ
ON/OFF
Mute
8192
Gain
MDS1
TP
CM1
AS0
TR0
SD0
4096
WSEL
DPLL
ON/OFF
ATT
4096
Gain
MDS0
CLVS
Gain
CM0
MT3
0
KF3
2048
VCO
SEL1
BiliGL
MAIN
PCT1
2048
Gain
DCLV1
VP7
EPWM
MT2
0
KF2
1024
ASHS
BiliGL
SUB
PCT2
1024
Gain
DCLV0
VP6
SPDC
MT1
0
KF1
512
SOCT0
FLFC
MCSL
512
PCC1
VP5
ICAP
MT0
0
KF0
256
VCO
SEL2
XWOC
SOC2
256
PCC0
VP4
SFSL
LSSL
0
0
128
KSL3
DAC
EMP
DCOF
128
SFP3
VP3
VC2C
0
0
0
64
KSL2
DAC
ATT
FMUT
64
SFP2
VP2
HIFC
0
0
0
32
KSL1
SYCOF
BSBST
32
SFP1
VP1
LPWR
0
0
0
16
KSL0
0
BBSL
16
SFP0
VP0
VPON
—
—
—
8
VC01
CS1
PLM3
ATTCH
SEL
8
SRP3
VP
CTL1
Gain
CAV1
—
—
—
4
VCO1
CS0
PLM2
ATD10
4
SRP2
VP
CTL0
Gain
CAV0
—
—
—
2
XVCO2
THRU
PLM1
ATD9
2
SRP1
0
FCSW
—
—
—
1
VCO2
CS
PLM0
ATD8
1
SRP0
0
INV
VPCO
4
5
6
7
8
9
A
B
C
D
E
Reg-
ister
Command
Address
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Data 1 Data 2 Data 3 Data 4
—: Don't care
– 28 –
CXD3021R
FOCUS SERVO OFF,
0V OUT
TRACKING GAIN UP
FILTER SELECT 1
TRACKING SERVO OFF
SLED SERVO OFF
SLED KICK LEVEL
(±1 × basic value) (Default)
KRAM DATA
($3400XX to $344fXX)
0
0
0
0
0
0
0
0
0
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
2
0 0 0 0
0 0 0 1
0 0 1 0
FOCUS
CONTROL
TRACKING
CONTROL
TRACKING
MODE
Reg-
ister
Command
Address
D23 to D20
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D1 D0
Reg-
ister
Command
3 SELECT
Address
D23 to D20
0 0 1 1
0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table".
0 0 0 0 — — — — — — — — — — — — — — — —
Data 1
D19 D18 D17 D16
Data 2
D15 D14 D13 D12
Data 3
D11 D10 D9 D8
Data 4
D7 D6 D5 D4
Data 5
D3 D2 D0 D0
Address 1
D23 to D20 D19 D18 D17 D16
Address 2
D15 D14 D13 D12
Address 3
D11 D10 D9 D8
Data 1
D7 D6 D5 D4
Data 2
D3 D2 D0 D0
§ 1-3. CPU Command Presets
Command Preset Table ($0X to 344X)
—: Don't care
Command Table ($4X to EX) cont.
—: Don't care
MODE
specification
1 0 0 0 ERC4
SCOR
SEL
SCSY SOCT1 0 0 OUTL 08
Function
specification
Audio CTRL
Spindle servo
coefficient setting
1 0 0 1
1 0 1 0
1 1 0 0
DAC
SMUTL
ATD7
EDC7
DAC
SMUTR
ATD6
EDC6
ZMUT
ATD5
EDC5
ZDPL
ATD4
EDC4
0
ATD3
EDC3
0
ATD2
EDC2
0
ATD1
EDC1
SLBS
ATD0
EDC0
9
A
C
Reg-
ister
Command
Address Data 1 Data 2 Data 3 Data 4
D3 D2 D1 D0 D3 D2 D1 D0
Data 5 Data 6
FSTIN 0 0 0
DIV4
—
—
DSP
SLEEP
—
—
DSSP
SLEEP
—
—
DAC
SLEEP
—
—
D3 D2 D1 D0
Data 7
– 29 –
CXD3021R
Command Preset Table ($348X to 34FX)
PGFS, PFOK, MIRR
CAV control
DOUT
Booster Surf Brake
Booster
Servo DAC output
FCS Bias Limit
FCS Bias Data
Traverse Center Data
3
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SELECT
Reg-
ister
Command
Address 1 Address 2
D23 to D20
Address 3
D15
D15 D14 D13 D12 D11
D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2
Data 3Data 2Data 1Address 3
D14 D13 D12
Data 1
D11 D10 D9 D8
Data 2
D7 D6 D5 D4
Data 3
D3 D2 D1 D0
0 0 1 1
D19 to D16
0 1 0 0
– 30 –
CXD3021R
Command Preset Table ($35X to 3FX)
FCS search, AGF
TRK jump, AGT
FZC, AGC, SLD move
DC measure, cancel
Serial data read out
FCS Bias, Gain,
Surf jump/brake
Mirr, DFCT, FOK
TZC, Cout, Bottom, Mirr
SLD filter
Filter
Clock, others
3
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
SELECT
Reg-
ister
Command
Address 1
Address 2
D23 to D20 D19 D18 D17 D16
Data 1
D15 D14 D13 D12
Data 2
D11 D10 D9 D8
Data 3
D7 D6 D5 D4
Data 4
D3 D2 D1 D0
0 0 1 1
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