Sony CXD3017Q Datasheet

CXD3017Q

CD Digital Signal Processor with Built-in Digital Servo and DAC

Description

The CXD3017Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter.

Features Digital Signal Processor (DSP) Block

• 1×, 2×, 4× speed playback supported

• 16K-RAM

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• SEC strategy-based error correction

• Subcode demodulation and Sub Q data error

detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry compensation circuit

• CPU interface on serial bus

• Error correction monitor signal, etc. output from a

new CPU interface

• Servo auto sequencer

• Digital audio interface outputs

• Digital level meter, peak meter

• CD TEXT data demodulation Digital Servo (DSSP) Block

• Microcomputer software-based flexible servo control

• Offset cancel function for servo error signal

• Auto gain control function for servo loop

• E:F balance, focus bias adjustment function

• Surf jump function supporting micro two-axis

• Tracking filter: 6 stages, focus filter: 5 stages Digital Filter, DAC and Analog Low-pass Filter Blocks

• DBB (digital bass boost) function

• Double-speed playback supported

• Digital de-emphasis

• Digital attenuation

• 8Fs oversampling filter

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDD –0.5 to +4.6 V

• Input voltage VI –0.5 to +4.6 V

(VSS – 0.5V to VDD + 0.5V)

• Output voltage VO –0.5 to +4.6 V (VSS – 0.5V to VDD + 0.5V)

• Storage temperature Tstg –55 to +150 °C

• Supply voltage difference

VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V

Note) AVDD includes XVDD and AVSS includes XVSS.

Recommended Operating Conditions

• Supply voltage VDD 2.7 to 3.6 V

• Operating temperature

Topr –20 to +75 °C

I/O Capacitance

• Input pin CI 9 (Max.) pF

• Output pin CO 11 (Max.) pF

• I/O pin CI/O 11 (Max.) pF

Note) Measurement conditions VDD = VI = 0V

fM = 1MHz

– 1 –

E99Y24-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

80 pin LQFP (Plastic)

Playback speed

CD-DSP block

DAC block

4×

2.7 to 3.6

2×

2.7 to 3.6 2.7 to 3.6

1×

2.7 to 3.6 2.7 to 3.6

VDD [V]

– 2 –

CXD3017Q

Block Diagram

PWM PWM

AOUT1

AIN1 LOUT1 AOUT2

AIN2 LOUT2

3rd-Order

Noise Shaper

Over Sampling

Digital Filter

Serial-In Interface

LMUT

RMUT

XTAO

XTAI

Timing

Logic

XRST

TEST

TES1

D/A

Interface

DOUT

EFM

demodurator

Error

Corrector

16K

RAM

Digital

OUT

Sub Code Processor

Clock

Generator

Asymmetry

Corrector

Digital

PLL

Digital

CLV

CPU

Interface

Servo

Auto

Sequencer

Signal Processor Block

DAC Block

SYSM

BCK

PCMD

LRCK

C2PO

WFCK

EMPH

GFS

XUGF

XTSL

RFAC

ASYI

ASYO

BIAS

XPCK

FILO

FILI

PCO

CLTV

MDP LOCK SENS DATA

XLAT CLOK SPOA SPOB XLON

SCOR SQSO SQCK

Servo Block

SERVO

Interface

SCLK COUT SSTP ATSK

MIRR DFCT

FOK

MIRR DFCT FOK

SERVO DSP

FOCUS SERVO

TRACKING

SERVO

SLED SERVO

PWM GENERATOR

FOCUS PWM GENERATOR

TRACKING PWM

GENERATOR

SLED PWM

GENERATOR

FFDR FRDR TFDR TRDR SFDR SRDR

RFDC

CE

TE

SE

FE

VC

IGEN

OPAmp

Analog SW

A/D

Converter

ADIO

– 3 –

CXD3017Q

Pin Configuration

21

22

23

24

25

26

27

28

29

30

40 39

38 37 36 35

34

31

32

33

4142

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63 64 65 66

61 62

71

72 73

74 75 76 77 78 79 80

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

LRCK

PCMD

BCK

EMPH

XV

DD

XTAI

XTAO

XV

SS

AVDD1

AOUT1

AIN1

LOUT1

AV

SS1

AV

SS2

LOUT2

AIN2

AOUT2

AV

DD2

RMUT

LMUT

SE FE

VC XTSL TES1 TEST V

SS

FRDR

COUT

FFDR TRDR TFDR SRDR SFDR SSTP MDP LOCK

MIRR

DOUT

V

DD

V

SS

FILI

CLTV

AV

SS

3

TE

ASYO

AV

DD

0

IGEN

AV

SS

0

ADIO

RFDC

AV

DD

3

PCO

BIAS

ASYI

FILO

RFAC

CE

SQCK

XLAT

SENS

DATA

XRST

SYSM

CLOK

V

DD

SQSO

SCLK

SCOR

ATSK

SPOA

SPOB

XLON

WFCK

XUGF

XPCK

GFS

C2PO

FOK DFCT

– 4 –

CXD3017Q

Pin Description

No.

Symbol I/O

Output values

Description

Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data output. SQSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Digital power supply. Anti-shock input/output. Microcomputer extension interface (input A) Microcomputer extension interface (input B) Microcomputer extension interface (output) WFCK output. XUGF output. MINT1 or RFCK is output by switching with the command. XPCK output. MNT0 is output by switching with the command. GFS output. MNT3 or XROF is output by switching with the command. C2PO output. GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected. Track count signal input/output. Mirror signal input/output. Defect signal input/output. Focus OK signal input/output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS

is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1. Spindle motor servo control output. Disc innermost track detection signal input. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital GND.

1, 0

—

1, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

1, 0

1, Z, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

—

O

I I I I I I

O

I

—

I/O

I

I O O O O O O O

I/O I/O I/O I/O

I/O

O

I O O O O O O

—

SQSO SQCK XRST SYSM DATA XLAT CLOK SENS SCLK VDD ATSK SPOA SPOB XLON WFCK XUGF XPCK GFS C2PO SCOR COUT MIRR DFCT FOK

LOCK MDP

SSTP SFDR SRDR TFDR TRDR FFDR FRDR VSS

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

25 26

27 28 29 30 31 32 33 34

– 5 –

CXD3017Q

Pin No.

Symbol I/O

Output values

Description

Test pin. Normally, GND. Test pin. Normally, GND. Crystal selection input. Low when the crystal is 16.9344MHz; high when the

crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Test pin. No connected. Analog GND. Operational amplifier constant current input. Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Asymmetry comparator voltage input. Asymmetry circuit constant current input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output. (slave = digital PLL) Master PLL filter input. Master PLL charge pump output. Analog power supply. Digital GND. Digital power supply. Digital Out output. D/A interface. LR clock output f = Fs. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a low

signal when there is no emphasis. Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. Master clock GND.

Analog

—

1, 0

—

Analog

1, Z, 0

— —

— 1, 0 1, 0 1, 0 1, 0

1, 0

—

I I

I I I I I

O

—

I

—

O

I I I

—

I

O

I

O — — —

O

O —

I

O —

TEST TES1

XTSL VC

FE SE TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI BIAS RFAC AVSS3 CLTV FILO FILI PCO AVDD3 VSS VDD DOUT LRCK PCMD BCK

EMPH XVDD

XTAI XTAO XVSS

35 36

37 38

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

64 65

66 67 68

– 6 –

CXD3017Q

Pin No.

Symbol I/O

Output values

Description

Analog power supply. L ch analog output. L ch operational amplifier input. L ch LINE output. Analog GND. Analog GND. R ch LINE output. R ch operational amplifier output. R ch analog output. Analog power supply. R ch zero detection flag. L ch zero detection flag.

—

— —

— 1, 0 1, 0

—

O

I

O — —

O

I

O —

O

AVDD1 AOUT1 AIN1 LOUT1 AVSS1 AVSS2 LOUT2 AIN2 AOUT2 AVDD2 RMUT LMUT

69 70 71 72 73 74 75 76 77 78 79 80

Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XROF is generated when the 16K RAM exceeds the ±4F jitter margin.

Monitor Pin Output Combinations

Command bit

Output data

MTSL1

0 0 1

0 1 0

XUGF MNT1 RFCK

XPCK MNT0 XPCK

GFS

MNT3

XROF

C2PO C2PO GTOP

MTSL0

– 7 –

CXD3017Q

Electrical Characteristics

1. DC Characteristics

(VDD = AVDD = 3.3 ± 0.3V, Vss = AVss = 0V, Topr = –20 to +75°C)

Item

High level Low level High level Low level High level Low level

High level Low level High level Low level

Input voltage (1)

Input voltage (2)

Input voltage (3)

Input voltage (4)

Output voltage (1)

Output voltage (2)

Input leak current (1) Input leak current (2) Input leak current (3)

Input leak current (4)

Tri-state pin output leak current

VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VIN4 VOH1 VOL1 VOH2 VOL2

ILI1 ILI2 ILI3

ILI4

ILO

0.7VDD

0.8VDD

VSS

VDD – 0.4

0

VDD – 0.5

0 –10 –10 –40

–40

0.2VDD

0.2VDD VDD VDD

0.4

VDD

0.4 10 10 40

40

V V V V V V V V V V

V µA µA µA

µA

Conditions Min. Typ.

Max.

Unit

Applicable pins

VI ≤ 5.5V

VI ≤ 5.5V Schmitt input

Analog input IOH = –4mA

IOL = 4mA IOH = –0.28mA

IOH = 0.36mA VI = Vss or

VDD VI = 0 to 5.5V VI = Vss or

VDD VI = 0.25VDD

to 0.75VDD VI = Vss or

VDD

∗1, ∗9

∗2

∗3

∗4, ∗5 ∗6, ∗8,

∗9

∗7

∗1, ∗4 ∗2, ∗3 ∗9

∗5

∗8

1-1. Applicable pins and classification

∗1

CMOS level input pins (1):

TEST, TES1

∗2

CMOS level input pins (2):

SYSM, DATA, XLAT, SSTP, XTSL

∗3

CMOS Schmitt input pins:

SQCK, XRST, CLOK, SCLK, SPOA, SPOB

∗4

Analog input pins (1):

ASYI, CLTV, FILI

∗5

Analog input pins (2):

VC, FE, SE, TE, CE, RFDC

∗6

Normal output pins (1):

SQSO, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, SFDR, SRDR, TFDR, TRDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT

∗7

Normal output pin (2):

FILO

∗8

Tri-state output pins:

SENS, MDP, FFDR, PCO

∗9

Normal input/output pins:

ATSK, COUT, MIRR, DFCT, FOK, LOCK

Note) When the external pull-down resistors are connected to the pins ∗2and ∗3, the resistance applied to

these pins should be 5kΩ or less in total.

– 8 –

CXD3017Q

2. AC Characteristics

(1) XTAI pin

(a) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)

(b) When inputting pulses to XTAI pin

(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)

(c) When inputting sine waves to XTAI pin via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 3.3 ± 0.3V)

Oscillation frequency

fMAX 7

34

MHz

Item Symbol Min. Typ. Max.

Unit

High level pulse width

tWHX

13 500

ns

Low level pulse width

tWLX

13 500

ns

Pulse cycle

tCX

26 1000

ns

Input high level VIHX

0.7VDD

V

Input low level VILX 0.2VDD

V

Rise time, fall time

tR, tF

10

ns

Item Symbol Min. Typ. Max. Unit

Input amplitude VI 0.5VDD VDD + 0.3 Vp-p

Item Symbol Min. Typ. Max. unit

tR tF

tWHX

tWLX

tCK

VILX

VIHX × 0.1

V

IHX × 0.9

V

IHX

XTAI

V

DD/2

– 9 –

CXD3017Q

(2) CLOK, DATA, XLAT and SQCK pin

(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width SQCK frequency SQCK pulse width

fCK

tWCK tSU tH tD tWL

fT

tWT

750 300 300 300 750

750

Note)

0.65

Note)

MHz

ns ns ns ns ns

MHz

ns

Item Symbol Min. Typ. Max. Unit

tWCK tWCK

1/fCK

tH

tSU

tWL

tD

1/fT

tWT tWT

tH

tSU

CLOK

DATA

XLAT

SQCK

SQSO

Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum

operating frequency is 300kHz and its minimum pulse width is 1.5µs.

– 10 –

CXD3017Q

(4) COUT, MIRR and DFCT pins

Operating frequency

(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)

COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency

fCOUT fMIRR fDFCTH

40 40

5

kHz kHz kHz

∗1 ∗2 ∗3

Item Symbol Min. Typ. Max. Unit

Conditions

∗

1

When using a high-speed traverse TZC.

∗

2

When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.11VDD to 0.23VDD

• ≤ 25%

∗

3

During complete RF signal omission. When settings related to DFCT signal generation are Typ.

(3) SCLK pin

SCLK frequency SCLK pulse width Delay time

fSCLK

tSPW tDLS

31.3 15

16 MHz

ns µs

Item Symbol Min. Typ. Max. Unit

tSPWtDLS

1/fSCLK

MSB LSB

XLAT

SCLK

Serial Read Out Data

(SENS)

. . .

A

B

A + B

– 11 –

CXD3017Q

1-bit DAC and LPF Block Analog Characteristics

Analog characteristics (VDD = AVDD = 3.3V, VSS = AVSS = 0V, Ta = 25°C)

Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

Note) The external load capacitance connect to the LPF block should be 30pF or less in total.

LPF external circuit diagram

Block diagram of analog characteristics measurement

Item

Total harmonic distortion

Signal-to-noise ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

Crystal

1kHz, 0dB data when AMUT ON (Using A-weighting filter)

384Fs 768Fs 384Fs 768Fs

98 98

0.0080

0.0080 102 102

0.0120

Min.

Typ.

Max.

Unit

%

dB

Audio Analyzer

SHIBASOKU (AM51A)

100k

22µ

330pF

27k

68pF

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Audio Analyzer

CXD3017Q

Rch A

Lch B

DATA RF

TEST DISC

768Fs/384Fs

(VDD = AVDD = 3.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Output voltage Load resistance Load capacitance

VOUT RL CL

30

∗1 ∗1

∗1, ∗2

Vrms

kΩ

pF

Item Symbol

20

Min.

Max.

0.71

Typ.

Applicable pins

Unit

∗

Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB.

Applicable pins

∗1

LOUT1, LOUT2

∗2

AOUT1, AOUT2

– 12 –

CXD3017Q

Contents

§1. CPU Interface

§1-1. CPU Interface Timing ........................................................................................................................ 13

§1-2. CPU Interface Command Table ........................................................................................................ 13

§1-3. CPU Command Presets .................................................................................................................... 24

§1-4. Description of SENS Signals and Commands ................................................................................... 30

§2. Subcode Interface

§2-1. 80-bit Sub Q Readout ........................................................................................................................ 46

§3. Description of Other Functions

§3-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 49

§3-2. Frame Sync Protection ......................................................................................................................50

§3-3. Error Correction ................................................................................................................................. 50

§3-4. DA Interface ....................................................................................................................................... 51

§3-5. Digital Out .......................................................................................................................................... 53

§3-6. Servo Auto Sequence ....................................................................................................................... 53

§3-7. Digital CLV ......................................................................................................................................... 60

§3-8. CD-DSP Block Playback Speed ........................................................................................................61

§3-9. DAC Block Playback Speed .............................................................................................................. 61

§3-10. Description of DAC Block Functions .................................................................................................. 62

§3-11. LPF Block .......................................................................................................................................... 65

§3-12. Asymmetry Compensation ................................................................................................................ 66

§3-13. CD TEXT Data Demodulation ........................................................................................................... 67

§4. Description of Servo Signal Processing System Functions and Commands

§4-1. General Description of Servo Signal Processing System .................................................................. 69

§4-2. Digital Servo Block Master Clock (MCK) ...........................................................................................70

§4-3. DC Offset Cancel [AVRG Measurement and Compensation] ........................................................... 71

§4-4. E:F Balance Adjustment Function ..................................................................................................... 72

§4-5. FCS Bias Adjustment Function .......................................................................................................... 72

§4-6. AGCNTL Function ............................................................................................................................. 74

§4-7. FCS Servo and FCS Search ............................................................................................................. 76

§4-8. TRK and SLD Servo Control ............................................................................................................. 77

§4-9. MIRR and DFCT Signal Generation ..................................................................................................78

§4-10. DFCT Countermeasure Circuit .......................................................................................................... 79

§4-11. Anti-Shock Circuit .............................................................................................................................. 79

§4-12. Brake Circuit ...................................................................................................................................... 80

§4-13. COUT Signal ..................................................................................................................................... 81

§4-14. Serial Readout Circuit ........................................................................................................................ 81

§4-15. Writing to the Coefficient RAM .......................................................................................................... 82

§4-16. PWM Output ...................................................................................................................................... 82

§4-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 83

§4-18. Description of Commands and Data Sets ......................................................................................... 83

§4-19. List of Servo Filter Coefficients ........................................................................................................ 107

§4-20. Filter Composition ............................................................................................................................ 109

§4-21. TRACKING and FOCUS Frequency Response .............................................................................. 115

§5. Application Circuit .................................................................................................................................. 116

Explanation of abbreviations AVRG: Average

AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect

– 13 –

CXD3017Q

§1. CPU Interface

§1-1. CPU Interface Timing

• CPU interface

This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.

• The internal registers are initialized by a reset when XRST = 0.

Note) Be sure to set SQCK to high when XLAT is low.

§1-2. CPU Interface Command Table

Total bit length for each register

Register

0 to 2

3

4 to 6

7 8 9 A B C D E

8 bits

8 to 24 bits

8 bits 20 bits 28 bits 24 bits 28 bits 16 bits

8 bits 16 bits 20 bits

Total bit length

750ns or more

D18 D19 D20 D21 D22 D23

750ns or more

Valid

CLOK

DATA

XLAT

Registers

D0 D1

– 14 –

CXD3017Q

FOCUS SERVO ON

(FOCUS GAIN

NORMAL)

FOCUS SERVO ON

(FOCUS GAIN

DOWN)

FOCUS SERVO OFF,

0V OUT

FOCUS SERVO OFF,

FOCUS SEARCH

VOLTAGE OUT

FOCUS SEARCH

VOLTAGE DOWN

FOCUS SEACH

VOLTAGE UP

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

BRAKE OFF

TRACKING GAIN

NORMAL

TRACKING GAIN UP

FILTER SELECT 1

TRACKING GAIN UP

FILTER SELECT 2

1

0

1

0

—

0

1

—

0

—

1

0

—

0

1

—

0

1

—

0

1

—

1

0

—

0

1

0 0 0 0

0 0 0 1

FOCUS

CONTROL

TRACKING

CONTROL

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Command Table ($0X to 1X)

—: Don’t care

– 15 –

CXD3017Q

TRACKING SERVO OFF

TRACKING SERVO ON

FORWARD TRACK JUMP

REVERSE TRACK JUMP

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED MOVE

REVERSE SLED MOVE

SLED KICK LEVEL

(±1 × basic value) (Default)

SLED KICK LEVEL

(±2

×

basic value)

SLED KICK LEVEL

(±3

×

basic value)

SLED KICK LEVEL

(±4

×

basic value)

0

1

—

0

1

0

1

0

1

—

0

1

0

1

—

0

1

—

0

1

0

1

—

2

3

0 0 1 0

0 0 1 1

TRACKING

MODE

SELECT

Register

Command

Address

D23 to D20

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

—: Don’t care

Command Table ($2X to 3X)

– 16 –

CXD3017Q

Command Table ($340X)

KRAM DATA (K00)

SLED INPUT GAIN

KRAM DATA (K01)

SLED LOW BOOST FILTER A-H

KRAM DATA (K02)

SLED LOW BOOST FILTER A-L

KRAM DATA (K03)

SLED LOW BOOST FILTER B-H

KRAM DATA (K04)

SLED LOW BOOST FILTER B-L

KRAM DATA (K05)

SLED OUTPUT GAIN

KRAM DATA (K06)

FOCUS INPUT GAIN

KRAM DATA (K07)

SLED AUTO GAIN

KRAM DATA (K08)

FOCUS HIGH CUT FILTER A

KRAM DATA (K09)

FOCUS HIGH CUT FILTER B

KRAM DATA (K0A)

FOCUS LOW BOOST FILTER A-H

KRAM DATA (K0B)

FOCUS LOW BOOST FILTER A-L

KRAM DATA (K0C)

FOCUS LOW BOOST FILTER B-H

KRAM DATA (K0D)

FOCUS LOW BOOST FILTER B-L

KRAM DATA (K0E)

FOCUS PHASE COMPENSATE FILTER A

KRAM DATA (K0F)

FOCUS DEFECT HOLD GAIN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 17 –

CXD3017Q

Command Table ($341X)

KRAM DATA (K10)

FOCUS PHASE COMPENSATE FILTER B

KRAM DATA (K11)

FOCUS OUTPUT GAIN

KRAM DATA (K12)

ANTI SHOCK INPUT GAIN

KRAM DATA (K13)

FOCUS AUTO GAIN

KRAM DATA (K14)

HPTZC / AUTO GAIN HIGH PASS FILTER A

KRAM DATA (K15)

HPTZC / AUTO GAIN HIGH PASS FILTER B

KRAM DATA (K16)

ANTI SHOCK HIGH PASS FILTER A

KRAM DATA (K17)

HPTZC / AUTO GAIN LOW PASS FILTER B

KRAM DATA (K18)

FIX

KRAM DATA (K19)

TRACKING INPUT GAIN

KRAM DATA (K1A)

TRACKING HIGH CUT FILTER A

KRAM DATA (K1B)

TRACKING HIGH CUT FILTER B

KRAM DATA (K1C)

TRACKING LOW BOOST FILTER A-H

KRAM DATA (K1D)

TRACKING LOW BOOST FILTER A-L

KRAM DATA (K1E)

TRACKING LOW BOOST FILTER B-H

KRAM DATA (K1F)

TRACKING LOW BOOST FILTER B-L

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 1SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 18 –

CXD3017Q

Command Table ($342X)

KRAM DATA (K20)

TRACKING PHASE COMPENSATE FILTER A

KRAM DATA (K21)

TRACKING PHASE COMPENSATE FILTER B

KRAM DATA (K22)

TRACKING OUTPUT GAIN

KRAM DATA (K23)

TRACKING AUTO GAIN

KRAM DATA (K24)

FOCUS GAIN DOWN HIGH CUT FILTER A

KRAM DATA (K25)

FOCUS GAIN DOWN HIGH CUT FILTER B

KRAM DATA (K26)

FOCUS GAIN DOWN LOW BOOST FILTER A-H

KRAM DATA (K27)

FOCUS GAIN DOWN LOW BOOST FILTER A-L

KRAM DATA (K28)

FOCUS GAIN DOWN LOW BOOST FILTER B-H

KRAM DATA (K29)

FOCUS GAIN DOWN LOW BOOST FILTER B-L

KRAM DATA (K2A)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

KRAM DATA (K2B)

FOCUS GAIN DOWN DEFECT HOLD GAIN

KRAM DATA (K2C)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

KRAM DATA (K2D)

FOCUS GAIN DOWN OUTPUT GAIN

KRAM DATA (K2E)

Not used

KRAM DATA (K2F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 19 –

CXD3017Q

Command Table ($343X)

KRAM DATA (K30)

SLED INPUT GAIN (when SFSK = 1 TG up2)

KRAM DATA (K31)

ANTI SHOCK LOW PASS FILTER B

KRAM DATA (K32)

Not used

KRAM DATA (K33)

ANTI SHOCK HIGH PASS FILTER B-H

KRAM DATA (K34)

ANTI SHOCK HIGH PASS FILTER B-L

KRAM DATA (K35)

ANTI SHOCK FILTER COMPARATE GAIN

KRAM DATA (K36)

TRACKING GAIN UP2 HIGH CUT FILTER A

KRAM DATA (K37)

TRACKING GAIN UP2 HIGH CUT FILTER B

KRAM DATA (K38)

TRACKING GAIN UP2 LOW BOOST FILTER A-H

KRAM DATA (K39)

TRACKING GAIN UP2 LOW BOOST FILTER A-L

KRAM DATA (K3A)

TRACKING GAIN UP2 LOW BOOST FILTER B-H

KRAM DATA (K3B)

TRACKING GAIN UP2 LOW BOOST FILTER B-L

KRAM DATA (K3C)

TRACKING GAIN UP PHASE COMPENSATE FILTER A

KRAM DATA (K3D)

TRACKING GAIN UP PHASE COMPENSATE FILTER B

KRAM DATA (K3E)

TRACKING GAIN UP OUTPUT GAIN

KRAM DATA (K3F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 1SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 20 –

CXD3017Q

Command Table ($344X)

KRAM DATA (K40)

TRACKING HOLD FILTER INPUT GAIN

KRAM DATA (K41)

TRACKING HOLD FILTER A-H

KRAM DATA (K42)

TRACKING HOLD FILTER A-L

KRAM DATA (K43)

TRACKING HOLD FILTER B-H

KRAM DATA (K44)

TRACKING HOLD FILTER B-L

KRAM DATA (K45)

TRACKING HOLD FILTER OUTPUT GAIN

KRAM DATA (K46)

TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2)

KRAM DATA (K47)

Not used

KRAM DATA (K48)

FOCUS HOLD FILTER INPUT GAIN

KRAM DATA (K49)

FOCUS HOLD FILTER A-H

KRAM DATA (K4A)

FOCUS HOLD FILTER A-L

KRAM DATA (K4B)

FOCUS HOLD FILTER B-H

KRAM DATA (K4C)

FOCUS HOLD FILTER B-L

KRAM DATA (K4D)

FOCUS HOLD FILTER OUTPUT GAIN

KRAM DATA (K4E)

Not used

KRAM DATA (K4F)

Not used

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 1 0 0SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 21 –

CXD3017Q

PFOK, RFAC

Booster Surf Brake

Booster

DFCT

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

SFBK1

THBON

IDFS3

1

0

SFBK2

FHBON

IDFS2

0

1

0

PFOK1

0

TLB10N

IDFS1

FBL9

FB9

TV9

PFOK0

0

FLB1ON

IDFS0

FBL8

FB8

TV8

0

TLB2ON

0

FBL7

FB7

TV7

0

FBL6

FB6

TV6

0

HBST1

IDFT1

FBL5

FB5

TV5

MRS

0

HBST0

IDFT0

FBL4

FB4

TV4

MRT1

0

LB1S1

0

FBL3

FB3

TV3

MRT0

0

LB1S0

0

FBL2

FB2

TV2

0

LB2S1

0

FBL1

FB1

TV1

0

LB2S0

INVRFDC

—

TV0

SELECT

Register

Command

Address 1 Address 2

D23 to D20

Address 3

D15

D15 D14

D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 3

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Command Table ($348X to 34FX)

0 0 1 1

D19 to D16

0 1 0 0

– 22 –

CXD3017Q

0 0 1 1

1

0

1

0

1

System GAIN

FOCUS SEARCH SPEED/

VOLTAGE/AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE/AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

Filter

Others

3

0 0 1 1

1

1 1 1

0 0

0

SYG3 SYG2

SYG1 SYG0

FI

FZB3

FI

FZB2

FI

FZB1

FI

FZB0

FI

FZA3

FI

FZA2

FI

FZA1

FI

FZA0

0

1

0

1

0

1

0

1

FT1

0

FZSH

VCLM

DAC

0

SFO2

FT0

DTZC

FZSL

VCLC

SD6

FBON

SFO1

FS5

TJ5

SM5

FLM

SD5

0

SDF2

FS4

TJ4

SM4

FLC0

SD4

0

SDF1

FS3

TJ3

SM3

RFLM

SD3

0

MAX2

FS2

TJ2

SM2

RFLC

SD2

0

MAX1

FS1

TJ1

SM1

AGF

SD1

FI

FZC

SFOX

FS0

TJ0

SM0

AGT

SD0

0

BTF

FTZ

SFJP

AGS

DFSW

0

FPS1

D2V2

FG6

TG6

AGJ

LKSW

0

FPS0

D2V1

FG5

TG5

AGGF

TBLM

0

TPS1

D1V2

FG4

TG4

AGGT

TCLM

0

TPS0

D1V1

FG3

TG3

AGV1

FLC1

0

SVDA

0

FG2

TG2

AGV2

TLC2

0

FG1

TG1

AGHS

TLC1

0

FG0

TG0

AGHT

TLC0

0

1

0

1

F1NM

0

F1DM

AGG4

F3NM

XT4D

F3DM

XT2D

T1NM

AGSD

T1UM

DRR2

T3NM

DRR1

T3UM

DRR0

DFIS

0

TLCD

ASFG

0

FTQ

LKIN

1

COIN

SRO1

MDFI

0

MIRI

AGHF

XT1D

ASOT

1

0

1

COSS

SFID

COTS

SFSK

CETZ

THID

CETF

THSK

COT2

ABEF

COT1

TLD2

MOT2

TLD1

0

TLD0

BTS1

0

BTS0

0

MRC1

0

MRC0

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

Command Table ($35X to 3FX)

—: Don’t care

– 23 –

CXD3017Q

Instruction Table

Register

4

5

6

7

8

9

A

B

C

D

E

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B)

Kick (D)

Auto sequence

(N) track jump

count

Mode

specification

Function

specification

Audio CTRL

Sleep setting

Serial bus

CTRL

Spindle servo

coefficient

setting

CLV CTRL

CLV mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

2048

VCO

SEL1

0

ADCPS

TRMI

—

1

0

—

1024

0

DSP

SLEEP

TRMO

—

1

0

—

512

SOCT

0

OPSL20OPSL2

1

DSSP

SLEEP

MTSL1

—

1

0

—

256

0

EMPH

ASYM

SLEEP

MTSL0

—

0

—

128

KSL3

OPSL10OPSL1

1

SMUT

0

—

0

—

64

KSL2

MCSL

AD10

LPF

SLEEP

0

—

0

—

32

1

0

AD9

0

—

0

—

16

0

AD8

0

—

0

—

8

0

ZDPL

AD7

—

0

—

4

VCO1

CS0

ZMUT

AD6

—

0

—

2

0

—

0

AD5

—

0

—

1

0

—

0

AD4

—

0

—

0

—

0

AD3

—

0

—

DCOF

AD2

—

0

—

0

AD1

—

0

—

DAC

PWDN

AD0

—

TXON

—

FMUT

—

TXOUT

—

LRWO

—

OUTL1

—

BSBST

—

OUTL0

—

BBSL

—

AS3

0.18ms

0.36ms

11.6ms

32768

CDROM

0

1

SL1

Gain

MDP1

0

CM3

AS2

0.09ms

0.18ms

5.8ms

16384

DOUT

Mute

DSPB

ON/OFF

DSPB

ON/OFF

0

1

SL0

Gain

MDP0

TB

CM2

AS1

0.05ms

0.09ms

2.9ms

8192

DOUT

ON/OFF

0

Mute

0

CPUSR

Gain

MDS1

TP

CM1

AS0

0.02ms

0.05ms

1.45ms

4096

WSEL

0

ATT

1

0

Gain

MDS0

Gain

CLVS

CM0

Command

Address

D3 D2 D1 D0

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0

Data 3

D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

– 24 –

CXD3017Q

FOCUS SERVO OFF,

0V OUT

TRACKING GAIN UP

FILTER SELECT 1

TRACKING SERVO OFF

SLED SERVO OFF

SLED KICK LEVEL

(±1 × basic value) (Default)

KRAM DATA

($3400XX to $344fXX)

0

1

0

—

0

1

2

0 0 0 0

0 0 0 1

0 0 1 0

FOCUS

CONTROL

TRACKING

CONTROL

TRACKING

MODE

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Register

Command

3 SELECT

Address

D23 to D20

0 0 1 1

0 0 1 1 0 1 0 0 0 See "Coefficient ROM Preset Values Table".

0 0 0 0 — — — — — — — — — — — — — — — —

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D0 D0

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Address 3

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D0 D0

§1-3. CPU Command Presets

Command Preset Table ($0X to 34X)

—: Don’t care

– 25 –

CXD3017Q

Command Preset Table ($348X to 34FX)

PFOK, RFAC

Booster Surf Brake

Booster

Servo DAC output

DFCT

FCS Bias Limit

FCS Bias Data

Traverse Center Data

3

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

SELECT

Register

Command

Address 1

Address 2

D23 to D20

Address 3

D15

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D1 D0D3 D2

Data 3Data 2Data 1Address 3

D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

0 0 1 1

D19 to D16

0 1 0 0

—: Don’t care

– 26 –

CXD3017Q

0 0 1 1

1

0

1

0

1

System GAIN

FOCUS SEARCH SPEED/

VOLTAGE AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

3

0 0 1 1

1

1 1 1

0

1 0

0

0 0

0

0 0 0

0 0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Filter

Others

1

0

1

0

1

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

Command Preset Table ($35X to 3FX)

—: Don’t care

– 27 –

CXD3017Q

Reset Initialization

Register

4

5

6

7

8

9

A

B

C

D

E

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B),

Kick (D)

Auto sequence (N)

track jump

count setting

MODE

specification

Function

specification

Audio CTRL

Sleep setting

Serial bus

CTRL

Spindle servo

coefficient setting

CLV CTRL

CLV mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

—

1

0

—

0

1

—

1

0

—

0

—

1

0

—

1

0

—

0

—

0

—

0

—

0

1

0

—

0

—

0

1

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

Command

Address

D3 D2 D1 D0

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0

Data 3

D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

– 28 –

CXD3017Q

ADDRESS

K00 K01 K02 K03 K04 K05 K06 K07 K08

K09 K0A K0B K0C K0D K0E K0F

E0 81 23 7F 6A 10 14 30 7F 46 81

1C

7F 58 82 7F

SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19 K1A K1B K1C K1D K1E K1F

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29 K2A K2B K2C K2D K2E K2F

4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E

FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix

∗

TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L

82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00

TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN Not used Not used

DATA CONTENTS

∗

Fix indicates that normal preset values should be used.

– 29 –

CXD3017Q

ADDRESS

K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A

K3B K3C K3D K3E K3F

80 66 00 7F 6E 20 7F 3B 80 44 7F 77 86

0D

57 00

SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B Not used ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN Not used

K40

K41

K42

K43

K44

K45

K46

K47

K48

K49 K4A K4B K4C K4D K4E K4F

04 7F 7F 79 17

6D

00 00 02 7F 7F 79 17 54 00 00

TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) Not used FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN Not used Not used

DATA CONTENTS

– 30 –

CXD3017Q

Description of SENS Signals

Low while the auto sequencer is in operation, high when the operation terminates. Outputs the same signal as the FOK pin.

High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks with frequeny division ratio set by $B. High when $B is

latched, and toggles each time COUT is counted just for the frequency diviison ratio set by $B.

Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter.

XBUSY FOK GFS

COUT

OV64

SENS output

§1-4. Description of SENS Signals and Commands SENS output

Notes) • The SENS output can be read from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0.

$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases.

• The signals output by $0X to $3X in the table above cannot be read during the auto sequence operation.

Microcomputer serial register (latching not required)

$0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X, 7X, 8X, 9X $AX $BX $CX $DX $EX $FX

FZC

AS (Anti Shock)

TZC

SSTP

AGOK

XAVEBSY TE Avrg Reg. FE Avrg Reg.

VC Avrg Reg.

TRVSC Reg.

FB Reg.

RFDC Avrg Reg.

FBIAS count STOP

SSTP

XBUSY

FOK

0

GFS

0

COUT frequency division

0

OV64

0

— — — — —

— 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit

—

SENS output Output data length