Sony CXD3009Q Datasheet

– 1 –

CXD3009Q

80 pin QFP (Plastic)

E97322B01-PS

CD Digital Signal Processor

Description

The CXD3009Q is a digital signal processor LSI for CD players and is equipped with built-in digital filters, zero detection circuit, 1-bit DAC, and analog low-pass filter on a single chip.

Features

Digital Signal Processor (DSP) Block

• Playback mode supporting CAV

(Constant Angular Velocity)

– Frame jitter-free

– Allows 0.5 to double-speed continuous playback

– Allows relative rotational velocity readout

– Supports external spindle control

• Wide capture range playback mode

– Spindle rotational velocity following method

– Supports normal-speed and double-speed playback

• 16K RAM

• EFM data demodulation

• Enhanced EFM frame sync protection

• SEC strategy-based error correction

• Subcode demodulation and Sub Q data error

detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry compensation circuit

• Serial bus-based CPU interface

• Error correction monitor signals, etc. are output

from a new CPU interface.

• Servo auto sequencer

• Digital audio interface output

• Digital peak meter

• CD-TEXT data demodulation

Digital Filter, DAC, Analog Low-Pass Filter Block

• DBB (Digital Bass Boost)

• Supports double-speed playback

• Digital de-emphasis

• Digital attenuation function

• Zero detection function

• 8Fs oversampling digital filter

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDD –0.3 to +4.6 V

• Input voltage VI –0.3 to +4.6 V

(Vss – 0.3V to VDD + 0.3V)

• Output voltage VO –0.3 to +4.6 V

• Storage temperature

Tstg –40 to +125 °C

• Supply voltage difference VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V

Note) AVDD includes XVDD, and AVSS includes XVSS.

Recommended Operating Conditions

• Supply voltage VDD 2.5 to 3.6 V

• Operating temperature

Topr –20 to +75 °C

Input/Output Capacitances

• Input capacitance CI 12 (max.) pF

• Output capacitance CO 12 (max.) pF

Note) Measurement conditions VDD = VI = 0V

fM = 1MHz

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 2 –

CXD3009Q

Block Diagram

EFM

demodurator

Clock

Generator

OSC

Error

Corrector

D/A

Interface

Serial-In Interface

Over Sampling

Digital Filter

Timing

Logic

3rd-Order

Noise Shaper

PWM PWM

16K

RAM

Digital

OUT

Digital

CLV

CPU

Interface

Servo

Auto

Sequencer

Asymmetry

Corrector

Digital

PLL

Sub Code Processor

C4M

RF

ASYI

ASYO

BIAS

XPCK

FILO

FILI

PCO

CLTV

FOK

SEIN

CNIN

DATO

XLTO

CLKO

SENS

DATA

XLAT

CLOK

XLON

SCOR

SBSO

EXCK

SQSO

SQCK

MDP

DOUT

LOUT2

AIN2

AOUT2

LOUT1

AIN1

AOUT1

XTSL

VPCO

VCKI

V16M

VCTL

XUGF

GFS

EMPH

WFCK

C2PO

LRCK

PCMD

BCK

EMPHI

LRCKI

PCMDI

BCKI

SYSM

RMUT LMUT

XTAI XTAO

PWMI

XRST

TEST

TES1

SPOA

SPOB

40

39

38

37

36

35

31

33

41

42

43

44

47

48

49

50

51

52

53

54

55

56

57

58

59

70

67

65

66

62

71

74

75

76

79

2

3

4

5

6

7

8

9

10 11

12

13

14

15

16

17

18

21

23

24

25

26 27

28

29

30

22

– 3 –

CXD3009Q

Pin Configuration

21

22

23

24

25

26

27

28

29

30

40 39

38 37 36 35

34

31

32

33

4142

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63 64 65 66

61 62

71 72

73

74 75 76 77 78 79 80

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

VDD

SYSM

AVss AV

DD

AOUT1

AIN1

LOUT1

AVss XV

DD

XTAI

XTAO

XVss AVss

LOUT2

AIN2

AOUT2

AV

DD

AVss

XRST

V

DD

LRCKI LRCK

ASYO ASYI BIAS RF AV

DD

CLTV

MDP

AVss FILI FILO PCO VCTL V16M VCKI VPCO

PWMI

Vss

EXCK

SBSO

EMPHI

DOUT

C4M

PCMD

XPCK

XUGF

V

DD

Vss

BCKI

BCK

SCOR

WFCK

C2PO

GFS

EMPH

XTSL

PCMDI

LMUT

SENS

XLAT

SQSO

RMUT

SQCK

DATA

SEIN

Vss

CLOK

Vss

CNIN

DATO

XLTO

CLKO

SPOA

SPOB

XLON

FOK

V

DD

TES1 TEST

– 4 –

CXD3009Q

Pin Description

Pin No.

Symbol I/O Description

GND Left-channel zero detection flag. Right-channel zero detection flag. SQSO readout clock input. Sub Q 80-bit serial output. SENS output to CPU. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS input from SSP. Track jump count signal input. Serial data output to SSP. Serial data latch output to SSP. Latched at the falling edge. Serial data transfer clock output to SSP. Microcomputer extended interface (input A). Microcomputer extended interface (input B). Microcomputer extended interface (output). Focus OK input.

Used for SENS output and the servo auto sequencer. Power supply (+3V). GND Spindle motor servo control. Spindle motor external control input. TEST pin; normally GND. TEST pin; normally GND. Charge pump output for the wide-band EFM PLL. VCO2 oscillation input for the wide-band EFM PLL. VCO2 oscillation output for the wide-band EFM PLL. VCO2 control voltage input for the wide-band EFM PLL. Master PLL charge pump output. Master PLL (slave = digital PLL) filter output. Master PLL filter input. Analog GND. Master VCO control voltage input. Analog power supply (+3V). EFM signal input.

— 1, 0 1, 0

1, 0 1, 0

1, 0 1, 0 1, 0

1, 0

—

1, Z, 0

1, 0

1, Z, 0

Analog

—

O O

I O O

I

I O O O

I

I O

I

— —

O

I

I O

I O O

I

—

I

—

I

VSS LMUT RMUT SQCK SQSO SENS DATA XLAT CLOK SEIN CNIN DATO XLTO CLKO SPOA SPOB XLON

FOK VDD

VSS MDP PWMI TEST TES1 VPCO VCKI V16M VCTL PCO FILO FILI AVSS CLTV AVDD RF

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17

18 19

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

– 5 –

CXD3009Q

Pin No.

Symbol I/O Description

Constant current input of the asymmetry circuit. Asymmetry comparator voltage input. EFM full-swing output (low = VSS, high = VDD). D/A interface. LR clock output f = Fs. LR clock input. D/A interface. Serial data output (two's complement, MSB first). D/A interface. Serial data input (two's complement, MSB first). D/A interface. Bit clock output. D/A interface. Bit clock input. GND Power supply (+3V). XUGF output. Switched to MNT1 or RFCK output by a command. XPLCK output. Switched to MNT0 output by a command. GFS output. Switched to MNT3 or XRAOF output by a command. C2PO output. Switched to GTOP output by a command. Crystal selector input. Low: 16.9344MHz; high: 33.8688MHz.

4.2336MHz output. 1/4 frequency-divided VCKI output in CAV-W mode. Digital Out output. Outputs a high signal when the playback disc has emphasis, and a low

signal when there is no emphasis. Inputs a high signal when de-emphasis is on, and a low signal when

de-emphasis is off. WFCK output. Outputs a high signal when either subcode sync S0 or S1 is detected. Sub P to W serial output. SBSO readout clock input. GND Power supply (+3V). Mute input. Active when high. Analog GND. Analog power supply (+3V). Left-channel analog output. Left-channel operational amplifier input. Left-channel LINE output. Analog GND. Power supply for master clock. Crystal oscillation circuit input. Input the external master clock via this pin. Crystal oscillation circuit output.

1, 0 1, 0

1, 0

—

— 1, 0 1, 0 1, 0 1, 0

1, 0 1, 0

1, 0

1, 0 1, 0 1, 0

—

I

I O O

I O

I

— —

O O O O

I O O

O

I O

O O

I

— —

I

— —

O

I O

—

I O

BIAS ASYI ASYO LRCK LRCKI PCMD PCMDI BCK BCKI VSS VDD XUGF XPCK GFS C2PO XTSL C4M DOUT

EMPH

EMPHI WFCK

SCOR SBSO EXCK VSS VDD SYSM AVSS AVDD AOUT1 AIN1 LOUT1 AVSS XVDD XTAI XTAO

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

54

55 56

57 58 59 60 61 62 63 64 65 66 67 68 69 70 71

– 6 –

CXD3009Q

Pin No.

Symbol I/O Description

GND for master clock. Analog GND. Right-channel LINE output. Right-channel operational amplifier input. Right-channel analog output. Analog power supply (+3V). Analog GND. System reset. Reset when low. Power supply (+3V).

—

— —

—

O

I

O — —

I

—

XVSS AVSS LOUT2 AIN2 AOUT2 AVDD AVSS XRST VDD

72 73 74 75 76 77 78 79 80

Notes) • PCMD is an MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window open.)

• XUGF is the frame sync obtained from the EFM signal, and a negative pulse. It is the signal before sync protection.

• XPLCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK and the EFM signal transition point coincide.

• GFS goes high when the frame sync and the insertion protection timing match.

• RFCK is derived with the crystal accuracy. This signal has a cycle of 136µs (during normal speed).

• C2PO represents the data error status.

• XRAOF is generated when the 16K RAM exceeds the ±4F jitter margin.

– 7 –

CXD3009Q

Electrical Characteristics DC Characteristics (VDD = AVDD = 3.3V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

∗

Item

Input voltage (1)

Input voltage (2)

Input voltage (3)

Output voltage (1)

Output voltage (2)

Output voltage (4)

Input leak current Tri-state pin output leak current

∗

1

∗

2

∗

3

∗

4

∗

5

∗

6

∗

7

∗1,∗2,∗

3

Schmitt input

Analog input IOH = –4mA

IOL = 4mA IOH = –2mA IOL = 4mA IOH = –0.28mA IOL = 0.36mA VI = 0 to 3.60V VO = 0 to 3.60V

High level input voltage Low level input voltage High level input voltage Low level input voltage

Input voltage High level output voltage

Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage

VIH (1) VIL (1) VIH (2) VIL (2)

VIN (3) VOH (1)

VOL (1) VOH (2) VOL(2) VOH (4) VOL (4) ILI ILO

0.7VDD

Vss

VDD – 0.4

0

VDD – 0.4

0

VDD – 0.4

0 –5 –5

0.2VDD

0.2VDD VDD VDD

0.4

VDD

0.4

VDD

0.4 5 5

V V V V

V V

V V V V

V µA µA

Conditions

Min. Typ.

Max.

Unit

Applicable

pins

Applicable pins

∗

1

XTSL, DATA, XLAT, PWMI, SYSM, EMPHI, PCMDI

∗

2

CLOK, XRST, EXCK, SQCK, FOK, SEIN, CNIN, VCKI, LRCKI, BCKI, SPOA, SPOB

∗

3

CLTV, FILI, RF, VCTL, AIN1, AIN2

∗

4

MDP, PCO, VPCO

∗

5

ASYO, DOUT, C4M, SBSO, SQSO, SCOR, EMPH, DATO, CLKO, XLTO, SENS, WFCK, V16M, LMUT, RMUT, XLON, LRCK, PCMD, BCK, XUGF, XPCK, GFS, RFCK, C2PO

∗

6

FILO

∗

7

SENS, PCO, VPCO

∗

note) : XVDDand XVSSare included for AV

PP

and AV

SS

,

respectively.

Those are the same for the explanation from the next page.

AC Characteristics

1. XTAI pin

(1) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 5%)

(2) When inputting pulses to XTAI pin

(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 5%)

(3) When inputting sine waves to XTAI pin via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 3.3V ± 5%)

– 8 –

CXD3009Q

Oscillation frequency fMAX 7 34 MHz

Item

Symbol Min. Typ.

Max. Unit

High level pulse width

tWHX

13 500

ns

Low level pulse width

tWLX

13

500

ns

Pulse cycle

tCK

26

1,000

ns

Input high level

VIHX

0.7VDD

V

Input low level VILX

0.2VDD

V

Rise time, fall time

tR, tF

10

ns

Item Symbol Min. Typ.

Max. Unit

Input amplitude V1 0.5VDD VDD + 0.3 Vp-p

Item

Symbol Min. Typ. Max. Unit

tR tF

tWHX

tWLX

tCK

VILX

VIHX × 0.1

V

IHX × 0.9

VIHX

XTAI

V

DD/2

– 9 –

CXD3009Q

2. CLOK, DATA, XLAT, CNIN, SQCK and EXCK pins

(VDD = AVDD = 3.3V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

∗

In pseudo double-speed playback mode, except when SQSO is Sub Q Read, the maximum operating frequency for SQCK is 300kHz and the minimum pulse width is 1.5µs.

3. BCKI, LRCKI and PCMDI pins (VDD = AVDD = 3.3V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK SQCK frequency EXCK SQCK pulse width

fCK

tWCK tSU tH tD tWL

fT fWT

750 300 300 300 750

750

∗

0.65

∗

MHz

ns ns ns ns ns

MHz

ns

Item Symbol Min. Typ. Max. Unit

tWCK tWCK

1/fCK

tH

tSU

tWL

tD

1/fT

tWT tWT

tH

tSU

CLK

DATA

XLT

EXCK

CNIN

SQCK

SQSO

SBSO

BCK pulse width DATAL, R setup time DATAL, R hold time LRCK setup time

tW tSU tH tSU

ns ns ns ns

Item Symbol

Conditions

Typ. 94 18 18 18

Min.

Max. Unit

VDD/2 VDD/2

tW(BCKI)tW(BCKI)

tSU

(PCMDI)

t

H

(PCMDI)

tSU

(LRCKI)

BCKI

PCMDI

LRCKI

– 10 –

CXD3009Q

1-bit DAC, LPF Block Analog Characteristics

Analog Characteristics (VDD = AVDD = 3.3V, VSS = AVSS = 0V, Ta = 25°C)

For both items, Fs = 44.1kHz. The total harmonic distortion and S/N ratio measurement circuits are shown below.

LPF External Circuit Diagram

Block Diagram for Measuring Analog Characteristics

Item

Total harmonic distortion

S/N ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

Crystal

1kHz, 0dB data

(using A-weighting filter)

384Fs 768Fs 384Fs 768Fs

90 90

0.015

0.015 94 94

0.025

Min. Typ.

Max. Unit

%

dB

Audio Analyzer

SHIBASOKU (AM51A)

100k

22µ

680p

12k

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Audio Analyzer

CXD3009Q

Rch A

Lch B

DATA RF

TEST DISC

768Fs/384Fs

– 11 –

CXD3009Q

(VDD = AVDD = 3.3V, VSS = AVSS = 0V, Topr = – 20 to +75°C)

Output voltage Load resistance

VOUT RL

∗1 ∗1

Vrms

kΩ

Item Symbol

20

Min.

Max.

0.70

∗

Typ.

Applicable pins

Unit

∗

Measured using the circuits on the previous page when a sine wave of 1kHz and 0dB is output.

Applicable pins

∗1

LOUT1, LOUT2

– 12 –

CXD3009Q

Description of Functions

1. CPU Interface and Commands

• CPU Interface

This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.

• Information on each address and the data is provided in Table 1-1.

• The internal registers are initialized by a reset when XRST is low; the initialization data is shown in Table 1-2. Note) When XLAT is low, SQCK must be set high.

750ns or more

Data

Address

750ns or more

300ns max

Valid

CLOK

DATA

XLAT

Registers 4 to E

D1 D2 D3 D0 D1 D2 D3

– 13 –

CXD3009Q

Command Table

Table 1-1

Register name

4

5

6

7

8

9

A

B

C

D

E

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B)

Kick (D)

Auto sequence

(N) track jump

count

MODE

specification

Function

specification

Audio CTRL

Serial bus

CTRL

Servo coefficient

setting

CLV CTRL

CLV mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

2048

VCO

SEL1

0

TRMI

—

VP7

EPWM

—

1024

0

TRMO

—

VP6

SPDC

—

512

SOCT

0

OPSL20OPSL2

1

MTSL1

—

VP5

ICAP

—

256

VCO

SEL2

SYCOF

EMPH

MTSL0

—

VP4

SFSL

—

128

KSL3

OPSL10OPSL1

1

SMUT

0

—

VP3

VC2C

—

64

KSL2

MCSL

AD10

0

—

VP2

HIFC

—

32

KSL1

0

AD9

0

—

VP1

LPWR

—

16

KSL0

0

AD8

0

—

VP0

VPON

—

8

0

ZDPL

AD7

—

Gain

CAV1

—

4

0

ZMUT

AD6

—

Gain

CAV0

—

2

VCO2

THRU

—

0

AD5

—

0

—

1

0

—

0

AD4

—

0

—

0

—

0

AD3

—

0

—

DCOF

AD2

—

0

—

0

AD1

—

0

—

0

AD0

—

TXON

—

FMUT

—

TXOUT

—

LRWO

—

OUTL1

—

BSBST

—

OUTL0

—

BBSL

—

AS3

0.18ms

0.36ms

11.6ms

32768

CDROM

0

SL1

Gain

MDP1

0

CM3

AS2

0.09ms

0.18ms

5.8ms

16384

DOUT

Mute

DSPB

ON/OFF

DSPB

ON/OFF

0

SL0

Gain

MDP0

TB

CM2

AS1

0.05ms

0.09ms

2.9ms

8192

DOUT

ON/OFF

0

Mute

CPUSR

Gain

MDS1

TP

CM1

AS0

0.02ms

0.05ms

1.45ms

4096

WSEL

0

ATT

0

Gain

MDS0

Gain

CLVS

CM0

Command

Address

D3 D2 D1 D0

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0

Data 3

D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

– 14 –

CXD3009Q

Reset Initialization

Table 1-2

Register name

4

5

6

7

8

9

A

B

C

D

E

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B)

Kick (D)

Auto sequence

(N) track jump

count setting

MODE

specification

Function

specification

Audio CTRL

Serial bus

CTRL

Servo coefficient

setting

CLV CTRL

CLV mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

—

1

0

—

0

1

—

1

0

—

0

—

1

0

—

1

0

—

0

—

0

—

0

—

0

—

0

—

0

1

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

1

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

Command

Address

D3 D2 D1 D0

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0

Data 3

D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

– 15 –

CXD3009Q

1-1. The meaning of the data for each address is explained below. $4X commands

RXF = 0 FORWARD RXF = 1 REVERSE

• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the Track jump/move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is

interrupted.

$5X commands

Auto sequence timer setting Setting timers: A, E, C, B

Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)

A = E = C = 0.11ms B = 0.23ms

$6X commands

Auto sequence timer setting Setting timer: D

Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)

D = 10.15ms

$7X commands

Auto sequence track jump/move count setting (N)

This command is used to set N when a 2N-track jump and an N-track move are executed for auto sequence.

• The maximum track count is 65,535, but note that with 2N-track jumps the maximum track jump count is determined by the mechanical limitations of the optical system.

• The number of tracks jumped is counted according to the signals input from the CNIN pin.

CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE

0 0 1 1 1 1

0 1 0 0 1 1

0 1 0 1 0 1

0

1 RXF RXF RXF RXF

Command

AS3

AS2

AS1

AS0

Blind (A, E), Over flow (C) Brake (B)

0.18ms

0.36ms

0.09ms

0.18ms

0.05ms

0.09ms

0.02ms

0.05ms

Command

D3

D2

D1

D0

KICK (D)

11.6ms

5.8ms

2.9ms

1.45ms

Command

Data 1 Data 2

Data 3 Data 4

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

2152142132122112102928272625242322212

0

Auto sequence track jump count setting

D3

D2

D1

D0

– 16 –

CXD3009Q

Command

D3

CDROM

DOUT

Mute

DOUT

ON/OFF

WSEL

VCO

SEL1

0

SOCT

VCO

SEL2

KSL3 KSL2 KSL1 KSL0

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 1

Data 2

MODE specification

Data 3

Command bit

C2PO timing

CDROM = 1

CDROM = 0

See Timing Chart 1-1.

CDROM mode; average value interpolation and pre-value hold are not performed.

Audio mode; average value interpolation and pre-value hold are performed.

Processing

Command bit DOUT Mute = 1 DOUT Mute = 0

Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted.

Processing

$8X commands

Command bit DOUT ON/OFF = 1 DOUT ON/OFF = 0

Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin.

Processing

Command bit

Sync protection window width WSEL = 1 WSEL = 0

±26 channel clock

∗1

±6 channel clock

Anti-rolling is enhanced. Sync window protection is enhanced.

Application

See the $BX commands.

∗

1

In normal-speed playback, channel clock = 4.3218MHz.

D3

0 0

VCO2 THRU

0 0 0 0 0 TXON

TXOUT OUTL1 OUTL0

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 4 Data 5 Data 6

– 17 –

CXD3009Q

Command bit

VCOSEL1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/1 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/2 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/4 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/8 frequency-divided.

KSL3 KSL2

Processing

∗1

Approximately twice the normal speed.

Command bit

VCOSEL2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Wide-band PLL VCO2 is set to normal speed, and the output is 1/1 frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/2 frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/4 frequency-divided.

Wide-band PLL VCO2 is set to normal speed, and the output is 1/8 frequency-divided.

Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/1 frequency-divided.

Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/2 frequency-divided.

Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/4 frequency-divided.

Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/8 frequency-divided.

KSL1 KSL0

Processing

∗2

Approximately twice the normal speed.

– 18 –

CXD3009Q

Command bit

TXOUT = 0

Processing

Various signals except CD-TEXT are output from SQSO pin. See $BX commands. CD-TEXT data is output from SQSO pin.

∗

See "4-9. CD-TEXT Data Demodulation".

TXOUT = 1

Command bit

OUTL1 = 0

Processing

WFCK, XPCK and C4M are output. WFCK, XPCK and C4M outputs are set to low.OUTL1 = 1

Command bit

OUTL0 = 0

OUTL0 = 1

Processing PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are set to low.

PCMD and PCMDI, BCK and BCKI, LRCK and LRCKI, EMPH and EMPHI are connected inside the IC, respectively. At this time, set PCMDI = BCKI = LRCKI = EMPHI = low.

Command bit

VCO2 THRU = 0

Processing V16M output is connected to VCKI inside the IC. Set VCKI to low in this time.

V16M output is not connected to VCKI inside the IC. Input the clock from VCKI in this time.

∗

These commands are used to set the internal or external connection of VCO2 used in CAV-W mode.

VCO2 THRU = 1

Command bit

TXON = 0

Processing Set TXON to 0 when the CD-TEXT data is not demodulated.

Set TXON to 1 when the CD-TEXT data is demodulated.

∗

See "4-9. CD-TEXT Data Demodulation".

TXON = 1

– 19 –

CXD3009Q

Timing Chart 1-1

Rch 16-bit C2 Pointer Lch 16-bit C2 Pointer

If C2 Pointer = 1,

data is NG

C2 Pointer for upper 8-bits C2 Pointer for lower 8-bits

Rch C2 Pointer

C2 Pointer for upper 8-bits C2 Pointer for lower 8-bits

Lch C2 Pointer

LRCK

CDROM = 0

CDROM = 1

C2PO