Sony CXD2701Q Data Book

IB

2

®

Semiconductor

IC

Semiconductor Integrated

1992

Circuit Data

Book

List of

Index

Description

Digital Filter 1C

A/D, D/A

Model Names/

by Usage

Converter

ADSP

(Audio

Signal

Digital

Interface IC

Digital

Processor)

Audio

Semiconductor Integrated

1992

Circuit Data

Book

SONY,

This

is the 1992 version

semiconductor

In preparation

been

collected and

products

Sony products. If,

welcome

suggestions

of

this data

added with

however,

and comments.

PREFACE

of

the Sony

manufactured

book,

a

you are dissatisfied with this

semiconductor IC

and marketed by Sony.

much

as

view

characteristic and application

of making this book a convenient

data book. This book

data as possible have

reference

book in any way, please

covers all the

for

users of

write; we

Sony reserves the right to change

Application circuits

Sony cannot assume

for

infringement

any

Unauthorized

shown are typical examples illustrating

responsibility

of third

reproduction

party patent

of

products

for

any problems arising out of

the

contents,

and

other

even

-3-

specifications

right

due to same.

partial,

is prohibited.

without prior notice.

the operation of

of

the use

these

the devices.

circuits or

Sony

Semiconductor

Data

Books

The following data

In addition, a List of

market,

is issued twice

Data books

offer information pertaining to the

available

are

books

Devices

1. TV

2. Video

3. CCD

4.

5. Digital

6.

7.

8. Radio

9.

10. ECL

11.

12.

13.

14. Laser Diodes

Recorder

Image Sensors &

Compact

Audio

Audio ICs

Analog

Floppy Dish/Hard

Communication

A/D, D/A

Logic/ASS

Microcomputers

Memories

Discrete

Semiconductors

Semiconductor Products

year.

a

for

respective

the

ICs

Discplayer ICs

ICs

Disk Drive

Converters

P ICs

covering all manufactured device on the

listed products.

products

Peripheral

System

applications.

ICs

-4-

1. List

2. Index by

of

Model

Usage

Names

Contents

*

—

Page

•

6

*•

7

3. IC

4.

5.

6. Data

Nomenclature

Precautions for IC

Absolute

1)

Protection

2)

Mounting

3)

Quality

Sheets

Digital

1)

A/D,

2)

ADSP (Audio

3)

Digital Audio interface

4)

Application

maximum

against

method

Assurance and

Filter IC

D/A Converter

Digital

*

ratings

electrostatic

Reliability

Signal Processor)

IC

breakdown

*

•

8

10

11

15

17

*

23 23 75

105

•

203

1. List

of

Model

Names

Type

CXD1160AP/AQ

CXD1211P

CXD1244S

CXD1355AQ

Page Type

107 CXD2552Q 77

205 CXD2554M/P

25

159 CXD2557M 67

CXD2555Q 94

Page

Type

CXD2560M

38 CXD2561BM

CXD2701Q 179

Page

49

85

-6-

2. Index

by

Usage

Digital Filter

1)

IC

Type

CXD1244S

CXD2554M

CXD2554P

CXD2560M

For middle class and sophisticated

Filter length 213, 16/18-bit output. Attenuate

For

popular

16/18-bit output.

8fs,

Filter length 213, 18/20-bit

deemphasis

version,

Attenuate

4/8fs,

CXD2557M Audio data zero detection

A/D, D/A Converter

2)

Type

CXD2552Q 1-bit D/A converter

CXD2561BM 1-bit D/A converter, 3rd order

A/D-D/A converter, Built-in digital

CXD2555Q

ADSP

3)

Type

CXD1160AP

CXD1160A0 CXD1355AQ

CXD2701Q

(Audio Digital Signal Processor)

1-bit

order

2nd

Software realized various digital audio data. Double accuracv

Programmable

for surround

shaper

noise

arithmetic possible

DSP

and 8 is

Programmable DSP— Equalizer for surround

Characteristics

and Riving

realized by fixing algorithm at

coefficient

Functions

versions,

Filter length

deemphasis

output. Attenuate,

Functions

noise shaper

Fu notions

over sampling digital filter

exterior

from

57,

4/Sfs,

deemphasis

filter,

equalizer

Page

25

38

49

67

Page

77

85

94

Page

107

159

179

I

Digital Audio Interface IC

4)

Type Functions

CXD1211P

Digital

data modulation,

audio

-7-

Transmission

Page

205

Nomenclature

1)

Currently,

products.

Conventional

(1)

[Example]

New nomenclature

(2)

[Example]

3. IC

of IC product name

both

the conventional and new nomenclature systems

Nomenclature

nomenclature system

CX

2,0

Oil A

'

—

Improvement

"A" is affixed

improved.

Product number

Identities

Category number

indicates

3:dd3-

MOS IC:

—

SonyICmark

C X A 1 1 A P

Package mark

P: Plastic Dual In-line

D:

Ceramic Dual

M: Small

L: Single

Quad Flat

Q:

S: Shrink Dual In-line

N: Very

R: Very Small

Improvement

"A" is affixed

Product number

Identifies

category

Microcomputer

mark

IC

number

hybrid IC mark

S)

Q,

individual product.

mark

Identifies

individual product,

Absolute

1}

The maximum

devices

are

maximum maximum

ceeded

even for

If the

maximum

device

deterioration

immediately. device

can

ably

shortened.

IC maximum

The following

for

ICs.

Maximum

(1)

(Vdd)

The

maximum

between

related to the

in

destroyed if

(2)

in

tion will

the (3)

operate

and

teristics

damaged.

at Ta

temperature

(4)

which

age material,

the

(5)

input current

other values

the power

This power

the internal

Allowable

The

maximum

IC.

Usage beyond

cause

ICs

heat

Operating

The

temperature

satisfactorily.

Even if this

some

is

For some

=

25'C

Storage

The

temperature

is

not

This

temperature

semiconductor.

Other values

The

input voltage

4,

maximum

normally

ratings".

ratings

operate,

ratings

Precautions for

ratings

ratings for

specified

The values shown in

table must never be ex-

a moment.

rating is ever

or damage will occur

Then,

the life will

even

if

maximum ratings

power supply voltage Vcc

voltage

supply

dielectric

circuit

this

voltage

power dissipation Pd

power consumption

the Allowable power

ultimate

generation.

ambient

temperature range

deterioration

noted,

ICs, the

are

not guaranteed

range.

temperature

operating.

and

lin,

may

that can

supply

pin and ground pin.

voltage

rating is directly

voltage

The transistors may

is exceeded.

destruction through

temperature

range within

in operating

the

IC is

electrical

characteristics

Tstg

range for

is restricted

intrinsic

the

Vin,

output voltage Voat.

output

current

be specified in

semiconductor

"absolute

by

exceeded,

the affected

consider-

be

are

used

be applied

of transistors

allowed

dissipa-

Topr

which

IC can

is exceeded

charac-

not always

even

storing

in

the

this

by the pack-

properties of

lout and

some ICs,

the

be

IC

IC Application

A

general example

Absolute

Main

In the circuit

ratings must

designed

situations

If this

ceeded, electrical

result.

This

gration in

Maxium

Ambient temperature

points on Circuit

design the

not

only after

among

•

Fluctuation in

•

Scattering

tics of electrical

tors,

capacitors,

•

Power dissipation

•

Ambient

•

Fluctuation

•

Abnormal

allowable

value

package

temperature

pulses

varies

Ratings.

be exceeded,

the following:

source

in the

in

input

and

types.

on the relation with

No assurance

Tstg

('Q

design.

absolute

considering

voltage

electrical

parts

(transistors,

etc.)

in circuit

signal

power

dissipation

thermal

with

amount

maximum

and

it must be

the worst

characteris-

adjustment

damage may

of IC inte-

Ta curve

resis-

is

ex-

-

10

Protection

2)

electrostatic

against

breakdown

There have been problems concerning

electrostatic destruction of electronic devices

the 2nd World War.

since

related to the advancement made in

of semiconductor devices; this

development

of semiconductor

Those

are closely

the field

with

is,

the

technology,

new problems in electrostatic destruction

have arisen. This situation, perhaps, can be

understood by recalling

Electrostatic destruction is again

people's

of LSI, VLSI, and ULSI. Here are

tions

device

Factors

generation

attention

for preventing

fabrication

causing electrostatic

in manufacture process

number of dielectric materials are used

A

manufacture process.

rials with the substrate can

electricity

ductor

which

device.

Factors that can cause

truction

in the manufacture process are

the

case of

we are entering the era

as

destruction in the

such

process.

Friction of these mate-

generate static

may destroy the

electrostatic des-

MOS

our

semicon-

FET.

drawing

sugges-

shown below:

Causes of

electrostatic

semiconductor parts in manufacture

process

Input

1

semi-

conductor

resistor

capacitor

solder dipping

visual correction

in

lead cutting

sand

Parts

mounting

-

J

1

blasting

destruction

Item

•

belt conveyer

•

work

table

•

human body

•

Parts hox

•

dipping machine

•

work table

•

human

•

body

soldering iron

cutting machine

•

sand blasting

machine

of

soldering correction

rear side

of parts

frame

inspection and

-

11

1

mounting

assembly

.

Output

repair

•

belt conveyer

•

work table

•

human body

•

parts box

*

soldering iron

Handling precautions for the prevention of

electrostatic

Explained below

be taken in fabrication

electrostatic

devices.

The following

©Equalize potentials

sporting or storing.

destruction

are procedures

destruction

basic

rules

of

that must

prevent

to

semiconductor

of

must be

terminals when tran-

the

obeyed.

©Equalize the potentials of the electric

device,

that may come in contact with the semi-

work

bench, and operator's

body

conductor device,

©Prepare an environment that does not

generate static electricity.

One method is keeping

the work

room

to

relative

about 50%.

Operator

Clothes

(1)

Do not use nylon,

rials which easily

For clothes, use cotton,

materials. Wear

protective clothing for static electricity

rubber

generate static

or

gloves

during

humidity in

and other mate-

electricity.

antistatic-treated

operation.

example

When

using

connect a

hand for

(3)

the semiconductor device when holding.

Limit the number of handling times to a

safety.

Handling of semiconductor device

touch

Do not

minimum. Do magazine or package

lutely necessary.

holding

of

grounding band

,

-

snap

a

wire for grounding,

copper

IMn resistance

lead.

the

not take

of

the

box

semiconductor

cotton glove

,,-groundirig wire

series near the

in

Touch the body

device

out

unless it is abso-

device

of the

of

grounding mat

\\X\X^

Grounding of

(2)

The

operator

wrist

strap

operator's

should connect the

his arm.

to

cotton

strap

gloves

-ground

Conductive gown

body

specified

DIP

:yp^

Equipment and tools

Grounding of

(1)

Ground

to be used. Check insulation beforehand

the

prevent leakage.

equipment and tools

equipments and tools

[Check point]

•

measuring instrument

•

conveyer

•

electric deburr

•

carrier

•

solder dipping

•

lead cutter

•

shelves and racks

-

12-

brush

tank

can type

that are

to

grounding

conductive sheet

of

carrier

Transporting, storing

methods

Magazine

(1)

conductive, or

Use

magazines,

tic IC

magazine

packaging

and

antistatic-treated

plas-

Grounding

(2)

Ground the

not put

electricity,

static

table.

work

grounding

Semiconductor

(3)

Use a

Insertion of

(4)

Insert the

of work

work

table

anything

which can easily

such as foam

of work

conductive sheet

device case

conductive case,

semiconductor

semiconductor device

mounting process or on

should

of

be

the

lead

plastic

The insertion

sheet.

points of caution

Other

(5)

Take

note

removing

for

used

antistatic-treated

table

as

table

the belt

done on a

of brush

kind

chips. Use

brushes.

illustrated.

generate

styrol, on the

grounding

device

during the

conveyer.

conductive

material

metal or

wire

Do

(2)

Bag

conductive bag to store

Use a

conductive

bag

conductive bag

magazine

I

ICs.

13-

Handling

(3)

The

strates

Do not

box,

ated.

delivery

must

use a

otherwise

delivery

of

used

box

made of

be

vinyl chloride

electricity

static

handling

of

box

for carrying

conductive

acrylic

or

delivery

will be

box

sub-

plastic.

delivery

gener-

Soldering

(1)

Use a

and an

(DC 500V)

10MQ

energizing.

example

operation

iron

soldering iron

insulation

of solder

with a

resistance

five minutes

after

tip

iron

grounding

greater

grounding

wire

than

from

Treatment

(4)

truck

After

package

work

rack,

Handling

(5)

as

When

ally,

use

cotton

Wear

possible,

handling

sure

be

polyethylene bag.

a

handling of mounted

conductive

after vehicle

transport,

delivery

box or

for

table

of mounted

gloves when

avoid touching

mounted

to use

conductive

plastic

grounding plate

place the

box

discharging.

substrates

conductive

a

^cotton

bag

transport

magazine,

the

on

handling.

soldered

bag.

substrate

glove

grounded

far

As

faces.

individu-

not

Do

Operation

(2)

After

the

into

possible.

inserted

Correction

(3)

When

and CR parts)

device

wear cotton

sure to

Manual

(4)

Solder

hand.

Removing

(5)

not use the

Do

semiconductor

the

equivalent.

or

soider-wick

77T

inserting

substrate,

Do

the

not carry

semiconductor

correcting

soldering

with wrist

semiconductor

Solder-Pult

device. Use a

solder

adjuster

voltage

output

24V

6 to

semiconductor

it as

solder

substrate with

the

device by

(semiconductor

parts

solder-dipping, be

after

gloves.

connected to

strap

when

remover

4

device

quickly as

the

car.

the

device

removing

Solder-wick

so.er pult

- 14-

Mounting

3)

Soldering and severability

Severability by JIS

(1)

JIS

specifies solderability of an

(lead) in "JIS-C7022 Test Procedure

method

IC

An abstract of this standard folfows;

flux

Rosin

must be dipped in it for

•

H63A

and

solder which been heated

for

•

Using

{%)

that

should

must

be used, and

or equivalent solder

the terminal must

5±1

seconds,

a microscope, measure

deposited with solder.

more than

be coated with

95%

device main

the

5-10

seconds.

must be used,

be dipped

230

to

the

specifies

JIS

of the total area

solder.

body

nw

for soldering warranty

Area

(2)

Soldering

terminal

A-2".

tion of the

shown in the following figure.

The tie-bar cut

terminal

in

the

i

C±5

area

warranty area for soldering

dam to

during device

end of the

exposed at the

:

dering is

C

resin is often covered with

with

area.

cut

tie-bar

prevent

restricted.

resin ;

portion

/

is warranted

terminal.

the sealing resin flowing out

fabrication; it is

process. Since the terminal

cut-off end, the

not in the soldering warranty

it is

for a specific

The warranted portion is

portion also

The

serves

cut offatthe

area

portion near the

burrs when sealing

for

as

por-

a

is

sol-

I

Resistance to soldering heat

Specification

(1)

specifies the method for

JIS

resistance to soldering

for guaranteeing the

used

against thermal stresses by

abstract

of this standard is as

•

the device terminal only

Dip

JIS

of

heat.

10±1 seconds in a solder

3±g-

for

bath of

or

350 C±10'C,

1.5 mm

260'C±5*C,

solder

tance of up to 1 to

main body.

testing

method

This

resistance

IC

soldering.

follows:

bath of

5

seconds

for a dis-

from the

the

An

once for

in

is

a

-15-

For the solder flow system

should be 260'C±5'C.

soldering

iron temperature should be

temperature

To solder

350*C±10"C.

•

Leave the

hours after dipping, then measure

device

•

Normally,

seconds at 260'C±5'C.

between the device main body

bath

device for more than two

characteristics.

the warranty is limited to 10

The

1.6 mm.

is

and solder

by

the

distance

Resistance

(2)

to soldering heat

when

mounting infrared reflow.

When

surface

etc) are dipped

the device

orate and thermal

the pallet.

Carefully

mount devices (SOP,

directly into a solder

moisture

observe

resistance may

generate cracks in

stress

the mounting

pot,

conditions,

Recommended temperature profile when

mounting infrared

figure

below.

reflows is shown

QFP

deteri-

in the

1

20*C

'

^,

preheated

4-C/set /

3 to

50 to 300 set

part reflow

235'CnTa*

\

10 see.

part

-»

time

-

16

5. Quality

Assurance

and

Reliability

The Concept to

There are 2

Sony

What

convincingly

Quality,

of

involves

ess. The

superior

fundamental

Semiconductors.

Customer

1,

2. Top level

comes first is the

to

Delivery, Cost

all operations

second

accomplishment.

demanded to

quality is concerned,

where

activities.

ed

effect an

this

To

assurance

ity

early stages

well into

production,

Quality

Assurance

principles

satisfaction

performance

ability to

given requirements

and

involved in

requisite is the

Here,

customer

fulfill

and

elaborate

is firmly

of research

system

established.

and

sales and

guiding

respond

in terms

Servicing.

the proc-

quest for

talent is

expectations,

pursue

of

From the

development

servicing,

This

relat-

qual-

orderly

high

of

control is

standards

applied for

Systematization and

ahead to

quality

In

plementing

ject to

aware of

are at the

their

With the

nomical,

time the most

quality is

relentless

provide

production.

respect, the force

this

the

constant

problems

the

of the

core

yield.

aim of

the most

criterion, Sony

the

urge for

program is

polishing.

gratifying

maintenance

the

improvement.

further

and

automation are

a stable output

in charge

nonetheless

Gifted people

inherent to

excellence

providing

useful

the most eco-

and at the

products

keeps

achievement.

pushed

of

tasks

their

reflected

where

fueling a

high

im-

sub-

well

on

same

I

-

n-

Quality assurance

system

of semiconductor

products

* L, IPQC

:

PrtCflSB Qua.

In

*2. Qai

: Quality

-

18-

14 y CaBttCl

Assurance Test

Quality

reliability test

1)

fabrication is

and

devices at a

assurance

Quality

Establishing

reliability

criteria

assurance in

quality

essential to keep

levels of

high

"Zero-defect" (ZD)

pling

on

checks,

products

in units of

criteria and

level.

movement.

have been

that

shipping

design

in the

semiconductor

the

This is

shipping lot,

the

done by

Further

"totally-

and in

quality

the

sam-

is done

the

inspected"

ensuring no

inspection is

at

detective items.

done

STD-105D.

Reliability

2)

The reliability

confirm reliability

fabrication

final

in accordance

test is done,

level.

stage,

sampling

This

with MIL-

periodically,

thus

to

Periodic

Electrical

Life Test

Environmental

Mechanical Test

Other Tests

"These tests

Reliability

Characteristics

LTPD: Lot

These tests

also serve to

Test

selected by

are

Tolerance

and

forecast

Test

Item

Test

temperature

high

temperature

high

humidity

pressure

soldering

cycle

heat

solderability

strength

length

If

necessary,

JIS C7021 C7022

sampling

Defective

Percent

inspection

reliability at

with

cooker

heat

standard.

data

operation

and

bias

resistance

are

tests

and EIAJ S0121

useful not

are

the

high

selected

consumer

according

IC121.

only

level.

In order to

level some

tested

to

improve

to

Testing

know the

types

again.

to

up

to 1000

up

to

up

100

Japan

Standard

design and

time

initial quality

are selected and

LOOOh

h

200

10s

cycles

Industrial

(JIS)

wafer

LTPD

10%

10% 10%

15%

15% 15%

processes,

I

but

19-

s

Reliability

High temperature

operation

High

with

High

Storage

Low

storage

High

high

High

high

Pressure

Temperature

Heat

Soldering

Solderability

Mechanical

Vibration

Constant

Free

Lead strength

(bend)

CPU")

Electrostatic

LTPD:

Test

Standards

Types of

temperature

bias

temperature

humidity

temperature and

humidity

shock

fall

Lot Tolerance Percent Defective

test Condition

and

storage

with bias

cooker

cycle

heat

resistance

shock

acceleration

strength

=

Ta

125'C, 150"C Typical

=

Ta

125C, 150'C

=

Ta

150'C

=

Ta

-65*C

=

Ta

85*C

Ta=85'C

=

Ta

121°C 100%RH

203k Fa

=

Ta

-S5C to

=

Ta

-6SC to

T

solder=260'C

T

solder=230"C (rosin

X, Y. Z

Haif part

X, Y,

10Hz to 2000Hz

Sinusoidal wave

X, Y,

2 200, 000m/

Centrifugal

Free fall from the height

plate

Device

strength

under the

RH

85%

RH

85%

+

150'C 100c

+

150'C

lS,O00m/s'

of sinusoidal

G 200m/s-

10Hz (4min)

to

vibration

acceleration

must

be designed again, when

below Standard

condition of

type flux)

wave of 0.5ms

1

based on JIS

supplying surge

=

C

Supply

voltages

Typical

of 75cm

200pF and Rs

to maple

Testing

3times for

each

16minutes for

each

lminute

for

electrostatic

voltage

=

0fi.

time LTPD

lOOOh

96h

100c

10s 10%

5s

direction

each direction

3times

to each pin

5%

10% 10%

10%

-20-

Flow Chart from

Development

Manufacturing

to

Sony attains

devices

them

with

sufficiently in each step

high quality and high

quality and

Product

Trial

reliability

Planning

Product

Business Planning

Planning

Examination of

Specification

Desired

Development

Acceptance of

and

Manufacturing

Large

Manufacturing

Planning

Reliability (I)

Scale

reliability of

from the initial steps

development.

of the

Review

Quality

Review

Trial

semiconductor

of

Mask,

Customer

Characteristics,

Quantity and

of

Evaluation

Function,

Schedule,

Circuit,

Characteristics,

Acceptance

products by

development and

Quality and

Cost

Wafer Process

Quality

Quality and Reliability

and Packaging

Reliability

and

designing

evaluating

Reliability

I

for Design

Evaluation

Acceptance

and Reliability (It)

Production

of Quality

Approval

Production

Shipping

^

|^*~

Characteristics,

Acceptance of

21

Quality and

Reliability

Reliability for

Production

Package

Name

Symbol

D

S 1 P

Standard

'

Shrink

2 t

PGA

PIGGY

BACK

SDIP

SZ1P

Q

Standard

ilat

package

SOP

Standard

2-direction

carrier

chip

8

1

Shrink flat

package

Standard chip

carrier

*P Plastic. C Ceramic

S

VQFP

vsop

TSOP

Q

Package

1

P

!'

F P

J

F

j

F K

name

Description

DUAL

IN-LINE

PACKAGE

SINGLE

IN-LINE

PACKAGE

ZIG-ZAG IN-LINE

PACKAGE

GRID

ARRAY

PIGGY

BACK

SHRINK

DUAL

IN-LINE

PACKAGE

SHRINK

ZIG-ZAG

IN-LINE.

PACKAGE

QUAD

FLAT

L-LEADED

PACKAGE

SMALL

OUTLINE

L-LEAUED

PACKAGE

SMALL

OUTLINE

J-LI-ADED

PACK

AUK

VEK'l

SMALL

QUAD

FLAT

PACKAGE

VERY

SMALL

OUTLINE

PACKAGE

THIN

SMALI

OUTLINE

PACKAGE

QUAD

FLAT

J-LEADEI)

PACKAGE

QUAD

FLAT

NON-LEADED

PACKAGE

Package

*f0^

w

<SJ

0>

^^"^

'"

1

''^^P^

00*

0fa

o

+

Maori: *

1

P

C

P

c

P

p

p c

p

p 05mm

p

c

Lead pitch

2,54 mm

(lOOMIL)

2.04mm

(11)0 MIL)

2,54 mm

(100MIU

ZigZag

in-line

2,54 mm

(IMMIL)

2.54mm

(100 MIL)

LTTBnm

(JIIMIL)

l.ijfimm

(70MIL)

Hg-Zng

in-line

10mm

D.Bmm

D.65mrn

L27:nm

(SDMIL)

1.27 mm

(50 MIL)

0.55mm

0.5mm

(0.55mm)

l.27mm

(50MIL)

1.27mm

(50MIL!

Features

Lead

Through

Hole Lead

Through

Hole

]j3ad

Through

Hole Lead

Through

Hole

Through

Hole Lead

Through

Hole Lead

Through

Hole

Lead

Gull-

J-l

Gull.

Gull-

J

Lead

Wing

,-..,:!

Wing

Lead

shape

leu

LC5C

F-

direction

yul

2

-direction

1

-direction

1

-direct ion

Package

under

side.

2-direction

1-direction

4-direction

2-di recti

2-directiors

4-direction

2 -direct

2-dtreerion

4-direction

Package

under

side

on

Uin

-22

Digital Filter IC

1)

Digital

Filter IC

Type

CXm

9AAG.

For middle class and sophisticated versions, 4/8fs.

Filter length 213,

CXD2554M For popular version,

CXD2554P

CXD2560M

16/18-bit output.

Sfs, Filter length 213. 18/20-bit output. Attenuate,

deemphasis

Functions Page

16/18-bit

4/8fs,

Attenuate

CXD2557M Audio data zero detection

output. Attenuate deemphasis

Filter length

57,

deemphasis

25

38

49

67

-24-

SONY,

CXD1244S

Digital Filter for

Description

CXD1 244S is a

over sampling rate,

Features

•

Built-in 4-times/S-times sampling digital filter for 2

channels.

Ripple within 0.00001 dB

•

Attenuation

•

Noise shaping,

•

Soft muting, de-emphasis and a

functions.

Application

Compact disc

Structure

Silicon gate

Absolute Maximum

•

Supply

«

•

voltage

Input voltage

Storage

Allowable

Recommended

•

Supply voltage

•

Operating

•

frequency

OSC

digital filter LSI with 4-times/8

developed

within

-100dB(24.1k

Attenuator

player

CMOS IC

Ratings (Ta=25°C)

temperature

power dissipation

Operating

temperature

Conditions

for compact disc

Player

CD

).

wide variety

-0.5

Vdd

Vi -0.5

Tstg -55

Pd

Vdd 4.75 to 5.25

-10

Topr

fx 12,0 to

-times

Package

player.

of built-in

+6,5

to

to Vdd +0.5 to +150 °C

500

+60 X

to

18.5

MHz

Outline

L-.-™uuuiiuuin.....

V

mW (Ta-60=C>

V

40 pin SDIP

!**»

5.3

l

..i.

(Plastic)

Unit:

r-=T

HI

SDIP-40P-12!

mm

I

25-

81114-YA

*

SONY.

Block

Diagram

M®—

Emp»-

z

1

-

McuHcurr

tj

¥ ¥ s

5

;

-

"

£ o

_j W

!d

e

t I *

COEF

oata

ft

<

i/M_l

/att-

ROM

RAM

CX312445

-9~

—

-® our^E/is

i*

SO**/

u.s.

-j

_

OF.L

s

®

MUTE

Configuration (Top View)

GND T

testi 2

ATT

Z Z

SHIFT

s

LATCH

X

SOFT

6 Si! NS

T ^T

INI

M.C.

S

X IN

GE

V»

i

V»

z

BCK

1£

DATA

Es

LRCK

E

DPOL

Ls

INAF

01 si

LFS

E

\v/£5

5 m

NX.

Z z

TE5T2

20 S

w

-26-

TESTS

Si!

TEST 7

M

"EST*

TESTS

Z

EMP

Z

APT/WS

<4|

BCKO

33]

DATAL

m

END

51]

GND

n

QATAR

M

is LRCKO

LE/WS

Z

0l!T16/te

Z

CFST

POL

Z

MUTE

TEST4

TEST

jj

3

SONY,

Pin Description

No. Symbol I/O

1 GND

2

3

TEST1

ATT Attenuate data

4 SHIFT Attenuate data 5 LATCH Attenuate data

6

SOFT Soft

7 INIT

8

9

11 Vdo

10,

NC

XIN 1

12 BCK 1 BCK input

13

14 LRCK 1

15

16

17

18

19

to 22 TEST 2 to

20

23

DATA 1 Serial data

DPOL

INAF

LFS

SONY/l

NC

MUTE Turns output to

24 DPOL 25

OFST

26 OUT16/18 Output 27 28

29

30.31

32

LEWS LE output (Sony

LRCKO LRCKO output

DATAR o

GND

DATAL o

33 BCKO

34

35

APTAWS o

NS 1

36 EMP 1

37 to 40

TEST

5 to 8

—

1 Output data

1

2

S

4

1 Output

—

1 Test

Test pin (Normally

muting

Synchronous

CLK

Master

(+5V)

Supply

fixed

input

clock input

shift

clock input

latch

ON/OFF active

with the

again

(f=384 Fs)

input

complement)

(2's

input

to

LRCK input

"L" : non inversion "H" :

polarity

When I/O sync is missed "H"

4Fs mode

Test

Offset

ON/OFF

format

pin (Normally

polarity 'L':

ON/OFF

data word length

Rch serial data output (2's

Lch serial data output

available

specified at "L": Sony, at "H":

fixed

to L'

offset value. Active at

or

(-)

'H':

(+)

at H

Active

specified

format)/WS output

(2's

BCKO output

APT output (Sony

shaping

Noise

Deemphasis

pin (Normally fixed to L'

format)AVS

Active

/OFF

ON

ON/OFF Active at

Description

"L" levei)

"H",

at

rising

edge

is

output.

at "H" only

levei)

at

{\

complement)

output

'H'

at

'H'

level)

1":

2

B

(PS

this

of

during

1

6

format)

signal.

inversion.

I'S.

2

l

S

H'.

bit at 'H': 18bit

CXD1244S

I

-27-

SONY,

CXCS44S

Electrical

DC

'H'

V input

V

Input leak

'H'

1'

AC

OSC

input BCK Input BCK

Input data

Input data Input LRCK

Input LRCK

Output BCK

Output

Output data

Output

Output Output BCK pulse width

Output

Output daki

Output BCK

Output

Output data hold time

Output

Note) Duty defined

Characteristics

characteristics

input voltage

input

voltage (Shift,

voltage (Except

input

voltage (Shift,

voltage

output voltage

output

voltage

characteristics

Item

frequency

pulse

set up

hold time

set up

hold time

pulse width

data set up time

hold time

BCK

pulse width

data

set up time

data hold time

data set up

held

pulse width

data

set up time

signal

Rise/Fall

Item

(Except

width

time

tirre

at 1/2

Shift,

Latch) VlH

Latch)

Shift, Latch) Vil-

Latch)

time

VDD, see

Symbol

Conditions Min.

—

li!

VOH lo=-2mA

Vol lo- 2mA

Symbol

Fx

Fbcx

twiB

Defined at Duty

(IDS

tlDH 20

tJLRS

tILRH

twos

tODS

toon

twOB

tODS

tODH

twos

tOI::.

tODH

twoa

toos

tODB

tfl,

tf

the

Timing

Sony

8Fs.

CL=50pF

Fx=16.9MHz

l

8Fs.

CL=50pF

Fx=:8.5MH2

Sony

8Fs BCK24

CL=50pF

Fx=1 6.9MHz

l

8Fs.

CL=50pF CL=50pF

Fx=1 6.9MHz

2

S output mode

2

output mode

S

—

Conditions

output mode

BCK24

output mode

Chart.

Typ. Max. Unit

Vdd

0.76

0.24

Vdd V

= 5

Vdd-0.5 V

0.4 V

Min.

12.0

40'

Typ. Min.

16.9 18.5

2.31

50

60

20

50 50

40

25 25

60

35

40

20

60

32

3C

V

uA

Unit

MHz

%

ns

-28-

SONYs

Timing Chart

•

Input

BCK

A

1

j

Vou/2

twia

CXD1244S

twii

_'

DATA

LRCK

Output

BCKO

DATAO

LRCKO

VooxC

^SdH—

o:T}

tF tfi

:

tlOS

"i-Voo/2

tons

Vdo/2

T.Sh

tlLRS

\/

--Vdo/2

twOB

—

"

—

h~~

W2

7

-«

t.Q

"

B

\

»-

toDH

Hy

?-

fODS

JL

Voo/2

-29-

SONY.

SHIFT

ATT

CXD1244S

twiIF

tins

LATCH

Item Symbol Conditions

Shift pulse

ATT set up time ATT

Latch pulse width TwiLA

Latch set up time

Schmitt input

width Twisf

hold

time

(SHIFT,

Vt.

Vt-

characteristics

Min. Typ. Max.

0.54xVdo

0.24xVdd 2.0

U,Oi

LATCH)

3.3 0.76xVdd

0.43xVqc V

1.0

Tias

TlAH

TlLAS

Unit

V

Voo/2

V

Min.

600 ns

300 ns

600

400

500

V

Typ. Max.

/

Unit

ns

-30-

SONY

Functions

Conceptual block diagram

An

outline

block

diagram of

this

LSI

is

shown

CXD1244S

below.

DPOL

6—

DPOL

I N

1. Noise

turning

NS

2.

shaping

For respective outputs FIR 1 to 3,

NS

to

register is

Soft

muting

By turning

Output

FIR1

noise shaping can be

"H"

cleared when I NIT

SOFT

4

"HTl",

to

amplitude

NS

-9-

FIR2

o

IR

EMP

SOFT/ATT figures are usually rounded off. However, by

MR.

applied.

is

at "L" or NS at "L".

data can be

smoothly muted or

S0

%

<U^

SOFT

ATT

demuted.

F1R3

OFST

J

°\>-OFST—

o

I

1

-6-

LFS

QOUT

I

SOFT

3. Digital attenuator

Can attenuate

output data by means

of transfer data

-

-31

from

external microcomputer.

an

SONY

CXD1244S

Command

1}

Attenuate data

The relationship between

and Audio output

is in

12

bit and

command and outpu!

Attenuate data Audio output

400 (H) dB 3FF (H)

3FE (H)

001 (H)

(H)

000

The attenuate value

ATT=20log

Example: Attenuate data

ATT=20log

Attenuator

2)

operation

Suppose that there are

Input data

1024

1018

1024

-0.0085

-0.017

-60.206

from 001 (H)

for 3FA (H)

pieces

ATT1>ATT3> ATT2 and that the place

If

next.

transferred

in Fig.l),the attenuation directly

of A

the value

before

carried on from the value at the

piece of attenuator data to

one

ATT2 is transferred

ATT2 is reached

of

can be

dB

-»

3FF (H) can

to

dB

dB=-0.051

attenuator data

of

time

another

set in 1024 steps.

shown in the chart below.

is

be obtained through the

dB

ATT1

ATT2

,

attenuator data ATT1 is

of

The value of ATT2 is reached (during the state

before.

approaches the

(during

(B or C) to approach the value

is the same as

the

value

state of B

and

ATT2. If ATT3 is transferred

of

C in Fig.1), the attenuation is

or

in

the case of softmuting.

following

ATT3

transferred first and

of

and

ATT3.

that

Transition

formula.

ATT2

from

Fig.

1

Transition

from one

attenuator value

-32-

to another

SONY

CXD1244S

data

ATT

SHIFT

timing

,

activated

DOOGGOOOOCOGCX

11 10 9 6

LSB

L^jm^ju^nnru

Input

3}

Attenuate function can be

Transfer format is indicated as follows,

LATCH

ATT data

(1)

400(H).

When Latch

(2)

With INIT at

(3)

is

a

is

|

12 bit

at "L",

. 400

word length

ATT cannot be

(H)

means

and

ATT

of

12

7

LSB first

transferred.

data.

by

is

as

set

ATT,

bit

6

transfer ATT

Shift and

Latch.

5 4 3 2

available

data is

MSB

000(H) to

I

ATT

3

OOO

POWER

SOFT

•

transition

The

•

During attenuate

•

When ATT data

4. Digital

deemphasis

turning

By

Time constant

i h)

ON

from ATT1 to

operation SOFT is set

=400 (H) Noise shaping

=400 (H)

EMP

"H", deemphasis

to

de-emphasis are

of

ATT2

takes

shaping is applied

Noise

place in soft

to either ON

is not

can be

ti=50us and

muting operation.

OFF, it turns back to the

or

applied regardless

regardless of

applied by

w=15hs

means of

at

-33-

of

NS ON or

NS ON or OFF.

IIR

f

.44.1kHz.

s

filter,

original

OFF.

ATT

data.

SONY

CXD1244S

Offset

6.

Offset

Pos/Neg

OFST

L L

H

H H

Muting

can be

selection

applied to

OPOL

X

H H

L L

of the

OUT

the output data

offset value

L

H

L

H

L

H

By turning MUTE to "H" or INIT to

offset is output. When INIT is at "L".

the

7.

Data polarity

Inversion and non

When DPOL

when DPOL

6. I/O synchronizing circuit

Principle

1)

window

A

the rising edge {LRCK

supply is

processing

turned

LRCKf the processing is

system and this LSI is

Resynchronization

2)

Even when

window, the sync

this effect it is necessary

operation is

inversion of the output data

is

is at "L",

featuring 10

on, should

in timing

LRCKf

executed

non inversion,

at "H",

inversion.

internal system clocks (XIN/2)

of

)

f

the center

with

started.

established.

means of

by

is inside the

miss with the

may

to

with the

center of the window.

Moreover, when

sync falls out

the

by means

possible as

is

16,-18

Offset

value

0000(H)

00000 (H)

02AA (H)

02AA8 (H)

FD55 (H)

(H)

FD554

output can be

the

"L"

data

is input

LRCK that is input, has

of

be out

LRCK_-

of the

Through this operation

INIT

window

mingling of

resync, without fault,

apply

INSTf timing. Sync,

of the

the

window. Synchronously

but

window. INAF output

of OFST and OPOL.

indicated

be selected by

can

entered

window the

in the following chart.

Then,

muted.

LSI.

this

to

means

set. The sync circuit

is

the window

sync

circuit stops

synchronization

with

offset value set at

the

DPOL.

of

observes

not. When the

or

the

appearance of

the

between

located close to one of the 2 edges

external noise or

after supply

circuit is

other

initialized

turns

Re sync

turned on. ReSync

is

LRCK is located

and

to "H" level.

whether

power

internal

the next

the exterior

of the

operation. To

in

the

Non synchronous MUTE

3)

When INAF is

at

H, data is output

regardless

34-

of offset

ON/OFF,

SONY

CXD1244S

9. Output format

The

output

format

^\^

pin)

signal

SOFT, MUTE.

above

DATAL. DATAR.

above indicated

10.

1)

2}

(Control

"gOTJV'lZS

LEFS

OUT16/18

(Output

LRCKO

BCKO

DATAL

DATAR

APT/WS

LEWS

I/O

Input

DPOL,

The

Output

LRCKO.

The

of this LSI

SONY

V

no effect

At

8LRCK

24BCK DATAL

DATAR

APT

LE

timing

latch

indicated input

output

will

OFST,

can be

8Fs

OPOL,

signals

APT.WS.

signals

selected as

l-S

•H'

L'

no effect

4LRCK

i 16BCK

Staggered

I

DATA

WS WS

SONY/I'S,

1N1T.

latched

are

LEWS

are iatched by

by

shown

MIX data

means

means of

chart

in the

4Fs

2

l

S

«-

*-

»

V

t-

LFS, OUT16/18,

of internal

internal

below.

MS, EMP

clocks

equivalent

to LRCK.

BCKO.

to

I

-

35

SONY

CXD1244S

3[

UL

8

SQifc

r

s o

-

c E

i=

g

- 36-

8S £

e

SONY:

CXD1244S

characteristics

Filter

-0.1990

-0.2000

£

1

-0.2005

E

-0.2010

0.0002

— 0.0001

m

8 o.oooo

i

).0

00

(for 4Fs)

Frequency

1

5

Ripple

5.0

characteristics

1

10.0

{KHz)

Frequency

characteristics

10.0 15.0

(KHz)

Frequency

Attenuate

15

20 0.0

i_^~-~~

,

20.0

characteristics

Filter

-0.1990

-0.-9S5

m

-0.2000

1

0.0001

s

0.0000

1 :

1

-0.0001

°"

_-

(for

Frequency

s.c io.o

Frequency

Ripple

5.0

Frequency

Attenuate

8Fs)

characteristics

is.o

(KHz)

characteristics

10

15.0

(KHz)

I

-50.0

100,0

132.3

jjL-Ji]

^

-50.0

1C0.0

Lid ,

3 S. 2

I

176.4 364,6

(KHz)

Frequency

I J

Ut

352.6

0.0

1

<-

ft All

L«

44.1 a8.2

0.0

Frequency

(KHz)

-37-

SONY*

9

CXD2554M/P

Digital

Description

The

oversampling

player.

Features

• A

• Filter

Ripple: ±0.1

Attenuation:

«

De-emphasis function

•

Attenuating

•

Dig

•

I/O format

Input:

Output: 2's complement MSB first

Applications

Compact

Structure

Silicon

Absolute Maximum

•

Supply voltage

• Input

•

Allowable

•

Storage

Filter for

CXD2554M/P

4-

and 8-times

characteristics

of

ital

f

set f

2's complement MSB first

(16-

disc player

gate

voltage

power dissipation

temperature

is a

digital filter

or less

5 dB

-40

dB or less

function (Buirt-in

nctio n

u

or

18-bit slot selectable)

CMOS

IC

Ratings

4-

LSI

CD

8-times

and

for

compact

a

noise shaper)

1st

(serial)

= -20

(Ta

Vcc

Vi -0.5

Pc 500

Tstg

(serial)

to +75X)

-0.5

-55

disc

to +6.5 to Voo

to +150

+0.5

V

v

mW (Ta

CXD2554M 24

CXD2554P

1

8 pin DIP

40

:

=

75

C;

SOP

(Plastic)

Recommended

•

Supply voltage

•

Operating

•

OSC frequency fx

Operating

temperature

Conditions

Voo

Topr -20

4.5

10

to to to 20

5.5

+75

-

38

V

"C

MHz (Duty 50

±10%)

E9033OB0Z-YA

SONY

CXD2554M

Block Diagram

CXD2554M/P

I

Configuration

test[T

8fs/4tt (~i~

Xour

d

<NC)[J£

V00

lNClfi~

BCKfi"

QcT

DATA

lrckQT

wrffTz

-39-

24 SLOT

23~|

LRCKO

OATAL

221

OATAR

IT]

(NO2C

vss

jg]

7a] [no

(no

77]

"^sIbcko

ATT

7?]

SHIFT

7T|

LATCH

TJ]

SONY

CXD2554P

Block

Diagram

COEFFICIENT

ROM

)[

CXD26&4WF

^C

RAM

FOR

* C

J3RDFIR

Configuration

i

—

@®

RAM FOP

3RD FIR

RAM

11TH FIR

BUFFER RAM

: x

h

swrTC--*

I

—S-e

TEST[T

8fs/4fs[7

xout[?

in[T

x

vdd[T

sckH;

[7

DATA

FOR

OFFSET

|

{

£E^D

xj-

|

P

SHAPER

NOISE

FRACTION

LATCH

I

NORMALIZE

ji]

JtJlRCKO

il

ll]DATAR

3^sslGNDI

iDbcko

ji]ATT

—A

SLOT

DATAL

RAM

FOR

=n

<vX

IIR

lrck[s

I NIT

ii]SHIFT

a

]o)

LATCH

-40-

SONY

Description

No.

CXD2554P CXD2554M

1 1 TEST I

2

3

4 4 5 6 Vdd

6

7 10 8 11 LHCK 1 LRCK

9

10

11 14

12 15

13

14 19

15

16 22 DATAL

17

18

-

2

3

9

12 'NIT

13

16

21

23 LRCKO LRCK output 24

5, 7,

8,

17,

18,

Symbol

8fs /4fe

XOUT

XIN I

BCK 1 BCK

DATA

LATCH

SHIFT

ATT 1

BCKO

(GND)

Vss

DATAR

SLOT

<NC)

20

(+5

3.

by

Description

level

FT:

8fe V.

-

(f

=

V)

rising

in

384fs)

edge

WO

pin. Fixed at 'L'

Test

I To specify

Master clock output

Mastef

-

Power supply

1 Serial data input (2's complement)

1 Re-

Latcti

1

1 Shift clock input

Attenuate

FIR

clock input (f

input

synchronized

clock input

data input

o BCK output

-

1 To specify output

-

supply

Powet

4fs mode: 8fs mode:

4fs

mode:

output

mode: LCH

8fs

connection

No

(C

WCK

RCH serial

LCH

!

complement)

s

(2

v)

output

data output

RCH time division serial data

and

serial

data output (2's

*H':

slot.

18-bit slot

CXD2554M.P

normal operation mode.

4fs

of this signal

(2's complement)

complement)

16-bit slot

V:

I

*

TEST, 8fs /4fs

and SLOT

pins:

Pull down resistance

-4]

-

—

SONY

Electrical Characteristics

DC characteristics (Voa

Pin item

All

inputs

except

Note 1

Note

TEST,

8fs

,<4fs,

SLOT

XIN Input leak current 2 llLK2

BCKO,

DATAR,

DATAL,

LRCKO

Note Note

AC

characteristics

Oscillation frequency

input Input BCK

Input Input Input LRCK Input LRCK

Output BCKO pulse width Output data set-up time

Output data hold time

Program

Latch

Rise

Fall time (SHIFT, LATCH)

Set-up

Hold time

Interval

Input capacitance ClN

XIN

"H" input

"L" input voltage Vl

Input leak current

2

Pull down

"L" input

"H" output voltage VOH Id

"L" output

Consumption current Idd

8fs

TEST,

1)

2) BCK,

time

DATA.

Item Symbol Condition Min. Typ. Max.

frequency

BCK

pulse

data set-up

hold time

data

set-up

hoid time

input

input pulse

base

(SHIFT, LATCH)

time

(ATT)

=

4.5 to ,5.5 V.

voltage

1

resistance

leak current

voltage

/W, BCK. DATA,

LRCK, (NTT. LATCH,

=

(Vdd

4.5

to

width

time

width

Symbol

5.5

tsET

Ta

= -20

+75=C)

to

Condition

Mi i

-

is

Voo/ov

:

C)

MHz

pF

0.7fi V:i

- -

-

ATT, SLOT

10 16.9344

100

20 20 50

50

40

25 25

250

500

1000

VlH

-

IlLXI

Rpd 7.5 15

IlL

Vo.

LRCK.

V.

fx

tWIB

Ids

ton

t«-BS

H-i

tl

twos

foDS

toDH

tPR

tWIT

tr

b

tHOLD

tlNT

Vi

Vdd/OV

=

V

ov

=

Vi

Vdd/OV

= -4

=

4

b

When

no load

placed Vi

=

fx

16,9344 MHz

MT LATCH, SHIFT,

SHIFT, ATT

=

-20

Ta

=

16.9344

fx

C1=50

=

fx

16.9344 MHz

to

8*8

mA Vod-0.5

mA

=

+75

Typ. Max.

3

5

- -

0.24 V.

±5

30

5

-

±20

-

0.4

40

20

4.0

-

—

-

200

CXD255UM/P

Unit

pF

V

.-

HA

ko

MA

V

mA

Unit

MHz

ns

-42

-

SONY

Timing Chart

Audio

input

CXD2554M/P

BCK

DATA

LRCK

Audio

output

BCKO

L

DATA

t

^DATA R

LRCK O

Program input

SHIFT

1st-

10%

A

f

-t

tlDS

/

tODS

•

I

tHOLO

90% gov

tPR

tWIB

A

tlDK

*

m

XZZ3C

tlLRS .

4-

twlB

-tso%

\

X

tlLBH

3(

twOB

~~^m

tWOB

.r

\

•

low

A

A.

tt

X

-J

x

y-o%

/

isr*r

MSB

"

\

LSB

JK

LATCH

43

VlOtt 10n|

|}

-

i]

SONY

Description of Functions

A.

B,

muting

Soft

The soft

(CD: fs

Digital attenuator

Output data

mute

function mutes or demutes output data

=

44.1 kHz).

can

be attenuated by use

ATT data comprises 8 bits. Bit

constitute attenuator

Command input

(1)

The attenuator data is in 7 bits,

between a command and output

data.

and

Dr is

audio output

on the

of data

the

allowing

is

transferred from an external micro computer. The

de-emphasis control bit,

digital

selection of

127 different

shown in the following table.

basis of

muting

a

whereas bits

settings.

time of

1024/fs

Ds through Da

The relation

CXDS554IAP

Attenuator

DetO

data

Do

Audio output

7F« dB

7E-!

to

OTihi

00;h;

An attenuator value between 01™ and 7E:h. can be calculated by

ATT .

Example)

ATT

synchronizing

C, I/O

Theory of operation

1)

tag

29

(*Pfif*

Suppose that attenuator

=

20 log

fl||l dB

circuit

The synchronizing

whether the

the LRCK

holds

next LRCK

the phases

Re

-synchronization

2)

if

the LRCK

could cause de-synchronization during operation of the IC (particularly

of

the

For this reason, re-synchronization must always be achieved after the turned on. The operation for re-synchronization is performed at the time

operation initializes

achieves re

differentiated

is

f

the CK2

out of the window

at the

arrives.

f

of serial input

in the window when

is

f

window).

-synchronization, thereby

-0.13

dB

to

-42.144dB

—

OO

)dB

data is 7A.

=

-0.417

dB

opens a window for six internal system clocks,

circuit

signal

time

This operation synchronizes an external system

data.

INIT

by

synchronizing

the

of

when

is in

it

the

circuit

positioning

LRCK

rise of

the power supply is turned

center of the

(LRCKf) that may

window,

power supply is turned on,

to cause a temporary

the LRCK

and lets

in the center

f

following equation.

the

CK2 (fx/4), to monitor

be input exists in it: If

on, the synchronizing circuit

start as soon as the

it

and this IC, and lines up

fluctuation of LRCK

a

when it is

power

the INIT rises.

de-synchronization

at either ero

supply has been

window.

of the

Tie

and then

-44-

SONY

CXD2S54M.P

Attenuator operation

Suppose

relations are ATT1

If ATT2 is

attenuation directly

is

the

another is the same

E. Input data

that there are three pieces

reached

time (B or

>ATT3>ATT2. Assume

transferred before

approaches the

(during

Fig. 1

timing

state of B or C

the

approach the value of ATT3,

C) to

ATT

as

Transition

in

Xi»XeHXo*X

the

from

of

value

the

value

of soft muting.

case

attenuator value to

one

*XD«XD9XcwX07

attenuator data,

that ATT1

of ATT1 is

of

in Fig,

reached (during

If ATT3

ATT2.

the attenuation is

1),

Transition from

ATT1, ATT2

is transferred

is

another

ATT3

and

followed

first,

the state of

transferred before the value

carried on

one piece of

that

and

ATT2.

by

A in Fig.

from the value at

attenuator data to

their

1),

of

the

ATT2

I

ATT data is

©

ATT data

©

F. About

After INIT is

D:- :

Dc to De:

IFfiT pin Is

»"

irLTirjiTLnnj

uATCH

Fig.

Timing of

2

configured

Digital de-emphasis

H: Emphasis ON

Emphasis OFF

L:

Note

Attenuator

}

the

,

f

on the

emphasis

that

data

counters and

ATT, SHIFT

LSB first basis.

control bit

time constants

registers for the

-45

LATCH

and

are

attenuators

IT

ti

=

50 (is

in the IC

and

=

x»

are

15

set at

fis

at fs

7F,h

=

.

44.1

kHz.

:

SONY

Digital offset

G.

An offset value

02AA0;hj in

and

In the muting mode, this offset

timing

I/O

<INPUT>

DATA

LRCK

<4fs mode outputs

BAT*

16-bit

slot mode

1 B-bit slot

DATAR

(WCKO)

a:<:

mode

is

added to

the IB-bit

d©s@sc:

JMMk.

33®©®^

mnnjiATinnnnn™

tfie digital

slot mode.

value

:

: :

:::

i3S®G©E©SSi

filter

triggers muting.

The value is 02AA:(-;

output.

3®©0®®s®®s®§®®@®c:::

=

T

1/fs

®®0®S©®®®^§0®®^.

16

in

the

-bit slot

: : :

:

3@@®®©®®®@®@§©®®c

JMI0Mi^MMM3^

CXQ2554M/P

mode

: :

UtCKO

<8fs

mode ouipul>

DATAL

slot

'16-bit

18-bit slot

DATAR

1 6-bit slot mode

18-bit slot mode

bo<o

_RC<0

mode

WMMMMMm%.

D5@S§L

P©3©&-

b@©@&

r

TJL

ATfinjmnmiriJijLrrj^^^

I

JMMd&MMMMMM^.

j%£m$33m®MM<L-

nmmm^mmpmm. f)i?mmmMpmmRfm

T vafs

-46-

=

T

t/4f

s

jMMM&^immim^

Mzm&immmm^m^^

j9®®0®®®®®8S®80®Sl

~

SONY

CXD255*M/P

Operation In

DATA-

LRO,BC«

D4T4-0UT

Note) To

Filter

0.400

o.coo

-0.400

initialize first turn on

input at

Characteristics

Frequency Characteristics

RESPONSE (dB)

POWER ON/OFF

^S*"^

1

VI

INIT

Note)

IN

.^SMS

12 CKs to XIN.

least

mBlscx

i

RJUI

3'

0"

power. After

state

Bringing

Quadrupled

1

(Pass

Der't

_^^^=

rj»n-r CCfl

~I----^

Vod reaches

INIT "H" completes

oversampling

band)

W*

25.0

=

—

__.

—

~~

—

4,5V

Frequency

RESPONSE MB)

OFT

1

__

_

and

mode

'a'

-J

the IC stabalizes

initialization.

Characteristics 2 (Stop band)

(Voo

levels

off),

-0.800

-1-200

0.400

o.ooo

0.400

-0.800

1.200

0.0 5,0

Frequency

RESPONSE MB)

0.0

tO.O

FREQUENCY

Octupled oversampling

Characteristics 1 (Pass

5.0 (0.0

FREQUENCY

15.0

(KHil

band)

*^~X_/>

15.0 200

(KHi)

20.0

mode

Frequency

RESPONSE

25.0

0,0

-25.0

-50.0

HffiiraflF

-75.0

o.o

47

Characteristics

MB)

ioo.o

100,0

150.0

FREQUENCY

(Stop

2

200.0

(KHi)

band)

p=*

H

200.0 300.0 400.0

FREQUENCY (KHi)

SONY

Package Outline Unit: mm

CXD2S54WF

CXD2554M

24

a

Hf

24

16.0

pin SOP

±5.3

(Plastic) 450

HHRHHHHHH

13

="

o

hwwumhi

11

1

0.3

±w

5

hnnnnmnnnnnrf

CXD2554P

18

pin DIP (Plastic) 300 mil

12

mil

Z'

3

H

1 1

±al

7

asiU

SONY NAME SOP-24P-L101

ESA0 NAME *SOP324-P-045Q-AU

JECEC CODE

02

10°

-

0.1

0.3

\vent

'

-.'

;i

|

>i

Hole

i

Z2&

--*

E

1

2.5 4

4

5

0.2

Lmnrmnnoni

TirTTuinpnt

0-5

II.

"V

0'

-15'

'

)

.

SOUY SAVE

SAME

EIAJ

JEDEC

COOE

QIP-

•DIPQ1H-P-0300-AU

1 8

-

P

1 1

-48-

SONY.

CXD2560M

Digital

Description

CXD2560M is an

The

filter

dual

noise

controls.

LSI

filters

shaper,

digital audio

for

for both left

Features

•

8-times

Built-in

channels.

characteristics

Filter

±

Hippie:

Attenuation:

Noise

shaper,

de-emphasis

format

I/O

Input : 2's

(16-bit or 18-bit slot

2"s

Output:

(18-bit or 20- bit slot

0.00001dB or less (Oto

Applications

DAT,

CD,

Structure

Siiicon-gate

Filter for Audio

8-times

applications.

right

and

attenuator,

-lOOdB

functions

complement

BS tuner, and

soft-muting, and

oversampling

or less (24.1

attenuator,

MSB/LSB

selectable)

MSB/LSB

selectable)

digital

CMOS IC

Applications

oversampling

It features

channels

digital filters for both

20k)

k to)

sort-muting and

first

first (serial)

amplifiers

digital

built-in

as well as a

de-emphasis

(serial)

Absolute

•

Supply voltage

•

Input voltage

•

Allowable

i

Storage te mpe rat u re

Maximum

power

Recommended

•

Supply vottage

•

Operating

•

OSC

Block

temperature

frequency

Diagram

Ratings

Vod

VI

dissipation

Pd

Tstg

Operating

Vdd

Topr

fx

=

(Ta

25 °C

-0.3

+7.0

to

-0.3

Voo+0.3

to

500

(Ta=+75

50 to +1 50 *C

Conditions

4.75 to 5.25

-20 to

+75

1

to 27 MHz

5

mW

°C

V

)

I

V

t;

-49-

E91411A22-ST

SONY

)

Pin Configuration

(Mini-fiat

SYSM

ATT

SHIFT

LATCH

CTL{

BCKI

DATA!

LRCKK

TEST(

package)

Vss

INIT

Vss

'2)

^3

S

icj

J?)

i^

)

aj

5

e)

r\

y

}

1

Pin Description

No.

Symbol I/O

1 Vss Power supply (0V)

2 SYSM

3 ATT

4

SHIFT

5 LATCH

6 CTL

7 INtT 8 BCKI BCK input

DATAI

9

10 LRCKI

11 TEST

12 Vss

13 128 Fs

14 INVI 1

15 INVO

16 INV02

17

MCLK 1 Master clock

18 Voo 19 BCKO

20 DL

21

DR

22 LRCKO

23 FLGL

2.4

FLGR R-channel

1 System mute input. "H":

When

1

When CTL

1

When

Fixed internally at "L" level. "H":

Re-synchronized

Data input

1

LRCK input

1 Test pin. Fixed at "L" level in normal

Power supply (OV)

1

Fs

28

Inverter

—

Power supply (+5V)

BCK output

L-

channel

'

R-channel data output

LRCK output

L-channel zero muting (lag

Top

View

CTL

ATT

"L":

"L": shift clock input.

latch clock input.

"L":

by

clock output

input

output

(INVi)

output (IFJVS)

input

(f=51 2Fs)

data output

zero muting

©FLGR

©FLGL

©LRCKO

@DR @DL

©BCKO

@VDO

©MCLK

©INV02

©INVO

©INVI

@«28Fs

FLGL

input CTL

data

rising

edge of this signal

output

flag output

Description

and FLGR outputs active.

"H": EMP

"H":

CTL

CTL "H":

direct

operation mode.

input

FS32

FS48

mode.

input.

"L": serial transfer mode.

-50-

SONY

Electrical

DC

,:

:,

H

"L" input

"H" input

"H* input

Input

"H"

"L"

Power supply

AC

Master clock input Master CK

Characteristics

Item Symbol

voltage VlH

inpul

voltage

current IlL

leak

current

leak

current

capacitance ClN

output voltage VOH

voltage Vol

output

current

Characteristics

Item

frequency Imclk

width tWMK

pulse

VlL

llH

Ice

BCKI frequency BCKI pulse

DATAI set-up

width

time

DATA hold time

LRCKI LRCKI hold time turn

ATT set-up ATT hold

LATCH effective

SHIFT pulse width

LATCH "L"

time

set-up

time

Interval width tWLA

(Voo=

Condition Min.

inputs

All

All inputs. Vin=OV ±5

CTL. all pins except

CTL,

All outputs All outputs, lo=-2mA All outputs, lo=+2mA

6 only, Vin=Vdo 80

Vin=Vdd ±5

6,

(Vdd=4.75 to 5.25V, Ta=-20 to +75

Symbol Condition

to

0.8VDD

Vdd-0.5

Min. Typ.

5.25V. Ta=-20 to

4.75

-

h75

Typ.

Max,

0.2VDD

200 530

5

Max.

15 27 MHz

18.5

facKi

tWBI

tcis

tDIH

turn

100

20 20 50

3.5 MHz

50

fMCLK

20

100

+20

Uts

Uth

tSLE

t«VSF

CTL="L"

GND=0V)

°C

,

Unit

10

Vod

0.4

60 niA

GND=0V)

,

X:

Unit

ns

V

uA

PF

V

I

remover

SHIFT

delay time

Data

Inverter delay time

Inverter delay

time

time tlSR

tepo

tiPDi

tiPD2 INV02

w*°

DL, DR, LRCKO

INVO 20

-51-

20

30

SONY

CXD2560M

Input/Output

!/:,:.<

BCKI

DATAI

LRCKI

ATT

SHIFT

L^TCH

Timing

^yf

-""

Chart (When no

\

yc

Mode data

tA'S

bit 1

*~*

/ V

tA'h

-t&.£

other specification

tois

p—

\T

*"

"

\

—

}

\

/

•"

threshold level is 0.5Vdd)

t»*«

/

twai

t

* X

tLRIH

^^

tWLA

-x

tLSn

"—

tWMSC

twSi

t^RIS

X

—

/

—

bit

twsF

—

Mode data

Mode data bit 16

-—

\

s

16~^

MoSe data bit

X

\ x~

•—

t&sz

'5

•

BCKO

DL. DH

.RCKO

NVI

INVO

INV02

"N / \

—

•+

t3P0

Q.BVD1)

-Q.ZVPO

X

X.

-•

:

;

X

—

tipta—

X X X

tiP3i

-52-

/

X >

X"

—

«—

X

\ /

X.

X

R

SONY

Description

Conceptual

(1 )

The

oversampling

IN

Operating

(2)

The

the

Bit-1 is

conceptual

operation

following

of Functions

block chart

block

operation.

FIR1

mode setting

mode is set

format.

set to

always

diagram

FIR2

"0".

for

between

LSI is shown

this

CTL

ATT,

ATT

MODE

II

SHIFT, or

SHIFT

7*

LATCH

below.

LATCH

Cascading

T

ATT

transferring

by

F1R1,

of

FIR3

mode data.

cxruiisou

—6

8-times

OUT

and

2.

produces

3

CFST

I

Mode

data format

is

in

bit-2

When

when set

When

att

shift

.atch

to

LATCH

ZH$$&^£M?^^

"

LRjimrniuiiuiiiJirLniirLr

"0"

attenuate mode

is

"1"

system

is "L" data

mode is set.

cannot

is set;

transferred.

be

u

S3-

SONY CXD256W

Attenuate Mode

(3)

This mode is used to set either

attenuate or de-emphasis mode.

Mode flag Function

1 MODE1

2 MODE2 Mode switch 3 EMP De- emphasis 4

MUTE

5 ATT1 Attenuate

6 ATT2 Attenuate 7 ATT3 Attenuate 8 ATT4

9

ATT5 Attenuate data

10

ATT6 Attenuate data

11 ATT7

12 ATT8 Attenuate 13

ATT9 Attenuate

14 ATT10

15 ATT11 16 ATT12

When the IN IT

the

internal

pin is "L"

resistor.

Mode switch

Output zero data

Attenuate data

Attenuate data (LSB)

MODE1

data (MSB)

data

MODE2.

,

Test mode Normal

System mode Attenuate

ON

ON OFF

EMP. and MUTE are

"H" L"

mode

OFF

re-set

to °L". Setting LATCH

mode

pin to "L",

enables

-54-

SONY

Attenuator

(j)

ATT data is a

400H {1

12bits information

ATT data is set to 400H

.0).

ATT data

(output amplitude)

transferred by bit-5 (MSB)

I NIT going

by

"L".

through

(LSB). The size is QOOH

bit-

16

CXD2580M

(0.0)

to

transfer

QOOH

The soft

before the ATT data. (Chart

Take

ATT2. Assume that ATT1 is

is

transferred before the ATT2 value is

value

to

mute function is performed when ATT data is

above

ATT

data

1.0

case of three attenuator data, ATT1 , ATT2 and

the

reached (during state A shown in

attained

another is the same as in the case

state

at

transferred first, followed by ATT2. If ATT2 is

C to approach the value of ATT3. The

state

B or

ATT data= 4D0H System mode

System mode

*400H case, noise

shaping

transfer

4O0H

000H. De-muting is performed by transferring 400H

is for the case of 400H.)

\a

CATT1)

X

\l

the figure),

attained (during

of soft

NS="High": Noise shaping OFF

NS="Low":

can operate whether or not NS is on or off.

attenuation

muting,

Noise

CATT3)

\

*-

CATT2)

ATT3 and when their relations are ATT1 > ATT3 >

directly approaches the

state B or state

shaping ON

-

T

1 024/Fs

transferred

the attenuation proceeds from the

C,

transition

before the

value

from one attenuator

(S)

ATT1

of ATT2. If ATT3 is

I

value

datum

-55

SONY

CX02G60M

Command input and

Attenuator data consists of 1 2-bit, thus

and output

is shown in the chart below.

Attenuator

400(H)

3FF (H)

3FE(H>

to

001 (H)

audio output

data Audio output

-0.0085dB

-0,01

-60.206dB

000 |H}

attenuator value between 001 (H) and

An

De-emphasis

@

ATT=20log

Example: Suppose the attenuator data is 3FA (H).

ATT=20log

I input data \

1024

V

'

1018

dB=-0.051dB

J

1024/

V

De-emphasis can be set by two methods

data, or direct input pin.

"H": direct input method

CTL

"L": serial transfer

•

Serial transfer of mode data

Emphasis ON/OFF is performed by the attenuator mode EMP

Fs32 Fs48

L":

ON

OFF

mode Fs

System

32k 44.1k 48k

H L

H

EMP: "H":

Fs Selection

~~~~~~^^

OdB

7dB

to

-00

dB

1

(CTL:

there are 1

"L")

32 and

Fs

L

3FF

which

Fs 48.

,024 various settings. The

(H) can

calculated by the following equation.

be

selected by the CTL pin: by a serial transfer of mode

are

L

relationship

between command

H

•

input

Direct

(CTL: "H")

Emphasis ON/OFF is performed at the ATT

ATT: "H": ON

"L": OFF

Fs Selection Performed at

""""""---^^

32k 44.1k

SHIFT, LATCH

SHIFT H

LATCH H L H

Mute

Output is muted

when MUTE

is raised

pin,

Fs

48k

L

"H",

L

In this case the output is zero

-

56-

data.

SONY

System mode

(4)

mode sets the I/O

This

data

offset, and so forth.

format,

CXC256CM

Mode flag

1 MODE1

MODE2

2

IFOBM

3 4 IBIT

OFORM

5

OBIT

6

OFST

7

TEST1

8

TEST2

9

10 NS

MT1

11

MT2

12

FS32

13

|

14

FS48

SYNC

15

STAT

16

the IN

When

LATCH

Setting

pin is

IT

pin to "L",

Mode

Input

Output

Append

Test mode

Test

Noise

Zero Zero

Selects

I/O

Stop

all the

*L*

Function

switch

data format

data

data word length

offset

mode

shaping

data

muting

de-emphasis Fs

synchronize

output

above are reset

enables

length 18-bit

word

format

setting

detect time

polarity

flag

clock

internal

the

to "L".

resistor.

mode

Test

Syste

LSB first

20-bit

ON

OFF

Bums

sets

"H"

FS32

FS48

"H"

m mod e

During normal use, During normal use,

mute V

32K

H L H L

Normal

nuatemode

Atte

first

MSB

16-bit

MSB first

18-bit

OFF

fixed at "L"

ON

300ms

sets mute

44.1

v

mode

K 48K

L

I

H

-57

-

SONY

Input

data

©

The input data format is set by

I

@

n

The input data word

Output

®

The output data

Output

@

The

Offset

©

When

Zero data

©

The input

format

1FORM: "H":

*L"

put d ata

word

length

IBIT:

"H": 18-bit

16-bit

V:

data

format

OFORM

output data word length

OBIT: "H":

:"H": LSB first

"L" : MSB first

data word length

20-bit

18-bit

V:

OFST is raised

OBIT: "H":

MT1:

02AAA (H)

"L" : 02AA8 (H)

detect time

data's zero detect

"H": 60ms

:

V

300ms

LSB

first

: MSB first

length

is set by IBIT,

is set by OFORM.

is set by OBIT

"H", output data

time

IFORM.

is set by

will have

MT1

an offset value

. (Refer to the

appended

section

on

depending

zero

(5}

on how OBIT

detect

functions for

CXD2560M

is set.

details

)

Zero muting flag

©

The zero

for

details.)

muting flag

MT2:

"H" : zero mute flag

"L"

:

polarity

(FLGL,

zero mute flag

FLGR) polarity

is

active when raised

is active when

is

set by MT2.

pulled

-58-

"H".

"L".

(Refer

to the section

on

(6)

muting

circuit functions

SONY

Input/Output

(D

synchronization

When SYNC goes "H", I/O

Example with SYNC flag

LATCH

SYNC

Internal LRCK

Output

®

When

data

Example

LATCH

STAT

~LT

-T

CFs)

Transferred

®

clock stop

the STAT

(DL, DH) are pulled "L".

with STAT flag raised "H".

~LT

J

synchronization is reset.

raised "H".

h

from

Internal LRCK

uCOM to

signal is raised "H". the

SYNC

"H"

3 cycle

internal

_r~L_r~L

\

synchronization

I/O

C$

reset

cycle output clock

3

LRCK

From here

®

returns to "L\

(LRCKO, BCKO)

the

SYNC

and the output

-flag

I

I- jT^L

Internal LRC<

Transferred

—

from

I

Mode settings are not

determined

by the final data transferred.

h

uCOM to

STAT "H".

limited to

i n f

LRCK

Internal

@

cycle section.

LRCKO. BCKO,

and DR

DL

nulled

"L".

SYNC and STAT,

-59-

3

are

Whether

From

here the STAT {lag

®

returns

to "L".

Attenuate mode or System mode is active, is

SONY

Zero detect function

(5)

Operation

Q)

The input data controls the operation of

zero mute flag (FLGL, FLGR)

*

Note 1 : See section on System mode

**

Zero detect method

©

The zero

Note

2:

See section on

data detect

and DC conditions are present, zero detect occurs.

**

Mute circuit

(6)

section

consists of a low-level detect and a DC detect section. When both

is

active.

zero detection

zero data detect period.

(6)

control.

and when continuing for zero data detect time

Low-level

•

,

Input data

CIS-bit example)

MSB _SQ

1

The low-level detect section senses The

DC detect section senses the input data doesn't change.

When 16-bit data is input.

When 18-bit data is input,

Mute circuit operation

(6)

Zero

(D

mute flag (FLGL,

The zero mute flag operations according

operation.

F

(CXD2560VI)

FLGR) operation

2|3|4 e

Low-level

Zero data

whether the input

detection

DC

detection section

DC

"v

DAC

FLGL,

Mute flag block i

,'

-.

8

delect section

detect

section consists

10

section structure

data's first 14-bit are ALLO or ALL1.

consists

to the block diagram below. The mute circuit

~-

3

i?

1

14|15

j

of bit- 15 and bit-16.

bit-1

of

5 through bit-18.

Mute

CTCuit

1

|l7|l8|

16

DC detect

section

FLGR

Jiagram

controls

this

on

SONY

Zero

(2)

As

and

Zero

@

•

muting

shown

INIT

mute

The

When When

of system

DATAI

zero

the

the MUTE ON

flag construction

in zero mute flag

mute

o-

Intamal MUTE O-

Intemal

flag operation

mute llag is active

signal goes

SYSM

function

block

(SYSM)

MT1

Zero

detection

SYSM

INIT

Zero

diagram,

zero mute

and attenuate

When signal

'hf, 2ero detect >s

activated.

o-

O-

mute

during the zero

the zero mute

"H",

Attenuate mode

in

soes

Hag

mode.

block

detect

flag is made

is

-flag is active by

MT2

diagram

cycle.

active.

used, the zero

not only zero

F.GL a-

flag becomes

mute

=LGR

detect

but

active.

aiso

MUTE

•

re-synchronization

INIT

zero

The

(lag is

(Fs=44.1k).

LATCH

Zero mute

mute flag is

active. Also,

INIT

Internal

FLGL

mute flag

Zero

FLGL.

FLGR

output

flag

(MUTE OFF

during INIT

active

INIT is raised "H"

after

INIT

_r

^C

output timing

1

Max

1/64F

timing

operates

re-synchronization.

X*

Active

J

t

ve

the MUTE ON

for

in the

the

(zero)

INIT

for

same way.)

INIT

When

signal is

held

-FT

JCZ

re-synchronize

function.

is pulled "L" the

active for

+

<,d<

8Fl

cycle

zero

approximately

+

ll~

SFs-

I

mute

100ms

-61

-

SONY

I/O

synchronization

(7)

Theory of operation

(D

The synchronizing circuit

whether the

is out of

_f

is in

the

synchronizes

circuit

opens a window for eight

differentiated

the

window when the

center of the window,

both an external

signal of the

rise of

LRCKI (LRCKI

power supply is turned

and lets it start as

system and this

LSI

internal

itself.

system clocks

that

J")

on, the

soon

synchronizing circuit

as the next LRCKI

(one clock=256Fs)

may be input is present.

holds

arrives. This

_f

to monitor

If

the LRCKI

it at the

CX32860M

time

process

it

IN IT re-synchronization

®

If

re-synchronization

important to

that INtT goes high

window.

Operation

©

Set input data to zero Set output data to

Output clocks Noise shaper

IIR

zero

Initialization

©

After Vdd

complete

I/O signal latch

(8)

Input

©

ATT, SHIFT,

These

Output

@

LRCKO,

These

384Fs oscillation

(9)

In CD

the

LRCKI

re-initialize

when I NIT is pulled

register

is cleared.

mute flag

process after power

reaches

the

timing

LATCH: when

input signals are

DL, DR:

output signals are

applications

cycle

is in the

_f

window

during

operation of the

the system after turning

initialize

(J~),

data.

zero data.

(LRCKO,

register is cleared.

(FLGL,

BCKO.

FLGR) becomes

over 4.75V

initialization.

latched to LRCKI by

latched

synchronized

utilizing

by

DSP, it is possible

when the power

IC.

synchronization

"L".

128Fs) are continuously

active.

ON.

and the MCLK

INIT

and

to

are

CTL

the appropriate

BCKO

by the appropriate

128Fs

to supply the

supply is turned

particularly when

the power

stabilizes, input

pulied

circuit

"H",

on.

and

output.

master

on.

fluctuation

a

is

it

at either end of the

Re-synchronization

then positions LRCKI

8 CK or more. Then

internal clock .

internal

clock.

CK (384Fs).

of LRCKI

window.

is

performed

in the center

J"

bring

could

cause

Thus it is

at the time

INIT

"H" to

of the

62

SONY

Application

any problems

Circuit

circuits

arising

shown

out

CXD2560M

typical examples

are

the

of

use

of these

illustrating Ihe

circuits

operation of the devices,

infringement of third party

or for any

r-

7.S--7;

At Fs

R=1kQ

=

L

3.3mH

-

24nF

C

= 44.1

kHz,

cannol assume

Sony

patent and other right due to

responsibility

same.

I

for

-63-

SONY

J

GXD2E60M

It

S

1

1§rfR

E

p

-64

SONY

CXD256QM

Characteristics (8Fs

Filter

1

X

s

0,1990

0.2000

0,0001

0.0000

o.o

example)

5.0

Frequency

Ripple

characteristics

10.0

(kHz)

characteristics

I

20.0

o.o

5.0

Frequency (kHz)

Attenuation

io.o

characteristics

15.0

I

-50.0

-100.0

o.o

t

Frequency

-65

.4

ire

(kHz)

-

-J] li.

264 6

552.8

SONY

x

Package Outline Unit :

24

ifififlifiUfll

T mumuuuu

i

0.3

mm

24p in SOP

3

1B.0"-

'Cm

±M

5

(Plastic)

13

r

If

ll2

*2?*

->c

1

n o H

ai

'

o

450m i I

D*

H

o

CM

.

±0.2

2.Z

0*

jjr

--—

C.l-0.3

\

M

021

V

ent H c

=>.]

0.13

I

'

e

(rL

mm

nnnnrtnr

- 66-

)

SONY

NAMEfSDP-24P-L101

EIAJ NAMeI*SOP024-P-04S0-AU

JEDEC

SONY,

CXD2557M

Digital

Audio Signal Silence

Description

The CXD2557M

digital signals and outputs a muting

continues for a

ts an

period of time.

fixed

LSI that

Features

•

Input format

Two's complement MSB first

16-bit serial data

48 slots

•

detection time

Sifence

16,382 samples

Silence detection level

Upper 12 bits

Application

Digital audio

Absolute

•

Supply voltage

•

Input voltage

•

Output voltage

•

Input protection

•

Output protection

•

Output current lo

•

Package

•

Storage

components

Maximum Ratings

(see note) Vdd

diode current Iik

diode

current

allowable

temperature

power dissipation

Note) Unless otherwise

reference to GND.

in

detects silence in

if the silence

signal

-0,5

-0.5

Vi

-0.5

Vo

Iok

-20

Po 0.8

Tstg

specified,

-65

voltage values are

Detector

to 7.0

to Vdd+0.5 V

to Vco+0.5

to 20 to 20 mA

±

to 150 °C

50

mA

Structure

Silicon gate CMOS IC

I

V

W

Recommended

•

Supply voltage

•

High-level input

•

Low-level input

•

rise and fall times (see note)

Input

•

Operating

Note)

voftage Vil GND to Vdd

temperature

Excluding schmitt trigger points.

Operating Conditions

Vdd 4.5

voltage Vih Vdd

Tt to 300

T* to +70 °C

to 5.5 (Typ.

x

0.7 to Vdd

5.0)

x

0.2 V

V

ns

67

>

SONY

Block Diagram and Pin

9—

OX-

LRCK

DMUT

-

W1

All

-

W2

13— ISbits Load Window. L : Active

=

W3

OX

W4

MUT Timing

resTi

JBTt

TEST*

LftC* y

DATA.

o«ur

Window

DETECT

CONTROLLER

1 DET

or

and DIF DET

10

W)

')

ecK

3

"TS

Vr>0

ii)

Count

v

J

bits

Load

Window.

Window, L : Active

Configuration

-^

sa'A .W1

w4

Window,

Active

L :

(^Yn

TESTS

@

(TjJtsoi

^)tsos

fin

HUT-L

(TO

MUT-R

hcjTsaa

i^rso*

L :

Active

(Top View)

OX-Data

SOUND

DETECTER

Lch

Data

OX-

SOUND

DETECTER

Rch

OX-Tlmina

DETECTER

TIMER

Lch

-Timing

OX

DETECTER

TIMER

Rch

CXCSl-lilM

-yVL1-_

-O^UT-R

Electrical Characteristics (Vdd=5.0 ± 10%.TA=0to+70t;)

Item

"H" output voltage Voh Ioh=—4mA 3.7 V

"L" output voltage

Schmitt input

hysteresis

Input leakage current lu Vi=VooorGND ±1 aA

Static current

range

consumption

Signal

Vol loL=4mA 0.4 V

vt>-vt-

ICCq

Measurement

conditions

Vi=VDoorGND,

all outputs open

Min.

Typ, Max. Unit

0.85 2.55 V

+50 uA

-68-

SONY

Pin Description

Symbol

No.

1 TEST1

2 TEST2

TEST4 1 Test input

3

4 LRCK 1 LR 2ch

5 SDATA G BCK 7 DMUT

Vdd Power supply (+5

e

TS04

9

TS02 Test

10

11 MUT-R

12 MUT-L 13 TS03 14 TSOI

15 TESTS

16 GND

WO

1 Test input.

1 Serial data

1 Bit

1 "H" forces

o Lch MUT o

1 Test input.

Normally Normally set to "L".

Normally set to "L".

word clock (fs) signal.

signal

clock

MUTON.

output

Test

output

Rch MUT output

output

Test output

output

Test

Normally set to "L".

Ovolt

set

t"

volts)

Description

1".

to

(488CK=1

set during

is

CXD2S57M

cycle)

normal operation.

I

-69

SONY

Description

1. System Configuration

This silence data detection

and consists of a silence

(OX-Timer)

2. Function

Silence data

(1

The silence

detection

of silence data.

•

Low-level detection

Detects

data, the circuit

•

Direct current detection

Detects

of Functions

which

and

detection

data

circuit. Simultaneous detection of both the low-level

whether

data detection circuit (OX-Data), a window generator

measures how long the silence continues.

Operation of System Circuits

circuit (OX-Data)

detection circuit is divided into two sections: a low-level

circuit:

the absolute value of the signal is sufficiently

checks whether the upper 12 bits are all

whether

circuit:

the signal value changes. Since all

checks only bits 12 through

circuits use the no-change

Window

(2)

The window

detection

•

Window generator

generator

(OX-Window)

generator generates the

and timer circuits.

circuits:

These

circuits generate the following

low-level detection

W3 (Lch, Rch),

(3)

MUT-T mute timing

circuit;

pulse.

the

Is

IC

compatible with the

of

16

each

word for

edge of the bit-clock data.

various

windows and pulses:

W2 (Lch, Rch), a latch pulse

(2)

silence

data latch pulse; and

data formats of the CDL-30, 35 and 40 series CD-use LSIs,

-Window), and a tinner circuit

(OX

detection circuit

state

O's

bits

direct-

or

and

all 1

current state is treated as detection

smail. Since the signal is two's complement

's.

up to bit 12 are either all O's or all 1's, this circuit

each channel. Also, for reading

latch

pulses and ioad pulses necessary for

W1 (Lch, Rch),

(1)

and a direct current

in data,

both detection

the silence data

a load window used by the

used by the direct current detection

W4 (Lch, Rch) the timer count

(4)

load

circuft:

pulse and

Timer circuit

(3)

This

circuit

muting signal.

(OX-Timing)

checks whether the silence

state continues for a time

-70-

equivalent

to 1 6,382 samples and outputs

the

SONY

CXD2557M

3, MUTE Output When Silence Is Detected

judged as "silence" Is input continuously for 1 6,382

If

data

output ("L"

1"*

MUI-L.

level)

/"

H

on the rising edge

16382nd

sifence data L

The mute signal is reset as

signal, the

of LRCK. and

on the next LRCK;

Note)

internal TRST L signal goes to "L" on the

internal counter loads the initial value. As a

the

same

The TRST L and R

Silence: "H"; sound: "L".

LRCK _/

Silence data Silence data

L R L

TRST L

MUT-L

TRST R

MUT-R

\ /

of the second subsequent LRCK cycle.

data

1

R

"\

16.382nd

silence

in the diagram below, tf,

shown

with- the Rch signal.

occurs

are flags showing whether the input data is

signals

~^\

Sound

data Sound dais

v

cycles

(1

6,382

\ / V_

for example, sound

edge of the fourth BCK

rising

result, the MUTE signal is reset on the rising

r

Sili

R

/

\ r~

\

nee data S

L

fs cycles of LRCK), the mute signal

"A

data is detected in the Lch

silence

cycle

or sound.

following

falling edge

the

/ \

ence

Silence

data

R

L

data

Silence dat

R

/

_/

is

edge

I

4. Forcing

When "H"

next LRCK. The MUTE

of the

edge

When DMUT

1)

LRCK

DMUT

R

MUT-U

DMUT

When

2)

LRCK

DMUT

MUTL. R

a MUTE Output Using the

is input to the DMUT pin, a MUTE

signal is reset in the same

is turned

J

//////////////////////////////////////////////////M

is

turned

J

while sound data is

ON

\ /

while sound data is continuing:

OFF

\ -J

DMUT

signal

Is

continuing:

\

-71

Input

forcefully output to both L

manner.

\

~\

\

-

and

channels on the rising

R

I

r~

/

\_

V-

SONY

E

a

3

O

3

a.

Sr

=

3

Q.

1

C

P

-72-

SONY

Package

Outline

Unit

: mm

16pin SOP (Plastic)

±a3

l&2

15 9

R B fl B B a II w

PS

«

en

lo

H

u

but

u

1

±MS

0.fl

B

1.2 7

0roU

30

Z.3MAX

i

azMAX

1

tQ

l 2

h

^4

04

5

I

S.AUE SOP-ISP -L121

SONY EIAJ

JEDEC

NAME

CXE

•30PC16-P-

-73-

D300-AX

A/D,

D/A

Converter

2)

A/D,

D/A Converter

Type

CXD2552Q

CXD2561BM

CXD25550

Functions

1-bit

D/A converter

D/A converter,

1-bit 1-bit A/D*D/A converter. Built-in digital filter,

2nd

order noise shaper

3rd order noise shaper

Page

77

85

94

-76-

SONY

CXD2552Q

1 Bit D/A

Converter

Description

The CXD2552Q

for digital

others.

audio

is 1 bit type D/A

products;

Features

•

PLM pulse

•

3rd order

•

Direct

•

Master clock

•

channel built

2

Absolute

•

Supply

•

Input

•

Allowable power

•

Storage

Recommended

•

Supply voltage Voo

•

Operating

•

OSC

•

Supply

converter

shaper

noise

digital sync

1024Fs

in

Maximum

voltage

frequency

voltage difference

Vdd

Vi

dissipation

Pd 500 mW

temperature

Tstg

Operating

temperature Topr

Vdo-Vdoj,

Vss-Vssj,

converter

compact disc

Ratings

-0.5

to +6.5

-0.3

to Voo+0.3

-55

to +150

Conditions

4.75 to 5.25

-10

to

fx 32.0 to

Voo-DVoo,

Vss-DVss, Vss-XVss

Vdd-XVdd ±

developed

player

V

(Ta=6Q°C

°C

60

49.7 MHz

and

± 0.1

V

°C

0.1V

V

Structure

Silicon gate

Applications

Compact disc

44

4s

CMOS IC

player,

QFP [Plastic)

digital amplifier, BS

tuner

I

Block

Sony

originated

Diagram

Corporation

by

and Pin

s

|3i

iHtHtf

(MCaiT

imW

h'TgWSt.*! cw

W

(Nipcon

CXD2552Q

Telegraph and

NTT

developed

Configuration

ill

and desioned

3±

Telephone

circuitry

LSI

the

Corporation).

77-

ihat incorporates

i i

the

Multi

i I

Stage Noise

Shaping

CB985BA0Y

techniQue

-

ST

—

SONY

Pin Description

Pin No. Symbol

1 V002

2 Vss

3

RH

4 Vdd

VSS2

5

B Vsub

7

LRCKO LRCK

8 DM2 I 9 DM1 Dither designation

10 POL PLM output

11 DVdo

12 TESTS Test pin. Fixed at "L"

13 MUTE Turns interpolator output

14

15

16

17 18 TEST1

19

20

21 INIT Resynchronized by rising edge of

22 128Fs

23 Vsub 24

25 DINIT

26 INAF

27 DVss 28 Vsub 29

30

31

32 Vss 33 VDD2 34 Vss

35

36 Vdd

37

LRCKI

DR!

DLI

BCKI

TEST2

SYNC

512Fs

Vsss

Vdd

L(-| Lch PLM output

LW

Vsub

I/O

-

— —

—

power supply

Analog

GND

Analog

PLM output (Opposite phase)

Roh

power

Analog Analog GND

Sub straight. Connect to GND.

output

Dither

polarity

Digital power supply

LRCK input

Rch data input

Lch data Input

.

BCK input

Test pin.

Test pin. Fixed at "L" level

Sync control

128Fs

—

Sub straight. Connect to GND.

51 2Fs output

Delay

When

—

Digital

—

Sub straight. Connect to GND.

—

Analog GND

—

Analog power supply

—

Analog GND

—

Analog power supply

—

Analog GND

Lch PLM output (Positive phase)

—

Analog power supply

-

Sub straight. Connect to GND.

Fixed

output

signal output

INIT

I/O

sync

GND

supply

"L"

level

at

"L"

is

missed "H" is output.

(Opposite

Description

Positive phase "H"

:

in normal operation mode.

into data.

in

normal operation mode.

in

normal operation

this

phase)

: Opposite

Effective at "H".

signal

::xn?552Q

phase

mode.

-78-

)

SONY

Pin No. Symbol I/O

38

39 XIN I 40

41

42

43

44 Vss

Electrical

DC

"H"

"L"

Input leak

•H"

"L"

"H"

-

'L

"H" output

"L"

"H" output

"L" output

"H" output

"L"

Current

XVss

XOUT

XVdd Clock

Vdd

R(+) Rch PLM

—

Characteristics

Item

input voltage

current

output voltage

output voltage (DINTT, INAF)

output voltage (512Fs, LRCKO) VOM

output

output voltage

output voltage (XOUT) Vol

consumption

(DIN IT, INAF) VOH lo=-1

voltage{512Fs,

(128Fs) VOH

voltage

(128Fs) Vol

(R+, R-,

voltage

(R+, R-, L+, L-) Vol

voltage

voltage (XOUT)

(Vdd=Vdd2=DVdd=XVdd=5,0V

LRCKO) Voi

U,

Clock GND

Crystal oscillation

oscillation output pin

Crystal

input

power supply

Analog

output (Positive phase)

Analog GND

Symbol Condition

VlK

VlL

lu

Vol

lo=1 mA

lo=-0.4mA Vdd-0.5

lo=0.4mA 0,4

lo=-0,3mA Vdd-O.5

to=0,3mA

L-) Voh lo=-1

lo=15mA

Voh I o

lOD

=-2,

I o=2.0mA

CXG2552C

Description

pin (1024Fs)

Vss=Vss

±

5%,

=DVss=XVss=0V, Topr=-10to

2

Min. Typ. Max.

0,76Vdd V

0.24Vdd

60

Unit

±5.0 uA

mA Voc-0.5 V

0.4 V

0,4 V

5mA Vdd-0.5 V

0.5

0mA

Vdd-^0.5 V

0.4 V

55 80

mA

°C)

V

V V

V

I

Characteristics

AC

BCKl pulse width

R set

DATAL, DATAL, R hold

LRCKI set up LRCKI hold time

output

PLM

(Vod=Voos=DVdo=XVdd=5.0V ±

Item Symbol

tw 38

up time tsud

time

time tr. tf CL=300pF

rise/fall

thdd

tsulr

thdlr

Condition

-79-

Vss=Vss2=DVs5=XVss=0V, Topr=-1 to

5%,

Min,

ia nsec

18

Typ.

10

60

Max Unit

nsec

nsec nsec

nsec

"C

SONY

•

Input

DATA

CXD25523

BCKi

L fl

LRDC1

Output

PLM

OUTPUT

troJm

Vdd

90 %

PLf-'ss

10% Voo

I

tfplm

-80-

SONY

CXD2552C

Analog

Total harmonic

Electrical

The

Characteristics

Item Symbol

distortion

ratio

S/N

testing

(Vdd=Vom=DVdd=XVdd=5.0V,

Condition

THD

S/N

1kHz, OdB data

(Fs=44.1kHz)

1kHz.

OdB/- =>dB data

(Fs=44.1kHz)

fitte used)

(A

Characteristics Testing

harmonic distortion

of total

100P

Method

and S/N ratio is

Vss=Vss2=DVss=XVss=ov,

Min. Typ.

96

in Fig. 1

shown

Fig. 1.

and 2.

.

Ta=25

Max. Unit

0.0030

SHIBAS0KU(flD725C)

1

%

dB

DIGITAL

SIGNAL

GENERATER

(158! T>

384

Fj

D/F

CCXD1244)

multiplier

3

CIRCUIT

OLI

BFs

\^

DAC

1CXD2552]=

m

l

Fig. 2.

-81

osc

ANALOG

CIRCUIT

-

ANALOG

SWITCH

BOX

SHIBAS0KUIAD725C)

DISTORTION

ANALYZER

_

SONY

Description of Function

Synchronizing Circuit

I/O

Theory

1)

A

(LRCK

When power supply is turned on, should LRCK

processing in

appearance

through this

Resynchronization

2)

Even when LRCK

synchronization

without fail after power supply is turned on.

timed

window.

Moreover, when synchronization falls out of the window, INAF output turns to "H" level.

operation

of

window featuring 8 internal clocks

of the LRCK input has entered the

J")

timing

of the next LRCK

operation.

may be

after

4 periods of Fs rate LRCK,

INIT input

l.i:e-n»

the center of the window. The processing is started synchronously with the

with

by means

is inside the window but located close to one of the two edges of the window,

X

upset by the mingling of external noise. To this effect, it is necessary to apply resync

INIT

Synchronization between the exterior system and this

.

J~

of INIT

(256Fs) is set.

window

or not.

be out of the window, the

J~

Resync

sync circuit is initialized

The

Here

operation is executed from the rising edge of INIT and

resynchronization is

The sync circuit observes whether the rising edge

and

LRCK

applied-

sync

circuit stops the internal

LSI

is

located at the

J"

CXD2552G

is established

center

the

of

Input Timing

LRCK

I

bck

,

ijijuwirLruiJiiirij^^

driXl

01 NIT

(Bfs

output

rate)

4 periods of

MSB

h

X*X*

rate LHCK

Fs

I

LSB

xa

X« XT

Xs

X*

X»X»»

k:

t

X«X»

X«X»X«Xff

via

uxx

SONY

!*

I

&

—

-41

A

j3

Si

s_*

3

i

A

41

&|_A

o

11

if

s B

|i

c

S

U

Id

Is

I

9-2

C a

3 *

a.

»2

IE

I

e 1

(A

d

s

|i

4 6

-

$

1

< A3

i 6

<

i 6

-

83

SONY

CXG2552Q

Package

Outline Unit:

mm

a

Q17.S

i n

:

C.

r- ( P L a S t i c ) 1 .

QFP-44P-L12^

NAME

SONY

EIAJ

JEDEC

•QFP044-P-l<:i4-AX

SAME CODE 1

1

g

f.

:,

84-

SONY

CXD2561BM

1-Bit D/A

Description

CXD2561

The

3rd-order noise

a

superior

SX

configuration,

Characteristics

characteristics can be

oversampling digital filter. (By

•

Distortion :

•

ratio

S/N

Features

•

2-channel D/A

•

Srd-order

•

PLM-method pulse

•

Master

Structure

Silicon gate CMOS

Applications

Compact-disc

Configuration

Converter for

BM is a 1 -bit stereo D/A

sbaper, in which DA

etc.)

0.0035%

: At least

noise shaper

clock ot 512fs

and below

95dB

converter on a single

conversion output

players,

(Top View)

achieved by employing

chip

digital amplifiers,

Audio

conversion with

using two chips

Applications

converter using

an

satellite-broadcast

tuners, etc.

I

DVoollJ

TEST

(2)

initQ

lrckM

DATAR (T)

DATAL

(J)

DVss

®

512FS

(9)

XV

ss

(10)

(is)

OUT

X

XV0D@

V

suefr?)

o

(2S)AVDDL

@L1(4}

@AV»5L

©u I-

@L2(+)

©L2(-)

©AVss

AVdo

©

(£)R2I

@R2t+)

@RH-1

AVsjfi

@

R){ + )

@

AVddR

(l5)

-

)

E91Y3S-ST

-85-

SONY

Block

Diagram

CX02S61BM

Absolute Maximum

Item Symbol Conditions

Supply

voltage

Input voltage

Allowable

Storage

Recommended

Supply voltage

Operating

OSC

power

dissipation Pd Ta=60"C

temperature

Operatir

Item Symbol Conditions

temperature

frequency

Ratings

Vdc -0.5

Vi -0.3

Tstg -55

Conditions

g

Vdo

Ta

Fx 512fs 16.0

Min.

Min. Typ.

4,75 5.00 5. 25

Typ. Max.

-10

-86

6,5 V

Vdd+0.3

500 mW

150

Max,

60

25.0

Unit

V

Unit

V

°C

MHz

SONY

Description

Symbol

No.

1 DVdo

2 TEST

IN IT

3

LRCK LRCK input (8fs)

4

5 DATAR

DATAL Left

6 7 BCK

DVss Digital GND

8

512fs

9

XVss

10

11 XIN 1

12

XOUT

XVdd

13 14 Vsub

AVddR

15 16 R1

17 AVssR 18 R1(-)

19 R2(+

R2(-)

20

21 AVdd

AVss

22 23 L2(-)

24

Law

25

LK-)

AVssL

26

27

L1W

AVddL

28

(+)

I/O

o

)

—

I

'

Digital power

Test pin. Fixed at

Signal

Right channel data

that

channel

activates

data

supply

Description

"Low* in normal use.

resynchronization

input

(Sfs): 16 to

input (Sfs); 16 to 1

BCK input

512fs Clock

Clock GND

Crystal oscillator input (512fs)

Crystal oscillator

Clock power supply

Connected to

Analog power supply

Right-channel PLM output (in-phase)

Analog GND for right channel

Right-channel PLM output

Right-channel PLM output Right-channel PLM output (opposite

Analog power Analog GND

Left-channel PLM Left-channel PLM Left-channel PLM output

Analog

Left-channel

Analog power supply for left channel

output

output (512fs)

substrate

for

supply

output (opposite

output (in-phase)

for left channel

GND

PLM output (in-phase)

GND

right

(opposite

(in-phase)

(opposite

channel

at rise

18-bit data,

8-bit data, tSB-first

phase)

LSB-flrst

I

-87

-

SONY

f^r

=v

Electrical

DC

(DVdd=XVdd=AVdo=AVddR=AVddL=5,0V

"High" level

input voltage

"Low" level

input voltage

Input

"High"

output

voltage

Characteristics

±

DVss=XVss=AVss=AVssL=AVssR=OV.

5%,

Item Symbol

XIN VlH

Other pins VlH 0.76Vdd

XIN

Other pins VlL

leakage current ll -5.0

512FS

level

L

W-)

XOUT

VlL

VcH

VoH lo=-15mA

VOH lo=-2,0mA Vdd-0.5

Conditions

lo=-0.4mA

512FS Vol lo=0,4mA

"Low" level

input voltage

Vol lo=l5mA

XOUT Vol lo=2.0mA

Current

consumption Idd

AC

Characteristics

(DVpp=XVoDaAVDD=AVDoR=AVopL=5.0V +

Item

BCK

pulse

width tw

DATAL, DATAR

LRCK setup

PWM output

'PWM output

XIN duly

cycle duty

setup time tsu

hold

time tsu

time

rise

fall

time tf Ci.=150pF

Symbol

time th

tr

DVss=XVss-AVss=AVssl=AVssR=0V,

5%,

Conditions Min.

CL=150pF

Vdo/2 at 25MHz

Min, Typ. Max,

0.9VOD

Vdc-0.5

Vdd-0.5

40 60

Typ. Max.

38

18 20

18

40

20

10

50 %

Ta=-10 to

0.10VDD V

0.24Vdd

5.0

0.4

0.5

0.4 V

Ta=-1

nsec

nsec nsec nsec

nsec

Unit

V V

V

uA

V

V V

V

mA

to 60

Unit

60

°C

1

-88-

SONY

Input/Output A/C Timing (sfs,

BCK24 or BCK32}

data,

BCKI

DATA L, R

LRC<

OUTPUT

PLM

10%Vdd

CPLM)—

tr

tw

(BCKD

P

S

S0

:

lft)0

-

r—

t*

:

isu

tr

cplm)—

(BCKQ

(LRCKIj

I

; r—

Analog

Characteristics

{DVdd=XVdd=AVddR=AVddL=5.0V

Item

Total harmonic

distortion factor

S/N ratio

Symbol

THn

mu

S/N

j

1kHz,

(Fs=44.1kHz)

,

1kHz,

O/-00 OdB

(Fs=44.1kHz»

+

5%,

Conditions

OdB data

data

DVss=XVss=AVss=

Min.

95

-

89-

AVssUAVbsR=OV, Ta=25

Max. Unit

Typ.

0.0035 %

dB

V

)

SONY

CXD2561 BM

Electrical Characteristics

Test

Method

The total harmonic distortion factor and S/N ratio

Figure A

220p

-w

r^<!

"j*

are

tested by the circuits shown in Figures A and B.

1O0P

r-t

6k

4700P

v»k ( .5k

1^>-mwh

L , R

Select

-

c fi

er

( AD7ZSO

SHIBtSOKU

DISTORTION

ANALYZER

Figure

3841

GENERATOR

B

DIGITAL

SIGNAL

C16BIT)

K'UJTIPLIER

•~s

WTA

128Fs

D/F

CXD2560

512Fs

8Fs

:_'

w

DAC

CXD256I

"OOP"

PLM

L

PLM

-90-

ANALOG

CIRCUIT

a

1

,;.:;

ANALOG

SWITCH

BOX

SHIBASQKU

DISTORTION

ANALYZER

CAD725C)

SONY

CXD256"

3M

Description

I/O Synchronization Circuit

Theory

J)

The

rising edge {LRCK

the

If

processing at

LRCK

Resynchronization

®

If the LRCK

affected by

switched on.

the rising edge of INIT, and it

of Functions

synchronizing circuit has a window

within

J")

LRCK

_f

INIT input

Internal

is outside the window

J"

centered on the window, and

timing

operation synchronizes this LSI to

This

.

by INfT

within the window, but is too close to

is

J"

such as external noise. Thus, it is

factors

Resynchronization is

IN IT sional

Approx. 4 cycles

it.

done at a timing of

initializes

the synchronizing

Resynchronization

/

lor

monitoring the

when

power is

of Fs-rate

J"

whether there

in

window.

the

input LRCK signal to determine

switched on, the

in synchronization with the occurrence of

restarts

systems.

external

sides

either

always necessary to resynchronize after power is

approximately four cycles of LRCK at the Fs rate from

circuit

to

this

3t

occurs

-iS-

synchronizing circuit stops internal

the window, synchronization may be

of

the LRCK

center

point

LRCK

the

is a

Input Timing

LRCK1

bcki

DLI

DRI

Rate)

(8fs

|

mrLriJinjuiJMiJinjinj^^

xj

.

xi

-

-91

r

mot

JJJJZ

SONY

CXD256?BM

i

it

=5

I

n

it

ZJ 'C

!l

si

St

Is

II

o S

&-=

8

~

e

O

I-"

is

8|

ii

if

o

c

o

Q.

<

-92-

SONY

Package Outline Unit

mm

:

i

28p

n SO? (Plastic) 375mi L

17.75

SI

-

NY IWfcl S OF

S3

UAW£i'S3

E1AJ

CODE

JEBEC

-

93

28P-L121

3

CtB-P-S3tlO-AX

I

SONY,

CXD2555Q

IBit

AD/DA Converter for Audio

Description

The CXD2555Q, which features a 2nd order

noise shaper, is an extremely cost-effective 1-bit, 1

-Chip

filters.

stereo

AD/DA

converter with

ort-chip

AX

digital

Features

•

2-channel AD and DA converters,

for

ters

converter,

•

Use of internal peripheral analog circuits for AD

converter greatly simplifies external elements,

•

Distortion: within

•

S/N ratio; DA converter: At least 90d8

decimation and over-sampling for each

all on a single chip.

0.01% (both AD and DA)

plus

digital fil-

AD converter: At least 80dB

Structure

Silicon-gate

Functions

•

On-chip

rate

•

Simple

multi-channel system

Block Diagram

CMOS

digital filter enables data input/output at

IXFs

of

connection

of multiple CXD2555QS

enable

Application

•The

32

dependent

rearward-packing and MSB-first/LSB-first,

•

Applicable

512Fs, 768Fs,and 1024Fs

•

Applicable to low Fs frequencies of 16k, Sk and

in

etc

44.1k, and 32k

•

Outputs

the type

serial data interface enables in-

slot

selection

to four

addition

to

different division clocks according

of LSI chips connected

Preliminary

data forward-packing/

of

master clocks:

usual Fs frequencies of

256Fs,

48k,

to

A0C1 -

oie

H.lifl

'*L

A

"

©

94

SONY

Pin Configuration

CXD2655Q

MWT11-)

Description

No.

1

Vdd

AOUT1

2

v

3

ss

UCLK

4

XCLK

5

6

7 XTLI

XTLO

3

9

Vss

v

10

S£

11

A0UT2C+)

12

Voo

13 A0UT2C-)

14 v

ss

v

15

ss

A1N2

16

Symbol I/O

—

(+)

-

—

_

— —

| Analog

1 crystal oscillator selection

1

power supply for

Analog in-phase output

for Channel 1 DA

GND

Analog

of clock frequency

for 1/2

Output

User clock

Master clock output for ICs

more

Power

Crystal oscillator circuit

Input for external master

Crystal

crystal

GND for

Analog

Ara

Analog Analog Analog GND

output

one connections

than

supply

oscillator circuit output.

oscillator selection pins,

master clock

for Channel 2 DA

GND

-,

phase output

0;,

power supply for

opposite phase output

for

Analog GND for

input for Channel 2 AD

Analog

externally connected

for

master

Channel Channel

-95-

Description

Channel

Channel 1 DA

for

of

clock

input

pins, XSLO to XS12

clock

for Channel 2

Channel

2 2

DA

1

converter

input

in slave

mode

CXD2555QS

Connect the

Connect

XSLO

to

converter

DA

2

for Channel

DA converter

AD converter

converter

through oscillator pin XTLI (Pin

IC.

clock

when the 256Fs

are

used. (XSL2

crystal oscillator

(Pins

34, 35,

the crystal oscillator

XSL2 (Pins 34, 35,

DA

converter

DA converter

2

output

—

"Low*

selected by the

and

36).

selected

and

36).

I

7).

and

)

by the

SONY

CXD2555Q

No.

Symbol

|

17!V

DD

18 NC

19

SUB

20 NC

21 v

ss

22 XMCK2 IC test

I/O

—

Analog power supply for

—

Connected

—

Falls to GND

—

GND for digital

pin. Always outputs at "Low"

23 TEST 1 Test pin. Usually

:

24 CLR

25 V

UD

26 MS

System-dear

resistor.

—

Power supply

Master/slave

1

mode.

Connected

Sampling

27 LRCK I/O

28

BCK I/O

29 SIN

30 SOUT

31 v

5i

32 MASL

33 MLSl

34

XLSO

35 XSL1

36 XSL2

mode (Pin

fers Channel 1 data at

Serial

bit

SOUT.

data

slave mode

serial

output

. 2-channel per 1 sample

complement

2-channel per 1

complement

—

GND for digital circuits.

For serial I/O

16-bit slot of

last

rearward packing.

means

With serial I/O,

16-bit serial data.

Crystal selection

frequency from XTLI

37 DASLO IC test pin.

DASL1

38 39 WO

40 V„

41 NC

42

43

44

45

46 v 47

NC

SUB

v

l: „

AIN1

ss

v

Si

D

48 AOUT1

—

-

—

-

—

1

-

—

(-)

pin. Normally fixed at "Low*.

IC test

Synchronization

window open

Power supply

Connected

Falls

GND through a capacitor on the

to

Analog power

Analog input

Analog GND for Channel 1 AD Analog GND

Analog

opposite

Description

Channel

board

circuit

to

through

input. Usually at

for digital circuits

circuit:

fixed

capacitor on

a

at

mode switching input. 'High*

with

pull-up

frequency clock pin for serial I/O system. Output

=

"High")

26

transfer clock pin (64Fs) for

Output when in master mode (Pin 26

(Pin 26

data is transmitted at falling edge.

of

2

;

"High"

=

"Low"). Serial input data is fetched at

32-bit slot

;

sample

of

32-bit slot.

2

;

with 16-bit serial data, selects either the first 16-bit

the 32-bit siot. "High"

either LSB-first or MSB-first for input/output to put

selects

"High"

pin.

Use

(Pin

Normally

fixed at "High".

window open input. "High*

(forced synchronization). Connected with pull-up resistor.

for digital circuits.

board (same potential

circuit

to a

supply for Channel 1 AD converter

for Channel 1 AD converter

for Channel 1 DA converter

2 AD converter

(same potential

"Low*. Connected

"High*, clear at low". Connected

as

the printed circuit board.

under

normal

with

=

resistor.

input when in slave mode (Pin 26

Channel 2 data at "Low".

;

serial

input data SIN

serial

input. Data format is

data

output Data format is based on the

data

supply) within

power

conditions.

pull-down resistor.

master

mode;

=

"High") ;

means forward

=

MSB-first; "Low"

XSLO to XSL2,

3-bit,

7).

converter

=

LSB-first.

select

to

=

window masked; "Low*

power

as

printed circuit

supply)

board.

phase output for Channel 1 DA converter

the IC.

pull-up

with

=

when

=

and

"Low"

"Low").

input

slave

in master

Trans-

serial output

when in

rising edge;

based on the

slot or

packing;

the clock input

"low"

within the IC.

the

in

=

9fi