Sony CXD1910AQ Datasheet
Description
The CXD1910AQ is a digital video encoder
designed for set top box, digital VCRs and other
digital video applications. The device accepts ITUR601 compatible Y, Cb, Cr data, and the data are
encoded to analog composite video and Y/C video
(S-Video) signal.
Features
• NTSC and PAL encoding mode
• Composite video and separate Y/C video (S-
Video) outputs
• Y, U, and V outputs
• 8/16-bit pixel data input mode
• 13.5 Mpps pixel rate
• 10-bit 3 channels DACs
• Supports I2C bus (400kHz) and SONY SIO
• Closed Caption (Line 21, Line 284) encoding
• Macrovision Pay-Per-View copy protection system
∗
Rev. 6.1
• Monolithic CMOS single 5.0V power supply
• 64-pin plastic QFP package
∗
This device is protected by U.S. patent numbers
4631603, 4577216 and 4819098 and other
intellectual property rights. Use of the Macrovision
anticopy process in the device is licensed by
Macrovision for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Absolute Maximum Ratings
• Supply voltage VDD –0.3 to +7.0 V
• Input voltage VI –0.3 to +7.0 V
• Output voltage VO –0.3 to +7.0 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –40 to +125 °C
(Vss = 0V)
Recommended Operating Conditions
• Supply voltage VDD 4.75 to 5.25 V
• Input voltage VIN Vss to VDD V
• Operating temperature Topr 0 to +70 °C
I/O Capacitance
• Input pin CI 11 (Max.) pF
• Output pin CO 11 (Max.) pF
Note) Test conditions: VDD = VI = 0V
fM = 1MHz
– 1 –
CXD1910AQ
E95235A66-ST
Digital Video Encoder
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
64 pin QFP (Plastic)
– 2 –
CXD1910AQ
XRST
PD0 to 7
PD8 to 15
PDCLK
SYSCLK
1/2
VSYNC
HSYNC
FID
XVRST
F1
SI/SDA
SCK/SCL
XCS/SA
SIO and I
2
C-Bus
controller
SYNC gen.
and
timing controller
Dempx,
level
translator
and
interpolator
4:2:2 to
4:4:4
U
V
Delay
LPF
LPF
Modulator
CHROMA
BURST FLAG
CSYNC
Sub carrier
gen.
Closed caption encoder
(for NTSC)
MACRO VISION
signal gen.
SYNC slope
gen.
Y, C/
Y, U, V
selector and
interpolator
10bit
DAC
10bit
DAC
10bit
DAC
VB
Y-OUT/Y
COMP-O/V
C-OUT/U
VG
IREF
VREF
TDO
TDI
TMS
TCK
TRST
57
59
60
62
51
52
48
49
50
56
25
29
24
32
26
20
21
46
43
44
45
41
1 to 4,
6 to 9
11 to 18
Y
55
37 to 39,
54
XTEST1 to 4
64
XIICEN
Block Diagram
– 3 –
CXD1910AQ
Pin Description
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE” = “0”:
These are inputs for multiplexed Y, Cb, and Cr signal.
When control register bit “PIF MODE” = “1”:
These are inputs for Y signal.
Digital ground
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE” = “0”:
These are inputs for multiplexed Y, Cb, and Cr signal.
When control register bit “PIF MODE” = “1”
These are inputs for Y signal.
Digital power supply
Digital ground
The reference current output pin.
Connect resistance “16R” which is 16 times output resistance “R”.
The voltage reference input pin.
Sets output full scale value.
Analog power supply
Analog ground
This is the output of 10-bit D/A converter.
When control register bit “YC/YUV” = “1”:
This pin outputs composite signal.
When control register bit “YC/YUV” = “0”:
This pin outputs color difference (V) signal.
Connect to VSS with a capacitor of approximately 0.1µF.
Connect to AVDD with a capacitor of approximately 0.1µF.
Analog power supply
Analog ground
This is the output of 10-bit D/A converter.
This pin outputs luminance (Y) signal.
8-bit pixel data input pins / Test data bus.
When control register bit “PIF MODE” = “0”:
These inputs are not used.
When control register bit “PIF MODE” = “1”:
These are inputs for multiplexed Cb and Cr signal.
When test mode, it's used for internal circuit test data bus.
Test mode is available only for device bender.
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PD7
PD6
PD5
PD4
VSS
PD3
PD2
PD1
PD0
VDD
PD15/TD7
PD14/TD6
PD13/TD5
PD12/TD4
PD11/TD3
PD10/TD2
PD9/TD1
PD8/TD0
VSS
IREF
VREF
AVDD1
AVSS1
COMP-O/V
VB
VG
AVDD2
AVSS2
Y-OUT/Y
I
I
I
I
—
I
I
I
I
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
O
I
—
—
O
O
I
—
—
O
Symbol I/O Description
– 4 –
CXD1910AQ
Analog power supply
Analog ground
This is the output of 10-bit D/A converter.
When control register bit “YC/YUV” = “1”:
This pin outputs chroma (C) signal.
When control register bit “YC/YUV” = “0”:
This pin outputs color difference (U) signal.
Test data bus.
This pin should be open.
When test mode, it’s used for internal circuit test data bus.
Test mode is available only for device bender.
Digital power supply
Test data bus.
These pins should be open.
When test mode, it’s used for internal circuit test data bus.
Test mode is available only for device bender.
Test mode control input pins. These pins are pulled up.
When these pins are “H”, the CXD1910AQ is not test mode.
Test mode is available only for device bender.
Digital ground
Test mode reset input pins.
When power on reset, set “L” for more than 40 clocks (SYSCLK).
Digital power supply
Test mode control input pins. This pin is pulled up.
Test mode control input pins. This pin is pulled up.
Test mode control input pins. This pin should be “H” input.
Test data bus. This pin should be open.
Digital ground
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SI serial data input.
When XIICEN = “L”, this pin is I2C-BUS mode; SDA input/output.
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SCK serial clock input.
When XIICEN = “L”, this pin is I2C-BUS mode; SCL input.
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; XCS chip select input.
When XIICEN = “L”, this pin is I2C-BUS mode; SA slave address select input
signal which selects I2C-BUS slave address.
Vertical sync reset input pin in active low. This pin is pulled up.
This is used to synchronize external vertical sync and internal vertical sync.
When XVRST is “L”, internal digital sync generator is reset according to F1 status.
Pin
No.
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
AVDD3
AVSS3
C-OUT/U
TD10
VDD
TD9
TD8
XTEST1
XTEST2
XTEST3
VSS
TRST
VDD
TDI
TMS
TCK
TDO
VSS
SI/SDA
SCK/SCL
XCS/SA
XVRST
—
—
O
I/O
—
I/O
I/O
I
I
I
—
I
—
I
I
I
O
—
I
I
I
I
Symbol I/O Description
– 5 –
CXD1910AQ
Field ID input.
For external synchronization with XVRST signal, the field for resetting is determined
by the main signal.
“H” indicates 1st field.
“L” indicates 2nd field.
Digital power supply
Test mode control input pin. This pin is pulled up.
When this pin is “H”, the CXD1910AQ is not test mode.
Test mode is available only for device bender.
System reset input pin in active low.
When power on reset, set “L” for more than 40 clocks (SYSCLK).
System clock input pin.
To generate correct subcarrier frequency, precise 27MHz is required.
Pixel data clock output pin for 13.5MHz.
This clock is divided from SYSCLK.
This is used when 16-bit pixel data mode.
Digital ground
Vertical sync signal output pin.
Horizontal sync signal output pin.
This pin's function is selected by XIICEN (Pin 64).
When XIICEN = “H”, this pin is SONY SIO mode; SO serial out output pin.
When XIICEN = “L”, this pin is not used and output is high impedance.
Field ID output pin.
When control register bit “FIDS” = “1”:
“L” indicates 1st field, “H” indicates 2nd field.
When control register bit “FIDS” = “0”:
“H” indicates 1st field, “L” indicates 2nd field.
Digital power supply
Serial interface mode select input pin. This pin is pulled up.
When XIICEN = “L”, Pins 48 to 50 and 61 are I2C-BUS mode.
When XIICEN = “H”, Pins 48 to 50 and 61 are SONY SIO mode.
Pin
No.
52
53
54
55
56
57
58
59
60
61
62
63
64
F1
VDD
XTEST4
XRST
SYSCLK
PDCLK
VSS
VSYNC
HSYNC
SO
FID
VDD
XIICEN
I
—
I
I
I
O
—
O
O
O
O
—
I
Symbol I/O Function
– 6 –
CXD1910AQ
Electrical Characteristics
DC characteristics (Ta = 0 to +70°C, Vss = 0V)
Item
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Output high voltage
Output low voltage
Input leak current
Input leak current
Supply current
VIH
VIL
VOH1
VOL1
VOH2
VOL2
II1
II2
IDD
VDD = 5.0V ± 5%
VDD = 5.0V ± 5%
IOH = –2.4mA
VDD =4.75 to 5.25V
IOL = 4.8mA
VDD = 4.75 to 5.25V
IOH = –1.2mA
VDD = 4.75 to 5.25V
IOL = 2.4mA
VDD = 4.75 to 5.25V
VI = 0 to 5.25V
VDD = 4.75 to 5.25V
VI = 0V
VDD = 5.0V ± 5%
VDD = 5.0V ± 5%
2.2
VDD–0.8
VDD–0.8
–10
–40 –100
0.8
0.4
0.4
10
–240
70
∗6
V
V
V
V
V
V
µA
µA
mA
∗1
∗1
∗2
∗2
∗3
∗3
∗4
∗5
Symbol Conditions Min. Typ. Max. Unit Pins
∗1
PD0 to 15, TD8 to 10, XTEST1 to 4, TRST, TDI, TCK, SI/SDA, SCK/SCL, XCS/SA, XVRST, F1, XRST,
SYSCLK, XIICEN
∗2
PDCLK, VSYNC, HSYNC, FID, SO
∗3
TDO, TD0 to 10
∗4
PD0 to 15, TD8 to 10, TCK, SI/SDA, SCK/SCL, F1, XRST, SYSCLK
∗5
XTEST1 to 4, TRST, TDI, TMS, XCS/SA, XVRST, XIICEN
∗6
Not include analog supply current
DAC characteristics 1 (AVDD = 5V, R = 200Ω, VREF = 1.35V, Ta = 25°C)
Item
Resolution
Linearity error
Differential linearity error
Output full-scale current
Output offset voltage
Output full-scale voltage
Precision guaranteed output
voltage range
n
EL
ED
IFS
VOS
VFS
VOC
–2.5
–1.5
6.25
1.25
1.25
10
6.75
1.35
1.35
2.5
1.5
7.25
1
1.45
1.45
bit
LSB
LSB
mA
mV
V
V
Symbol Measurement conditions Min. Typ. Max. Unit
– 7 –
CXD1910AQ
AC characteristics
1. Pixel Data Interface
(1) 8-bit mode
tPDS tPDH
SYSCLK
PD0 to 7
(Ta = 0 to +70°C, VDD = 4.25 to 5.25V, Vss = 0V)
Pixel data setup time to SYSCLK
Pixel data hold time to SYSCLK
tPDS
tPDH
10
3
ns
ns
Item Symbol Min. Typ. Max. Unit
(2) 16-bit mode
tPDS tPDH
PDCLK
PD0 to 15
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
Pixel data setup time to PDCLK
Pixel data hold time to PDCLK
tPDS
tPDH
20
0
ns
ns
Item Symbol Min. Typ. Max. Unit
Item
Resolution
Linearity error
Differential linearity error
Output full-scale current
Output offset voltage
Output full-scale voltage
Precision guaranteed output
voltage range
n
EL
ED
IFS
VOS
VFS
VOC
–2.0
–1.0
9.5
1.9
1.9
10
10.0
2.0
2.0
2.0
1.0
10.5
1
2.1
2.1
bit
LSB
LSB
mA
mV
V
V
Symbol Measurement conditions Min. Typ. Max. Unit
DAC characteristics 2 (AVDD = 5V, R = 200Ω, VREF = 2.0V, Ta = 25°C)
– 8 –
CXD1910AQ
2. Serial Port Interface
fSCK
tPWLSCK tPWHSCK
tCSS
tSIS tSIH
tSOD
tSOH
tCSH
SCK
XCS
SI
SO
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
SCK clock rate
SCK pulse width Low
SCK pulse width High
Chip select setup time to SCK
Chip select hold time to SCK
Serial input setup time to SCK
Serial input hold time to SCK
Serial output delay time from SCK
Serial output hold time from SCK
fSCK
tPWLSCK
tPWHSCK
tCSS
tCSH
tSIS
tSIH
tSOD
tSOH
DC
100
100
150
150
50
10
3
3
30
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Item Symbol Min. Typ. Max. Unit
3. XVRST, F1
tVS tVH
PDCLK
XVRST
F1
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
XVRST, F1 setup time to PDCLK
XVRST, F1 hold time to PDCLK
tVS
tVH
20
0
ns
ns
Item Symbol Min. Typ. Max. Unit
– 9 –
CXD1910AQ
4. SYSCLK, PDCLK, VSYNC, HSYNC, FID
tPWHCLK tPWLCLK
fSYSCLK
tPDCLKD
tOD
tOH
SYSCLK
PDCLK
VSYNC,
HSYNC,
FID
tPDCLKD
(Ta = 0 to +70°C, VDD = 4.75 to 5.25V, Vss = 0V)
SYSCLK clock rate
SYSCLK pulse width Low
SYSCLK pulse width High
PDCLK delay time from SYSCLK
Control output delay time from SYSCLK
Control output hold time from SYSCLK
fSYSCLK
tPWLCLK
tPWHCLK
tPDCLKD
tCOD
tCOH
11
11
3
27
20
25
MHz
ns
ns
ns
ns
ns
Item Symbol Min. Typ. Max. Unit
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