Sony CXD1852Q Datasheet

MPEG1 Decoder

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Description

The CXD1852Q is a single-chip MPEG1 decoder
with a built-in CD-ROM decoder which allows
decoding of MPEG1 system, video and audio layers.
A built-in CD-ROM decoder enables direct connection
with a CD-DSP. Combining this chip with a control
microcomputer and 4-Mbit DRAM, etc. allows
configuration of a MPEG1 decoding system for video
CD players, etc.

Features

• Supply voltage: 3.3 ± 0.3V

• Input and output voltages: LVTTL compatible

• 5V can be applied as the input voltage (excluding

some pins)

• Allows decoding of MPEG1 system, video and

audio layers

• Built-in CD-ROM decoder allows direct connection

with a CD-DSP

• CD-ROM decoded output can be transferred to

and stored in an external DRAM

• RGB and YCbCr video data output allowed

• Built-in video sync generator

• Audio data output can support various DAC

• Supports various special playback modes

• Video CD PAL high resolution still picture can be

decoded with a single 4-Mbit DRAM

• 8-bit parallel and 4-line serial host interfaces

• CD-DA through operation allowed

CXD1852Q

120 pin QFP (Plastic)

Structure

Silicon gate CMOS IC

Applications

Video CD players, MPEG1 decoder boards, etc.

Block Diagram

CD-DSP

I/F

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CD-ROM

Decoder

To each circuit block

Host

interface

I/F

Host

MPEG

System

Decoder

DRAM

Controler

DRAM

I/F

MPEG

Audio

Decoder

MPEG

Video

Decoder

Video Postprocessor

&

Sync Generator

Signal

Video Sync

Audio

I/F

Video

I/F

– 1 –

E96656-PS

1. Pin Configuration

CXD1852Q

VSS

XTL0O

XTL0I

DD

V
HA2
HA3
HD0
HD1
HD2
HD3
HD4
HD5
HD6

DD

V

VSS
HD7

MA3
MA4
MA2
MA5
MA1

SS

V

MA6
MA0

BC

TCKI

TDI

TENA1

TDO

VST

10
11
12
13
14
15
16
17
18
19
20
21
22

25
26
27
28
29
30

23
24

HA1

119120

HA0

118

XRST

117

HRW

XHIRQ

116

115

XHDT

114

XHCS

113

DOIN

112

BCKI

111

DATI

110

LRCI

109

C2PO

108

DD

V

XTL2I

106

107

SS

V

XTL2O

105

104

DD

BCKO

FSXI

V

103

102

101

LRCO

100

DATO

99

DOUT

98

XSGRST

CLK0O

97

CSYNC

96

FID/FHREF

CBLNK/FSC

95

94

93

1

2
3
4
5
6
7
8
9

HSYNC

VSYNC

92

91

SS

V

DD

V

90
89

DCLK
B/Cb7

88

B/Cb6

87

B/Cb5

86

B/Cb4

85
84

B/Cb3
B/Cb2

83
82

B/Cb1

81

B/Cb0
G/Y7

80

G/Y6

79

G/Y5

78

G/Y4

77

G/Y3

76

SS

V

75

VDD

74

G/Y2

73

G/Y1

72

G/Y0

71

R/Cr7

70

R/Cr6

69

R/Cr5

68

R/Cr4

67

R/Cr3

66
65

R/Cr2
R/Cr1

64

R/Cr0

63

XVOE

62

SS

V

61

313233

SS

V

MA7

34

MA8

35

XRAS

37

36

XMWE

XCAS2/MA9

38

MD7

XCAS0

39

40

MD8

41 42

MD6

MD9

43

MD5

44

MD10

45

DD

V

– 2 –

46

SS

V

MD4

47

48

MD11

49

MD3

50

MD12

51

MD2

52

MD13

MD1

53

54

MD14

55

MD0

56

MD15

57

OSDB

OSDEN

58

59

OSDR

OSDG

60

DD

V

2. Pin Description

Pin No. Symbol I/O Description

CXD1852Q

2
3

5, 6, 119,
120

7 to 13,
16

17 to 21,
23, 24,
32, 33

34
35

36

VDD
VSS
XTL0O

XTL0I

HA0 to HA3

HD0 to HD7

MA0 to MA8

XRAS
XMWE

XCAS2/
MA9

O

I

I

I/O

O

O
O

O

+3.3V power supply
Connect to ground.
Video decoder master clock. Input the clock to XTL0I or connect an

oscillator between XTL0I and XTL0O. The recommended frequencies are
27MHz, 28.6363MHz (NTSC 8fsc) and 35.4686MHz (PAL 8fsc).

When the host interface operates in parallel mode, these pins are the
register address inputs. In serial mode, HA0 is the serial data input, and
HA1 to HA3 should be fixed to low level.

When the host interface operates in parallel mode, these pins are the
register data I/Os. In serial mode, HD0 is the serial data output, and HD1
to HD7 should be fixed to low level.

DRAM address signal outputs. Connect to the DRAM address pins so that
the numbers match.

Row address strobe signal output. Connect to the DRAM RAS signal pin.
DRAM write enable signal output. Connect to the DRAM WE signal pin.
Used when connecting 8 Mbits of DRAM. Connect to the upper word

(256K to 512K-1) DRAM CAS signal pin (for both the upper and lower
bytes) when the DRAM configuration is 256 Kwords × 16 bits × 2, and to
the MA9 pin (for two DRAMs) when the DRAM configuration is 512 Kwords
× 8 bits × 2.

37

38 to 43,
46 to 55

56

57 to 59

62

63 to 70

71 to 73,
76 to 88

81 to 88

XCAS0

MD0 to
MD15

OSDEN
OSDB,

OSDG,
OSDR

XVOE

R/Cr0 to
R/Cr7

G/Y0 to
G/Y7

B/Cb0 to
B/Cb7

O

I/O

I

I

I

O

DRAM column address strobe signal output. Connect to the lower word
(0 to 256K-1) DRAM CAS signal pin (for both the upper and lower bytes)
when the DRAM configuration is 256Kwords × 16 bits × 2, and to all
DRAM CAS signal pins in all other cases.

DRAM data signal I/Os. Connect to the DRAM data pins so that the
numbers match.

OSD enable signal. The enabled polarity is changed by the register
settings.

OSD data inputs. When the signal input to the OSDEN pin is enabled, the
color registered in the color table which is specified by these three inputs
(3 bits) is output as the image data.

Video output enable signal. Image data output and DCLK output are
enabled when this pin is low, and disabled when this pin is high (high
impedance). Note that the output control register must be set to output
enable for output to be enabled.

Image data outputs. The output data format (RGB, YCbCr, etc.) and the
correspondence between the pins and output data can be changed by
setting the registers.

89

DCLK

I/O

Dot clock (DCLK) signal. The DCLK frequency is normally 13.5MHz.
DCLK can be input from this pin, or frequency divided from the clock input
and output from this pin.

– 3 –

Pin No. Symbol I/O Description

Horizontal sync signal. When using the built-in sync generator, the dot

92

HSYNC

I/O

clock (DCLK) is frequency divided and output. When not using the sync
generator, this pin is an input.

Vertical sync signal. When using the built-in sync generator, the dot clock

93

VSYNC

I/O

(DCLK) is frequency divided and output. When not using the built-in sync
generator, this pin is an input.

Field identification signal (FID) and horizontal sync phase reference signal
(FHREF). The signal to be used is set in the register. When set to FID, this
pin is an output if using the built-in sync generator, and an input if not

94

FID/FHREF

I/O

using the built-in sync generator. High corresponds to odd fields. When set
to FHREF, this pin outputs the signal obtained by frequency dividing XTL0.
When XTL0 is 8fsc, this signal is equivalent to the HSYNC cycle, and can
be used for phase comparison with the HSYNC signal.

Composite blanking signal (CBLNK) and fsc signal. The signal to be used
is set in the register. When set to CBLNK, this pin is an output if using the
built-in sync generator, and an input if not using the built-in sync generator.
When set to fsc, this pin outputs the signal obtained by frequency dividing

95

CBLNK/
FSC

I/O

XTL0. The frequency division ratio can be selected from 1/8 or 1/16.

CXD1852Q

96

97

98

99
100
101
102

103

106

107

109
110

CSYNC

XSGRST

CLK0O
DOUT

DATO
LRCO
BCKO

FSXI

XTL2O

XTL2I

C2PO
LRCI

Composite sync signal obtained by frequency dividing DCLK. This pin

O

cannot be input.
Sync generator reset signal input. The built-in sync generator is initialized

I

by setting this pin low.
Output for clock obtained by frequency dividing XTL0. The frequency

O

division ratio can be selected from 1, 1/2, 1/4 or 1/8.
Audio digital output.

O

Audio serial data output to DAC.

O

L/R clock output to DAC.

O

Bit clock output to DAC.

O

Audio interface clock input. Input 256fs (11.2896MHz), 384fs

I

(16.9344MHz), 512fs (22.5792MHz), or 768fs (33.8688MHz), etc.
Master clock for CD-ROM and audio decoders. Input the clock to XTL2I or

O

connect an oscillator between XTL2I and XTL2O. The recommended
frequency is 45MHz. Note that this clock is for the internal circuits, and the

I

input and output are not synchronized.
C2 pointer input from CD-DSP. Indicates that the DATI input contains an

I

error.
LR clock input from CD-DSP. Indicates the L or R channel of DATI.

I
111
112
113
114

115

DATI
BCKI
DOIN
XHCS

XHDT

I/O

Serial data input from CD-DSP.

I

Bit clock input from CD-DSP. This clock strobes the DATI input.

I

Digital data input from CD-DSP.

I

Chip select signal input during register access.

I

Wait signal output during register access. This pin is valid only when the
host interface operates in parallel mode. This pin functions as an open
drain, and should therefore be pulled up. It should be pulled up when the
host interface operates in serial mode as well.

– 4 –

Pin No. Symbol I/O Description

CXD1852Q

116

117

118

25
26
27
28
29
30

HRW

XHIRQ

XRST
BC

TCKI
TDI
TENA1
TDO
VST

R/W signal input when the host interface operates in parallel mode. Serial

I

clock input in serial mode.
Interrupt request signal output. This pin functions as an open drain, and

O

should therefore be pulled up.
Hardware reset signal input. All operation is initialized by setting this pin

I

low.
Test. Leave open.

—

Test. Leave open.

—

Test. Leave open.

—

Test. Leave open.

—

Test. Leave open.

—

Test. Connect to ground.

—

– 5 –

3. Electrical Characteristics

3-1. Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)

CXD1852Q

Item
Supply voltage
Input pin voltage
Input pin voltage
Output pin voltage
Output pin voltage
I/O pin voltage
Allowable power dissipation
Operating temperature
Storage temperature

∗1

XTL0I and XTL2I pins

∗2

Input pins other than those in ∗1above.

∗3

XTL0O and XTL2O pins

∗4

Output pins other than those in ∗3above.

Symbol Rating Unit Remarks
VDD
VI
VI
VO
VO
VI/O
PD
Topr
Tstg

–0.5 to +4.6

–0.5 to VDD + 0.5

–0.5 to +5.5

–0.5 to VDD + 0.5

–0.5 to +5.5
–0.5 to +5.5

1.0

–20 to +75

–55 to +150

V
V
V
V
V

V
W
°C
°C

∗1
∗2
∗3
∗4

3-2. Recommended Operating Conditions (Ta = –20 to +75°C, VSS = 0V)

Item
Supply voltage
High level input voltage
High level input voltage
Low level input voltage
Input rise time
Input fall time
Operating temperature

∗1

XTL0I and XTL2I pins

∗2

I/O pins and input pins other than those in ∗1above.

Symbol Min.
VDD
VIH
VIH
VIL
Tr
Tf
Topr

3.0

2.2

2.2
0
0
0

–20

Typ.

3.3
—
—
—
—
—
—

Max.

3.6

VDD

5.0

0.8
50
50
75

Unit Remarks

V

∗1

V

∗2

V

V
ns
ns
°C

– 6 –

CXD1852Q

3-3. DC Characteristics (Ta = –20 to +75°C, VSS = 0V, VDD = 3.3 ±0.3V)

Item

Average operating
supply current

Input leak current
High level output voltage
High level output voltage
Low level output voltage
Low level output voltage

Output leak current
Feedback resistance

Logic threshold value
High level output voltage
Low level output voltage

∗1

Input pins other than XTL0I and XTL2I

∗2

I/O pins and output pins other than XTL0O and XTL2O

∗3

Oscillators (between XTL0I and XTL0O, and between XTL2I and XTL2O)

∗4

XTL0I and XTL2I pins

∗5

XTL0O and XTL2O pins

Symbol

IDD
II

VOH
VOH
VOL
VOL

IOZ
RFB

LVth
VOH
VOL

Measurement conditions Min.

—

VI = 0 to 5.0V
IOH = –2mA
IOH = –100µA
IOL = 4mA
IOL = 100µA
VO = 0 to 5.0V,

output disabled status
VI = 0V or VI = VDD

–40

VDD – 0.8

—
—
—

–40

250k

—
IOH = –12mA
IOL = 12mA

VDD/2

—

Typ.

—
—

—

VDD – 0.4

—

0.04
—

1M

VDD/2

—
—

Max.

100

40
—
—

0.4
—

40

2.5M
—
—

VDD/2

Unit Remarks

mA

∗1

µA

∗2

V

∗2

V

∗2

V

∗2

V

∗2

µA

∗3

Ω

∗4

V

∗5

V

∗5

V

3-4. Clock Signal AC Characteristics

tCX0

tWLX0

XTL0I tWHX0

tCX2

tWLX2

XTL2I tWHX2

Item
XTL0I frequency
XTL0I cycle
XTL0I high level interval
XTL0I low level interval
XTL2I frequency
XTL2I cycle
XTL2I high level interval
XTL2I low level interval

∗1

When using in combination with the XTL0O pin as an oscillator, the maximum oscillation frequency is 50MHz.

∗2

When using in combination with the XTL2O pin as an oscillator, the maximum oscillation frequency is 50MHz.

Symbol Min.
fX0

tCX0
tWHX0
tWLX0

fX2

tCX2
tWHX2
tWLX2

—

33.3
10
10

44.7
—

8
8

Typ.

—
—
—
—

45.1584

22.2
—
—

Max.

60
—
—
—

45.4
—
—
—

Unit Remarks

MHz

ns
ns
ns

MHz

ns
ns
ns

∗1
∗1

∗2
∗2

– 7 –

3-5. Host Interface AC Characteristics

3-5-1. Serial Mode (write, read)

XHCS

CXD1852Q

tSCS tWLSK tCSK

HRW

(SCK)

tSSI tHSI

HA0

(SI)

HD0
(SQ)

Item
Serial clock frequency
Serial clock cycle
Serial clock high level interval
Serial clock low level interval
Chip select setup time
Chip select hold time
Serial input setup time

tWHSK

tDSQtLZSQ

Symbol Min.
fSK

tCSK
tWHSK
tWLSK
tSCS
tHCS
tSSI

—
500
100
100

0

500

30

Max.

2
—
—
—
—
—
—

tHCS

tOHSQ

Unit Remarks

MHz

ns
ns
ns
ns
ns
ns

tHZSQ

Serial input hold time
Serial output enable time
Serial output determination time
Serial output hold time
Serial output disable time

tHSI
tLZSQ
tDSQ
tOHSQ
tHZSQ

30

0

—

5
0

—
15
40
—
15

ns
ns
ns
ns
ns

– 8 –

3-5-2. Parallel Mode, Register Write

HA0 to 3

tSA

tWCSH

XHCS

XHRW

CXD1852Q

tHA

tWWL1

XHDT

HD0 to 7

Item
Address setup time
Address hold time
Chip disable time
Write pulse width
Write pulse hold time
Wait signal delay time
HD output disable time (for WR)
HD input setup time
HD input hold time

tDWA1

Symbol Min.

tSA
tHA
tWCSH
tWWL1
tHW1
tDWA1
tHZQ2
tSD1
tHD1

20
20
20
60
10
—
—
25
25

tHW1

tSD1 tHD1tHZQ2

Max.

—
—
—
—
—
15
15
—
—

inputoutput

Unit Remarks

ns
ns
ns
ns
ns
ns
ns
ns
ns

∗1
∗2

∗3
∗2, ∗4
∗1, ∗4
∗5
∗2
∗2

∗1

Specified for the edge of XHCS or HRW, whichever is later.

∗2

Specified for the edge of XHCS or HRW, whichever is earlier.

∗3

Interval during which both XHCS and HRW are low.

∗4

Applies only to access resulting in wait status.

∗5

Do not apply data while output is enabled.

– 9 –