Sony CXD1818R Datasheet

CD-ROM Decoder

For the availability of this product, please contact the sales office.

Description

The CXD1818R is a CD-ROM decoder LSI with a built-in Fast SCSI controller. This supports 32× speed playback.

Features

• Ultra SCSI controller (Target mode)

• Maximum transfer speed of 20MB/s (when using

Ultra SCSI synchronous transfer)

• SCSI overhead reduced by executing multiple

SCSI sequences

• Supports SCAM Level 2

• Compatible with CD-ROM, CD-I and CD-ROM XA

formats

• Real-time error correction

• Capable of handling up to 32× speed playback

• Multiblock auto-transfer function

• Can read subcode-Q data for each byte from the

sub CPU

• Real-time subcode (R to W) error correction

• Serial transfer of commands to CD DSP

• Connectable with standard DRAM of up to 8M bits

(1024K bytes)

• DRAM bit width selectable for 8 bits or 16 bits

• ESP function

CXD1818R

144 pin LQFP (Plastic)

Applications

CD-ROM drives

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VDD –0.5 to +7.0 V

• Input voltage VI –0.5 to VDD + 0.5 V

• Output voltage VO –0.5 to VDD + 0.5 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –55 to +150 °C

Recommended Operating Conditions

• Supply voltage VDD 4.5 to 5.5 (5.0 typ.) V

• Operating temperature Topr –20 to +75 °C

• Crystal oscillation X'tal 40 MHz

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E97528-PS

Connection Example

CXD1818R

Buffer RAM

16bit10bit

CD DSP

CPU data bus CPU address bus

sub CPU

EXCK SBIN SCOR WFCK C2PO BCLK MDAT LRCK XLAT DATO DSTB GRST DACD LRCO BCKO DSPCK GSCR XROF

Address Decoder

XRASXLCASXUCAS XMWR

CXD1818R

CD-ROM Decoder

SCSI I/F

A (6:0)XCS XWR XWAT XRD D (7:0) INT

MDB

(15:0)MA(9:0)

XDB (7:0)

8bit7bit

XATN XBSY XACK XRST

XSEL

XMSG

XCD

XREQ

XIO

XDBP,

SCSI Bus

– 2 –

Block Diagram

CXD1818R

EXCK

SBIN

SCOR

WFCK

C2PO BCLK

MDAT

LRCK

DSPCK

GSCR DATO

XLAT

DSTB BCKO DACD LRCO GRST XROF

MA (0:9) MDB (0:15)XMWRXUCAS

54 to 60, 62 to 64 71 to 78, 80 to 87

Buffer

Address Gen.

Priority Resolver

90 91 92 93 94

96 97

99 100 101 102 103 106 107 108 109 110

CD DSP

I/F

CD-ROM Decoder Block

Deinterleave & ECC

Sync Control

Descrambler

XLCASXRAS

DMA

Sequencer

Subcode

Main Data

Error Correction

67 68

16byte FIFO

FIFO Control

Buffer

Handshake

24bit Transfer Byte Counter

Microcode

Core

Registers

Microcode

ROM

SCSI

Handshake

SCSI

Phase Ctrl

Arbitration

Selection

SCSI Controller Block

VCO

• 5

• 8

•

41 29

30 26 24 36 39 35 43

44 45

XDB (0:7) XDBP

XREQ XACK

XRST XBSY XATN XSEL XCD XMSG XIO

CM1 AC

sub CPU

I/F

142

143

141

XWRINT

123 to 129 131 to 138

144

XRD

D (7:0)A (0:6) XWAT XTL2 CLK

122

Clock

Gen.

XTL1

XRESXCS

– 3 –

Pin Configuration

CXD1818R

GRST XROF

TST0 TST1 TST2 TST3

V TST4 TST5 TST6 TST7

VDD

XWAT

VDD

INT

XCS

XWR

XRD

108

LRCO

107

DACD

106

BCKO

105

104

DSTB

102103

XLAT

101

DATO

100

GSCR

DSPCK

LRCK

MDAT

BCLK

C2PO

WFCK

SCOR

109 110

111 112 113

114 115

116 117

118

119 120

121 122

123

124

125 126

A3 A4

127

128

129

130 131

D0 D1

132

133

134

135

136

137

138

139 140 141 142 143 144

XDB0

XDB1

XDB2

XDB3

XDB4

14 15

XDB5

XDB6

SBIN

EXCK

XDB7

MDB15

XDBP

MDB14

MDB13

XATN

MDB12

MDB11

MDB10

27 28

XBSY

MDB9

MDB8

XACK

XRST

MDB7

MDB6

7677

MDB5

MDB4

MDB3

XWSG

MDB2

XSEL

72 71 70 69

67 66 65

61 60 59 58 57

54 53 52

51 50

49 48 47 46 45 44

42 41

40 39 38

MDB1 MDB0

V VSS XMWR XLCAS XUCAS XRAS MA9 MA8 MA7

V MA6 MA5 MA4 MA3 MA2 MA1 MA0 XRES

V VSS CLK XTL1 XTL2 AVDD AVSS AC CM1 XIO V

XREQ V

XCD V

VSS

– 4 –

Pin Description

Symbol I/O Logic Classification Description

No.

CXD1818R

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17

VSS VDD XDB0 VSS XDB1 VSS VDD XDB2 VSS XDB3 XDB4 VSS VSS VDD XDB5 VSS XDB6

— —

I/O

—

I/O

— —

I/O

— I/O I/O

—

— I/O

— —

Negative

—

Negative

— —

Negative

— Negative Negative

—

— Negative

Power Power SCSI I/F Power SCSI I/F Power Power SCSI I/F Power SCSI I/F SCSI I/F Power Power Power SCSI I/F Power SCSI I/F

VSS VDD SCSI data bus bit 0 VSS SCSI data bus bit 1 VSS VDD SCSI data bus bit 2 VSS SCSI data bus bit 3 SCSI data bus bit 4 VSS VSS VDD SCSI data bus bit 5 VSS

SCSI data bus bit 6 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

VSS XDB7 VSS VDD XDBP VSS XATN VSS XBSY VSS VDD XACK XRST VSS VSS VDD VSS

—

I/O

— —

I/O

—

I/O

—

I/O

—

— I/O I/O

—

Negative

— —

Negative

—

Negative

—

Negative

—

— Negative Negative

—

Power SCSI I/F Power Power SCSI I/F Power SCSI I/F Power SCSI I/F Power Power SCSI I/F SCSI I/F Power Power Power Power

VSS SCSI data bus bit 7 VSS VDD SCSI data bus parity VSS SCSI control bus XATN signal VSS SCSI control bus XBSY signal VSS VDD SCSI control bus XACK signal SCSI control bus XRST signal VSS VSS VDD

VSS 35 36

XMSG XSEL

I/O I/O

Negative Negative

SCSI I/F SCSI I/F

SCSI control bus XMSG signal

SCSI control bus XSEL signal

– 5 –

CXD1818R

Pin No.

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Symbol I/O Logic Classification Description

VSS VDD XCD VSS XREQ VSS XIO CM1 AC AVSS AVDD XTL2 XTL1 CLK VSS

— —

I/O

—

I/O

—

I/O

I — — O

I O —

— —

Negative

—

Negative

—

Negative

— —

—

Power Power SCSI I/F Power SCSI I/F Power SCSI I/F VCO Charge Pump Out VCO Control Analog Power Analog Power System I/F System I/F System I/F Power

VSS VDD SCSI control bus XCD signal VSS SCSI control bus XREQ signal VSS SCSI control bus XIO signal Multiplier VCO charge pump output Multiplier VCO control voltage input Analog VSS Analog VDD Crystal oscillation circuit output Crystal oscillation circuit input Clock output

VSS 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

VDD XRES MA0 MA1 MA2 MA3 MA4 MA5 MA6 VSS MA7 MA8 MA9 XRAS XUCAS XLCAS XMWR

—

I O O O O O O O — O O O O O O O

—

Negative

—

Negative Negative Negative Negative

Power System I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F Power BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F

VDD CXD1818R reset signal Address bus output bit 0 to buffer memory Address bus output bit 1 to buffer memory Address bus output bit 2 to buffer memory Address bus output bit 3 to buffer memory Address bus output bit 4 to buffer memory Address bus output bit 5 to buffer memory Address bus output bit 6 to buffer memory VSS Address bus output bit 7 to buffer memory Address bus output bit 8 to buffer memory Address bus output bit 9 to buffer memory Buffer memory RAS (Row Address Strobe) signal Buffer memory CAS (Column Address Strobe) signal Buffer memory CAS (Column Address Strobe) signal

Data write strobe signal to buffer memory 69 70 71 72 73

VSS VDD MDB0 MDB1 MDB2

—

— I/O I/O I/O

— —

Power Power BufMem I/F BufMem I/F BufMem I/F

VSS VDD Buffer memory data bus bit 0 Buffer memory data bus bit 1 Buffer memory data bus bit 2

– 6 –

Symbol I/O Logic Classification Description

No.

CXD1818R

74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89

MDB3 MDB4 MDB5 MDB6 MDB7 VSS MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 VSS VDD

EXCK

I/O I/O I/O I/O I/O

— I/O I/O I/O I/O I/O I/O I/O I/O

—

— —

BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F Power BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F BufMem I/F Power Power

CD DSP I/F

Buffer memory data bus bit 3 Buffer memory data bus bit 4 Buffer memory data bus bit 5 Buffer memory data bus bit 6 Buffer memory data bus bit 7 VSS Buffer memory data bus bit 8 Buffer memory data bus bit 9 Buffer memory data bus bit 10 Buffer memory data bus bit 11 Buffer memory data bus bit 12 Buffer memory data bus bit 13 Buffer memory data bus bit 14 Buffer memory data bus bit 15 VSS VDD SBIN readout clock

(connected to the EXCK pin (Pin 65) of the CXD3000)

93 94

95 96 97 98

99 100 101

102 103 104

SBIN

SCOR

WFCK C2PO

BCLK MDAT LRCK VSS DSPCK

GSCR DATO

XLAT DSTB VSS

—

O O O

—

I I

I I I

—

I I

CD DSP I/F

CD DSP I/F CD DSP I/F

CD DSP I/F CD DSP I/F CD DSP I/F Power CD DSP I/F

CD DSP I/F CD DSP I/F

—

Power

Subcode serial signal (connected to the SBSO pin (Pin 64) of the CXD3000)

Subcode sync signal (connected to the SCOR pin (Pin 63) of the CXD3000)

Write frame clock (connected to the WFCK pin (Pin 62) of the CXD3000)

C2 pointer signal. Indicates that an error exists in MDAT. Bit clock. MDAT strobe signal Serial data stream from CD DSP LR signal. Indicates MDAT left or right channel VSS DSP crystal input SCOR synchronized with DSP data output

(connected to the GRSCOR pin (Pin 113) of the CXD3000) Serial data output from sub CPU to CD DSP DATO latch signal. Latched at the rising edge. DATO transfer clock VSS

105 106

107

VDD BCKO

DACD

—

Power CD DSP I/F

CD DSP I/F

VDD Bit clock

(connected to the BCKI pin (Pin 30) of the CXD3000) Audio data output to DAC

(connected to the PCMDI pin (Pin 28) of the CXD3000)

– 7 –

CXD1818R

Pin No.

108

109

110 111

112 113 114 115 116 117 118 119 120

Symbol I/O Logic Classification Description

LRCO

GRST

XROF TST0

TST1 TST2 TST3 VSS TST4 TST5 TST6 TST7 VSS

I I

I I I

—

I I I I

—

Negative

—

CD DSP I/F

CD DSP I/F Test I/F

Test I/F Test I/F Test I/F Power Test I/F Test I/F Test I/F Test I/F Power

LR clock output to DAC (connected to the LRCKI pin (Pin 26) of the CXD3000)

GRSCOR resynchronization output (connected to the SCSY pin (Pin 68) of the CXD3000)

DSP RAM overflow input (connected to the XROF pin (Pin 45) of the CXD3000)

Test pin 0 Test pin 1 Test pin 2 Test pin 3 VSS Test pin 4 Test pin 5 Test pin 6 Test pin 7

VSS 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137

VSS XWAT A0 A1 A2 A3 A4 A5 A6 VSS D0 D1 D2 D3 D4 D5 D6

—

I I I I I I I

— I/O I/O I/O I/O I/O I/O I/O

—

Negative

—

Power sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F Power sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F

VSS Wait signal for sub CPU buffer memory access CXD1818R built-in register address bus bit 0 CXD1818R built-in register address bus bit 1 CXD1818R built-in register address bus bit 2 CXD1818R built-in register address bus bit 3 CXD1818R built-in register address bus bit 4 CXD1818R built-in register address bus bit 5 CXD1818R built-in register address bus bit 6 VSS Sub CPU data bus bit 0 Sub CPU data bus bit 1 Sub CPU data bus bit 2 Sub CPU data bus bit 3 Sub CPU data bus bit 4 Sub CPU data bus bit 5

Sub CPU data bus bit 6 138 139 140 141 142 143 144

D7 VSS VDD INT XCS XWR XRD

I/O

— —

I I I

— —

Selectable

Negative Negative Negative

sub CPU I/F Power Power sub CPU I/F sub CPU I/F sub CPU I/F sub CPU I/F

Sub CPU data bus bit 7

VSS

VDD

Interrupt to sub CPU

CXD1818R chip select signal

CXD1818R built-in register write signal

CXD1818R built-in register read signal

– 8 –

CXD1818R

Electrical Characteristics (VDD = 5V ± 10%, VSS = 0V, Topr = –20 to +75°C)

Item

TTL input level pin High level input voltage

TTL input level pin Low level input voltage

CMOS input level pin High level input voltage

CMOS input level pin Low level input voltage

CMOS Schmitt input level pin High level input voltage

CMOS Schmitt input level pin Low level input voltage

CMOS Schmitt input level pin Input voltage hysteresis

TTL Schmitt input level pin High level input voltage

TTL Schmitt input level pin Low level input voltage

Symbol Conditions Min. Typ. Max. Unit

VIH1

VIL1

VIH2

VIL2

VIH4

VIL4

VIH4 – VIL4

VIH5

VIL5

2.2

0.8

0.7VDD

0.3VDD

0.8VDD

0.2VDD

0.6

2.2V

0.8V

Applicable

pins

∗1

∗2

∗3

∗4

TTL Schmitt input level pin Input voltage hysteresis

SCSI Schmitt input level pin High level input voltage

SCSI Schmitt input level pin Low level input voltage

SCSI Schmitt input level pin Input voltage hysteresis

Bidirectional pin with pull-up resistor Input current

Input voltage High level output voltage High level output voltage SCSI high level output voltage Low level output voltage SCSI low level output voltage Input leakage current Oscillation cell high level input voltage

VIH5 – VIL4

VIHS

VILS

VIHTS – VILTS

IIL3 VIN6

VOH1 VOH2 VOHS VOL1 VOLS II1 VIH4

VIN = 0V Analog input

IOH = –2mA IOH = –6mA

IOL = 4mA IOL = 48mA VIN = VSS or VDD

2.2V

–40

VSS VDD – 0.8 VDD – 0.8

2.5

–10

0.7VDD

0.4

–100

0.8V

–240

VDD

3.7

0.4

0.5 10

µA

V V V V V V

µA

∗4

∗11

∗5

∗13

∗6 ∗7

∗12

∗8

∗11

∗9

∗10

Oscillation cell low level input voltage Oscillation cell logic threshold value Oscillation cell feedback resistance value Oscillation cell high level output voltage Oscillation cell low level output voltage

VIL4 LVTH RFB VOH3 VOL3

VIN = VSS or VDD IOH = –12mA IOL = 12mA

– 9 –

250k

0.5VDD

0.5VDD 1M

0.3VDD

2.5M

0.5VDD

V V

Ω

V V

∗1

D7 to 0, MDBF to 0, MDAT, LRCK, C2PO, SBIN, SCOR, WFCK, XROF

∗2

GRST, DACD, LRCK, BCKO, TST7 to 0

∗3

XRES

∗4

A6 to 0, XWR, XRD, XCS, BCLK, DSPCK, GSCR

∗5

D7 to 0, MDBF to 0

∗6

All output pins except XTL2, XRAS, XUCAS, XLCAS, XMWR and CLK

∗7

XRAS, XUCAS, XLCAS, XMWR, CLK, CM1

∗8

All output pins except XTL2

∗9

All input pins except ∗5and XTL1

∗10

Input: XTL1, Output: XTL2

∗11

XRST, XBSY, XSEL, XATN, XMSG, XCD, XIO, XREQ, XACK, XDBP, XDB7 to 0

∗12

XREQ, XACK, XDBP and XDB7 to 0 when active negation is ON

∗13

I/O Capacitance (VDD = VI = 0V, f = 1MHz)

CXD1818R

Item Input capacitance Output capacitance I/O capacitance

Symbol Min. Typ. Max. Unit CIN COUT CI/O

9 11 11

pF pF pF

– 10 –

AC Characteristics

1. Sub CPU Interface (Output Load = 50pF)

(1) Read

A6 to 0

XCS

XRD

D7 to 0

Tsar

Tdrd

CXD1818R

Thar

Trrl

Tfrd

Item Address setup time (for XCS & XRD ↓) Address hold time (for XCS & XRD ↑) Data delay time (for XCS & XRD ↓) Data float time (for XCS & XRD ↑)

(2) Write

A6 to 0

XCS

XWR

D7 to 0

Tsaw

Symbol Min. Typ. Max. Unit Tsar Thar Tdrd Tfrd

Twwl

10 10

Thwa

Tsdw Thdw

35 15

ns ns ns ns

Item Address setup time (for XCS & XWR ↓) Address hold time (for XCS & XWR ↑) Data setup time (for XCS & XWR ↓) Data hold time (for XCS & XWR ↑) Low level XWR pulse width

Symbol Min. Typ. Max. Unit Tsaw Thaw Tsdw Thdw Twwl

20 10 20 10 30

ns ns ns ns ns

– 11 –

2. CD DSP Interface

BCKRED = "H"

BCLK

DATA

LRCK C2PO

BCKRED = "L"

BCLK

Tbck Tbck

Tsb1

Tbck Tbck

Thb1

CXD1818R

Tsb2Thb2

DATA

LRCK C2PO

Item BCLK frequency BCLK pulse width DATA setup time (for BCLK) DATA hold time (for BCLK) LRCK, C2PO setup time (for BCLK) LRCK, C2PO hold time (for BCLK)

Tsb1

Thb1

Symbol Min. Typ. Max. Unit Fbck Tbck Tsb1 Thb1 Tsb2 Thb2

19 10 10 10 10

Tsb2Thb2

26 MHz

ns ns ns ns ns

– 12 –

3. DRAM Interface (Output Load = 30pF)

(1) Read

iCLK

Tma0

MA9 to 0

Trasl

XRAS

CXD1818R

Tma1

Trc

Trash

XUCAS XLCAS

XMWR

MDBF to 0

Tcasl

Tcash

Tmdrh

Tmdrs

Symbol Min. Typ. Max. Unit Trc Tma0 Tma1 Trasl Trash Tcasl Tcash

5Tw

13 11

6 6 7 6

24 22 12 11 14 12

45 41 23 20 25 22

ns ns ns ns ns ns ns

"H"

Data setup time (for XTL2 ↑) Data hold time (for XCAS ↑)

Tmdrs Tmdrh

2 0

– 13 –

ns ns

(2) Write

iCLK

MA9 to 0

XRAS

XUCAS XLCAS

XMWR

Tma0

Trasl

Tmwrl

Tma1

Tmdws

Tcasl

CXD1818R

Trc

Trash

Tcash

Tmwrh

Tmdwh

MDBF to 0

Item Random read/write cycle time Address delay time (for XTL2 ↑) Address delay time (for XTL2 ↑) XRAS ↓ delay time (for XTL2 ↑) XRAS ↑ delay time (for XTL2 ↑) XCAS ↓ delay time (for XTL2 ↑) XCAS ↑ delay time (for XTL2 ↑) XMWR ↓ delay time (for XTL2 ↑) XMWR ↑ delay time (for XTL2 ↑) Data setup time (for XTL2 ↑) Data hold time (for XTL2 ↑)

Symbol Min. Typ. Max. Unit Trc Tma0 Tma1 Trasl Trash Tcasl Tcash Tmwrl Tmwrh Tmdws Tmdwh

5Tw

13 11

6 6 7 6 7 6

24 22 12 11 14 12 14 11 28 14

45 41 23 20 25 22 25 21 51 26

ns ns ns ns ns ns ns ns ns ns ns

– 14 –

(3) Refresh (RAS only refresh)

iCLK

Tma0

MA9 to 0

CXD1818R

XRAS

XUCAS XLCAS

XMWR

Item Random read/write cycle time Address delay time (for XTL2 ↑) XRAS ↓ delay time (for XTL2 ↑) XRAS ↑ delay time (for XTL2 ↑)

Trasl

Trash

Symbol Min. Typ. Max. Unit Trc Tma0 Trasl Trash

5Tw

6 6

24 12 11

43 23 20

ns ns ns ns

“H”

– 15 –

4. SCSI Interface

(1) SCSI asynchronous transfer timing

When receiving: Initiator → Target

XREQ

CXD1818R

XACK

XDB

Taads Tardh

When transmitting: Target → Initiator

XREQ

XACK

XDB

Tards

Taadh

Item XDB setup time (for XACK ↓)

Taanrad

Taaarnd

Taanrad

Symbol Min. Typ. Max. Unit Taads

ns XDB hold time (for XREQ ↑) XDB setup time (for XREQ ↓) XDB hold time (for XREQ ↓) XREQ rise delay time (for XACK ↓) XREQ fall time (for XACK ↑)

Tardh Tards Taadh Taaarnd Taanrad

0 30 60 30 30

– 16 –

70 85

ns ns ns ns ns

(2) SCSI synchronous transfer timing

When receiving: Initiator → Target

XACK

XDB

Tnads

Tnadh

When transmitting: Target → Initiator

Tnrap Tnrnp

XREQ

CXD1818R

XDB

Tnrds

Tnrdh

Item XDB setup time (for XACK ↓) XDB hold time (for XACK ↓) XDB setup time (for XREQ ↓) XDB hold time (for XREQ ↓) XREQ assert time XREQ negate time

Symbol Min. Typ. Max. Unit Tnads Tnadh Tnrds Tnrdh Tnrap Tnrnp

15 10 80

105

110

ns ns ns ns ns ns

– 17 –

(3) Fast SCSI synchronous transfer timing

When receiving: Initiator → Target

XACK

XDB

Tfads

Tfadh

When transmitting: Target → Initiator

Tfrap Tfrnp

XREQ

CXD1818R

XDB

Tfrds

Tfrdh

Item XDB setup time (for XACK ↓) XDB hold time (for XACK ↓) XDB setup time (for XREQ ↓) XDB hold time (for XREQ ↓) XREQ assert time XREQ negate time

Symbol Min. Typ. Max. Unit Tfads Tfadh Tfrds Tfrdh Tfrap Tfrnp

15 10 55 55

ns ns ns ns ns ns

– 18 –

(4) SCSI synchronous transfer (Ultra) timing

When receiving: Initiator → Target

XACK

XDB

Tuads

Tuadh

When transmitting: Target → Initiator

Turap Turnp

XREQ

CXD1818R

XDB

Turds

Turdh

Item XDB setup time (for XACK ↓) XDB hold time (for XACK ↓) XDB setup time (for XREQ ↓) XDB hold time (for XREQ ↓) XREQ assert time XREQ negate time

Symbol Min. Typ. Max. Unit Tuads Tuadh Turds Turdh Turap Turnp

15 10

11.5

16.5

ns ns ns ns ns ns

– 19 –

5. XTL1 and XTL2 Pins

(1) When using self-excited oscillation

CXD1818R

Item

Symbol Min. Typ. Max. Unit

Oscillation frequency Fmax 40.0 MHz

(2) When inputting a pulse to the XTL1 pin

TwlxTwhx

Vihx

DD/2

Vilx

Item

High level pulse width

Symbol Min. Typ. Max. Unit

Twhx

ns Low level pulse width Pulse cycle

Twhx Tw

10 25

XRES Pin Reset to IC

Trs

Item

Symbol Min. Typ. Max. Unit

XRES "L" hold time Trs 100 ns

– 20 –

CXD1818R

Contents

[1] Description of Registers........................................................................................................................... 22

1-1. Description of Decoder Block Registers............................................................................................... 22

1-2. Description of SCSI2 Controller Block Registers.................................................................................. 51

1-3. Common Registers............................................................................................................................... 66

[2] Description of SCSI Controller Block Commands ................................................................................. 77

2-1. Precautions when Executing Commands............................................................................................. 78

2-2. Category 00 Commands....................................................................................................................... 78

2-3. Category 01 Commands....................................................................................................................... 83

2-4. Category 10 Commands....................................................................................................................... 85

2-5. Category 11 Commands....................................................................................................................... 88

[3] Appendix A................................................................................................................................................. 93

3-1. List of CD-ROM Decoder Block Registers............................................................................................ 93

3-2. List of SCSI Controller Block Registers................................................................................................ 99

3-3. List of Common Registers .................................................................................................................. 103

3-4. Register Reset Conditions.................................................................................................................. 105

[4] Appendix B............................................................................................................................................... 111

4-1. Summary of SCSI Controller Block Commands................................................................................. 111

– 21 –

[1] Description of Registers

The CXD1818R's register address area is allotted as shown in the table below.

CXD1818R

Address

00h to 4Fh

50h to 6Fh 70h to 7Fh

0xx xxxx

100 xxxx 101 xxxx

110 xxxx 111 xxxx

CD-ROM decoder block

SCSI2 interface block CD-ROM decoder/SCSI2 interface common block

Description

1-1. Description of Decoder Block Registers

1-1-1. 00h

(1) RAWMIN (raw minute) register (read)

RAWMIN (raw minute) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

00h (R)

REWMIN

The Header Minute byte for the sector being sent from the CD DSP while DECINT is active can be read from this register. A difference of two sectors exists between the RAWxxx and BFxxx registers during the write-only and real-time correction modes.

(2) CONFIG0 (configuration 0) register (write)

CONFIG0 (configuration 0) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

00h (W)

CINT POL

RAM SIZE1

RAM SIZE0

RAM8 BITW

RAM2 CAS

"L"

CLK SEL1

CLK SEL0

bit 7: CINTPOL (sub CPU interrupt polarity)

High: The INT pin becomes active high. When the register is inactive, it goes low. Low: The INT pin becomes active low. When the register is inactive, it goes to high impedance.

bits 6, 5: RAMSIZE1, 0 (DRAM size 1, 0)

Set these bits according to the total size of the DRAM connected to this IC.

RAMSIZE1

"L"

"L" "H" "H"

RAMSIZE0 DRAM total size

"L"

"H"

"L"

"H"

1M bits 2M bits 4M bits 8M bits

bit 4: RAM8BITW (DRAM 8-bit wide)

This bit is set according to the bit width of the DRAM data bus to be connected. High: Set this bit high when the DRAM to be connected has the 8-bit width. Low: Set this bit low when the DRAM to be connected has the 16-bit width.

(Set low when two 8-bit width DRAMs are connected in parallel.)

CONFIG0

– 22 –

bit 3: RAM2CAS (DRAM 2 CAS)

When the DRAM bus width is 16 bits, set this bit according to the number of CAS and WE signals. When the DRAM bus width is 8 bits, this bit has no meaning. High: Set this bit high when the IC is connected to a DRAM with 2 CAS signals and 1 WE signal. Low: Set this bit low when the IC is connected to a DRAM with 1 CAS signal and 2 WE signals.

bit 2: RESERVED

Normally set low.

bits 1, 0: CLKSEL1, 0 (CLK select 1, 0)

These bits determine the clock frequency output from the CLK pin.

CXD1818R

CLKSEL1

"L" "L"

"H" "H"

CLKSEL0 Clock frequency

"L"

"H"

"L"

"H"

Fixed to high Same frequency as XTL1 1/2 of XTL1 RESERVED

1-1-2. 01h

(1) RAWSEC (raw second) register (read)

RAWSEC (raw second) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

01h (R)

RAWSEC

The Header Second byte for the sector being sent from the CD DSP while DECINT is active can be read from this register.

(2) CONFIG1 (configuration 1) register (write)

CONFIG1 (configuration 1) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

01h (W)

SW OPEN

SYC NGC2

SYC NGC1

SYC NGC0

DCK SEL

"L"

SBC ECC1

SBC ECC0

bit 7: SWOPEN (sync window open)

High: The Sync mark detection window opens. In this case, the IC's internal Sync protection circuit

is disabled.

Low: The Sync mark detection window is controlled by the IC's internal Sync protection circuit.

bits 6 to 4: SYCNGC2 to 0 (sync NG count 2 to 0)

The Sync mark detection window opens once the number of Sync marks specified by these bits is inserted. Setting a value of 1h or less for these bits is prohibited. (After a reset, these bits are set to 2h.)

bit 3: DCKSEL (Dsp Clock Select)

High: DSPCLK 16.9344MHz Low: DSPCLK 33.8688MHz

bit 2: RESERVED

Normally set low.

– 23 –

CONFIG1

bits 1, 0: SBCECC1, 0 (subcode ECC 1, 0)

These two bits specify the error correction method when decoding the subcode.

CXD1818R

SBECC1

"X" "L"

"H"

SBECC0 Subcode error correction

"L" "H" "H"

Error correction not performed. Single error correction performed. Double error correction performed.

1-1-3. 02h

(1) RAWBLK (raw block) register (read)

RAWBLK (raw block) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

02h (R)

RAWBLK

The Header Block byte for the sector being sent from the CD DSP while DECINT is active can be read from this register.

(2) DSPIF (DSP interface) register (write)

DSPIF (DSP interface) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

02h (W)

C2PO L1st

LCH LOW

BCK RED

BCKL MD1

BCKL MD0

LSB 1st

"L"

BFSH DFSL

DSPIF

This register controls the connection mode with the CD DSP. After the IC is reset, the sub CPU sets this register according to the CD DSP to be connected. bit 7: C2PL1ST (C2PO lower byte first)

High: When two bytes of data are input, C2PO inputs the lower byte first followed by the upper byte. Low: When two bytes of data are input, C2PO inputs the upper byte first followed by the lower byte.

Here, "upper byte" means the upper 8 bits including MSB from the CD DSP and "lower byte" means the lower 8 bits including LSB from the CD DSP. For example, the Header minute byte is the lower byte and the second byte, the upper byte.

bit 6: LCHLOW (Lch low)

High: When LRCK is low, determined to be the left channel data. Low: When LRCK is high, determined to be the right channel data.

bit 5: BCKRED (BLCK rising edge)

High: Data is strobed at the rising edge of BCLK. Low: Data is strobed at the falling edge of BCLK.

bits 4, 3: BCKMD1, 0 (BCLK mode 1, 0)

These bits are set according to the number of clocks output for BCLK during 1/2 LCLK cycle by the CD digital signal processing LSI (CD DSP).

BCKMD1

"L" "L"

"H"

BCKMD0

"L" "H" "X"

16BCLKs/WCLK 24BCLKs/WCLK 32BCLKs/WCLK

– 24 –

bit 2: LSB1ST (LSB first)

High: Connected with the CD DSP which outputs data with LSB first. Low: Connected with the CD DSP which outputs data with MSB first.

bit 1: RESERVED

Normally set low. Any change to the bits in this register must be made in the decoder disable status. (After the IC is reset, the address is 28h.)

bit 0: BFSHDFSL (buffering subheader flag select)

High: The Sub Headers written two times are compared and, if they do not match, the result

reports an error to bits 3 to 0 of BFHDRFLG.

Low: When the C2PO of the Sub Headers written two times are both high, that reports an error to

the bits 3 to 0 of BFHDRFLG.

1-1-4. 03h

(1) RAWMD (raw mode) register (read)

RAWMD (raw mode) register

CXD1818R

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

03h (R)

RAWMD

The Header Mode byte for the sector being sent from the CD DSP while DECINT is active can be read from this register.

(2) RFINTVL (refresh interval) register (write)

RFINTVL (refresh interval) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

03h (W) b7 b6 b5 b4 b3 b2 b1 b0

RFINTVL

This register determines the refresh interval. The refresh interval is RFINTVL × 4 × TW. Here, TW represents the XTL1 clock frequency. Note that this IC performs RAS only refresh.

– 25 –

1-1-5. 04h

(1) BFMIN (buffer minute) register (read)

BFMIN (buffer minute) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1818R

04h (R)

BFMIN

During the execution of a write-only or real-time error correction command and after execution of a repeat correction command, the Header Minute byte of the current sector can be read from this register. This register is invalid when the decoder is disabled or a monitor-only command is being executed.

(2) DSPCTL (DSP control) register (write)

DSPCTL (DSP control) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

04h (W)

DSTB SL1

DSTB SL0

DIS XLAT

XFR BYT1

XFR BYT0

FAST DSTB

EXCK SEL1

EXCK SEL0

DSPCTL

bits 7, 6: DSTBSL1, 0

These bits determine the frequency of the DSTB and XLAT clocks used for passing data (DATO) to the CD DSP. The sub CPU sets these bits according to the frequency of the clock on the XTL1 pin. (The maximum frequency for DSTB is 1MHz.)

DSTBDL1

0 0

DSTBDL0 Frequency

0 1

1/24 of XTL1

1/32 of XTL1 1 1

0 1

1/48 of XTL1

1/64 of XTL1

bit 5: DISXLAT (disable XLAT output)

High: After the contents of the DSPCMD register are transferred to the DSP, a latch pulse is not

output from the XLAT pin. In this case, the sub CPU uses DSPCMDLT (bit 0 of the CHPCTL0 register) to output a latch pulse from the XLAT pin at the appropriate time.

Low: After the contents of the DSPCMD register are transferred to the DSP, a latch pulse is output

from the XLAT pin.

bits 4, 3: XFRBYT1, 0 (transfer command byte length 1,0)

These bits determine the number of bytes in the command data (DSPCMD register) to be transferred to the CD DSP. The relationship between the settings and the number of transferred bytes is shown in the following table.

XFRBYT1

"L"

"L" "H" "H"

XFRBYT0 Number of transferred bytes

"L"

"H"

"L"

"H"

Prohibited

1 2 3

– 26 –

bits 2: FASTDSTB

When this bit is high, it is possible to make the frequencies faster of the DSTB, DATO and XLAT outputs to the CD DSP set in DSTBSL1 and 0 (DSPCTL bits 7 and 6).

CXD1818R

DSTBSL1

0 0 1 1

bit 1: EXCKSEL1 bit 0: EXCKSEL0

These bits determine the frequency of the EXCK clock that is used to get the subcode from the CD DSP. The sub CPU sets these bits according to the clock frequency on the XTL1 pin and the playback speed.

EXCKSEL1

"L" "L" "H" "H"

DSTBSL0 Frequency

0 1 0 1

1/48 of XTL1 1/16 of XTL1 1/8 of XTL1 1/4 of XTL1

EXCKSEL0 EXCK clock

"L" "H" "L" "H"

1/32 of XTL1 1/16 of XTL1 1/8 of XTL1 Prohibited

1-1-6. 05h

(1) BFSEC (buffer second) register (read)

BFSEC (buffer second) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

05h (R)

BFSEC

During the execution of a write-only or real-time error correction command and after execution of a repeat correction command, the Header Second byte of the current sector can be read from this register. This register is invalid when the decoder is disabled or a monitor-only command is being executed.

(2) DSPCMD (DSP command) register (write)

DSPCMD (DSP command) register

Adr. bit7 bit6 bit5

bit4

05h (W) b7 b6 b5 b4 b3 b2 b1 b0

bit3 bit2 bit1 bit0 Reg.

DSPCMD

The data to be serially transferred to the CD DSP is written in this register. This register is a three-byte LIFO (last-in, first-out) register.

– 27 –

1-1-7. 06h

(1) BFHDRBLK (buffer header block) register (read)

BFHDRBLK (buffer block) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1818R

06h (R)

BFHDRBLK

During the execution of a write-only or real-time error correction command and after execution of a repeat correction command, the Header Block byte of the current sector can be read from this register. This register is invalid when the decoder is disabled or a monitor-only command is being executed.

(2) CONFIG2 (configuration 2) register (write)

CONFIG2 (configuration 2) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

06h (W)

DLAR NWMS

SBAI TMSL

"L" LRSEL MMC

CSCT ASET

EDCT OECC

ASCON

CONFIG2

bit 7: DLARNWMS (DLARA renewal mode select)

This bit is valid only when ATDLRNEW (DECCTL0 bit 0) = high. High: DLARA is incremented when the data transfer to the host is completed for one sector. Low: When the data transfer to the host is completed for one sector, DLARA is renewed in the

written area of that sector like before.

bit 6: SBAITMSL (subcode buffering area increment timing select)

High: The internal subcode buffering area is incremented when the 1st pack of data is loaded and

de-interleaved.

Low: The internal subcode buffering area is incremented when the subcode sync is detected and

inserted.

bit 5: RESERVED

Always set low.

bit 4: LRSEL (LRCK select)

This bit is valid only with the CD-DA and ESP commands. High: Data buffering is triggered by the falling edge of LRCK. Low: Data buffering is triggered by the rising edge of LRCK.

bit 3: MMC (multi media command)

High: Block error flag transfer appears as two bytes. Low: Block error flag transfer appears as one byte like before.

bit 2: CSCTASET (current sector area set)

High: When BFARA is set, CSCTARA is also set to that value. Low: CSCTARA cannot be set.

bit 1: EDCTOECC (EDC to ECC)

High: When ASCON (CONFIG2 bit 0) = high and the sector contains a C2PO or the EDC

calculation results are NG in the write only mode, error correction is started automatically.

bit 0: ASCON (asynchronous correction on)

When error correction finishes, if the next buffered sector has not been corrected, error correction continues. → Setting this bit and "Real-time correction mode (DECCTL1 (17h) bits 5 to 3 = "011")" results in

the same functions as the conventional "Asynchronous correction mode (DECCTL1 (17h) bits 5 to 3 = "100")". In addition, this bit can also be used during "Write only mode (DECCTL1 (17h) bits 5 to 3 = "010")".

– 28 –

1-1-8. 07h

(1) BFMD (buffer mode) register (read)

BFMD (buffer mode) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1818R

07h (R)

BFMD

During the execution of a write-only or real-time error correction command and after execution of a repeat correction command, the Header Mode byte of the current sector can be read from this register. This register is invalid when the decoder is disabled or a monitor-only command is being executed.

(2) DMACTL (DMA control) register (write)

DMACTL (DMA control) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

07h (W)

HCAS CYCS

DMA CYC4

DRQ PRS

DRQ PRS2

HWKR QDIS

EDOD RAM

EDCF FEN

ECAS CYCS

DMACTL

bit 7: HCASCYCS

High: DMA for data transfer to the host is performed in the page mode with a minimum 8 CAS

cycles.

Low: DMA for data transfer to the host is performed in the page mode with a minimum 4 CAS

cycles.

bit 6: DMACYC4 (DMA cycle 4)

High: The basic number of access clocks to the buffer is 4 clocks. Low: The basic number of access clocks to the buffer is 5 clocks.

bit 5: DRQPRS (DSP data write request priority select)

High: DMA for writing DSP data to the buffer has priority over refresh operation. Low: Refresh operation has priority over DMA for writing DSP data to the buffer like before.

bit 4: DRQPRS2 (DSP data write request priority 2)

High: DMA for buffering DSP data is performed preceeding DMA for host transfer. Low: As usual.

bit 3: HWKRQDIS (host DMA weak request disable)

High: (during send data commands via the buffer)

DMA from the buffer to the FIFO does not start unless there is 8 bytes or more of space in the FIFO. (during receive data commands via the buffer) DMA from the FIFO to the buffer does not start until 8 bytes or more or the last data are written to the FIFO.

Low: (during send data commands via the buffer)

DMA from the buffer to the FIFO starts if there is space in the FIFO. (during receive data commands via the buffer) DMA from the FIFO to the buffer starts as soon as data is written to the FIFO. Setting this bit high reduces the number of times DMA is executed for the host. (because the page mode is always used)

bit 2: EDODRAM

High: Buffer access is performed in the EDO DRAM mode. Low: Buffer access is performed in the normal DRAM mode.

bit 1: EDCFFEN

High: EDC calculations are performed using the page mode and the FIFO. Low: EDC calculations are performed by the conventional method.

bit 0: ECASCYCS

This bit is valid only when EDCFFEN (DMACTL bit 1) = high. High: DMA for EDC calculations is performed in the page mode with a minimum 8 CAS cycles. Low: DMA for EDC calculations is performed in the page mode with a minimum 4 CAS cycles.

– 29 –

1-1-9. 08h

(1) BFFILE (buffer file) register (read)

BFFILE (buffer file) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1818R

08h (R)

BFFILE

During the execution of a write-only or real-time error correction command and after execution of a repeat correction command, the Sub Header File byte of the current sector can be read from this register. This register is invalid when the decoder is disabled or a monitor-only command is being executed.

1-1-10. 09h

(1) BFCHAN (buffer channel) register (read)

BFCHAN (buffer channel) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

09h (R)

BFCHAN

During the execution of a write-only or real-time error correction command and after execution of a repeat correction command, the Sub Header Channel byte of the current sector can be read from this register. This register is invalid when the decoder is disabled or a monitor-only command is being executed.

1-1-11. 0Ah

(1) BFSUBM (buffer sub mode) register (read)

BFSUBM (buffer sub mode) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

0Ah (R)

BFSUBM

During the execution of a write-only or real-time error correction command and after execution of a repeat correction command, the Sub Header Sub Mode byte of the current sector can be read from this register. This register is invalid when the decoder is disabled or a monitor-only command is being executed.

– 30 –

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