Sony CXD1804AR Datasheet

CD-ROM Decoder

For the availability of this product, please contact the sales office.

Description

The CXD1804AR is a CD-ROM decoder LSI with a

built-in Fast SCSI controller.

Features

• Fast SCSI controller (Target mode)

• Maximum transfer speed of 10MB/s (when using
Fast SCSI synchronous transfer)

• SCSI overhead reduced by executing multiple
SCSI sequences

• Supports SCAM Level 2

• Compatible with CD-ROM, CD-I and CD-ROM XA
formats

• Real-time error correction

• Capable of handling up to twelvefold-speed playback

• Multiblock auto-transfer function

• Can read subcode-Q data for each byte from the
sub CPU

• Real-time subcode (R to W) error correction

• Serial transfer of commands to CD DSP

• Connectable with standard DRAM of up to 8M bits
(1024K bytes)

• DRAM bit width selectable for 8 bits or 16 bits

CXD1804AR

144 pin LQFP (Plastic)

Applications

CD-ROM drives

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VDD –0.5 to +7.0 V

• Input voltage VI –0.5 to VDD + 0.5 V

• Output voltage VO –0.5 to VDD + 0.5 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –55 to +150 °C

Recommended Operating Conditions

• Supply voltage VDD 4.5 to 5.5 (5.0 typ.) V

• Operating temperature Topr –20 to +75 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96658-PS

Connection Example

CXD1804AR

Buffer RAM

16bit10bit

CD DSP

CPU data bus
CPU address bus

sub CPU

XUCAS

EXCK
SBIN
SCOR
WFCK
C2PO

BCLK
MDAT
LRCK
XLAT
DATO
DSTB

Address
Decoder

XRAS

XLCAS

XWR

XMWR

CXD1804AR

CD-ROM Decoder

SCSI I/F

XRD D (7:0)

XWAT

MDB

(15:0)

MA

(9:0)

&

XDBP, XDB (7:0)

A (6:0)XCS

8bit7bit

XATN
XBSY
XACK
XRST

XSEL

XMSG

XCD

XREQ

XIO

INT

SCSI Bus

– 2 –

Block Diagram

CXD1804AR

EXCK

SBIN
SCOR
WFCK

C2PO
BCLK

MDAT

LRCK

DATO

XLAT

DSTB

MA (0:9) MDB (0:15)XMWRXUCAS

51 to 57, 59 to 61

Buffer

Address Gen.

Priority Resolver

87

88

89

90
91
92
93
94
98
99

100

CD DSP

I/F

Deinterleave & ECC

Sync Control

Descrambler

XLCASXCAS

63

62

DMA

Sequencer

Subcode

Main Data

Error Correction

68 to 75, 77 to 84

65

64

3

•
5

•
8

•

10

•

XDB (0:7)

16byte FIFO

FIFO Control

Buffer

Handshake

24bit Transfer Byte Counter

Microcode

Core

&

Registers

SCSI

Handshake

SCSI

Phase Ctrl

Arbitration

Selection

11

XDBP

•

15

•

18

•

20

•

23

XREQ

45

XACK

31

XRST

32

XBSY

28

XATN

26

XSEL

40

XCD

43

XMSG

39

XIO

47

Microcode

ROM

CD-ROM Decoder Block SCSI Controller Block

sub CPU

I/F

142

143

141

XWRINT

123 to 129 131 to 138

144

XRD

122

D (7:0)A (0:6) XWAT XTL2 CLK

Clock

Gen.

120

119

XTL1

121

50

XRESXCS

– 3 –

Pin Configuration

CXD1804AR

TST6
TST7

V

TST8

TST9
TST10
TST11
TST12

V

VDD
XTL2
XTL1

CLK

XWAT

V

V

VDD

INT

XCS

XWR

XRD

SS

NC

NC

V

95

96

97

94

LRCK

93

MDAT

92

BCLK

91

C2PO

90

WFCK

89

SCOR

88

SBIN

108

TST5

107

TST4

106

TST3

105

TST2

104

TST1

TST0

102103

DD

SS

V

V

101

100

DSTB

99

XLAT

98

DATO

109
110

111

SS

112
113

114
115
116
117

SS

118

119
120
121
122
123

A0

124

A1

125

A2

126

A3

127

A4

128

A5

129

A6

130

SS

131

D0

132

D1

133

D2

134

D3

135

D4

136

D5

137

D6

138

D7

139

SS

140
141
142
143
144

6

1

2

SS

V

5

4

3

SS

DD

V

V

XDB0

XDB1

9

10

8

7

SS

V

SS

DD

V

V

XDB2

11

XDB3

12

XDB4

13

14 15

16

SS

SS

DD

V

V

V

XDB5

19

18

17

SS

NC

V

XDB6

21

20

SS

SS

V

V

XDB7

87

22

EXCK

86

23

DD

V

DD

V

85

24

XDBP

SS

V

SS

V

MDB15

84

25

NC

MDB14

83

26

XATN

MDB13

82

27 28

SS

V

MDB12

81

XBSY

MDB11

80

29

SS

V

79

30

MDB9

MDB10

78

31

DD

V

XACK

32

MDB8

7677

33

XRST

SS

V

SS

V

75

34

MDB7

74

35

SS

V

MDB6

73

36

NC

MDB5

NC

72
71
70
69

68

67
66
65

64

63

62

61
60
59
58
57

56

55

54
53
52

51
50

49
48
47
46
45
44

43

42

41

40

39

38

37

MDB4
MDB3
MDB2
MDB1
MDB0
VDD
VSS
XMWR
XLCAS
XUCAS
XRAS
MA9
MA8
MA7

SS

V
MA6
MA5
MA4
MA3
MA2
MA1
MA0
XRES
V

DD

VSS
XIO
VSS
XREQ

SS

V
XCD
VDD
VSS
XSEL
XMSG
V

SS

VDD

– 4 –

Pin Description

CXD1804AR

Pin
No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15

Symbol I/O Logic Classification Description

VSS
VDD
XDB0
VSS
XDB1
VSS
VDD
XDB2
VSS
XDB3
XDB4
VSS
VSS
VDD
XDB5

—
—

I/O

—

I/O

—
—

I/O

—
I/O
I/O

—

—

—
I/O

—
—

Negative

—

Negative

—
—

Negative

—
Negative
Negative

—

—

—
Negative

Power
Power
SCSI I/F
Power
SCSI I/F
Power
Power
SCSI I/F
Power
SCSI I/F
SCSI I/F
Power
Power
Power
SCSI I/F

VSS
VDD
SCSI data bus bit 0
VSS
SCSI data bus bit 1
VSS
VDD
SCSI data bus bit 2
VSS
SCSI data bus bit 3
SCSI data bus bit 4
VSS
VSS
VDD

SCSI data bus bit 5
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

VSS
NC
XDB6
VSS
XDB7
VSS
VDD
XDBP
VSS
NC
XATN
VSS
XBSY
VSS
VDD
XACK
XRST

—
—

I/O

—

I/O

—
—

I/O

—
—

I/O

—

I/O

—

—
I/O
I/O

—
—

Negative

—

Negative

—
—

Negative

—
—

Negative

—

Negative

—

—
Negative
Negative

Power
NC
SCSI I/F
Power
SCSI I/F
Power
Power
SCSI I/F
Power
NC
SCSI I/F
Power
SCSI I/F
Power
Power
SCSI I/F
SCSI I/F

VSS
NC
SCSI data bus bit 6
VSS
SCSI data bus bit 7
VSS
VDD
SCSI data bus parity
VSS
NC
SCSI control bus XATN signal
VSS
SCSI control bus XBSY signal
VSS
VDD
SCSI control bus XACK signal

SCSI control bus XRST signal
33
34
35
36

VSS
VSS
NC
NC

—
—
—
—

—
—
—
—

Power
Power
NC
NC

VSS

VSS

NC

NC

– 5 –

CXD1804AR

Pin

No.

37
38
39
40
41
42
43
44
45
46
47
48
49
50
51

Symbol I/O Logic Classification Description

VDD
VSS
XMSG
XSEL
VSS
VDD
XCD
VSS
XREQ
VSS
XIO
VSS
VDD
XRES
MA0

—

—
I/O
I/O

—

—
I/O

—
I/O

—
I/O

—

—

O

I

—

—
Negative
Negative

—

—
Negative

—
Negative

—
Negative

—

—
Negative

Power
Power
SCSI I/F
SCSI I/F
Power
Power
SCSI I/F
Power
SCSI I/F
Power
SCSI I/F
Power
Power
System I/F
BufMem I/F

VDD
VSS
SCSI control bus XMSG signal
SCSI data bus XSEL signal
VSS
VDD
SCSI control bus XCD signal
VSS
SCSI control bus XREQ signal
VSS
SCSI control bus XIO signal
VSS
VDD
CXD1804AR reset signal

Address bus output bit 0 to buffer memory
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

MA1
MA2
MA3
MA4
MA5
MA6
VSS
MA7
MA8
MA9
XRAS
XUCAS
XLCAS
XMWR
VSS
VDD
MDB0

O
O
O
O
O
O

—

O
O
O
O
O
O

O
—
—

I/O

—

Negative
Negative
Negative
Negative

—
—

BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
Power
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
Power
BufMem I/F
BufMem I/F

Address bus output bit 1 to buffer memory
Address bus output bit 2 to buffer memory
Address bus output bit 3 to buffer memory
Address bus output bit 4 to buffer memory
Address bus output bit 5 to buffer memory
Address bus output bit 6 to buffer memory
VSS
Address bus output bit 7 to buffer memory
Address bus output bit 8 to buffer memory
Address bus output bit 9 to buffer memory
Buffer memory RAS (Row Address Strobe) signal
Buffer memory CAS (Column Address Strobe) signal
Buffer memory CAS (Column Address Strobe) signal
Data write strobe signal to buffer memory
VSS
VDD

Buffer memory data bus bit 0
69
70
71
72
73

MDB1
MDB2
MDB3
MDB4
MDB5

I/O
I/O
I/O
I/O
I/O

BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F

Buffer memory data bus bit 1

Buffer memory data bus bit 2

Buffer memory data bus bit 3

Buffer memory data bus bit 4

Buffer memory data bus bit 5

– 6 –

CXD1804AR

Pin
No.

74
75
76
77
78
79
80
81
82
83
84
85
86

87

Symbol I/O Logic Classification Description

MDB6
MDB7
VSS
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
VSS
VDD

EXCK

I/O
I/O

—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

—

—

O

—

—
—

BufMem I/F
BufMem I/F
Power
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
BufMem I/F
Power
Power

CD DSP I/F

Buffer memory data bus bit 6
Buffer memory data bus bit 7
VSS
Buffer memory data bus bit 8
Buffer memory data bus bit 9
Buffer memory data bus bit 10
Buffer memory data bus bit 11
Buffer memory data bus bit 12
Buffer memory data bus bit 13
Buffer memory data bus bit 14
Buffer memory data bus bit 15
VSS
VDD
SBIN read clock

(connected to the EXCK pin (Pin 65) of the CXD2500)

88

89

90
91

92
93
94
95
96
97
98

99
100
101
102

SBIN

SCOR

WFCK
C2PO

BCLK
MDAT
LRCK
VSS
NC
NC
DATO
XLAT
DSTB
VSS
VDD

—
—
—

O
O

O
—
—

I

I

I
I

I
I
I

—
—
—

CD DSP I/F

CD DSP I/F

CD DSP I/F
CD DSP I/F

CD DSP I/F
CD DSP I/F
CD DSP I/F
Power
NC
NC
CD DSP I/F
CD DSP I/F
CD DSP I/F

—

Power

—

Power

Subcode serial signal
(connected to the SBSO pin (Pin 64) of the CXD2500)

Subcode sync signal
(connected to the SCOR pin (Pin 63) of the CXD2500)

Write frame clock
(connected to the WFCK pin (Pin 62) of the CXD2500)

Indicates that an error exists in C2 pointer signal MDAT.
Bit clock. MDAT strobe signal.
Serial data stream from CD DSP
LR signal. Indicates MDAT L or R channel.
VSS
NC
NC
Serial data output from sub CPU to CD DSP
DATO latch signal. Latches at the rising edge.
DATO transfer clock
VSS

VDD
103
104
105
106
107

TST0
TST1
TST2
TST3
TST4

I
I
I
I
I

Test I/F
Test I/F
Test I/F
Test I/F
Test I/F

Test pin 0

Test pin 1

Test pin 2

Test pin 3

Test pin 4

– 7 –

CXD1804AR

Pin

No.
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122

Symbol I/O Logic Classification Description

TST5
TST6
TST7
VSS
TST8
TST9
TST10
TST11
TST12
VSS
VDD
XTL2
XTL1
CLK
XWAT

I
I
I

—

I
I
I
I

I
—
—

O

I

O
O

Negative

—

—
—

Test I/F
Test I/F
Test I/F
Power
Test I/F
Test I/F
Test I/F
Test I/F
Test I/F
Power
Power
System I/F
System I/F
System I/F
sub CPU I/F

Test pin 5
Test pin 6
Test pin 7
VSS
Test pin 8
Test pin 9
Test pin 10
Test pin 11
Test pin 12
VSS
VDD
Crystal oscillation circuit output
Crystal oscillation circuit input
Clock output

Wait signal for sub CPU buffer memory access
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139

A0
A1
A2
A3
A4
A5
A6
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VSS

—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

—

I
I
I
I
I
I
I

—

—

sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
Power
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F
Power

CXD1804AR built-in register address bus bit 0
CXD1804AR built-in register address bus bit 1
CXD1804AR built-in register address bus bit 2
CXD1804AR built-in register address bus bit 3
CXD1804AR built-in register address bus bit 4
CXD1804AR built-in register address bus bit 5
CXD1804AR built-in register address bus bit 6
VSS
Sub CPU data bus bit 0
Sub CPU data bus bit 1
Sub CPU data bus bit 2
Sub CPU data bus bit 3
Sub CPU data bus bit 4
Sub CPU data bus bit 5
Sub CPU data bus bit 6
Sub CPU data bus bit 7

VSS
140
141
142
143
144

VDD
INT
XCS
XWR
XRD

—

O

I
I
I

—
Selectable
Negative
Negative
Negative

Power
sub CPU I/F
sub CPU I/F
sub CPU I/F
sub CPU I/F

VDD
Interrupt to sub CPU
CXD1804AR chip select signal
CXD1804AR built-in register write signal
CXD1804AR built-in register read signal

– 8 –

CXD1804AR

Electrical Characteristics (VDD = 5V ± 10%, VSS = 0V, Topr = –20 to +75°C)

Item

TTL input level pin
High level input voltage

TTL input level pin
Low level input voltage

CMOS input level pin
High level input voltage

CMOS input level pin
Low level input voltage

CMOS Schmitt input level pin
High level input voltage

CMOS Schmitt input level pin
Low level input voltage

CMOS Schmitt input level pin
Input voltage hysteresis

TTL Schmitt input level pin
High level input voltage

TTL Schmitt input level pin
Low level input voltage

Symbol Conditions Min. Typ. Max. Unit

VIH1

VIL1

VIH2

VIL2

VIH4

VIL4

VIH4 – VIL4

VIH5

VIL5

2.2

0.8

0.7VDD

0.3VDD

0.8VDD

0.2VDD

0.6

2.2V

0.8V

Applicable

V

V

V

V

V

V

V

V

V

pins

∗1

∗1

∗2

∗2

∗3

∗3

∗3

∗4

∗4

TTL Schmitt input level pin
Input voltage hysteresis

SCSI Schmitt input level pin
High level input voltage

SCSI Schmitt input level pin
Low level input voltage

SCSI Schmitt input level pin
Input voltage hysteresis

Bidirectional pin with pull-up resistor
Input current

High level output voltage
High level output voltage
SCSI high level output voltage
Low level output voltage
SCSI low level output voltage
Input leakage current
Oscillation cell high level input voltage
Oscillation cell low level input voltage

VIH5 – VIL4

VIHS

VILS

VIHTS – VILTS

IIL3
VOH1

VOH2
VOHS
VOL1
VOLS
II1
VIH4
VIL4

VIN = 0V
IOH = –2mA

IOH = –6mA

IOL = 4mA
IOL = 48mA
VIN = VSS or VDD

2.2V

–90

VDD – 0.8
VDD – 0.8

2.5

–10

0.7VDD

0.4

0.4

–200

0.8V

–440

3.7

0.4

0.5
10

0.3VDD

V

V

V

V

µA

V
V
V
V
V

µA

V
V

∗4

∗11

∗11

∗11

∗5
∗6

∗7

∗12

∗8

∗11

∗9

∗10

Oscillation cell logic threshold value
Oscillation cell feedback resistance value
Oscillation cell high level output voltage
Oscillation cell low level output voltage

LVTH
RFB
VOH3
VOL3

VIN = VSS or VDD
IOH = –12mA
IOL = 12mA

– 9 –

250k

0.5VDD

0.5VDD
1M

2.5M

0.5VDD

V

Ω

V
V

∗1

D7 to 0, MDBF to 0

∗2

MDAT, LRCK, C2PO, SBIN, SCOR, TD12 to 0

∗3

BLCK, WFCK, XRES

∗4

A6 to 0, XWR, XRD, XCS

∗5

D7 to 0, MDBF to 0

∗6

All output pins except XTL2, XRAS, XUCAS, XLCAS, XMWR and CLK

∗7

XRAS, XUCAS, XLCAS, XMWR, CLK

∗8

All output pins except XTL2

∗9

All input pins except ∗5and XTL1

∗10

Input: XTL1, Output: XTL2

∗11

XRST, XBSY, XSEL, XATN, XMSG, XCD, XIO, XREQ, XACK, XDBP, XDB7 to 0

∗12

XREQ, XACK, XDBP and XDB7 to 0 when active negation is ON

I/O Capacitance (VDD = VI = 0V, f = 1MHz)

CXD1804AR

Item
Input capacitance
Output capacitance
I/O capacitance

Symbol Min. Typ. Max. Unit
CIN
COUT
CI/O

9
11
11

pF
pF
pF

– 10 –

AC Characteristics

1. Sub CPU Interface (Output Load = 50pF)

(1) Read

A6 to 0

XCS

XRD

D7 to 0

Tsar

Tdrd

CXD1804AR

Thar

Trrl

Tfrd

Item
Address setup time (for XCS & XRD ↓)
Address hold time (for XCS & XRD ↑)
Data delay time (for XCS & XRD ↓)
Data float time (for XCS & XRD ↑)

(2) Write

A6 to 0

XCS

XWR

D7 to 0

Tsaw

Symbol Min. Typ. Max. Unit
Tsar
Thar
Tdrd
Tfrd

Twwl

10
10

0

Thwa

Tsdw Thdw

35
15

ns
ns
ns
ns

Item
Address setup time (for XCS & XWR ↓)
Address hold time (for XCS & XWR ↑)
Data setup time (for XCS & XWR ↓)
Data hold time (for XCS & XWR ↑)
Low level XWR pulse width

Symbol Min. Typ. Max. Unit
Tsaw
Thaw
Tsdw
Thdw
Twwl

20
10
20
10
30

ns
ns
ns
ns
ns

– 11 –

2. CD DSP Interface

BCKRED = "H"

BCLK

DATA

LRCK

C2PO

BCKRED = "L"

BCLK

Tbck Tbck

Tsb1

Tbck Tbck

Thb1

CXD1804AR

Tsb2Thb2

DATA

LRCK
C2PO

Item
BCLK frequency
BCLK pulse width
DATA setup time (for BCLK)
DATA hold time (for BCLK)
LRCK, C2PO setup time (for BCLK)
LRCK, C2PO hold time (for BCLK)

Tsb1

Thb1

Symbol Min. Typ. Max. Unit
Fbck
Tbck
Tsb1
Thb1
Tsb2
Thb2

19
10
10
10
10

Tsb2Thb2

26 ns

ns
ns
ns
ns
ns

– 12 –

3. DRAM Interface

(1) Read

iCLK

CXD1804AR

MA9 to 0

XRAS

XCAS

XMWR

MDB7 to 0

Tma0

Item

Tma1

Trasl Trash

Tcasl

Tmds

Symbol Min. Typ. Max. Unit

Trc

Tcash

Tmdh

"H"

Random read/write cycle time
Address delay time (for XTL2 ↑)
Address delay time (for XTL2 ↓)
XRAS ↓ delay time (for XTL2 ↑)
XRAS ↑ delay time (for XTL2 ↑)
XCAS ↓ delay time (for XTL2 ↑)
XCAS ↑ delay time (for XTL2 ↑)
Data setup time (for XCAS ↑)
Data hold time (for XCAS ↓)

Trc
Tma0
Tma1
Trasl
Trash
Tcasl
Tcash
Tmds
Tmdh

5Tw

13
11

6
6
7
6
2
0

24
22
12
11
14
12

4

45
41
23
20
25
22

6

ns
ns
ns
ns
ns
ns
ns
ns
ns

– 13 –

(2) Write

iCLK

MA9 to 0

XRAS

Tma0

CXD1804AR

Tma1

Trc

Trasl Trash

XCAS

XMWR

Tmdl

MDB7 to 0

Item
Random read/write cycle time
Address delay time (for XTL2 ↑)
Address delay time (for XTL2 ↓)
XRAS ↓ delay time (for XTL2 ↑)
XRAS ↑ delay time (for XTL2 ↑)
XCAS ↓ delay time (for XTL2 ↑)
XCAS ↑ delay time (for XTL2 ↑)

Tmwrl

Tcasl

Tcash

Tmwrh

Symbol Min. Typ. Max. Unit
Trc
Tma0
Tma1
Trasl
Trash
Tcasl
Tcash

5Tw

13
11

6
6
7
6

24
22
12
11
14
12

45
41
23
20
25
22

ns
ns
ns
ns
ns
ns

ns
XMWR ↓ delay time (for XTL2 ↑)
XMWR ↑ delay time (for XTL2 ↑)
Data setup time (for XTL2 ↑)
Data hold time (for XTL2 ↑)

Tmwrl
Tmwrh
Tmdws
Tmdwh

7
6

14

7

– 14 –

14
11
28
14

25
21
51
26

ns

ns

ns

ns

(3) Refresh (RAS only refresh)

iCLK

Tma0

MA9 to 0

XRAS

CXD1804AR

Trasl Trash

XCAS

XMWR

Item
Random read/write cycle time
Address delay time (for XTL2 ↑)
XRAS ↓ delay time (for XTL2 ↑)
XRAS ↑ delay time (for XTL2 ↑)

Symbol Min. Typ. Max. Unit
Trc
Tma0
Tras1
Trash

5Tw

12

6
6

24
12
11

43
23
20

ns
ns
ns
ns

"H"

"H"

– 15 –

4. SCSI Interface

(1) SCSI asynchronous transfer timing

When receiving: Initiator → Target

XREQ

CXD1804AR

XACK

XDB

Taads Tardh

When transmitting: Target → Initiator

XREQ

XACK

XDB

Tards

Taadh

Item

XDB setup time (for XACK ↓)

Taanrad

Taaarnd

Taaarnd

Taanrad

Symbol Min. Typ. Max. Unit
Taads

15

ns
XDB hold time (for XREQ ↑)
XDB setup time (for XREQ ↓)
XDB hold time (for XREQ ↓)
XREQ rise delay time (for XACK ↓)
XREQ fall time (for XACK ↑)

Tardh
Tards
Taadh
Taaarnd
Taanrad

0
30
60
30
30

– 16 –

70
85

ns
ns
ns
ns
ns

(2) SCSI synchronous transfer timing

When receiving: Initiator → Target

XACK

XDB

Tnads

Tnadh

When transmitting: Target → Initiator

Tnrap Tnrnp

XREQ

CXD1804AR

XDB

Tnads

Tnadh

Item
XDB setup time (for XACK ↓)
XDB hold time (for XACK ↓)
XDB setup time (for XREQ ↓)
XDB hold time (for XREQ ↓)
XREQ assert time
XREQ negate time

Symbol Min. Typ. Max. Unit
Tnads
Tnadh
Tnrds
Tnrdh
Tnrap
Tnrnp

15
10
80

105

90

110

ns
ns
ns
ns
ns
ns

– 17 –

(3) Fast SCSI synchronous transfer timing

When receiving: Initiator → Target

XACK

XDB

Tfads

Tfadh

When transmitting: Target → Initiator

Tfrap Tfrnp

XREQ

CXD1804AR

XDB

Tfrds

Tfrdh

Item
XDB setup time (for XACK ↓)
XDB hold time (for XACK ↓)
XDB setup time (for XREQ ↓)
XDB hold time (for XREQ ↓)
XREQ assert time
XREQ negate time

Symbol Min. Typ. Max. Unit
Tfads
Tfadh
Tfrds
Tfrdh
Tfrap
Tfrnp

15
10
55
55

40

60

ns
ns
ns
ns
ns
ns

– 18 –

5. XTL1 and XTL2 Pins

(1) When using self-excited oscillation

CXD1804AR

Item

Symbol Min. Typ. Max. Unit

Oscillation frequency Fmax 40.0 MHz

(2) When inputting a pulse to the XTL1 pin

Tw

TwlxTwhx

Vihx

V

DD/2

Vilx

Item

High level pulse width

Symbol Min. Typ. Max. Unit
Twhx

10

ns
Low level pulse width
Pulse cycle

Twhx
Tw

10
25

ns

ns

– 19 –

CXD1804AR

Contents

[1] Description of Registers........................................................................................................................... 21

1-1. Description of Decoder Block Registers............................................................................................... 21

1-2. Description of SCSI2 Controller Block Registers.................................................................................. 46

1-3. Common Registers............................................................................................................................... 60

[2] Description of SCSI Controller Block Commands ................................................................................. 68

2-1. Precautions when Executing Commands............................................................................................. 69

2-2. Category 00 Commands....................................................................................................................... 69

2-3. Category 01 Commands....................................................................................................................... 74

2-4. Category 10 Commands....................................................................................................................... 76

2-5. Category 11 Commands....................................................................................................................... 79

[3] Appendix A................................................................................................................................................. 84

3-1. List of CD-ROM Decoder Block Registers............................................................................................ 84

3-2. List of SCSI Controller Block Registers................................................................................................ 90

3-3. List of Common Registers .................................................................................................................... 94

3-4. Register Reset Conditions.................................................................................................................... 96

[4] Appendix B............................................................................................................................................... 102

4-1. Summary of SCSI Controller Block Commands................................................................................. 102

– 20 –

[1] Description of Registers

The CXD1804AR's register address area is allotted as shown in the table below.

CXD1804AR

Address

00h to 4Fh

50h to 6Fh
70h to 7Fh

0xx xxxx

100 xxxx
101 xxxx

110 xxxx
111 xxxx

CD-ROM decoder block

SCSI2 interface block
CD-ROM decoder/SCSI2 interface common block

Description

1-1. Description of Decoder Block Registers

1-1-1. 00h

(1) RAWMIN (raw minute) register (read)

RAWMIN (raw minute) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

00h (R)

REWMIN

The Header Minute byte for the sector being sent from the CD DSP while DECINT is active can be read from
this register. A difference of two sectors exists between the RAWxxx and BFxxx registers during the write-only
and real-time correction modes.

(2) CONFIG0 (configuration 0) register (write)

CONFIG0 (configuration 0) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

00h (W)

CINT
POL

RAM
SIZE1

RAM
SIZE0

RAM8
BITW

RAM2
CAS

EXCK
SEL

CLK
SEL1

CLK
SEL0

bit 7: CINTPOL (sub CPU interrupt polarity)

High: The INT pin becomes active high. When the register is inactive, it goes low.
Low: The INT pin becomes active low. When the register is inactive, it goes to high impedance.

bits 6, 5: RAMSIZE1, 0 (DRAM size 1, 0)

Set these bits according to the total size of the DRAM connected to this IC.

RAMSIZE1

"L"
"L"
"H"
"H"

RAMSIZE0 DRAM total size

"L"

"H"

"L"

"H"

1M bits
2M bits
4M bits
8M bits

bit 4: RAM8BITW (DRAM 8-bit wide)

This bit is set according to the bit width of the DRAM data bus to be connected.
High: Set this bit high when the DRAM to be connected has the 8-bit width.
Low: Set this bit low when the DRAM to be connected has the 16-bit width.

(Set low when two 8-bit width DRAMs are connected in parallel.)

CONFIG0

– 21 –

bit 3: RAM2CAS (DRAM 2 CAS)

When the DRAM bus width is 16 bits, set this bit according to the number of CAS and WE signals.
When the DRAM bus width is 8 bits, this bit has no meaning.
High: Set this bit high when the IC is connected to a DRAM with 2 CAS signals and 1 WE signal.
Low: Set this bit low when the IC is connected to a DRAM with 1 CAS signal and 2 WE signals.

bit 2: EXCKSEL (EXCK select)

This bit determines the frequency of the EXCK clock that is used to get the subcode from the CD
DSP. This bit is set by the sub CPU on the basis of the playback speed and the clock frequency on
the XTL1 pin. (The maximum frequency for EXCK is 1MHz.)
High: The EXCK frequency is 1/48 the frequency of the XTL1 pin. Set this bit high when the XTL1

frequency is greater than 32MHz.

Low: The EXCK frequency is 1/32 the frequency of the XTL1 pin. Set this bit low when the XTL1

frequency is less than 32MHz.

bits 1, 0: CLKSEL1, 0 (CLK select 1, 0)

These bits determine the clock frequency output from the CLK pin.

CXD1804AR

CLKSEL1

"L"

"L"
"H"
"H"

CLKSEL0 Clock frequency

"L"

"H"

"L"

"H"

Fixed to high
1/2 of XTL1
Same frequency as XTL1
RESERVED

1-1-2. 01h

(1) RAWSEC (raw second) register (read)

RAWSEC (raw second) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

00h (R)

RAWSEC

The Header Second byte for the sector being sent from the CD DSP while DECINT is active can be read from
this register.

(2) CONFIG1 (configuration 1) register (write)

CONFIG1 (configuration 1) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

00h (W)

SW
OPEN

SYC
NGC2

SYC
NGC1

SYC
NGC0

HWKR
QDIS

"L"

SBC
ECC1

SBC
ECC0

bit 7: SWOPEN (sync window open)

High: The Sync mark detection window opens. In this case, the IC's internal Sync protection circuit

is disabled.

Low: The Sync mark detection window is controlled by the IC's internal Sync protection circuit.

bits 6 to 4: SYCNGC2 to 0 (sync NG count 2 to 0)

The Sync mark detection window opens once the number of Sync marks specified by these bits is
inserted. Setting a value of 1h or less for these bits is prohibited. (After a reset, these bits are set to
2h.)

– 22 –

CONFIG1

bit 3 HWKRQDIS (host DMA weak request disable)

High: (For the send system command passed through a buffer)

When the FIFO does not have eight empty bytes or more, the DMA does not start to the
FIFO from the buffer.
(For the receive system command passed through a buffer)
When the data of eight bytes or more are written (or the last data is written) in the FIFO, the
DMA starts to the buffer from the FIFO.

Low: (For the send system command passed through a buffer)

When the FIFO is not filled with data, the DMA starts to the FIFO from the buffer.
(For the receive system command passed through a buffer)
The DMA starts to the buffer from the FIFO immediately after the data are written in the

FIFO.
The number of times of the DMA execution for the host is reduced by setting this bit high.
(Because the page mode is always used.)

bit 2: RESERVED

Normally set low.

bits 1, 0: SBCECC1, 0 (subcode ECC 1, 0)

These two bits specify the error correction method when decoding the subcode.

CXD1804AR

SBECC1

"X"
"L"

"H"

SBECC0 Subcode error correction

"L"
"H"
"H"

Error correction not performed.
Single error correction performed.
Double error correction performed.

1-1-3. 02h

(1) RAWBLK (raw block) register (read)

RAWBLK (raw block) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

02h (R)

RAWBLK

The Header Block byte for the sector being sent from the CD DSP while DECINT is active can be read from
this register.

(2) DSPIF (DSP interface) register (write)

DSPIF (DSP interface) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

02h (W)

C2PO
L1st

LCH
LOW

BCK
RED

BCKL
MD1

BCKL
MD0

LSB
1st

"L"

BFSH
DFSL

DSPIF

This register controls the connection mode with the CD DSP. After the IC is reset, the sub CPU sets this
register according to the CD DSP to be connected.
bit 7: C2PL1ST (C2PO lower byte first)

High: When two bytes of data are input, C2PO inputs the lower byte first followed by the upper byte.
Low: When two bytes of data are input, C2PO inputs the upper byte first followed by the lower byte.

Here, "upper byte" means the upper 8 bits including MSB from the CD DSP and "lower byte"

means the lower 8 bits including LSB from the CD DSP. For example, the Header minute

byte is the lower byte and the second byte, the upper byte.

– 23 –

bit 6: LCHLOW (Lch low)

High: When LRCK is low, determined to be the left channel data.
Low: When LRCK is high, determined to be the right channel data.

bit 5: BCKRED (BLCK rising edge)

High: Data is strobed at the rising edge of BCLK.
Low: Data is strobed at the falling edge of BCLK.

bits 4, 3: BCKMD1, 0 (BCLK mode 1, 0)

These bits are set according to the number of clocks output for BCLK during 1/2 LCLK cycle by the
CD digital signal processing LSI (CD DSP).

CXD1804AR

BCKMD1

"L"
"L"

"H"

BCKMD0

"L"
"H"
"X"

16BCLKs/WCLK
24BCLKs/WCLK
32BCLKs/WCLK

bit 2: LSB1ST (LSB first)

High: Connected with the CD DSP which outputs data with LSB first.
Low: Connected with the CD DSP which outputs data with MSB first.

bit 1: RESERVED

Normally set low.
Any change to the bits in this register must be made in the decoder disable status. (After the IC is
reset, the address is 28h.)

bit 0 BFSHDFSL (buffering subheader flag select)

High: The Sub Headers written two times are compared and, if they do not match, the result

reports an error to bits 3 to 0 of BFHDRFLG.

Low: When the C2PO of the Sub Headers written two times are both high, that reports an error to

the bits 3 to 0 of BFHDRFLG.

1-1-4. 03h

(1) RAWMD (raw mode) register (read)

RAWMD (raw mode) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

03h (R)

RAWMD

The Header Mode byte for the sector being sent from the CD DSP while DECINT is active can be read from
this register.

(2) RFINTVL (refresh interval) register (write)

RFINTVL (refresh interval) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

03h (W) b7 b6 b5 b4 b3 b2 b1 b0

RFINTVL

This register determines the refresh interval. The refresh interval is RFINTVL × 4 × TW. Here, TW represents
the XTL1 clock frequency. Note that this IC performs RAS only refresh.

– 24 –

1-1-5. 04h

(1) BFMIN (buffer minute) register (read)

BFMIN (buffer minute) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1804AR

04h (R)

BFMIN

During the execution of a write-only or real-time error correction command and after execution of a repeat
correction command, the Header Minute byte of the current sector can be read from this register. This register
is invalid when the decoder is disabled or a monitor-only command is being executed.

(2) DSPCTL (DSP control) register (write)

DSPCTL (DSP control) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

04h (W)

DSTB
SL1

DSTB
SL0

DIS
XLAT

XFR
BYT1

XFR
BYT0

"L"

SBAI
TMSL

FAST
EXCK

DSPCTL

bits 7, 6: DSTBSL1, 0

These bits determine the frequency of the DSTB and XLAT clocks used for passing data (DATO) to
the CD DSP. The sub CPU sets these bits according to the frequency of the clock on the XTL1 pin.
(The maximum frequency for DSTB is 1MHz.)

DSTBDL1

0
0

DSTBDL0 Frequency

0
1

1/24 of XTL1

1/32 of XTL1
1
1

0
1

1/48 of XTL1

1/64 of XTL1

bit 5: DISXLAT (disable XLAT output)

High: After the contents of the DSPCMD register are transferred to the DSP, a latch pulse is not

output from the XLAT pin. In this case, the sub CPU uses DSPCMDLT (bit 0 of the
CHPCTL0 register) to output a latch pulse from the XLAT pin at the appropriate time.

Low: After the contents of the DSPCMD register are transferred to the DSP, a latch pulse is output

from the XLAT pin.

bits 4, 3: XFRBYT1, 0 (transfer command byte length 1,0)

These bits determine the number of bytes in the command data (DSPCMD register) to be
transferred to the CD DSP. The relationship between the settings and the number of transferred
bytes is shown in the following table.

XFRBYT1

"L"

"L"
"H"
"H"

XFRBYT0 Number of transferred bytes

"L"

"H"

"L"

"H"

Prohibited

1
2
3

bits 2: RESERVED

Normally set low.

– 25 –

bit 1 SBAITMSL (subcode buffering area increment timing select)

High: The internal subcode buffering area is incremented when the first pack of data is retrieved

and de-interleaving is performed.

Low: The internal subcode buffering are is incremented when the subcode Sync mark is detected

and inserted.

bit 0 FASTEXCK (fast EXCK)

High: The EXCK frequency is 1/8 the frequency of the XTL1 pin.
Low: The EXCK frequency depends on the settings of EXCKSEL (CONFIG0 bit 2)

1-1-6. 05h

(1) BFSEC (buffer second) register (read)

BFSEC (buffer second) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1804AR

05h (R)

BFSEC

During the execution of a write-only or real-time error correction command and after execution of a repeat
correction command, the Header Second byte of the current sector can be read from this register. This register
is invalid when the decoder is disabled or a monitor-only command is being executed.

(2) DSPCMD (DSP command) register (write)

DSPCMD (DSP command) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

05h (W) b7 b6 b5 b4 b3 b2 b1 b0

DSPCMD

The data to be serially transferred to the CD DSP is written in this register. This register is a three-byte LIFO
(last-in, first-out) register.

1-1-7. 06h

(1) BFHDRBLK (buffer header block) register (read)

BFHDRBLK (buffer block) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

06h (R)

BFHDRBLK

During the execution of a write-only or real-time error correction command and after execution of a repeat
correction command, the Header Block byte of the current sector can be read from this register. This register is
invalid when the decoder is disabled or a monitor-only command is being executed.

1-1-8. 07h

(1) BFMD (buffer mode) register (read)

BFMD (buffer mode) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

07h (R)

BFMD

During the execution of a write-only or real-time error correction command and after execution of a repeat
correction command, the Header Mode byte of the current sector can be read from this register. This register is
invalid when the decoder is disabled or a monitor-only command is being executed.

– 26 –

1-1-9. 08h

(1) BFFILE (buffer file) register (read)

BFFILE (buffer file) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1804AR

08h (R)

BFFILE

During the execution of a write-only or real-time error correction command and after execution of a repeat
correction command, the Sub Header File byte of the current sector can be read from this register. This
register is invalid when the decoder is disabled or a monitor-only command is being executed.

1-1-10. 09h

(1) BFCHAN (buffer channel) register (read)

BFCHAN (buffer channel) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

09h (R)

BFCHAN

During the execution of a write-only or real-time error correction command and after execution of a repeat
correction command, the Sub Header Channel byte of the current sector can be read from this register. This
register is invalid when the decoder is disabled or a monitor-only command is being executed.

1-1-11. 0Ah

(1) BFSUBM (buffer sub mode) register (read)

BFSUBM (buffer sub mode) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

0Ah (R)

BFSUBM

During the execution of a write-only or real-time error correction command and after execution of a repeat
correction command, the Sub Header Sub Mode byte of the current sector can be read from this register. This
register is invalid when the decoder is disabled or a monitor-only command is being executed.

1-1-12. 0Bh

(1) BFDTYP (buffer data type) register (read)

BFDTYP (buffer data type) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

0Bh (R)

BFDTYP

During the execution of a write-only or real-time error correction command and after execution of a repeat
correction command, the Sub Header Data Type byte of the current sector can be read from this register. This
register is invalid when the decoder is disabled or a monitor-only command is being executed.

– 27 –

1-1-13. 0Ch

(1) RAWHDRFLG (raw header flag) register (read)

RAWHDRFLG (raw header flag) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1804AR

0Ch (R) MIN SEC

BLO
CK

MODE

CDR
DTEN

This register indicates the C2PO value for the RAWHDR register.
bit 7 Minute
bit 6 Second
bit 5 Block
bit 4 Mode
bit 3 to 1 RESERVED
bit 0 CD-R Mode Detect Enable

(2) CDRMOD (CD-R mode) register (write)

CDRMOD (CD-R mode) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

0Ch (W)

CDR
DTEN

bit 0 CDRDTEN (CD-R mode detect enable)

High: The CDRINT status results when the decoder is operating in the monitor-only, write-only,

real-time correction or asynchronous correction mode if either of the conditions below is met.
(1) Bits 7 to 5 of the Raw Mode byte are not "000".
(2) The error flag of the Raw Mode byte is not established. (Values after processing by

setting of MDBYTCTL (DECCTL0 bit 2))

Low: The CD-R Mode byte is not detected.

RAWHDR

CDRMODE

1-1-14. 0Dh

(1) BFHDRFLG (buffer header flag) register (read)

BFHDRFLG (buffer header flag) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

0Dh (R) MIN SEC

BLO
CK

MODE FILE CHAN

SUB
MODE

DATA
TYPE

– 28 –

HDRFLG

CXD1804AR

This register shows the error status of each byte in the BFHDR and BFSHDR registers. High means an error.
bit7 Minute
bit6 Second
bit5 Block
bit4 Mode
bit3 File
bit2 Channel
bit1 Submode
bit0 Data Type

1-1-15. 0Eh

(1) DECSTS0 (decoder status 0) register (read)

DECSTS0 (decoder status 0) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

0Eh (R)

bit 7: SHRTSCT (short sector)

Indicates that the Sync mark interval was less than 2351 bytes since the previous DECINT. This
sector does not remain in the buffer memory.

bit 6: NOSYNC

Indicates that the Sync mark was inserted because one was not detected in the prescribed position
for the current sector.

bit 5: CORINH (correction inhibit)

This is high if the current sector Mode and Form could not be determined when the AUTODIST bit
of the DECCTL register is set high. ECC or EDC is not executed in this sector. The CORINH bit is
invalid when AUTODIST is set low. It is high in any of the conditions below when the AUTODIST bit
is set high.
(1) When an error was found in the Mode byte.
(2) When the Mode byte is a value other than 01h or 02h.
(3) When the Mode byte is 02h and the C2 pointer is high in the Submode byte.

bit 4: ERINBLK (erasure in block)

When the decoder is operating in the monitor-only, write-only or real-time mode which prohibits
erasure correction, this indicates that at least a 1-byte error flag (C2PO) has been raised in the
data excluding the Sync mark from the current sector CD DSP.

bit 3: CORDONE (correction done)

Indicates that there is an error corrected byte in the current sector.

bit 2: EDCNG

Indicates that an error was found in the current sector through an EDC check.

bit 1: ECCNG

Indicates that an uncorrectable error was found somewhere between the Header byte and the
Parity byte in the current sector. (Bit 1 = don't care in the Mode2, Form2 sectors.)

bit 0: TGTNTMET (target not met)

Indicates that the current sector address and the target address in the TGTMNT, TGTSEC, and
TGTBLK registers do not match. The error pointer is not referenced in this instance.

DECSTS0

– 29 –

1-1-16. 0Fh

(1) DECSTS1 (decoder status 1) register (read)

DECSTS1 (decoder status 1) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.

CXD1804AR

0Fh (R)

bits 7 to 3: RESERVED
bit 2: EDCALL0 (EDC all 0)

This is high when there are no error flags in all the 4 EDC parity bytes of the current sector and

their values are all 00h.
bit 1: CMODE (correction mode)
bit 0: CFORM (correction form)

These bits indicate the Mode and Form of the current sector the decoder has discriminated to

correct errors when the decoder is operating in the real-time correction or repeat correction mode.

CFORM

"X"
"L"
"H"

CMODE

"L"
"H"
"H"

MODE1
MODE2, FORM1
MODE2, FORM2

1-1-17. 10h, 11h

(1) LSTARA-H, L (last area-high, low) register (read/write)

LSTARA-H, L (last area-high, low) register

DECSTS1

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.
10h (R/W)
11h (R/W) b7 b6 b5 b4 b3 b2 b1

b8
b0

LSTARA-H
LSTARA-L

This register specifies the last order area. Set bits 7 to 1 of the LSTARA-H register low when writing in this
register.

1-1-18. 12h, 13h

(1) LHADR-H, L (last HADR-high, low) register (read/write)

LHADR-H, L (last HADR-high, low) register

Adr. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Reg.
12h (R/W)
13h (R/W) b7 b6 b5 b4 b3 b2 b1

b8
b0

LHADR-H

LHADR-L

When host automatic transfer mode is disabled, this register specifies the upper limit for HADRC (the upper 9
bits); for the subcode buffering command, this register specifies the upper limit for the address (upper 9 bits).
The lower 11 bits are 7FFh. Set bits 7 to 1 of the LHADR-H register low when writing in this register.

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