Sony CXD1257AR Datasheet
CCD Camera Timing Generator
Description
The CXD1257AR generates the timing pulses
required by the CCD image sensors as well as signal
processing circuits.
Features
• NTSC and PAL compatible
• Electronic shutter function
• H-driver
• Compatible with digital and analog camera systems
• Standby function
Applications
CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX026CKA, ICX027CKA
ICX054AK, ICX055AK
ICX056AK
CXD1257AR
64 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD Vss – 0.5 to +7.0 V
• Input voltage VI Vss – 0.5 to VDD + 0.5 V
• Output voltage VO Vss – 0.5 to VDD + 0.5 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage VDD 5.0 ± 0.25 V
• Operating temperature Topr –20 to +75 °C
Block Diagram
SYNC
GEN
62
60
59
57
63
64
1
2
41
42
43
44
45
46
22
37
VD INITIALIZE
HD INITIALIZE
1/2
HIGH-SPEED
PULSE
GENERATION
CIRCUIT
38
39
8
21
VSS
40
28
ADR . COUNT
H – ROM
LATCH
GATE
DRIVER
26
3
27
24
VDD
25
GATE
10
56
ADR . COUNT
DECODER
49
48
47
V – ROM
LATCH
GATE
COUNTER
51
50
19
18
17
15
16
MODE
SET
ADR . COUNT
ROG – ROM
LATCH
CONTROLLER
SHUT
53
54
52
29
ROM
30
31
DECODER
32
33
34
GATE
35
20
11
12
13
14
23
36
HTSG
61
4
MICROCOMPUTER
5
6
7
9
55
58
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E91817B4X-PK
Pin Description
CXD1257AR
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol I/O Description
OSCO
OSCI
EF
ED0
ED1
ED2
SMD1
Vss
SMD2
XVCT
D1
D2
D3
D4
A5
O
Inverter output for oscillation.
I
Inverter input for oscillation.
I
Not used. (With pull-up resistor)
I
Shutter speed setting. Strobe input for serial mode. (With pull-up resister)
I
Shutter speed setting. Clock input for serial mode. (With pull-up resister)
I
Shutter speed setting. Data input for serial mode. (With pull-up resister)
I
Shutter mode setting. (With pull-up resister)
—
GND
I
Shutter mode setting. (With pull-up resister)
O
Not used. (Open)
I
Fix at Low in normal operation. (With pull-down resister)
I
Fix at Low in normal operation. (With pull-down resister)
I
Fix at Low in normal operation. (With pull-down resister)
I
Low: NTSC, High: PAL. (With pull-down resister)
O
Not used. (Open)
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A4
A3
A0
A1
A2
Vss
RG
NC
VDD
VDD
H1
H2
Vss
XSUB
XV2
XV1
XSG1
O
Not used. (Open)
O
Not used. (Open)
O
Not used. (Open)
O
Not used. (Open)
O
Not used. (Open)
—
GND
O
Reset gate pulse output.
—
—
Power supply.
—
Power supply for H1 and H2.
O
Clock output for CCD horizontal register drive.
O
Clock output for CCD horizontal register drive.
—
GND for H1 and H2.
O
CCD discharge pulse output.
O
Clock output for CCD vertical register drive.
O
Clock output for CCD vertical register drive.
O
CCD sensor charge readout pulse output.
33
34
35
XV3
XSG2
XV4
O
Clock output for CCD vertical register drive.
O
CCD sensor charge readout pulse output.
O
Clock output for CCD vertical register drive.
– 2 –
CXD1257AR
Pin
No.
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Symbol I/O Description
TEST2
MCK
XSHP
XSHD
Vss
XSP1
XSP2
XSH1
XSH2
XDL1
XDL2
BFG
CLP1
CLP2
CLP3
I
Test input. Set at Low in normal operation.
O
NTSC: 1820fH/3, PAL: 1816fH/3. Output.
O
Precharge level sample-and-hold pulse.
O
Data sample-and-hold pulse.
—
GND
O
Color separation sample-and-hold pulse.
O
Color separation sample-and-hold pulse.
O
Switching sample-and-hold pulse.
O
Switching sample-and-hold pulse.
O
Delay line clock output.
O
Delay line clock output.
O
Pulse output for chroma modulator in encoder.
O
Clamp pulse output.
I/O
Clamp pulse output. When GM is set at High, standby mode switching input.
I/O
Clamp pulse output. When GM is set at High, standby mode switching input.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CLP4
PBLK
ID
WEN
GM
VDD
CL
PS
HD
VD
HTSG
TEST
XCK
CK
O
Clamp pulse output.
O
Blanking cleaning pulse output.
O
Line identification output.
O
Write enable output for low-speed shutter operation.
I
Low: Analog signal processing, High: Digital signal processing. (With pull-down resister)
—
Power supply.
O
NTSC: 910fH, PAL: 908fH. Clock output.
Switching for electronic shutter speed input method. (With pull-up resister)
I
Low: Serial input, High: Parallel input.
I
Horizontal synchronizing signal input.
I
Vertical synchronizing signal input. (During Low, 9H for NTSC and 7.5H for PAL)
Control input for XSG1 and XSG2. (With pull-up resistor)
I
Low: XSG1, XSG2 halted, High: XSG1, XSG2 generated.
I
Test input. Set at Low in normal operation. (With pull-down resister)
O
NTSC: 1820fH, PAL: 1816fH. Clock output.
I
NTSC: 1820fH, PAL: 1816fH. Clock input.
– 3 –
CXD1257AR
Electrical Characteristics
DC Characteristics (VDD = 5V ± 0.25V, Topr = –20 to +75°C)
Item
Symbol Conditions Min. Typ. Max. Unit
Supply voltage VDD
Input voltage 1
(Input pins other than those below)
Input voltage 2
(Pins 59 and 60)
Output voltage 1
(Output pins other than those below)
Output voltage 2
(Pins 22, 37, 38, 39, 57, and 63)
Output voltage 3
(Pins 26 and 27)
Output voltage 4
(Pin 1)
Feedback resister
Pull-up resister
Pull-down resister
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
VOH2
VOL2
VOH3
VOL3
VOH4
VOL4
RFB
RPU
RPD
IOH = –2mA
IOL = 4mA
IOH = –4mA
IOL = 8mA
IOH = –8mA
IOL = 8mA
IOH = –1mA
IOL = 1mA
VIN = Vss or VDD
VIL = 0V
VIH = VDD
4.75
0.7VDD
2.2
VDD – 0.5
VDD – 0.5
VDD – 0.5
VDD/2
500k
40k
40k
5.0
2M
100k
100k
5.25
0.3VDD
0.8
0.4
0.4
0.4
VDD/2
5M
250k
250k
V
V
V
V
V
V
V
V
V
V
V
V
V
Ω
Ω
Ω
I/O Pin Capacitances
Item
Input pin capacitance
Output pin capacitance
I/O pin capacitance
(VDD = VI = 0V, fM = 1MHz)
Symbol Min. Typ. Max. Unit
CIN
COUT
CI/O
9
11
11
pF
pF
pF
– 4 –
Description of Operation
1. Mode Control
CXD1257AR
Symbol
GM
PS
EF
HTSG
D1
D2
D3
D4
Pin No. L H
55
58
3
61
11
12
13
14
Analog signal processing Digital signal processing
Serial shutter Parallel shutter
speed setting speed setting
Fix at High in normal operation
XSG1, 2 XSG1, 2
OFF ON
Fix at Low in normal operation
Fix at Low in normal operation
Fix at Low in normal operation
NTSC PAL
– 5 –
2. Changes in I/O Signals in Each Mode
CXD1257AR
Symbol
GM
D2
TEST2
XSP1
XSP2
XSH1
XSH2
XDL1
XDL2
BFG
Pin No. Analog color Digital color 1 Digital color 2
55
12
36
41
42
43
44
45
46
47
Color separation
sample-and-hold
pulse output
Color separation
sample-and-hold
pulse output
Switching sampleand-hold pulse
output
Switching sampleand-hold pulse
output
Delay line clock
Delay line clock
Burst flag gate
pulse output
L
L
L
H
L
L
H
L
H
Color separation
Halted at High
sample-and-hold
pulse output
Color separation
Halted at High
sample-and-hold
pulse output
Switching sample-
Halted at Low
and-hold pulse
output
Switching sample-
Halted at Low
and-hold pulse
output
Halted at High
Halted at Low
Burst flag gate
pulse output
(normally not used)
Halted at High
Halted at Low
Burst flag gate
pulse output
(normally not used)
Standby control input
CLP2
49
Clamp pulse output
Low: Standby
High: Normal
operation
Standby control
Low: All circuits
halted for
CLP3
50
Clamp pulse output
standby mode
High: Only CL
output for
standby mode
ID
∗
When CLP2 = High, normal operation occurs regardless of whether CLP3 is high or low.
53
Line identification
output
Line identification
output
Standby control input
Low: Standby
High: Normal
operation
∗
Standby control
Low: All circuits
halted for
standby mode
High: Only CL
output for
standby mode
Line identification
output
∗
(Mode combinations other than those shown above cannot be used.)
Note) In the standby mode described above, XCK, XSG1, XSG2, XV1, XV2, XV3, XV4, XSUB, H1, H2, RG,
XSHD, XSHP, XSP1, XSP2, XSH1, XSH2, XDL1, and XDL2 pins are halted at Low. MCK, CLP1, CLP4,
PBLK, ID, XVCT, WEN, BFG, A0, A1, A2, A3, A4, and A5 pins are halted at the state just before
standby.
– 6 –
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