Sony CXD1199AQ Datasheet

—1—

E93Z06A78-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Absolute Maximum Ratings (Ta=25 °C)

• Supply voltage VDD –0.5 to +7.0 V

• Input voltage VI –0.5 to VDD +0.5 V

• Output voltage VO –0.5 to VDD +0.5 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –55 to +150 °C

Recommended Operating Conditions

• Supply voltage VDD +3.5 to +5.5 V

(+5.0 typ.)

• Operating temperature Topr –20 to +75 °C

Description

The CXD1199AQ is a CD-ROM decoder LSI with a

built-in ADPCM decoder.

Features

• Supports CD-ROM, CD-I and CD-ROM XA formats

• Real-time error correction

• Supports double speed playback

• Connectable with standard SRAM of up to 1 M-bits

(128 K-byte)

• All audio output sampling frequencies : 132.3 kHz
(built-in oversampling filter)

• De-emphasis digital filter

• Digital attenuator

• Intel CPU 80 series host interface

• Operates on 3.5 V

Applications

CD-ROM drives

Structure

Silicon gate CMOS IC

CD-ROM DECODER

100 pin QFP (Plastic)

CXD1199AQ

For the availability of this product, please contact the sales office.

—2—

CXD1199AQ

Block Diagram

11

12

13

14

22

23

31

–

39

24

25

26

27

30

41

42

64

66

67-75

76

77

80

81

82

83

84

43-45, 48-52, 55-63

GND

ADDRESS GEN

ECC

CORRECTOR

DMA FIFO

HD0-7, P

XHWR

HDRQ

DATO

MUTE

BCKO

WCKO

LRCO

XHAC

XHRS

XHRD

HINT

HA1

HA0

XHCS

SYNDROME GEN

GALOIS FIELD

SYNC CONTROL

DESCRAMBLER

CDP I/F

DMA

SEQUENCER

PRIORITY

RESOLVER

C2PO

ADPCM

DECORDER

DIGITAL

FILTER

DAC I/F

Sub CPU I/F

1, 2, 5-10

16-20

21, 46, 47, 96-100

D0-7

XCS

XRD

XWR

XINT

A0-A4

EMP

TD0-7

CLOCK

GEN

XRST

HCLK

CLK

RMCK

CKSL

XTL1

XTL2

BCLK

HOST DMA

HOST. I/F

MA0-16

XMOE

XMWR

MDB0-7, P

LRCK

DATA

85

86

87

88

89

91

92

93

94

95

3

285378

V

DD

4

15294054657990

—3—

CXD1199AQ

Pin Description

Pin No. Symbol I/O Description

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35

D0
D1

VDD

GND

D2
D3
D4
D5
D6
D7

XCS
XRD
XWR
XINT
GND

A0
A1
A2
A3
A4

TD0
XHRS
XHCS

HA0
HA1

HINT

XHRD

VDD

GND

XHWR

HD0
HD1
HD2
HD3
HD4

I/O
I/O

—

—
I/O
I/O
I/O
I/O
I/O
I/O

I
I
I

O

—

I
I
I
I
I

I/O

O

I
I
I

O

I
—
—

I

I/O
I/O
I/O
I/O
I/O

Sub CPU data bus
Sub CPU data bus
Power supply (+5 V)
GND
Sub CPU data bus
Sub CPU data bus
Sub CPU data bus
Sub CPU data bus
Sub CPU data bus
Sub CPU data bus
IC select negative logic signal from sub CPU
Sub CPU strobe negative logic signal to read this IC internal register
Sub CPU strobe negative logic signal to write this IC internal register
Interrupt request negative logic signal from IC to sub CPU
GND
Sub CPU address
Sub CPU address
Sub CPU address
Sub CPU address
Sub CPU address
Test I/O
Negative logic signal indicating that IC has been reset from host; open drain output
IC select negative logic signal from host
Host address signal
Host address signal
Interrupt request negative logic signal to host; open drain output
Host strobe negative logic signal to read this IC internal register
Power supply (+5 V)
GND
Host strobe negative logic signal to read this IC internal register
Host data bus
Host data bus
Host data bus
Host data bus
Host data bus

—4—

CXD1199AQ

Pin No. Symbol I/O Description

36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

HD5
HD6

HD7
HDP
GND

HDRQ

XHAC

MA0

MA1

MA2

TD1

TD2
MA3
MA4
MA5
MA6
MA7

VDD

GND

MA8
MA9

MA10
MA11
MA12
MA13
MA14
MA15
MA16

XMOE

GND

XMWR

MDB0
MDB1
MDB2
MDB3

I/O
I/O
I/O
I/O

—

O

I
O
O
O

I/O
I/O

O
O
O
O
O

—
—

O
O
O
O
O
O
O
O
O
O

—

O

I/O
I/O
I/O
I/O

Host data bus
Host data bus
Host data bus
Host data bus
GND
Host DMA request positive logic signal
Host DMA acknowledge negative logic signal
Buffer memory address (LSB)
Buffer memory address
Buffer memory address
Test I/O
Test I/O
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Power supply (+5 V)
GND
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory address
Buffer memory output enable negative logic signal
GND
Buffer memory write enable negative logic signal
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus

—5—

CXD1199AQ

Pin No. Symbol I/O Description

71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

MDB4
MDB5
MDB6
MDB7
MDBP

XTL2
XTL1

VDD

GND

CLK

HCLK

CKSL

RMCK

LRCK
DATA

BCLK

C2PO

EMP

XRST

GND
DATO
LRCO

WCKO

BCKO
MUTE

TD7
TD6
TD5
TD4
TD3

I/O
I/O
I/O
I/O
I/O

O

I
—
—

O
O

I

I

I

I

I

I

I

I
—

O
O
O
O

O
I/O
I/O
I/O
I/O
I/O

Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus
Buffer memory data bus (for error flag)
Crystal oscillation circuit output
Crystal oscillation circuit output (16.9344 MHz)
Power supply (+5 V)
GND

16.9344 MHz clock output

8.4672 MHz clock output
Clock select signal for CD-ROM decoder
Clock signal for CD-ROM decoder
LR clock signal from CD DSP (for discriminating L, R channels)
Data signal from CD DSP
DATA pin strobe clock signal (bit clock)
Error flag (C2 pointer) positive logic signal from CD DSP
Emphasis ON positive logic signal from CD DSP
Reset negative logic signal
GND
Data signal to DAC (D/A converter)
LR clock signal to DAC
Word clock signal to DAC
Bit clock signal to DAC
Mute positive logic signal
Test I/O
Test I/O
Test I/O
Test I/O
Test I/O

—6—

CXD1199AQ

Electrical Characteristics

DC characteristics (VDD=5 V±10 %, VSS=0 V, Topr=–20 to 75 °C)

Item

TTL input level pin

∗1

High level input voltage
TTL input level pin

∗1

Low level input voltage
CMOS input level pin

∗2

High level input voltage
CMOS input level pin

∗2

Low level input voltage
CMOS Schmitt input level pin

∗3

High level input voltage
CMOS Schmitt input level pin

∗3

Low level input voltage
CMOS Schmitt input level pin

∗3

Input voltage hysteresis
TTL Schmitt input level pin

∗4

High level input voltage
TTL Schmitt input level pin

∗4

Low level input voltage
TTL Schmitt input level pin

∗4

Input voltage hysteresis
Bidirectional pin with pull-up resistance

∗5

Input current

Input pin with pull-up resistance

∗6

Input current
High level output voltage

∗7

Low level output voltage

∗7

Input leakage current

∗8

Output leakage current

∗9

Oscillation cell ∗10High level input voltage
Oscillation cell Low level input voltage
Oscillation cell Logic threshold value
Oscillation cell Feedback resistance value
Oscillation cell High level output voltage
Oscillation cell Low level output voltage

Symbol

VIH1

VIL1

VIH2

VIL2

VIH4

VIL4

VIH4–VIL4

VIH5

VIL5

VIH5–VIL4

IIL3

IIL4

VOH1
VOL1

Iη

IOZ

VIH4
VIL4

LVTH

RFB
VOH2
VOL2

Conditions

VIN=0 V

VIN=0 V
IOH=–2 mA

IOL=4 mA
VIN=VSS or VDD
High-impedance
state

VIN=VSS or VDD
IOH=–3 mA
IOL=3 mA

Min. Typ. Max. Unit

2.2 V

0.8 V

0.7 VDD V

0.3 VDD V

0.8 VDD V

0.2 VDD V

0.6 V

2.2 V V

0.8 V V

0.4 V

–90 –200 –440 µA

–40 –100 –240 µA

VDD–0.8 V

0.4 V

–10 10 µA
–40 40 µA

0.7 VDD V

0.3 VDD V

0.5 VDD V

250 K 1 M 2.5 M Ω

0.5 VDD V

0.5 VDD V

—7—

CXD1199AQ

AC characteristics (VDD=3.5 V, VSS=0 V, Topr=–20 to 75 °C)

Item

TTL input level pin

∗1

High level input voltage
TTL input level pin

∗1

Low level input voltage
CMOS input level pin

∗2

High level input voltage
CMOS input level pin

∗2

Low level input voltage
CMOS Schmitt input level pin

∗3

High level input voltage
CMOS Schmitt input level pin

∗3

Low level input voltage
CMOS Schmitt input level pin

∗3

Input voltage hysteresis
TTL Schmitt input level pin

∗4

High level input voltage
TTL Schmitt input level pin

∗4

Low level input voltage
TTL Schmitt input level pin

∗4

Input voltage hysteresis
Bidirectional pin with pull-up resistance

∗5

Input current

Input pin with pull-up resistance

∗6

Input current
High level output voltage

∗7

Low level output voltage

∗7

Input leakage current

∗8

Output leakage current

∗9

Oscillation cell

∗10

High level input voltage
Oscillation cell Low level input voltage
Oscillation cell Logic threshold value
Oscillation cell Feedback resistance value
Oscillation cell High level output voltage
Oscillation cell Low level output voltage

Symbol

VIH1

VIL1

VIH2

VIL2

VIH4

VIL4

VIH4–VIL4

VIH5

VIL5

VIH5–VIL4

IIL3

IIL4

VOH1
VOL1

Iη

IOZ

VIH4
VIL4

LVTH

RFB
VOH2
VOL2

Conditions

VIN=0 V

VIN=0 V
IOH=–1.6 mA

IOL=3.2 mA
VIN=VSS or VDD
High-impedance
state

VIN=VSS or VDD
IOH=–1.3 mA
IOL=1.3 mA

Min. Typ. Max. Unit

2.2 V

0.6 V

0.7 VDD V

0.3 VDD V

0.8 VDD V

0.2 VDD V

0.5 V

2.2 V V

0.6 V V

0.3 V

–20 –50 –110 µA

–10 –25 –60 µA

VDD–0.8 V

0.4 V

–10 10 µA
–40 40 µA

0.7 VDD V

0.3 VDD V

0.5 VDD V

1.2 M 2.5 M 5 M Ω

0.5 VDD V

0.5 VDD V

—8—

CXD1199AQ

∗

1. D7 to 0, A4 to 0, XWR, XRD, XCS, MDB7 to 0, MDBP, HD7 to 0, HDP, TD7 to 0

∗

2. DATA, LRCK, C2PO, EMP, CKSL, RMCK

∗

3. BCKL, XRST, CKSL

∗

4. A4 to 0, XWR, XRD, XCS, HA1, HA0, XHWR, XHRD, XHCS, XHAC

∗

5. D7 to 0, MDB7 to 0, MDBP, HD7 to 0, HDP, TD7 to 0

∗

6. HA1, HA0, XHWR, XHRD, XHCS, XHAC

∗

7. All output pins except XTL2.

∗

8. All input pins except ∗5, ∗6 and XTL1.

∗

9. HINT

∗

10. input : XTL1; output : XTL2

I/O capacitance (VDD=VI=0 V, f=1 MHz)

Item
Input pin
Output pin
I/O pin

Symbol

CIN
COUT
COUT

Min. Typ. Max.

9
11
11

Unit

pF
pF
pF

—9—

CXD1199AQ

AC Characteristics (VDD=5 V±10 %, VSS=0 V, Topr=–20 to 75 °C, output load=50 pF)
Value in parentheses in the tables for VDD=3.5 V, VSS=0 V, Topr=–20 to +75 °C and output load=50 pF.
Others for VDD=5 V±10 % and VDD=3.5 V.

1. Sub CPU interface

(1) Read

(2) Write

A0

XCS

XRD

D7 to D0

Tsar Tdrd

Trr1

Thar

Tfrd

Item
Address setup time (for XCS & XRD ↓)
Address hold time (for XCS & XRD ↑)
Data delay time (for XCS & XRD ↓)
Data float time (for XCS & XRD ↑)
Low level XRD pulse width

Symbol

Tsar
Thar
Tdrd

Tfrd
Trr1

Min.
30 (70)
20 (50)

0

100 (150)

Typ. Max.

60 (100)

15 (25)

Unit

ns
ns
ns
ns
ns

A0

XCS

XWR

D7 to D0

Tsaw

Tww1

Thaw

Tsdw

Thdw

Item
Address setup time (for XCS & XWR ↓)
Address hold time (for XCS & XWR ↑)
Data setup time (for XCS & XWR ↑)
Data hold time (for XCS & XWR ↑)
Low level XWR pulse width

Symbol

Tsaw
Thaw
Tsdw
Thdw

Tww1

Min.
30 (70)
20 (50)
40 (70)
10 (30)
50 (80)

Typ. Max. Unit

ns
ns
ns
ns
ns

—10—

CXD1199AQ

2. CD DSP Interface

(1) Read

Tbck Tbck

Tsb1

Tsb2

Thb1

Thb2

BCKRED=“H”

BCLK

DATA

LRCK
C2PO

Tbck Tbck

Tsb1

Tsb2

Thb1

Thb2

BCKRED=“L”

BCLK

DATA

LRCK
C2PO

Item
BCLK frequency
BCLK pulse width
Data setup time (for BCLK)
Data hold time (for BCLK)
LRCK, C2PO setup time (for BCLK)
LRCK, C2PO hold time (for BCLK)

Symbol

Fbck

Tbck
Tsb1
Thb1
Tsb2
Thb2

Min.

88
20
20
20
20

Typ. Max.

11.3

Unit

MHz

ns
ns
ns
ns
ns

—11—

CXD1199AQ

3. Host interface

(1) Read

HA0, 1

XHCS

XHRD

HD7 to 0, P

Thsar Thdrd

Thrd1

Thhar

Thfrd

Item
Address setup time (for XHCS & XHRD ↓)
Address hold time (for XHCS & XHRD ↑)
Data delay time (for XHCS & XHRD ↓)
Data float time (for XHCS & XHRD ↑)
Low level XHRD pulse width

Symbol

Thsar
Thhar
Thdrd

Thfrd

Thrd1

Min.
30 (70)
20 (50)

0

100 (150)

Typ. Max.

60 (100)

15 (25)

Unit

ns
ns
ns
ns
ns

HA0, 1

XHCS

XHWR

HD7 to 0, P

Thsar

Thww1

Thhar

Thswd Thhwd

Item
Address setup time (for XHCS & XHWR ↓)
Address hold time (for XHCS & XHWR ↑)
Data setup time (for XHCS & XHWR ↑)
Data hold time (for XHCS & XHWR ↑)
Low level XHWR pulse width

Symbol

Thsar

Thhar
Thswd
Thhwd

Thww1

Min.
30 (70)
20 (50)
40 (70)
10 (30)

60 (100)

Typ. Max. Unit

ns
ns
ns
ns
ns

(2) Write

—12—

CXD1199AQ

4. Host DMA cycle

(1) Read

Tdar

Tdad

Thrd1

Thac

Tsac

Thfrd2Thdrd2

HDRQ

XHAC

XHRD

HD7 to 0, P

Item
HDRQ fall time (for XHAC ↓)
HDRQ rise time (for XHAC ↑)
XHAC setup time (for XHRD ↓)
XHAC hold time (for XHRD ↑)
Data delay time (for XHRD ↓)
Data float time (for XHRD ↑)
Low level XHRD pulse width

Symbol

Tdad

Tdar
Tsac
Thac

Thdrd2

Thfrd2

Thrd1

Min.

5 (20)
0 (20)

0

100 (150)

Typ. Max.

45 (70)
45 (70)

60 (100)

15 (25)

Unit

ns
ns
ns
ns
ns
ns
ns

Tdar

Tdad

Thww1

Thac

Tsac

Thhwd2Thswd2

HDRQ

XHAC

XHWR

HD7 to 0, P

Item
HDRQ fall time (for XHAC ↓)
HDRQ rise time (for XHAC ↑)
XHAC setup time (for XHWR ↓)
XHAC hold time (for XHWR ↑)
Data setup time (for XHWR ↓)
Data hold time (for XHWR ↑)
Low level XHWR pulse width

Symbol

Tdad

Tdar
Tsac
Thac

Thswd2
Thhwd2

Thww1

Min.

5 (20)

0 (20)
40 (70)
10 (30)

60 (100)

Typ. Max.

45 (70)
45 (70)

Unit

ns
ns
ns
ns
ns
ns
ns

(2) Write

—13—

CXD1199AQ

5. DAC interface

BCKO

DATO

WCKO
LRCO

Tbco Tbco

Tsbo

Tsbo

Thbo

Thbo

Item
BCKO frequency
BCKO pulse width
DATO, WCO1, WCO2, LRCO setup time
(for BCKO ↑)
DATO, WCO1, WCO2, LRCO hold time
(for BCKO ↑)

Symbol

Fbco
Tbco

Tsbo

Thbo

Min.

50
30

30

Typ.

8.4672

Max. Unit

MHz

ns
ns

ns