Sony CXD1175AP, CXD1175AM Datasheet
CXD1175AM/AP
8-bit 20MSPS Video A/D Converter (CMOS)
Description
The CXD1175A is an 8-bit CMOS A/D converter
for video use. The adoption of a 2-step parallel
system achieves low consumption at a maximum
conversion speed of 20MSPS minimum, 35MSPS
typical.
Features
• Resolution: 8 bit ± 1/2LSB (DL)
• Maximum sampling frequency: 20MSPS
• Low power consumption: 60mW (at 20MSPS typ.)
(reference current excluded)
• Built-in sampling and hold circuit
• Built-in reference voltage self-bias circuit
• 3-state TTL compatible output
• Power supply: 5V single
• Low input capacitance: 11pF
• Reference impedance: 300Ω (typ.)
Applications
TV, VCR digital systems and a wide range of fields
where high speed A/D conversion is required.
Structure
Silicon gate CMOS monolithic IC
CXD1175AM
24 pin SOP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VDD 7V
•Reference voltage VRT,VRBVDD + 0.5 to Vss – 0.5V
• Input voltage VIN VDD + 0.5 to Vss – 0.5V
(Analog)
• Input voltage VI VDD + 0.5 to Vss – 0.5V
(Digital)
• Output voltage VO VDD + 0.5 to Vss – 0.5V
(Digital)
• Storage temperature
Tstg –55 to +150 °C
Recommended Operating Conditions
• Supply voltage AVDD, AVss 4.75 to 5.25 V
DVDD, DVss
| DVss – AVss | 0 to 100 mV
• Reference input voltage
VRB 0 and above V
VRT 2.8 and below V
• Analog input VIN 1.8Vp-p above
• Clock pulse width
TPW1, TPW0 23ns (min) to 1.1µs (max)
• Operating ambient temperature
Topr –40 to +85 °C
CXD1175AP
24 pin DIP (Plastic)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E89321F78-PS
Block Diagram and Pin Configuration
CXD1175AM/AP
OE
DV
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
DV
CLK
SS
DD
10
11
12
1
24
DVSS
Reference voltage
VRB
2
3
4
5
Lower data
latches
Lower encoder
(4 bit)
Lower
comparators with
S/H (4 bit)
6
7
Lower encoder
(4 bit)
8
Upper data
Lower
comparators with
S/H (4 bit)
23
20
19
18
17
22
21
VRBS
AVSS
AVSS
V
IN
AVDD
VRT
latches
9
Upper encoder
(4 bit)
Upper
comparators with
S/H (4 bit)
Clock generator
16
15
14
13
VRTS
AVDD
AVDD
DV
DD
– 2 –
Pin Description and Equivalent Circuits
No. Symbol Equivalent circuit Description
DVDD
When OE = Low, Data is output.
1
OE
1
When OE = High, D0 to D7 pins turn
to High impedance.
DVSS
CXD1175AM/AP
2, 24
3 to 10
11, 13
12
16 VRTS
17
DVSS
D0 to D7
DVDD
CLK
VRT
Digital ground
Di
D0 (LSB) to D7 (MSB) output
Digital +5V
DVDD
12
DVSS
AVDD
Clock input
Shorted with VRT generates, +2.6V.
16
AVDD
Reference voltage (Top)
23
14, 15, 18
19
20, 21
22 VRBS
VRB
AVDD
VIN
AVSS
19
17
23
Reference voltage (Bottom)
AVSS
Analog +5V
AVDD
Analog input
AVSS
Analog GND
AVSS
Shorted with VRB generates +0.6V.
22
– 3 –
CXD1175AM/AP
Digital output
Compatibility between analog input voltage and the digital output code is indicated in the chart below.
Input signal
voltage
VRT
:
:
:
:
VRB
Clock
Amalog input
Data output
Step
0
:
127
128
:
255
TPW1 TPW0
N
N – 3 N – 2 N – 1 N N + 1
Digital output code
MSB LSB
1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1
:
0 0 0 0 0 0 0 0
N + 1
N + 2
N + 3
N + 4
OE input
Output 1
Output 2
Td = 18ns
Timing Chart 1
tr = 4.5ns tf = 4.5ns
90%
2.5V
tPLZ
10%
tPHZ
90%
tPZL
tPZH
Timing Chart 2
10%
1.3V
1.3V
: Point for analog signal sampling.
5V
0V
OH
V
VOL (≠DVSS)
OH (≠DVDD)
V
V
OL
– 4 –
Electrical Characteristics
CXD1175AM/AP
Analog characteristics
Item Symbol Conditions Min. Typ. Max. Unit
Conversion speed
Analog input band width
(–1dB)
Offset voltage
Integral non-linearity error
Differential non-linearity erro
Differential gain error
Differential phase error
Aperture jitter
Sampling delay
∗1
The offset voltage EOB is a potential difference between VRB and a point of position where the voltage
drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”.
EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to
1/2LSB of the voltage when the output data changes from “11111111” to “11111110”.
∗1
Fc
BW
EOT
EOB
EL
r
ED
DG
DP
taj
tsd
(Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)
VDD = 4.75 to 5.25V
Ta = –40 to +85°C
VIN = 0.5 to 2.5V
fIN = 1kHz ramp
Envelope
Potential difference to VRT
Potential difference to VRB
End point
NTSC 40 IRE mod ramp
Fc = 14.3MSPS
0.5
–10
0
18
–35
+15
+0.5
±0.3
1.0
0.5
30
4
20
–60
+45
+1.3
±0.5
MSPS
MHz
mV
LSB
%
deg
ps
ns
– 5 –
CXD1175AM/AP
DC characteristics
Item Symbol Conditions Min. Typ. Max. Unit
Supply current
Reference pin current
Analog input capacitance
Reference resistance
(VRT to VRB)
Self-bias I
Self-bias II
Digital input voltage
Digital input current
Digital output current
IDD
IREF
CIN
RREF
VRB1
VRT1 – VRB1
VRT2
VIH
VIL
IIH
IIL
IOH
IOL
IOZH
IOZL
(Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)
Fc = 20MSPS
NTSC ramp wave input
VIN = 1.5V + 0.07Vrms
Shorts VRB and VRBS
Shorts VRT and VRTS
VRB = AGND
Shorts VRT and VRTS
VDD = 4.75 to 5.25V
Ta = –40 to +85°C
VIH = VDD
VDD = max
OE = VSS
VDD = min
OE = VDD
VDD = max
VIL = 0V
VOH = VDD – 0.5V
VOL = 0.4V
VOH = VDD
VOL = 0V
4.5
230
0.60
1.96
2.25
3.5
–1.1
3.7
12
6.6
11
300
0.64
2.09
2.39
17
8.7
450
0.68
2.21
2.53
1.0
5
5
16
16
mA
mA
pF
Ω
V
V
V
µA
mA
µA
Timing
Item Symbol Conditions Min. Typ. Max. Unit
Output data delay
Tri-state output
enable time
Tri-state output
disable time
(Fc = 20MSPS, VDD = 4.75 to 5.25V, VRB = 0.5V, VRT = 2.5V, Ta = –40 to +85°C)
TDL
tPZH
tPZL
tPHZ
tPLZ
With TTL 1 gate and 10pF load
RL = 1kΩ, CL = 20pF
OE = 5V → 0V
RL = 1kΩ, CL = 20pF
OE = 0V → 5V
18
3
7
7
15
30
13
26
ns
ns
ns
– 6 –
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