Sony CXB1818Q Datasheet

CXB1818Q

Laser Diode Driver

Description

The CXB1818Q is a high-speed monolithic Laser Diode Driver/Current Switch with ECL/PECL input level. Open collector outputs are provided at the output pins (Q, QBX) and have the capacity of driving modulation current of 50mAp-p at a maximum data rate of 622Mbps. Along with the modulation current generator there is the laser diode bias current generator which has capacity of sourcing up to 60mA (Bias). The laser diode bias current can be controlled by either a voltage or current into the bias adjust pin (BiasAdj) and the bias set pin (SBias), depending on how these pins are configured. Control of the bias current is achieved through the APC (Automatic Power Control) circuit. In order to avoid having a large current go through the laser diode, this IC also provides an Activity detector function for laser protection. The Activity detector circuit detects data edge transitions and if no data transition occurs after a certain period, then both the modulation and bias currents are shutdown. The bias currents are shut it down by in order to pull down the output voltage of APC OP.Amp.

When the automatic shutdown is conducted, it is possible to select whether the laser diode alarm output is activated or not. Additionally, this IC has the DFF for the input signal correction and the internal Duty Cycle correction circuit that can control the falling edge of the input pulse up to a maximum of 1.0ns(Min.).

Features

• Maximum data rate (NRZ): 622Mbps

• Alarm and Shutdown function

• DFF for input signal correction

• Input signal Duty cycle correction

• Automatic Power Control (APC) for bias current

• Activity detector function for laser protection

• Alarm signal mask function during shutdown

• Differential PECL inputs or AC coupled inputs

– 1 –

E99227-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Applications

• SONET/SDH: 622Mbps

• Fibre channel: 531Mbps

Absolute Maximum Ratings

• Supply voltage VCC – VEE –0.3 to +6.0 V

• Input voltage VIN VEE to VCC V

• Differential input voltage

|

VD – VDB

|

0 to 2.5 V

• Bias output current 0 to 80 mA

• SBias input/output current 0 to 5 mA

• Bias control current

IBset (Ibiasadj) 0 to 5 mA

• Bbias control voltage VBset (Vbiasadj) 0 to 3 V

• Modulation output current 70 mA

• Modulation adjust current

IQset (Idrvadj) 0 to 15 mA

• Storage temperature Tstg –65 to +150 °C

Recommended Operating Conditions

• DC supply voltage

VCC – VEE 3.14 to 3.46 V

• Operating ambient temperature Ta –40 to +85 °C

Structure

Bipolar silicon monolithic IC

40 pin QFP (Plastic)

– 2 –

CXB1818Q

Block Diagram and Pin Configuration

Tset

VREF

VCC6

LDAlm

LDAlmB

V

CC3

V

EE3

ADCDis

FFSel

ClkB

Timer

CompB CompA DrvAdj DrvMon

TM

V

CC1

VEE1

QBX

NC

Q

V

EE5

Bias

SBias

BiasAdj

V

EE4

V

CC4

V

EE2

Clk

DB

D

VCC2

MaskSel

RSB

RS

SDN

SDNB

WCompIn

RsetPD

APCOut

DRV Cont

Duty Cycle Cont

In_ALM

D-FF

MUX

Vbb Gen.

Reference Generator

Vref

Bias Circuit

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

2122232425262728

2930

31

32

33

34 35

36 37

38 39

40

– 3 –

CXB1818Q

Pin Description

Pin No.

1

VCC4

3.3

Positive power supply for APC circuit.

2

VEE4

0

Negative power supply for APC circuit.

6

VEE5 0

Negative power supply for bias circuit.

7

Q

1.3 to 3.3

6mA to 30mA

∗1

6mA to 50mA

∗2

9 QBX 1.3 to 3.3

6mA to 30mA

∗1

6mA to 50mA

∗2

Modulation current output. Open collector output.

10

VEE1

0

Negative power supply for driver circuit.

11

VCC1

3.3

Positive power supply for driver circuit.

12

TM

1.5

Chip temperature monitor.

13 DrvMon

0mA

to

1.4mA

Modulation current (IQ) monitor. IQ is monitored by connecting a resistor (Rmon) to this pin.

14

DrvAdj

0mA

to

9mA

Modulation current (IQ) setting.

3

BiasAdj

1.5 to 0

Bias current setting.

4

SBias

0mA

to

2.5mA

Bias current setting or monitor.

5

Bias

0mA

to

60mA

Bias current output. Open collector output.

Symbol

Typical pin voltage [V]

DC AC

Equivalent circuit

Description

3

VCC

VEE

10pF

260

240

30

8

4 5

VEE

Current Source

7 9

13

14

VCC

Rmon

VEE

22.5 150

∗1

Ta = –40 to 0°C

∗2

Ta = 0 to +85°C

Complementary current output. Q and QBX are not symmetrical output. Use Q output for laser diode.

8

NC

—

No connected.

—

10

12

V

EE

– 4 –

CXB1818Q

15 CompA

Modulation current driver compensation. Normally, connects 180pF capacitor between CompA and CompB pins.

16 CompB

Capacitor connection for activity detector (IN_ALM) operation. This pin sets the period of inactive time for activity detector. Inactive time is controlled by connecting a capacitor to this pin.

17 Timer

DC AC

VCC

VEE

30pF

180pF

10k

15 16

VCC

2.1k

VEE

10pF

100

200µA

Ctimer

25µA

2.4k

17

Activity detector circuit control. High (connected to VCC or open):

Activity detector is disable.

Low (connected to VEE):

Activity detector is enable.

18

ADCDis

VEE

to

VCC

(open)

VCC

VEE

3.8k3.8k

15µA

35k 35k 35k 35k

18

Input data D-FF selection control. High (open):

FF not used (Through mode)

Low (connect to VEE):

FF used (FF mode)

19 FFSel

VEE

or

open

19

VCC

VEE

100k

4.5k

4.5k 4.5k9k

Pin No.

Symbol

Typical pin voltage [V]

Equivalent circuit Description

– 5 –

CXB1818Q

Negative power supply for data input circuit.

22

VEE2

0

No.

Symbol

Typical pin voltage [V]

DC AC

Equivalent circuit Description

20 ClkB 1.6 to 2.4

21

Clk

1.6 to 2.4

Differential PECL clock input.

20 21

VCC

VEE

550 550

200

400µA

200

23

DB

1.6 to 2.4

24

D

1.6 to 2.4

25

VCC2

3.3

Differential PECL data input.

Positive power supply for data input circuit.

24

25

23

22

300 300

200

10k

1mA

200

300µA

26 MaskSel

VEE

or

open

Alarm signal control for optical power output forced shutdown. High (open):

Alarm signal is High for shutdown.

Low (connect to VEE):

Alarm signal stays Low for shutdown.

26

VCC

VEE

4.5k 4.5k9k

1k

2.2k

27 RSB 0.5

28 RS 2.0

Window comparator top/bottom threshold voltage for LD_ALARM. The alarm (fault) assert voltage can be set by the external resistor. Default voltages are RS equal to 2.0V and RSB equal to 0.5V. (Option)

VCC

VEE

100µA

2.5k

15k

5k

27

28

– 6 –

CXB1818Q

No.

29

SDNB 0 to 3.3

30

SDN 0 to 3.3

32

VREF 1.7

Complementary TTL input to disable the output current. (Shutdown input) When left open, High.

Temperature compensated reference voltage for APC. Approximately 1.7V (Constant for VEE reference)

Symbol

Typical pin voltage [V]

DC

AC

Equivalent circuit Description

VCC

VEE

5k

300

60µA

29 30

300300

1.9mA

VCC

VEE

200

2.4k

9.1k

32

31 Tset

Output duty cycle control. This pin controls the falling edge of the input High pulse. Variable delay limit of that is from 0 to 1.0ns. Duty cycle is controlled by connecting a resistor value between VCC and this pin.

2.4k

70µA

V

CC

VEE

220

140

20pF

Rset

31

33

VCC6

3.3

Positive power supply for alarm output circuit.

34

LDAlm 0.2 to 3.0

35

LDAlmB 0.2 to 3.0

Activates when the fault is detected in the laser monitor diode circuit. (Pseudo LVTTL output)

VCC

VEE

34 35