– 1 –
CXB1585N
E96301-ST
Fibre Channel Repeater
Description
The CXB1585N is a repeater IC with a built-in PLL
clock recovery circuit for Fibre Channel 1.06Gbaud.
This IC incorporates a port bypass circuit and is
suitable for disk array and FC-AL HUB, etc.
Features
• Conforms to ANSI X3T11 Fibre Channel standard
• Single 3.3V power supply
• Low power consumption: 330mW (Typ.)
• Low jitter
• PLL lock detection circuit
• Port bypass circuit
• Small plastic package (24-pin SSOP)
Applications
• Fibre channel arbitrated loop 1.0625Gbaud HUB
• Disk array
Structure
Bipolar silicon monolithic IC
Pin Configuration
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
24 pin SSOP (Plastic)
13
14
15
16
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
9
10
11
12
1
LPFNEG
LPFPOS
V
CCP
TDOUT
∗
TDOUT
LKDT
TEST2
SDOUT
∗
SDOUT
V
CCE
V
EEE
V
EEG
REXT
VEEP
V
EET
REFCLK
TDIN
SDIN
∗
SDIN
V
CCG
TEST1
TDIN
∗
LKREF
∗
TDSEL
∗
– 3 –
CXB1585N
Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V)
Item Unit
V
V
V
V
mA
mA
mA
°C
°C
4
5.5
VCC
2
0
20
0
70
150
–0.3
–0.5
VCC – 2
–2
–20
0
–30
–55
–65
VCC
VI_T
VI_E
VIS_E
IOH_T
IOL_T
IO_E
Ta
Tstg
Supply voltage
TTL DC input voltage
ECL DC input voltage
ECL differential input voltage
TTL output current (High level)
TTL output current (Low level)
ECL output current
Operating ambient temperature
Storage temperature
Max.Typ.Min.Symbol
Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V)
Item Unit
V
°C
3.465
70
3.33.135
0
VCC
Ta
Supply voltage
Ambient temperature
Max.Typ.Min.Symbol
– 4 –
CXB1585N
Pin Description
Pin
No.
Symbol Type
Typical pin
I/O voltage
Equivalent circuit Description
TEST1
TEST2
TTL
input
3.3V
1, 19
Test pin.
Connect to Vcc.
3
TDSEL
∗
TTL
input
TTL level
High; SDOUT outputs
the SDIN
retimed data.
Low; SDOUT outputs
TDIN data.
4, 5
SDIN
SDIN
∗
ECL
input
ECL level
Serial data input.
VCCE
VEEE
ECL_IN
ECL_IN
∗
VCCG
V
EEG
V
CCE – 1.3V
6
LKREF
∗
TTL
input
TTL level
Low; PLL takes the
frequency from
REFCLK.
2
VCCG
Power
supply
3.3V
—
Positive power supply
for internal logic gate.
– 5 –
CXB1585N
9
REFCLK
TTL
input
TTL level
Reference clock input.
This pin is used for
the PLL to take the
frequency.
Input 53.125MHz to
this pin.
10
VEET
Power
supply
0V
Negative power supply
for REFCLK input.
11
VEEP
Power
supply
0V
Negative power supply
for internal PLL.
12
REXT
External
parts
connection
pin
—
Connects the resistor
which determines the
VCO center
frequency.
4.7kΩ resistor should
be connected
between this pin and
VEEP.
13,
14
LPFNEG
LPFPOS
External
parts
connection
pin
—
Connects the
external loop filter.
7, 8
TDIN
TDIN
∗
ECL
input
ECL level
Serial data input.
VCCE
VEEE
ECL_IN
ECL_IN
∗
VCCG
V
EEG
V
CCE – 1.3V
Pin
No.
Symbol Type
Typical pin
I/O voltage
Equivalent circuit Description