Sony CXB1583Q Datasheet

266Mbaud Fibre Channel Transceiver IC

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Description

The CXB1583Q is a transceiver IC with the built-in

PLLs into a single chip.

For receiver, the 265.625Mbaud serial data is received and it is output as a 10-bit parallel data; for transmitter, the 265.625Mbaud 10-bit parallel data is received and it is output as a serial data after conversion.

Features

• Transmitter/receiver into a single chip

• Conforms to ANSI X3T11 fibre channel standard

• PLL for a clock synthesizing and for clock recovery

• Single 3.3V power supply

• Low power consumption: 860mW (Typ.)

• 80-pin plastic package

• Comma signal detector

• Test pattern (±K28.5) generation circuit

• Loop-back circuit

• Supports data rage of 200Mbaud

Applications

265.625Mbaud fibre channel

Structure

Bipolar silicon monolithic IC

CXB1583Q

80 pin QFP (Plastic)

Pin Configuration

SDOUT

TXSIN

ECKENB

ALTENB

TPGEN

TXSER

REFCLK

V

CCE EEE

V

LOL

EEG

V

CCG

V

EEG

CCG

V LPBK

EET

V

CCG

V

EEG

V

∗

ECK

49

ECK

48

∗

TXSOUT

47

46

∗

E

CC

EE

SDIN

V

43

45

44

SDIN

42

G

CC

EE

V

41

40

MS1 MS0

39

CDETENB

38 37

CCT

V

∗

36

POR

35

TXLKDT RXLKDT

34

EET

V

33 32

PCLKOUT0 PCLKOUT1

31

EEG

V

30

CCG

V

29

CDET

28

PDO9

27

PDO8

26

EET

V

25

PDO7

24

CCT

V

23

VCCG

22

EEG

V

21

∗

LPFB

52

LPFA

51

P

CC

V

50

P1

P2

EE

REXT

TJMON

LPFC

LPFD

LCKREF

60

61

∗

62 63

64

65

∗

66 67 68 69

∗

70 71 72 73

∗

74

∗

75 76 77 78

79 80

59

58

57

56

55

V

53

54

1

PDI0

2

PDI1

3

PDI2

4

PDI3

5

PDI4

6

PDI5

7

8

PDI6

9

PDI7

10

PDI8

11

PDI9

12

PDO0

13

PDO1

14

15

16

T

EE

CC

V

PDO3

PDO2

17

18

PDO4

19

20

T

EE

V

PDO6

PDO5

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96501-ST

CXB1583Q

Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V)

Item Unit Power supply TTL DC input voltage ECL DC input voltage ECL differential input voltage TTL output current (high level) TTL output current (low level) ECL output current Operating ambient temperature Storage temperature

VCC VI_T VI_E VIS_E IOH_T IOL_T IO_E Ta Tstg

–0.3 –0.5

VCC – 2

–2

–20

0 –30 –55 –65

Max.Typ.Min.Symbol

5.5

VCC

20

70

150

4

V V

V 2 0

V

mA mA

0

mA

°C °C

Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V)

Supply voltage Ambient temperature

Item Unit

VCC Ta

0

3.33.135

Max.Typ.Min.Symbol

3.465 70

V

°C

– 2 –

Block Diagram

CXB1583Q

PDI (0 to 9)

ALTENB

∗

REFCLK

10

26.6Mbps

REFCLK

(26.6MHz)

DQ

10

K28.5

Gen.

TX_PLL

∗

TPGEN

1 0

TXCLK (26.6MHz)

TXLOAD (266MHz)

P/S

TXSER

SoutPin

TXSIN

∗

TXSIN

0 1

TXSOUT

SDOUT

TXLKDT

∗

EEP

V

PDO (0 to 9)

PCLKOUT0

PCLKOUT1

CDET

LPFA

LPFB

REXT

26.6Mbps

10

S/P

CDETENB

RTDATA

RXCLK (266MHz)

RPCLK (26.6M)

RX_PLL

LPFC

LPFD

LPBK

SDIN

1 0

∗

SDIN

LOL

RXLKDT

∗

LCKREF

– 3 –

Pin Description

CXB1583Q

No.

Symbol Type

1 t o 1 0 PDI0 to 9

11, 12, 14, 16, 17, 19,

PDO0 to 9 20, 24, 26, 27

TTL input

TTL output

Typical pin I/O voltage

TTL level

VCCG

TTL-IN

VEET

Equivalent circuit Description

Parallel data input.

VEEG

VCCT

TTL-OUT

Parallel data output.

13, 18, 25, 33,78VEET

15, 23, 37

VCCT 21, 30,

42, 68,

VEEG 71, 80

22, 29, 41, 69,

VCCG 72, 79

28 CDET

Power supply

TTL output

0V —

3.3V —

0V —

3.3V —

TTL level

VEET

VCCT

TTL-OUT

VEET

Negative power supply for TTL input/output.

Positive power supply for TTL output.

Negative power supply for internal logic gate.

Positive power supply for internal logic gate.

Byte synchronization output. Outputs high level when +Comma (0011111) or –Comma (1100000) is detected to the serial data.

– 4 –

CXB1583Q

No.

32

31

Symbol Type

PCLKOUT0

PCLKOUT1

TTL output

Typical pin I/O voltage

TTL level

Equivalent circuit Description

VCCT

Receive byte clock 0

TTL-OUT

output. This clock is used to take the parallel data (PDO0 to 9) at the next-stage system.

VEET

VCCT

Receive byte clock 1

TTL-OUT

output. PCLKOUT0 inverted clock.

34 RXLKDT

TXLKDT

35

TTL output

TTL level

VEET

VCCT

TTL-OUT

VEET

VCCT

TTL-OUT

VEET

RX_PLL lock detection signal output. Outputs high level when the PLL is locked to the serial data or the serial data has no signal; Outputs low level when the PLL is not locked. RXLKDT output may sporadically go high when the PLL starts to lock to the serial data.

TX_PLL lock detection signal output. Outputs high level when the PLL is locked to REFCLK and operating normally; Outputs low level when the PLL is not operating normally.

– 5 –

CXB1583Q

No.

36

Symbol Type

∗

POR

38 CDETENB

TTL output

TTL input

Typical pin I/O voltage

TTL level

VCCG

TTL-IN

VEET

Equivalent circuit Description

VCCT

Power-on reset signal output.

TTL-OUT

Outputs high level after the power is turned on and low level is held for approximately 100ns.

VEET

Byte synchronization enable signal input. When high level is input, +Comma (0011111) or –Comma (1100000) is detected and the parallel data is synchronized with this byte. (See the Timing Chart.) When low level is input,

VEEG

byte synchronization is not performed.

39, 40

43, 44

MS0, MS1

SDIN

∗

SDIN

TTL input

ECL input (differential)

3.3 V or TTL high level

ECL level

VCCG

TTL-IN

VEET

VCCE

ECL-IN

VEEE

Test pin. Connect to Vcc.

VEEG

VCCG

VCCE – 1.3V

∗

VEEG

Serial data input.

45, 63

46, 64

VCCE

VEEE

Power supply

3.3V

0V

– 6 –

—

Positive power supply for ECL input/output.

Negative power supply for ECL input/output.

CXB1583Q

Pin No.

47, 48

49, 50

Symbol Type

ECL TXSOUT TXSOUT

∗

output

(differ-

ential)

ECL ECK ECK

∗

output

(differ-

ential)

Typical pin I/O voltage

ECL level

One is left open; another is connected to Vcc via 47kΩ.

VCCE

ECL-IN

Equivalent circuit Description

VCCE

Parallel/serial

ECL-OUT

conversion output. This output is

∗

ECL-OUT

enabled when TXSER is high.

VEEE

VCCG

Test pin.

VCCE – 1.3V

∗

Connect either of these pins to Vcc via a 47kΩ resistor.

51 VCCP

52,53LPFA

LPFB

54,55VEEP1

VEEP2

56 REXT

Power

supply

Ex-

ternal

part

con-

nection

Power

supply

External part connection

3.3V

—

0V

—

VEEE

VCCP

LPF_C LPF_D

VEEP2

—

VCCP

REXT

VEEG

Positive power supply for internal PLL.

RX_PLL external loop filter connection. (See Fig. 1 of the Notes on Operation.)

VEEP1

Negative power supply for internal PLL.

Connects the resistor which determines the VCO center frequency. (See Fig. 1 of the Notes on Operation.)

– 7 –

VEEP2