Sony CXB1582Q Datasheet

Description

The CXB1582Q is a receiver IC with a built-in PLL clock recovery circuit for high-speed serial data reception. It can be used together with the transmitter IC CXB1581Q as a chip set, and 1062.5Mbaud, 20bit or 531.25Mbaud, 10-bit operation can be selected.

Features

• Conforms to ANSI X3T11 Fibre channel standard

• Supports GLM (Gigabaud Link Module) interface

• Built-in low-jitter PLL clock recovery circuit

• Single 3.3V power supply or dual 3.3V/5V power

supply (for 5V TTL interface) operation can be

selected.

• Low power consumption: 910mW (Typ.) when

operating with a single 3.3V power supply

• 1062.5Mbaud, 20-bit or 531.25Mbaud, 10-bit

operation can be selected.

• PLL lock detection circuit

• Power-on reset signal output circuit

Pin Configuration

Applications

Fibre channel 1062.5Mbaud and 531.25Mbaud communications

Structure

Bipolar silicon monolithic IC

– 1 –

CXB1582Q

E95930-ST

Fibre Channel Receiver

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

80 pin QFP (Plastic)

21

22

23

24

25

26

27

28

29

30

40 39

38 37 36 35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63 64 65 66

61 62

71

72 73

74 75 76 77 78 79 80

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

VEEG V

CCG

LBEN

SHD

LCKREF

∗

SYNCEN

SDRSEL

PPSEL

REFCLK

RTCAP

POR

∗

V

CCT5

V

CCT3

V

EET

V

EEG

V

CCG

V

CCG

RX19 RX18 RX17

ECLKSEL

∗

PDTEST SSEL0 SSEL1 LKDT

∗

SYNC RBC1 RBC0 V

EET

V

CCT5

RX3

V

CCT3

V

EET

RX0 RX1 V

EEG

V

CCG

V

CCT5

V

CCT3

RX2

SOUT

∗

V

CC

E

PTEST

LPF_A

V

EE

P2

V

EE

G

EXCLK

LBIN

∗

V

CC

E

SDIN

∗

V

EE

E

TJMON

REXT

V

CC

P

LPF_B

V

EE

P1

V

CC

G

RX16

V

CC

T5

RX12

V

CC

T3

RX15

RX14

RX13

V

EE

T

V

EE

T

RX11

RX4

RX10

RX9

RX8

V

CC

T3

V

CC

T5

RX7

RX6

RX5

V

EE

T

– 2 –

CXB1582Q

Absolute Maximum Ratings (VEEE, VEET, VEEG, VEEP = 0V)

Item Unit

V V V

V

V mA mA mA

°C °C

4

VCCG + 5,

or 5.5

5.5

VCC

2 0

20

0

70

150

–0.3

VCCG – 2,

or –0.3

–0.5

VCC – 2

–2

–20

0 –30 –55 –65

VCC VCCT5 VI_T

VI_E VIS_E IOH_T IOL_T IO_E Ta Tstg

Supply voltage (excluding VCCT5) Supply voltage for TTL output TTL DC input voltage

ECL DC input voltage ECL differential input voltage TTL output current (High level) TTL output current (Low level) ECL output current Operating ambient temperature Storage temperature

Max.Typ.Min.Symbol

Recommended Operating Conditions (VEEE, VEET, VEEG, VEEP = 0V)

During single 3.3V power supply operation

Item Unit

V

°C

3.465 70

3.33.135

0

VCC Ta

Supply voltage (including VCCT5) Ambient temperature

Max.Typ.Min.Symbol

During dual 3.3V/5V power supply operation (VCCT3 open)

Item Unit

V V

°C

3.465

5.25 70

3.3 5

3.135

4.75 0

VCC VCCT5 Ta

Supply voltage (excluding VCCT5) Power supply for TTL output Ambient temperature

Max.Typ.Min.Symbol

– 3 –

CXB1582Q

Block Diagram

RBC1

RBC0

LCKREF

∗

SDRSEL

REFCLK

LPF_A

LPF_B

REXT

SSEL1

LBEN

1 0

10

Parallel Clock Generator

PLL

EXCLK

ECLKSEL

∗

SYNCEN

POR

∗

LKDT

∗

Power On Reset Output Generator

DFF

S/P

Converter

Data Output Controll

SYNC

RTCAP

53.125MHz

SOUT/SOUT

∗

RX00 to 09

RX10 to 19

53.125Mbaud

10

0 1

SDIN/SDIN

∗

SHD

LBIN/LBIN

∗

531.25 or

1062.5MHz

SSEL0

PPSEL

53.125MHz

20

Byte

Sync

ECL Output

Selector

– 4 –

CXB1582Q

Pin Description

1, 10,

19, 29,

32, 74

VEET

Power supply

0V

Negative power supplies for TTL output.

78

to

80,

2 to 4,

7 to 9,

11

RX19

to

RX17, RX16

to

RX14, RX13

to

RX11, RX10

TTL output

TTL level

Parallel data outputs (Byte_1).

—

VEET

VCCT5

VCCT3

RX10 to 19

12

13,

16

to

18,

20

to

22,

27 28

RX09, RX08, RX07

to

RX05, RX04

to

RX02, RX01, RX00

TTL output

TTL level

Parallel data outputs (Byte_0). The first data of the serial data is RX00 and the last data is RX19 (RX09 during 531Mbaud mode).

VEET

VCCT5

VCCT3

RX00 to 09

5, 14,

23, 3073VCCT3

Power supply

3.3V or open

Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; leave open when using the IC with a dual 3.3V/5V power supply.

VCCT5

VEET

VCCT3

VCCG

6, 15,

24, 3172VCCT5

Power supply

3.3V or 5V

Positive power supply for TTL output. Set to 3.3V when using the IC with a single 3.3V power supply; to 5V when using the IC with a dual 3.3V/5V power supply.

VCCT5

VEET

VCCT5

VCCG

Pin No.

Symbol Type

Typical pin I/O voltage

Equivalent circuit Description

– 5 –

CXB1582Q

25, 42, 62, 76,77VCCG

Power supply

3.3V

Positive power supplies for internal logic gate.

33 RBC0

TTL output

TTL level

Receive byte clock 0 output. This clock is used when loading parallel data (RX00 to RX19) using the system in the next stage.

—

26, 41,

61, 75

VEEG

Power supply

0V

Negative power supplies for internal logic gate.

—

VEET

VCCT5

VCCT3

RBC0

34 RBC1

TTL output

TTL level

Receive byte clock 1 output. Inverse of the RBC0 clock.

VEET

VCCT5

VCCT3

RBC1

35 SYNC

TTL output

TTL level

Byte sync output. This pin outputs high level when +Comma (0011111) or –Comma (1100000) is detected in the serial data. (See the Timing Charts.)

VEET

VCCT5

VCCT3

SYNC

Pin No.

Symbol Type

Typical pin I/O voltage

Equivalent circuit Description

– 6 –

CXB1582Q

36

LKDT

∗

TTL output

TTL level

PLL lock detection signal output. This pin outputs low level when the PLL is locked to the serial data and high level when the PLL becomes unlocked.

VEET

VCCT5

VCCT3

LKDT

∗

3738SSEL1

SSEL0

TTL input

TTL level

SOUT/SOUT∗output signal selection. (See Table 1.)

VEET

VCCG

SSEL0 SSEL1

V

EET

39 PDTEST

TTL input

0V

Test. Connect to VEEG.

VEET

VCCG

PDTEST

V

EET

40

ECLKSEL

∗

TTL input

TTL high level or 3.3V

External clock selection. When this pin is set to low level, the clock input to EXCLK is used as the bit rate clock.

VEET

VCCG

ECLKSEL

∗

V

EET

Pin No.

Symbol Type

Typical pin I/O voltage

Equivalent circuit Description

– 7 –

CXB1582Q

4344SDIN

∗

SDIN

ECL input (differen

-tial)

ECL level

Serial data inputs. These input pins are enabled when SHD is set to low level.

45,

58

VCCE

Power supply

3.3V

Positive power supplies for ECL I/O.

—

VEEE

SDIN

∗

SDIN

VCCE

VEEG

VCCG

VCCE – 1.3V

4647LBIN

∗

LBIN

ECL input (differen

-tial)

ECL level

Serial data inputs for loop-back test. These input pins are enabled when LBEN is set to high level.

VEEE

LBIN

∗

LBIN

VCCE

VEEG

VCCG

VCCE – 1.3V

48

EXCLK

ECL input

ECL level

External clock input. When ECLKSEL∗is set to low level, the clock input to this pin is used as the bit rate clock. This pin is biased to become low level when left open.

49

VCCP

Power

supply

3.3V

Positive power supply for internal PLL.

VEEGVEEE

EXCLK

V

CCE V

CCG

VCCE – 1.3V

50

REXT

External part connec

-tion pin

—

Connects the resistor which determines the VCO center frequency. Connect a 4.7kΩ resistor between this pin and VEEP1. (See Notes on Operation and Fig. 1.)

VCCP

VEEP2

REXT

—

51 VEEP1

Power

supply

0V

Negative power supply for internal PLL.

—

52 VEEP2

Power

supply

0V

Negative power supply for internal PLL.

—

Pin No.

Symbol Type

Typical pin I/O voltage

Equivalent circuit Description