Sony CXB1575AQ Datasheet
CXB1575AQ
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155Mbps Clock & Data Recovery with High Sensitivity Limiting Amplifier
Description
The CXB1575AQ achieves 3R optical-fiber communication receiver functions (Reshaping and Regenerating
and Retiming) on a single chip. This IC also equipped
with the signal interruption alarm output, which is
used to discriminate the existence of data input.
Features
• Auto-offset canceler circuit
• Signal interruption alarm output
• No reference clock required
• Single 3.3V power supply
Applications
• SONET/SDH: 155.52Mbps
• ATM: 155.52Mbps
40 pin QFP (Plastic)
Absolute Maximum Ratings
• Supply voltage VCC – VEE –0.3 to +5.0 V
• Storage temperature Tstg –65 to +150 °C
• Input voltage difference: | VD–VDN | Vdif 0 to 2.5 V
• TTL input voltage VinT –0.5 to 5.5 V
• Output current (Continuous) IO 0 to 50 mA
(Surge) 0 to 100 mA
Recommended Operating Conditions
• Supply voltage VCC – VEE 3.069 to 3.465 V
• Termination voltage (for RCK/RDATA) VCC – VT1 1.8 to 2.2 V
• Termination voltage (for SDE) VT2 VEE V
• Termination resistance (for RCK/RDATA) RT1 46 to 56 Ω
• Termination resistance (for SDE) RT2 460 to 560 Ω
• Operating temperature Ta –40 to +85 °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E97Y13-PS
Block Diagram and Pad Configuration
CXB1575AQ
REXT
LKDT
EEG
V
VCCG
EXCK
CKSEL
SQLCH
SDC
SDE
SDEN
31
32
33
34
35
36
37
38
39
40
30
VCO
P1
EE
V
29
P1
EE
V
charge
pump
1
0
28
Mux.
NC
Up
Down
P2
EE
V
27
phase/
frequency
detector
LPFB
26
D-FF
Reset
LPFA
25
D
CK
24
P
CC
V
CAP1B
23
peak
hold
22
CAP1
21
R1
EE
V
peak
hold
20
19
18
17
16
15
14
13
12
11
VEER2
DN
D
CCR
V
DOWN
HYS
V
EER3
CAP2
CAP3
NC
1
E1
CC
V
2
3
RDATA
RDATAN
5
4
G
E1
EE
EE
V
V
6
7
G
CC
V
E2
EE
V
8
RCKN
9
RCK
10
E2
CC
V
– 2 –
Pin Description
Pin No.
Symbol
Typical pin
voltage (V)
AC
DC
Equivalent circuit
CXB1575AQ
Description
1
2
3
4
5, 33
6, 34
7
8
VCCE1
RDATAN
RDATA
VEEE1
VEEG
VCCG
VEEE2
RCKN
3.3
0
0
3.3
0
1.6
to
2.4
1.6
to
2.4
1.6
to
2.4
VCCE1
2
3
EEE1
V
VCCE2
Positive supply for
RDATA/RDATAN output circuits.
Retimed data outputs.
Ground for RDATA/RDATAN
output circuits.
Ground for digital circuits.
Positive supply for digital circuits.
Ground for RCK/RCKN outputs
circuits.
10
11
12
13
Recovered clock outputs.
8
1.6
RCK
9
to
9
2.4
VEEE2
VCCE2
NC
CAP3
3.3
2
10p
12
13
VCCR
Positive supply for RCK/RCKN
output circuits.
No connect
Connect a peak hold capacitor
for signal detector.
Typically 470pF.
CAP2
2
5µA 5µA
VEER
– 3 –
Pin No.
Symbol
Typical pin
voltage (V)
AC
DC
Equivalent circuit
CXB1575AQ
Description
14
15
16
VEER3
HYS
DOWN
0
0.2
3
17 VCCR 3.3
18
D
16
Bias
Generator
VCCR
15
EER3
V
VCCR
V
EER3
Ground for signal detector.
Connect to VEER3 through an
external resistor to determine
signal detect hysteresis width
(∆P).
When connect to VEER3 directly;
∆P ≈ 6dB (Typ.)
When connected 8.2kΩ to VEER3;
∆P ≈ 3dB (Typ.)
Connect to VCCR through an
external resistor to decrease
signal detect level (SDL). When
open, SDL sets to 18mVp-p.
(single-ended)
Positive supply for signal
detector.
VCCR
19
22
23
20
21
24
DN
CAP1
CAP1B
2.2
2.2
VEER2 0
VEER1
VCCP
3.3
Serial data stream inputs.
18
19
22
23
Connect an external capacitor,
which determines low cut-off
EER2VEER1
V
frequency for DC feedback loop.
Typically 0.22µF.
Ground for post amplifier.
Ground for post amplifier.
0
Both VEER1 and VEER2 must be
grounded.
Positive supply for PLL circuits.
– 4 –
Pin No.
Symbol
Typical pin
voltage (V)
AC
DC
Equivalent circuit
CXB1575AQ
Description
VCCP
25
26
27
28
29, 30
31
LPFA
LPFB
VEEP2
NC
VEEP1
REXT
3.1
3.1
0
0
0.4
25
26
Bias
Generator
V
EEP1VEEP2
VCCP
31
Connect an external loop filter
capacitor.
Typically 0.68µF (155.52Mbps).
Ground for PLL circuits.
No connect
Ground for PLL circuits.
Both VEEP1 and VEEP2 must be
grounded.
Connect to VEEP1 through an
external resistor to determine
VCO frequency.
Typically 1.8kΩ.
32 LKDT
35
EXCK
1.3
0.2
to
3.1
35
VCCG
EEG
V
VCCG
EEG
V
V
EEP2
32
Lock detector (TTL).
Driven low, while synchronization
is lost.
External clock input (ECL).
For testing only.
Normally, left open.
– 5 –
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