Sony CXB1572Q Datasheet

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E96638-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

Description

The CXB1572Q achieves the 2R optical-fiber communication receiver functions (Reshaping and Regenerating) on a single chip. This IC is also equipped with the signal interruption alarm output function, which is used to discriminate the existence of data input.

Features

• Auto-offset canceler circuit

• Signal interruption alarm output

• 2-level switching function of identification maximum voltage amplitude for alarm block

• Single 3.3 V power supply

Applications

• FDDI : 125 Mb/s

• SONET/SDH : 155.52 Mb/s

• ESCON : 200 Mb/s

• Fiber channel : 265.625 Mb/s

• ATM : 155.52 Mb/s

Absolute Maximum Ratings

• Supply voltage VCC – VEE –0.3 to +7.0 V

• Storage temperature Tstg –65 to +150 °C

• Input voltage difference : I VD – VD I Vdif 0 to +2.5 V

• SW input voltage Vi VEE to VCC V

• Output current (Continuous) IO 0 to 50 mA

(Surge current) 0 to 100 mA

Recommended Operating Conditions

• Supply voltage VCC – VEE 3.0 to 3.6 V

• Termination voltage (for data/alarm) VCC – VT1 1.8 to 2.2 V

• Termination voltage (for alarm 2) VT2 VEE V

• Termination resistance (for data/alarm)RT1 46 to 56 Ω

• Termination resistance (for alarm 2) RT2 460 to 560 Ω

• Operating temperature Ta –40 to +85 °C

Structure

Bipolar silicon monolithic IC

Post amplifier for Optical Fiber Communication Receiver

32 pin QFP (Plastic)

CXB1572Q

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CXB1572Q

Block Diagram and Pin Configuration

Q

V

CC

DA

SD

Q

SD

V

CC

D

V

CC

DA

VCCA

UP

DOWN

CAP2

CAP3

NC

NC NC

V

CCA

V

CCD

V

EEA

V

EED

NC

CAP1

R2K

R3K

peak hold

Limiting Amplifier Block

peak hold

Alarm Block

29

26

32

30

31

28

27

20

25

23

22

21

18

19

8

2

1

6

7

5

16

14

12

11

10

9

13

15

R1

R2

R1

R2

4

3

∆V

R3

R4

24

CAP1

V

CC

P

V

EE

I

SW

V

CC

A

D

V

CC

A

Rp

17

NC

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CXB1572Q

Pin Description

60k

40k

V

REF

VEEA

V

CCA

4

31

30

VccA

V

EEA

SW

986

123.4

Vcs

3

2

1

5

32

VCCA

V

EEA

100

1.5k

10k

100p

200

3k

2k

5 6

11

10

9

8

Typical pin

Pin No. Symbol voltage (V) Equivalent circuit Description

DC AC

1

2

3

4

5

6

7

8

9

10

11

VCCP

VCCA

VEEI

SW

D

VCCA

CAP1

R2K

R3K

CAP1

0 V

–3.3 V

0 V

(OPEN)

or

–3.3 V

–1.3 V

0 V

–1.8 V

–0.9 V

to –1.7 V –0.9 V

to –1.7 V

Positive power supply for external power supply.

Generates the default voltage between UP and DOWN. The voltage (5.3 mV for input conversion) can be generated between UP and DOWN (Pins 30 and 31) as alarm setting level 1 by this pin to Open. The voltage (12 mV for input conversion) can be generated as alarm setting level 2 by connecting this pin to VEEA.

Switches the identification maximum voltage amplitude. High voltage when open; the identification maximum voltage amplitude becomes 50 mVp-p. Low voltage when connecting this pin to VEE; the amplitude becomes 20 mVp-p.

Limiting amplifier block input. Be sure to make this input with AC coupled.

Positive power supply for analog block.

Pins 8 and 11 connect a capacitor which determines the cut-off frequency for feedback block, and 2 kΩ is connected between Pins 8 and 9; 3 kΩ between Pins 10 and

11. A resistor which is to be inserted in parallel with a capacitor can be selected 5 ways by external wiring, and DC feedback gain can be varied due to compensate the input duty cycle distortion.

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CXB1572Q

Typical pin

Pin No. Symbol voltage (V) Equivalent circuit Description

DC AC

12 13 14 15 16 17

18

19

20

21

22

23 24

25 26 27

VEEA VCCA VEED VCCD

NC

Q

VCCDA

SD

VCCDA VCCD

NC

–3.3 V

0 V

–3.3 V

0 V

0 V 0 V

–0.9 V

to

–1.7 V

–0.9 V

to

–1.7 V

–0.9 V

to

–1.7 V

–0.9 V

to

–1.7 V

Negative power supply for analog block. Positive power supply for analog block. Negative power supply for digital block. Positive power supply for digital block.

No connected.

Data signal output. Terminate this pin in 50 Ω at VTT = –2 V.

Positive power supply for output buffer.

Alarm signal output. Terminate this pin in 50 Ω at VTT = –2 V.

Positive power supply for digital block. Positive power supply for digital block.

No connected.

CCDA

V

19

18

VEED

CCDA

V

VEED

21 22

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CXB1572Q

Typical pin

Pin No. Symbol voltage (V) Equivalent circuit Description

DC AC

28

29

30

31

32

CAP3

CAP2

DOWN

UP

VCCA

–1.8 V

–1090 mV

(for

VEEI

= –3.3 V)

–1020 mV

(for

VEEI

= –3.3 V)

0 V

Connects a peak hold circuit capacitor for alarm block. 470 pF should be connected to VCCA each.

CAP2 pin → Peak hold capacitor connection for alarm level setting block. CAP3 pin → Peak hold capacitor connection for limiting amplifier signal.

Connects a resistor for alarm level setting. Default voltage can be generated without an external resistor. (Please refer to pin description of pin No. 3.)

Positive power supply for analog block.

31

30

29

80

10p

200 200

28

80

10p

VCCA

5µA

V

EEA

VccA

986

123.4

Vcs

SW

EEA

V

3