Sony CXA3621GE Datasheet

CXA3621GE

Fingerprint Sensor

Description

The CXA3621GE is an electrostatic capacitance

method fingerprint sensor.

This monolithic IC integrates the sensor block, sense amplifier (3-bit gain adjustment), sample-andhold, output amplifier and output buffer needed to acquire fingerprint images, as well as the timing generator for determining the operation of these functions onto a single chip.

Features

• Electrostatic capacitance type sensor (charge transfer method)

• Number of pixels: 192 × 128

• 317 DPI

• Low power consumption (50mW or less) ∗ When P/S: 18µW or less

• Single 3.0V power supply

• Sensor gain control: 3 bits

• S/N ratio improved by on-chip sensor block parasitic capacitance cancel function

30 pin LLGA (Plastic)

Applications

Fingerprint verification units

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage AVDD, DVDD VSS – 0.5 to +7.0 V

• Input voltage VI VSS – 0.5 to VDD + 0.5 V

• Output voltage VO VSS – 0.5 to VDD + 0.5 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –25 to +125 °C

• Allowable power dissipation PD 1100 mW

Recommended Operating Conditions

• Supply voltage AVDD, DVDD 2.7 to 3.6 V

• Ambient operating temperature Ta 0 to +50 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E02127-PS

Block Diagram

CXA3621GE

C_SP

UC

XSP (D/I)

CLK (D/I)

ADCLK (D/O)

Timing

Generator

S_CNT

Load

R_SP

UC UC

SENSOR

UC UC UC UC

...........

192

Sense AMP (×192)

192

S/H & SW (×192)

192

Row Shift Register

...........

UC UC

.........

128

........

C_CLK

Column Shift Register

3bit

DAC

Output

Buffer

3

DI (D/I)

AOUT (A/O)

R_CLK

VOS (Bias)

– 2 –

Detailed Block Diagram

CXA3621GE

C_SP

...........

192 (Dummy)

...........

UC UC UC UC UCUC

SVss[1:128]

128

DUMMY SENSOR

SVss[1:128]

........

UC

C_CLK

C_LOG

SR[1:128]

.........

128

SENSOR (UC)

128

C_COUT

UC

SVss

UC

SR

................

192

................

UC

C[1:192]

UC UC UC UC UC

IN_N[1:192]

192

VCS_O

BIAS_O

DUMMY

SAMP

SAMP (192)

S[4:5]

S[3:5]N

DD

SV

VM

PAMP_D

OUT

VCSN

OAMP

SD1

OUT

SC[1:192] SC[1:192]N

192 192

VOS

PAMP_S

S[6:7]

S[6:7]N

R_LOG

CLK

DCLK

C_CO

XSP

DC_VOS

BUF

LAND No.

7C 7D

7E

7F 6B

6C

6D

6E

6F

5B

5C 5D

5E

5F

4F

4E

4D 4C

4B

3F

28 27

26

25 24

23

22

21

20

19

18 17

16

15

14

13

12 11

10

9

Pin Symbol SGND (P/S) AV

DD (P/S)

AVss (P/S)

AOUT (A/O) VOS (Bias)

VCS_O (Bias)

NC

DD (P/S)

DV

SS (P/S)

CSRO (D/O)

RSRO (D/O) C_CK (D/O)

ADCLK (D/O)

SVDS (D/O)

PS (D/I)

CLK (D/I)

XSP (D/I) DI2 (D/I)

DI1 (D/I)

DI0 (D/I)

DSR DSVss

C_SP

TG

S[4:5]

C_CLK

S[3:5]N

DCLK

SR

SD1

SD

DI[0:1]

SVDS

DC_VM

– 3 –

BIAS_SA

8

TEST3 (D/I)

TEST2 (D/I)

7

TEST1 (D/I)

6

5

VCS_S (Bias)

4

VM (Bias)

3

AV

2

SGND (P/S)

1

SS (P/S)

DD (P/S)

3E

3D

3C

3B

2F

2E

2D

2C

Pin Description

CXA3621GE

Serial

No.

—

1 2

3 4 5

6 7 8

9 10 11

12

Land No.

2B 2C 2D

2E

2F

3B 3C 3D

3E

3F

4B 4C

4D

Symbol SUB SGND AVDD

AVSS VM VCS_S

TEST1 TEST2 TEST3 DI0 DI1 DI2

XSP

I/O Power Power Power

Power

A/O A/O

D/I

Description

Substrate electrode (chip rear surface electrode) 3.0V (VDD). Sensor lightning conductor electrode. (Connect to the GND which

is the other system of operating power supply.) Analog power supply 3.0V. Analog GND. Sense amplifier reference voltage monitor 1.5V (1/2 VDD).

(Do not connect.) Sense amplifier current source bias monitor. (Do not connect.) Test mode selection. (Connect to GND.) Test mode selection. (Connect to GND.) Test mode selection. (Connect to GND.) Gain setting input (LSB). Gain setting input. Gain setting input (MSB). Sense start pulse (negative pulse).

The column and row shift registers and the timing generator are

cleared by this signal. 13 14 15 16 17 18 19 20 21 22 23

24 25

26 27

28

4E 4F 5F

5E 5D 5C

5B

6F

6E 6D 6C

6B

7F

7E 7D

7C

CLK PS SVDS ADCLK C_CK RSRO CSRO DVSS DVDD NC VCS_O

VOS AOUT

AVSS AVDD

SGND

D/I

D/I D/O D/O D/O D/O D/O

Power Power

—

A/O A/O A/O

Power Power

Power

Main clock 2MHz. Power saving mode setting. (Low: Operation; High: Standby) Integrating pulse monitor. (Do not connect.) Delay clock. (Do not connect.) Column shift register clock. (Do not connect.) Column shift register final output. (Do not connect.) Row shift register final output. (Do not connect.) Digital GND. Digital power supply 3.0V. No connection. (Do not connect.) Output amplifier current source bias monitor. (Do not connect.) Output amplifier reference voltage monitor 1.09V (4/11VDD).

(Do not connect.) Sensor output. Analog GND. Analog power supply 3.0V. Sensor lightning conductor electrode. (Connect to the GND which

is the other system of operating power supply.)

– 4 –

CXA3621GE

Electrical Characteristics

DC Characteristics (Vss = 0V, Ta = 25°C)

Item Analog supply voltage Digital supply voltage Current consumption

(for operation) Current consumption

(for standby) Input voltage (High) Input voltage (Low) Output voltage (High) Output voltage (Low)

Input leak current Output voltage

Output voltage

Symbol

AVDD DVDD

IDD1

IDD2 VIH

VIL VOH VOL

IL VM

VOS

VDD = 3V, P/S = L

VDD = 3V, P/S = H, CLK = L Digital (CMOS) input cell

Digital (CMOS) input cell VDD = 3V, IOH = –800µA VDD = 3V, IOL = 2.4mA VDD = 3V,

digital (CMOS) input cell [3V/0V] VDD = 3V VDD = 3V

Conditions

Min.

2.7

5.0

0.7VDD Vss

2.6 0

–1

1.4

1.00

Typ.

3.0

8.5

1.5

1.09

Max.

3.6

13.0

5

VDD

0.3VDD

3.0

0.4 1

1.6

1.20

Unit

V V

mA

µA

V V V V

µA

V V

AC Characteristics (VDD = 3.0V, VSS = 0V, Ta = 25°C)

Item

Clock input period

Symbol

CLK

Conditions

Min.

400

Typ. Max.

Unit

ns

Number of sensor defects

1

Output voltage (Air_Level) Output voltage (Water_Level)

∗1

Output voltage Air Level means the output level in the condition where nothing is placed against the sensor

AOUT AOUT

∗

2

∗

0 850 950

1090 1200

3 1350 1450

surface (in other words, in air). This rating value is obtained by measuring 32 points within one line of the sensor output and then taking the average. The gain setting for this measurement is (011).

∗2

Output voltage Water Level specifies the degree to which the output level changes from the Air Level when a drop of water is placed on the sensor surface. However, it is unrealistic to place a drop of water on each sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level when a drop of water is placed on the surface) are built into the sensor chip, and the average of these output values is calculated. The difference from the Air Level noted above becomes the Water Level. The gain setting for this measurement is (011).

Defects

mV mV

– 5 –