Sony CXA3562R Datasheet

LCD Driver

Description

The CXA3562R is a driver IC developed for use with Sony polycrystalline silicon TFT LCD panels. It supports digital 2-parallel and single input, and the input data is analog demultiplex ed into 12 phases and output. The CXA3562R can directly drive an LCD panel, and the VCOM setting circuit and precharge pulse waveform generator are also on-chip.

Features

• Supports 10-bit 2-parallel and single input

• Supports signals up to UXGA

(1/2 clock when using UXGA signals)

• Low output deviation by on-chip output offset cancel circuit

• Supports both line inversion and dot and line inversion

• On-chip timing generator with ECL

• VCOM voltage generation circuit

• Precharge pulse waveform generation circuit

CXA3562R

100 pin LQFP (Plastic)

Applications

LCD projectors and other video equipment

Absolute Maximum Ratings (VSS = 0V)

• Supply voltage VCC 16 V

VDD 5.5 V

• Operating temperature Topr –20 to +70 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation PD 2300 mW

Recommended Operating Conditions

• Supply voltage VCC 15.0 to 15.5 V

VDD 4.75 to 5.25 V

• Operating temperature Topr –20 to +70 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E01115-PS

Block Diagram and Pin Configuration

TEST

SL_INV

SL_SCN

SL_DAT

DIRC

F/H_CNT

VREF_O

VREF_I

69

71727374

70

Vref Gen.

D/A

TG

D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 D_A3 D_A2 D_A1 D_A0

GND GND GND GND

GND D_B9 D_B8 D_B7 D_B6 D_B5 D_B4 D_B3 D_B2 D_B1 D_B0

75

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

100

VDDPS

GND

65

666768

S/H S/H

S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H S/H

FRP_OD

FRP_EV

CAL_PLS

GND

PRG

SID_LV

PRG_LV

SID_OUT

SID_OUTX

5758

596061626364

Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel

Line Inv. Offset Cancel

Line Inv. Offset Cancel Line Inv. Offset Cancel Line Inv. Offset Cancel

Line Inv. Offset Cancel

Offset Cancel Level Gen.

VCCVCOM_OFST

VCOM_OUTNCSH_OUT1

51

5253545556

VCOM Gen.SID Gen.

CXA3562R

50

PV

49

SH_OUT2

48

NC

47

SH_OUT3

46

NC

45

SH_OUT4

44

NC

43

SH_OUT5 NC

42

SH_OUT6

41 40

GND

39

GND

38

PGND

37

GND

36

GND

35

SH_OUT7

34

NC

33

SH_OUT8

32

NC

31

SH_OUT9

30

NC

29

SH_OUT10

28

NC

27

SH_OUT11

26

PV

CC

1 2 3 4 5 6

MCLK

FRP

MCLKX

SHST

TEST

7

8 9 10 11 121314 15 16 17 18 19 20 21 22 232425

GND

POSCTR0

POSCTR1

POSCTR2

SHTEST

POSCTR3

GND

SIG.C

SIG_OFST

CAL_OL

CAL_OH

GND

CAL_IH

– 2 –

NC

CAL_IL

DCFBOFF

SH_OUT12

Pin Description

CXA3562R

Pin No.

2 3

Symbol I/O

MCLK MCLKX

Standard voltage level

PECL differential (amplitude

0.4V or more

I

between VDD to 2V) or TTL input

High: ≥2.0V

IFRP4

Low: ≤0.8V

High: ≥2.0V

ISHST5

Low: ≤0.8V

VDD

GND

Equivalent circuit Description

50k

140k8k

Dot clock input. PECL differential input or TTL input. For TTL input, input to MCLK and connect MCLKX to GND through a capacitor.

LCD panel AC drive inversion timing input. High: inverted

140k

2 3

1k 1k

60k 60k100µ

V

DD

192

4

Low: non-inverted See the Timing Chart.

GND

V

DD

50k

192

5

Internal sample-and-hold timing circuit reset pulse input. This pin is also used as the offset cancel level insertion timing input. A reset is applied to the internal

GND

timing generator at the falling edge.

6 7 8 9

POSCTR0 POSCTR1 POSCTR2 POSCTR3

High: ≥2.0V

I

Low: ≤0.8V

1 to 5.0V

ISIG.C16

0 to 5.0VISIG_OFST17

GND

V

DD

GND

V

GND

VDD

6

16

DD

17

50k

192

Output phase adjustment. The output phase is adjusted in MCLK period units when SL_DAT (Pin 72) is high, and in

987

1/2 MCLK period units when SL_DAT is low.

V

CC

20µ

30k

Signal center voltage (inversion folded voltage) adjustment input. The SH_OUT output center voltage can be adjusted in the range from 7.0 to 8.0V.

V

CC

10µ

30k

Output signal offset adjustment from signal center voltage. The SH_OUT output 100% white level (at 3FF input) voltage can be adjusted in the range from 0 to 1V from the center voltage.

– 3 –

CXA3562R

No.

18 19

21 22

Symbol I/O

CAL_OL CAL_OH

CAL_IH CAL_IL

Standard voltage level

3.0 to 6.0V

O

9.0 to 12.0V

O

3.0 to 6.0V

IDCFBOFF24

GND

Equivalent circuit Description

V

CC

40µ 1k

Level output for canceling the

145

18 19

GND

VCC

20k

offset between channels. Connect directly to CAL_IL and CAL_IH, respectively.

Level input for canceling the offset between channels. Connect directly to CAL_OL and CAL_OH, respectively. When using two CXA3562R, connect the CAL_IL and CAL_IH of both chips to the CAL_OL and CAL_OH of only one CXA3562R.

Offset cancel function off. Normally connect to GND to use with the offset cancel function on.

GND

VDD

24

21 22

145

30k

24k

20µ

24k

High (offset cancel function off) when open.

GND

25, 27,

29, 31,

33, 35,

41, 43,

45, 47,

49, 51

53

54

SH_OUT12

to

SH_OUT1

VCOM_OUT

VCOM_OFST

1.5 to 13.5V

O

5.0 to 8.0V

O

0 to 5.0VI

PVCC

300

GND

VCC

GND

VDD VCC

GND

54

80µ

100k

500

2k

100

145

25 29 33 41 45 49

80µ

27 31

Demultiplexed output of AC

35

inverse driven video signals.

43

Can be connected directly to

47

the LCD panel.

51

LCD panel common voltage output. Can be set in the range from

53

the SH_OUT center potential Vsig.c to Vsig.c – 2V by VCOM_OFST.

LCD panel common voltage adjustment. VCOM_OUT can be set in the range from the SH_OUT center potential Vsig.c to Vsig.c – 2V by inputting 0 to 5V.

– 4 –

CXA3562R

Pin No.

56 57

58 59

Symbol I/O

SID_OUTX SID_OUT

PRG_LV SID_LV

Standard voltage level

1.5 to 13.5V

O

1.0 to 5.0V

I

High: ≥2.0V

IPRG60

Low: ≤0.8V

Equivalent circuit Description

VCC

100k

0.2p

100k

V

DD

GND

0.2p

50k 50k

60

GND

VDD VCC

58 59

GND

100k 10k

145

29µ

V

50µ

56 57

CC

Precharge waveform output. SID_OUTX outputs the inverse of SID_OUT based on the output center voltage. These pins cannot directly drive the LCD panel, so input to the LCD panel with an external a buffer.

Precharge level setting. Adjusts the SID_OUT and SID_OUTX output potential. PRG_LV is reflected when the PRG input pin (Pin 60) is high, and SID_LV is reflected when PRG is low.

Timing pulse input for switching the Pins 56 and 57 output levels. (See PRG_LV (Pin 58) and SID_LV (Pin 59).)

IVREF_I68

OVREF_O69

High: ≥2.0V Low: ≤0.8V

IF/H_CNT70

Open: Low

3.2V

V

DD

GND

68

VDD

GND

VDD

GND

20µ

70

70µ 10µ

1k

280µ

2k

20k

12.4k

192

200k

33.3k

50k

69

Internal D/A converter reference voltage input. Normally connect directly to VREF_O.

Reference voltage output. Normally connect directly to VREF_I, and connect to GND through a 0.5 to 1.0µF capacitor.

SH_OUT output timing selection. High: SH_OUT1 to SH_OUT6 and SH_OUT7 to SH_OUT12 are output at different timing. Low: SH_OUT1 to SH_OUT12 are output at the same timing.

– 5 –

CXA3562R

Pin No.

38

26, 50

55 67

11 to 15,

20, 36,

37, 39,

40,

61 to 65,

86 to 90

23, 28,

30, 32,

34, 42,

44, 46,

48, 52

Symbol I/O

PGND PVCC VCC VDD

GND

NC

Standard voltage level

IPS66

15.5V

5V

GND

5V

GND

Equivalent circuit Description

V

DD

Power saving. Power saving mode when set to low lev el. Low (power saving mode) when open. Normally connect to VDD.

66

GND

70k

180k

30µ

Power GND. Po wer VCC. 15V power supply. 5V power supply.

GND.

OTEST1, 75

ISHTEST10

High: ≥2.0V

IDIRC71

Low: ≤0.8V

1.7 to 3.2V

2.5V

V

DD

10

GND

VDD

GND

1µ

V

250k

DD

71

192

2k

192

20µ

20k 20k

20k

10µ

192

50k

75

1

DAC output monitor test. Normally connect to VDD.

20k

Test. Leave open.

10µ

Scan direction setting. High: output as a time series in ascending order of output pin symbol (in order from SH_OUT1 to SH_OUT12) Low: output in descending order

– 6 –

CXA3562R

No.

Symbol I/O

ISL_DAT72

ISL_SCN73

ISL_INV74

Standard voltage level

High: ≥2.0V Low: ≤0.8V Open: Low

High: ≥2.0V Low: ≤0.8V Open: High

High: ≥2.0V Low: ≤0.8V Open: Low

Equivalent circuit Description

V

DD

GND

V

DD

73

72

192

200k

50k

Digital input mode switch setting. High: single input from the A port Low: parallel input from both the A and B ports

A and B port input switching interlocked/non-interlocked setting relative to scan direction setting during parallel input. High: A and B port switching interlocked to DIRC

GND

V

GND

DD

50k

192

74

200k

Low: fixed regardless of DIRC

SH_OUT odd-numbered and even-numbered output polarity inverted/non-inverted setting. High: odd-numbered and evennumbered outputs inverted Low: non-inverted

76

to

85

91

to

100

D_A9 to D_A0

D_B9 to D_B0

High: ≥2.0V

I

Low: ≤0.8V

High: ≥2.0V

I

Low: ≤0.8V

91

VDD

to

GND

VDD

to

GND

8576

100

192

50k

A port digital data input.

50k

B port digital data input.

– 7 –

Electrical Characteristics Measurement Circuit

CXA3562R

D_A9 D_A8 D_A7 D_A6 D_A5 D_A4 D_A3 D_A2 D_A1 D_A0

GND GND GND GND

GND D_B9 D_B8 D_B7 D_B6 D_B5 D_B4 D_B3 D_B2 D_B1 D_B0

1µ

DD

V

TEST

SL_INV

SL_SCN

SL_DAT

DIRC

F/H_CNT

69

71727374

FRP

70

SHST

POSCTR0

75

76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

TEST

MCLK

MCLKX

DD

V

VREF_O

VREF_I

POSCTR1

POSCTR2

VDD

A

VDDPS

POSCTR3

666768

65

SHTEST

GND

PRG

596061626364

SIG.C

47p 47p

SID_LV

PRG_LV

5758

CAL_OL

SIG_OFST

SID_OUT

SID_OUTX

GND

CAL_OH

A

VCCVCOM_OFST

CAL_IH

VCC

VCOM_OUTNCSH_OUT1

51

5253545556

NC

CAL_IL

DCFBOFF

360p

50

PVCC

49

SH_OUT2

48

NC

47

SH_OUT3

46

NC

45

SH_OUT4

44

NC

43

SH_OUT5

42

NC

41

SH_OUT6

40

GND

39

GND

38

PGND

37

GND

36

GND

35

SH_OUT7

34

NC

33

SH_OUT8

32

NC

31

SH_OUT9

30

NC

29

SH_OUT10

28

NC

27

SH_OUT11

26

PV

SH_OUT12

360p

CC

360p

A

VCC

– 8 –

CC

15.5V

DD

V

5V

V