Sony CXA3512R Datasheet

Description

The CXA3512R is a driver IC for the analog inputs of SVGA or higher Sony polycrystalline silicon TFT LCD panels. It has a line invert amplifier and analog demultiplexers, as well as the timing generator and output buffers required for these. The CXA3512R can directly drive an LCD panel. The VCOM setting circuit and precharge pulse waveform generator are also on-chip.

Features

• High-speed signal processing supports XGA high refresh signal

• Overall wide band response

• Low output deviation by on-chip output offset cancel circuit

• Invert amplifier with small phase delay difference between inverted signal and non-inverted signal

• On-chip timing generator with ECL

• Dot clock phase adjustment function

• VCOM voltage generation circuit

• Precharge pulse waveform generation circuit

Absolute Maximum Ratings

• Supply voltage Vcc 16 V

VDD 5.5 V

• Operating temperature –20 to +70 °C

• Storage temperature –65 to +150 °C

• Allowable power dissipation PD 2300 mW (single layered board mounted)

Recommended Operating Conditions

• Supply voltage Vcc 15.0 to 15.5 V

VDD 4.75 to 5.25 V

• Ambient temperature –20 to +70 °C

LCD Driver

– 1 –

E99803A9Z-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA3512R

64 pin LQFP (Plastic)

For the availability of this product, please contact the sales office.

– 2 –

CXA3512R

Block Diagram

S/H S/H S/H

VCOM

OFFSET CANCEL

BUFFER

S/H S/H S/H

OFFSET CANCEL

BUFFER

S/H S/H S/H

OFFSET CANCEL

BUFFER

S/H S/H S/H

OFFSET CANCEL

BUFFER

S/H S/H S/H

OFFSET CANCEL

BUFFER

S/H S/H S/H

OFFSET CANCEL

BUFFER

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33343536373839404142434445464748

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

CAL_R CAL_O

CAL_I

V

DD

DGND

MCLK

MCLKX

GND

GND DLYCTR CLKOUT

CLKOUTX

NC

CLKIN

CLKINX

F/H_CNT

PRGPOL

PRG

NC

POSCTR1

POSCTR2

NC

GND

STATUS

ENB

D1OR2

DIRCTR

NC

DCFBSW

NC

VIDEO_I

VIDEO_R

VIDEO_O

SH_IN

NC

VCCGND

GND

SID_IN

SID_R

SID_O

FRP

SIGCNT

VCOMOFF

VCOMOUT

SHOUT1 NC SHOUT2 NC SHOUT3 NC PV

CC

GND GND PGND NC SHOUT4 NC SHOUT5 NC SHOUT6

D

CLOCK DELAY

S/H pulses

TIMING GENERATOR

offset

cancel mode timing

SID

INVERT AMP

CALIBRATION AMP

– 3 –

CXA3512R

Pin Description

No.

Symbol I/O

Standard voltage level

Equivalent circuit

Description

1 PRGPOL

I

High: ≥ 2.5V Low: ≤ 0.8V OPEN High

Selects the latch polarity of the PRG pulse used as the time reference. High: PRG pulse is latched at the falling edge of CLKIN. Low: PRG pulse is latched at the rising edge of CLKIN. Select the polarity with sufficient timing margin after adjusting the analog video and CLKIN phases with DLYCTR.

1

VDD

40k

100k

20k

12µ

20k

VDD

VDD VDD

2

PRG I

High: ≥ 2.5V Low: ≤ 0.8V

PRG pulse input. See the Timing Chart.

2

VDD

145

50k

150k

VDD

50k

5 6

POSCTR1 POSCTR2

I

See Table A-1.

Output phase adjustment. Each pin has 4 setting values, for a total of 16 settings. (Adjustment in 1 dot clock units in XGA mode, 1/2 dot clock units in SVGA mode, and 1 dot clock units in SXGA mode.) See Tables A-1, A-2 and A-3.

5 6

VDD

60k

2k

VDD

10 STATUS

I

High: ≥ 2.5V Low: ≤ 0.8V OPEN High

Used in XGA and UXGA modes (when using 2 ICs for a gammacorrected IC). During forward scan, high: 2nd device, low: 1st device During reverse scan, high: 1st device, low: 2nd device See Table B.

10

VDD

40k

100k

20k

12µ

20k

VDD

VDD VDD

11

ENB

I

High: ≥ 2.5V Low: ≤ 0.8V

ENB pulse input. See the Timing Chart.

11

VDD

145

50k

150k

VDD

50k

13 D1OR2 I

High: ≥ 2.5V Low: ≤ 0.8V OPEN High

CLKOUT pin frequency selection. High: same frequency as MCLK Low: double the MCLK frequency

13

VDD

40k

100k

20k

12µ

20k

VDD

VDD VDD

– 4 –

CXA3512R

14 DIRCTR

I

High: ≥ 2.5V Low: ≤ 0.8V OPEN High

Scan direction setting. Low: output as a time series in descending order (reverse scan) of output pin symbol (in order from SHOUT6 to SHOUT1) High: output in ascending order (forward scan)

14

VDD

40k

100k

20k

12µ

20k

VDD

VDD VDD

16 DCFBSW

I

OPEN High

Offset cancel circuit on/off switch. High: cancel circuit on Use this pin at on (open).

16

VDD

40k

100k

10µ

VDD

40k

17 19 21 28 30 32

SHOUT6 SHOUT5 SHOUT4 SHOUT3 SHOUT2 SHOUT1

O

1.5 to 13.5V

Demultiplexer outputs. Can be connected directly to the LCD input pins.

30 32

28 19 21

17

VCC

300

33 VCOMOUT

O

3 to 7V

LCD common voltage of panel output. Can be set to VSIGCNT to (VSIGCNT – 3V) by the Pin 34 input.

70µ

VCC

33

VCC

145 60k

500

VCC

500

34 VCOMOFF

I

0 to 10V

VCOMOUT (Pin 33) voltage setting. VCOMOUT is the same potential as SIGCNT for input of 0V, and approximately 3V lower than that for input of 10V.

34

VCC

2k

100k

60µ

VCC

35

SIGCNT

I

7V

Signal center voltage (inversion folded voltage) input. Normally, set to 7V.

35

VCC

2k

20µ

No.

Symbol I/O

Standard voltage level

Equivalent circuit

Description

– 5 –

CXA3512R

36 FRP

I

High: ≥ 2.5V Low: ≤ 0.8V

Invert pulse input. High: inverse Low: non-inverse See the Timing Chart.

36

VDD VDD

10k

100k

50µ

VDD

37 SID_O

O

2 to 12V

SID block output. Provide an external buffer for precharge.

37

VCC

145

78k

0.2p

VCC

78k

0.2p

38 SID_R

I

3.3V

Precharge signal invert offset adjustment. When using the CXA2111R SID, connect to the V33 output of the CXA2111R.

38

VCC

30k

VCC

10µ

39 SID_IN

I

2.3 to 3.3V

Precharge waveform input. Can be connected directly to the CXA2111R SID output. Connect to 5V when not using the SID block.

39

VCC

145

VCC

40µ

44 SH_IN

I

2 to 10V

Analog demultiplexer input. Connect to the VIDEO_O (Pin 45) output. Do not input 2V or less.

44

VCC

200

550µ

200

45 VIDEO_O

O

2 to 10V

Invert amplifier output. Connect directly to Pin 44. When using two CXA3512R in parallel in XGA or UXGA mode, use the invert amplifier of only one IC, and connect the output to Pin 44 of both ICs.

600µ

45

VCC

VCC VCC

VCC

600µ

Pin No.

Symbol I/O

Standard voltage level

Equivalent circuit

Description

– 6 –

CXA3512R

46 VIDEO_R

I

3.3V

Input the 100% white level DC of the signal input to VIDEO_I. When using the CXA2111R, connect to the V33 output of the CXA2111R. When using bipolar DAC output for VIDEO_I, connect to the DAC supply voltage.

46

VCC

30k

VCC

10µ

47 VIDEO_I

I

2 to 3.3V

Video input. Connect a gamma-corrected

1.5Vp-p analog video output. Can be connected directly to the CXA2111R video output. Connect to 5V when not using the invert amplifier.

47

VCC

145

VCC

420µ

49 CAL_R

I

2.7V

Calibration level input for offset cancel. Input the DC level during noninverse with the most highly visible gradation. Normally, approximately

2.5 to 3V.

49

VCC

145

VCC

50µ

50 CAL_O

O

3 to 11V

Calibration amplifier output. Connect directly to Pin 51. When using two CXA3512R in parallel in XGA or UXGA mode, use the calibration amplifier of only one IC, and connect the output to Pin 51 of both ICs.

50

VCC

145

700

100µ

VCC

51

CAL_I

I

3 to 11V

Calibration level input for offset cancel. Connect to CAL_O.

51

VCC

30k

54 55

MCLK MCLKX

I

PECL differential (amplitude

0.4V or more between VDD and 2V) or TTL input

Dot clock inputs. PECL differential input or TTL input. For TTL input, input to MCLK and connect MCLKX to GND via a capacitor. Always input the dot clock or equivalent signal to these pins even when not using CLKOUT. (Otherwise, noise may result.)

54 55

VDD

1k

140k

100µ

VDD

60k

Pin No.

Symbol I/O

Standard voltage level

Equivalent circuit

Description

– 7 –

CXA3512R

58 DLYCTR

I

3 to 5V

Dot clock phase adjustment. The CLKOUT phase relative to MCLK can be changed by the voltage of this pin. Connection to the CXA2111R DLY_CNT output allows digital control using the I2C register of the CXA2111R.

58

VDD

10k

25µ

VDD

5960CLKOUT

CLKOUTX

O

VDD – 0.3V to VDD

Phase-adjusted dot clock outputs.

59 60

VDD

150

VDD

1m1m

6263CLKIN

CLKINX

I

VDD – 0.3V to VDD

Dot clock inputs for timing generation. Connect the CLKOUT (CLKOUTX) pin. When not using the CLK phase adjustment function, the dot clock can also be input directly to these pins by PECL differential input.

62 63

VDD

145

2k

100µ

2k

VDD VDD

64 F/H_CNT

I

High: ≥ 2.5V Low: ≤ 0.8V OPEN High

SHOUT output timing selection. High: SHOUT 1 to 3 and SHOUT 4 to 6 are output at different timing. Low: SHOUT 1 to 6 are output at the same timing.

64

VDD

40k

20k

12µ

20k

VDD

100k

VDD VDD

23 26 42

52 53

PGND PVCC VCC

VDD DGND

GND

15.5V

15.5V 5V GND

Power GND. Power VCC.

Connect directly to VCC. 15V power supply. 5V power supply. Digital GND.

8, 9, 24, 25, 40, 41, 56, 57

GND

Analog GND.

3, 4, 7, 12, 15, 18, 20, 22, 27, 29, 31, 43, 48, 61

NC

No connection. Not connected to anything.

Pin No.

Symbol I/O

Standard voltage level

Equivalent circuit

Description

– 8 –

CXA3512R

Electrical Characteristics (See Electrical Characteristics Measurement Circuit)

(VDD = 5V, VCC = 15.5V, VSIGCEN = 7V, Ta = 25 ± 3°C)

No. Item Symbol

Measurement contents

Min. Typ.

Max. Unit

1

2

3

4

5

6

7

8

9

10

11

12

VDD current consumption

VCC current consumption

Input – output gain Invert amplifier

gain

Invert amplifier slew rate

Invert amplifier output band width

Output delay deviation for inverse/noninverse

SID output gain

SID block output slew rate

VCOM adjustable range

First stage SH_OUT slew rate

SH_OUT slew rate

IDD

ICC

ASHOUT

AINV

SRINV

BWINV

TDIFF

ASID

SRSID

VCOM

SRSH1

SROUT

IDD = IVDD

ICC = IVCC1 + IVCC2

ASHOUT = VSHOUT (AC)/VIN

AINV = VINV (AC)/VIN Input a square wave from VIN

so that the VINV output amplitude is 3.0Vp-p. Measure the slew rate at 10 to 90% of output waveform rise or fall. (for inverse or noninverse)

Input 2.5V DC, 100mVp-p AC from Pin 47 (VIDEO_IN) and measure VINV. The frequency that is –3dB to 100kHz. (for inverse or non-inverse)

Invert amplifier delay time difference for inverse and noninverse.

ASID = VSID (AC)/VSID_IN Input an invert pulse to Pin 44

(FRP), load capacitance C7 = 47pF, and apply DC input voltage to VSID_IN so that VSID is 2.5V/11.5V. Measure the slew rate at 10 to 90% of output waveform rise or fall.

VCOM output voltage when Pin 34 (VCOMOFF) is varied from 0 to 10V.

First stage sample-and-hold slew rate on Block Diagram.

Input a square wave from VIN so that the VOUT1 to VOUT6 output amplitude is 3.5Vp-p. Measure the slew rate at 10 to 90% of output waveform rise or fall. (load 270pF, for inverse or non-inverse)

20

30

—

30

Vsig – 2

—

28

45

3

2

700

90

2

4

50

—

700

150

42

65

—

4

4.4

—

Vsig

—

mA

times

V/µs

MHz

ns

times

V/µs

V

V/µs

Measurement points

IVDD IVCC1

IVCC2 VSHOUT

VIN VINV

VIN

VINV

VSID VSID_IN

VSID

VCOM

—

VOUT1 to VOUT6