Sony CXA3271GE Datasheet
Fingerprint Sensor
Description
The CXA3271GE is an electrostatic capacitance
method fingerprint sensor.
This monolithic IC integrates the sensor block, sense
amplifier (3-bit gain adjustment), sample-and-hold,
output amplifier and output buffer needed to acquire
fingerprint images, as well as the timing generator for
determining the operation of these functions onto a
single chip.
Features
• Electrostatic capacitance type sensor (charge transfer method)
• Number of pixels: 192 × 128
• 317 DPI
• Low power consumption (50mW or less)
• Single 3.3V power supply
• Sensor gain control: 3 bits
• S/N ratio improved by on-chip sensor block parasitic capacitance cancel function
Applications
Fingerprint verification units
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
• Supply voltage VDD VSS – 0.5 to +7.0 V
• Input voltage VI VSS – 0.5 to VDD + 0.5 V
• Output voltage VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –25 to +125 °C
• Allowable power dissipation PD 970 mW
Operating Conditions
• Supply voltage 3.15 to 3.45 V
• Recommended operating temperature 0 to +50 °C
– 1 –
E00235-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXA3271GE
30 pin LLGA
– 2 –
CXA3271GE
Block Diagram
XSP (D/I)
CLK (D/I)
ADCLK (D/O)
UC UC
S_CNT
C_CLK
C_SP
Load
R_SP
R_CLK
UC UC UC UC
UC
UC
UC
UC
UC
UC UC
DI (D/I)
AOUT (A/O)
VOS (Bias)
3
3bit
DAC
Output
Buffer
192
128
Sense AMP (×192)
SENSOR
S/H & SW (×192)
Row Shift Register
Timing
Generator
Column Shift Register
........
128
.........
...........
192
...........
192
192
– 3 –
CXA3271GE
Detailed Block Diagram
UC UC
C_CLK
UC UC UC
UC
UC
UC
UC
UC
UC
UC UC UC UC UCUC
192
55
D (1 to 192)
8
6
2
3
128
SENSOR (UC)
TG
XSP
MODEHDC_CLK
C_CK
R_LOG
DCLK
VCS_O
S (1 to 5)
S (1 to 5) N
C_SP
PG (1 to 128)
SRN (1 to 128)
........
128
.........
...........
192 (Dummy)
...........
.....................
192
..................
192
192
C_SP
C_COUT
C_LOG
SR
VOS
IN_N (1 to 192)
SC (1 to 192) SC (1 to 192) N
SC (1 to 192) SC (1 to 192) N
C_CO
CLK
XSP
SAMP (192)
S (1 to 5) N
S (1 to 5)VHVM
VL
DCLK
OUT
VCS_O
VH
VM
VL
OAMP
IN
DA AMP
OUT
VM
IN
DA AMP
OUT
VH
IN
DA AMP
OUT
VL
IN
DA AMP
OUT
VDS
DA
VS (1 to 8) N
BIAS_O
VS (3 to 8)
DEC
TEST1/2
DSELN
XSP
D1 (D to 2)
VS (3 to 8)
VS (1 to 8) N
BIAS_SA
AVDD (P/S)
AV
SS (P/S)
TEST1 (D/I)
TEST2 (D/I)
MODE (D/I)
DI0 (D/I)
DI1 (D/I)
DI2 (D/I)
XSP (D/I)
HD (D/I)
CLK (D/I)
C_CLK (D/I)
C_CK (D/O)
ADCLK (D/O)
RSRO (D/O)
CSRO (D/O)
DV
SS (P/S)
DV
SS (P/S)
DV
DD (P/S)
VCS_S (Bias)
VL (Bias)
VM (Bias)
VH (Bias)
VOS (Bias)
VCS_O (Bias)
AOUT (A/O)
AV
SS (P/S)
AV
DD (P/S)
Pin Symbol
2C
2D
2E
2F
3B
3C
3D
3E
3F
4B
4C
4D
4E
4F
5F
5E
5D
5C
5B
6F
6E
6D
6C
6B
7F
7E
7D
7C
LAND No.
8
7
6
5
4
3
2
15
14
13
12
11
10
9
1
BUF
16
23
22
21
26
25
24
28
27
20
19
18
17
– 4 –
CXA3271GE
Pin Description
Serial
No.
Land No. Symbol I/O Description
Substrate electrode (chip rear surface electrode) 3.3V.
Analog power supply 3.3V.
Analog GND.
Test mode selection. Connect to GND.
Test mode selection. Connect to GND.
Connect to GND.
Gain setting input. (LSB)
Gain setting input.
Gain setting input. (MSB)
Sense start pulse input (negative pulse).
The column and row shift registers and the timing generator are cleared
by this signal.
Connect to GND.
Main clock. (1 to 2MHz)
Column shift register clock.
Connect to C_CK (4E).
Column shift register clock output.
Connect to C_CLK (4D).
Outputs the internally delayed input clock.
Digital power supply 3.3V.
Digital GND.
Digital GND.
Column shift register final output. (Connection is not required.)
Row shift register final output. (Connection is not required.)
Output amplifier reference voltage monitor. (1.65V)
Sensor charge voltage monitor. (1 LSB = 80mV)
Adjustable within the range of 1.92 to 2.48V by the three bits DI[0:2].
Sense amplifier reference voltage monitor. (1.85V)
Dummy cell charge voltage monitor for canceling parasitic capacitance.
VL = 2VM – VH
Sense amplifier current source bias monitor.
(Do not connect.)
Substrate electrode (chip rear surface electrode) 3.3V.
Analog power supply 3.3V.
Analog GND.
Sensor output.
Output amplifier and output buffer current source bias monitor.
(Do not connect.)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
19
18
17
16
15
24
23
22
21
20
28
27
26
25
2B
2C
2D
2E
2F
3B
3C
3D
3E
3F
4B
4C
4D
4E
4F
5B
5C
5D
5E
5F
6B
6C
6D
6E
6F
7B
7C
7D
7E
7F
SUB
AVDD
AVSS
TEST1
TEST2
MODE
DI0
DI1
DI2
XSP
HD
CLK
C_CLK
C_CK
ADCLK
DVDD
DVSS
DVSS
CSRO
RSRO
VOS
VH
VM
VL
VCS_S
SUB
AVDD
AVSS
AOUT
VCS_O
Power
Power
Power
D/I
D/I
D/I
D/I
D/I
D/I
D/I
D/I
D/I
D/I
D/O
D/O
Power
Power
Power
D/O
D/O
A/O
A/O
A/O
A/O
A/O
Power
Power
Power
A/O
A/O
– 5 –
CXA3271GE
Electrical Characteristics
1. DC Characteristics (Topr = 25°C, Vss = 0V)
Timing Definition
CLK
tpr
V
DD
0V
V
DD
0V
V
DD
0V
tpf
Output
2. AC Characteristics (Topr = 25°C, Vss = 3.3V)
Item
Analog supply voltage
Digital supply voltage
Input voltage (High)
Input voltage (Low)
Output voltage (High) CMOS
Output voltage (Low) CMOS
Input leak current
Output voltage
Output voltage
Output voltage
Output voltage
Output voltage
Output voltage
Current consumption
Symbol
AVDD
DVDD
VIH
VIL
VIH
VIL
IL
VH
VH
VL
VL
VM
VOS
IDD
Conditions
CMOS input cell
CMOS input cell
VDD = 3.3V, IOH = –800µA
VDD = 3.3V, IOL = 2.4mA
CMOS input pin
VDD = 3.3V (D0 D1 D2) = (L L L)
VDD = 3.3V (D0 D1 D2) = (H H H)
VDD = 3.3V (D0 D1 D2) = (L L L)
VDD = 3.3V (D0 D1 D2) = (H H H)
VDD = 3.3V (D0 D1 D2) = (∗ ∗ ∗)
VDD = 3.3V (D0 D1 D2) = (∗ ∗ ∗)
VDD = 3.3V
Min.
3.15
3.15
0.7VDD
Vss
2.8
0
–5
1.75
1.55
4
Typ.
3.3
3.3
1.92
2.48
1.76
1.2
1.84
1.65
10
Max.
3.45
3.45
VDD
0.3VDD
3.3
0.4
5
1.92
1.75
14
Unit
V
V
V
V
V
V
µA
V
V
V
V
V
V
mA
Item
Clock input period
Output rise delay time
Output fall delay time
Number of sensor defects
Output voltage Air Level
Output voltage Water Level
Applicable pins
CLK
C_CK, ADCLK, RSRO, CSRO
C_CK, ADCLK, RSRO, CSRO
AOUT
AOUT
Symbol
tpr
tpf
Conditions
CL = 30pF
CL = 30pF
∗1
∗2
Min.
400
600
200
Typ. Max.
160
200
5
1300
Unit
ns
ns
ns
Sensors
mV
mV
– 6 –
CXA3271GE
∗1
Output voltage Air Level means the output level in the condition where nothing is placed against the sensor
surface (in other words, in air). This rating value is obtained by measuring 32 points within one line of the
sensor output and then taking the average.
The gain setting for this measurement is (011).
∗2
Output voltage Water Level specifies the degree to which the output level changes from the Air Level when
a drop of water is placed on the sensor surface. However, it is unrealistic to place a drop of water on each
sensor surface when sorting products, so 32 virtual capacitors (parasitic capacitance equal to the level
when a drop of water is placed on the surface) are built into the sensor chip, and the average of these
output values is calculated. The difference from the Air Level noted above becomes the Water Level.
The gain setting for this measurement is (011).
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