Sony CXA3106AQ Datasheet

Description

The CXA3106AQ is a PLL IC for LCD monitors/ projectors with built-in phase detector, charge pump, VCO and counter.

The various internal settings are performed by serial data via a 3-line bus.

Applicable LCD monitor/projector resolution are NTSC, PAL, VGA, SVGA, XGA, and SXGA etc.

Features

• Supply voltage: 5V ± 10% single power supply

• Package: 48-pin QFP

• Power consumption: 350mW

• Sync input frequency: 10 to 100kHz

• Clock output signal frequency: 10 to 160MHz

• Clock delay: 1/16 to 20/16 CLK

• Sync delay: 1/16 to 20/16 CLK

• I/O level: TTL, PECL (complementary)

• Low clock jitter

• 1/2 clock output

Pin Configuration (Top View)

Functions

• Phase detector enable

• UNLOCK output

• Output TTL disable function

• Power save function (2 steps)

Applications

• CRT displays

• LCD projectors

• LCD monitors

• Multi-media

– 1 –

CXA3106AQ

E97812A03

PLL IC for LCD Monitor/Projector

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

48 pin QFP (Plastic)

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

36

35

34

31

32

33

40

39

38

37

41 42 43 44

45 46 47 48

IOV

CC

IOGND

VCOH

VCOL

VCO

HOLD

SYNCH

SYNCL

SYNC

SENABLE

SCLK

SDATA

PECLV

CC

VBB

DSYNCH

DSYNCL

CLKH

CLKL

CLK/2H

PECLV

CC

IOGND

TTLV

CC

TTLGND

IRVCC

IRGND

RC1

RC2

IREF

VCOHGND

VCOGND

VCOV

CC

PLLGND

PLLV

CC

IOVCC

IOGND

TLOAD

CS

SEROUT

DIVOUT

UNLOCK

DV

CC

DGND

CLK/2

CLKN

CLK

DSYNC

CLK/2L

CLK/2N

1

2

3

4

5

6

7

8

9

10

11

12

– 2 –

CXA3106AQ

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage IOVCC, DVCC, TTLVCC, PECLVCC, PLLVCC,

VCOVCC, IRVCC, –0.5 to +7.0 V IOGND, DGND, TTLGND, VCOHGND, PLLGND, VCOGND, IRGND –0.5 to +0.5 V

• Input voltage VCOH, VCOL, SYNCH, SYNCL, VCO, HOLD, SYNC, SENABLE, SCLK, SDATA, TLOAD, CS IOGND – 0.5 to IOVCC + 0.5 V RC2 IRGND – 0.5 to IRVCC + 0.5 V

• Output current SEROUT, DIVOUT, UNLOCK, CLK/2N, CLK/2, CLKN, CLK, DSYNC, CLK/2L, CLK/2H, CLKL, CLKH, DSYNCH, DSYNCL, VBB –30 to +30 mA IREF, RC1 –2 to +2 mA

• Storage temperature Tstg –65 to +150 °C

• Operating ambient temperature

Ta –25 to +75 °C

• Allowable power dissipation PD 750 mW

Recommended Operating Conditions

Min. Typ. Max.

• Supply voltage IOVCC, DVCC, TTLVCC, PECLVCC, PLLVCC, VCOVCC, IRVCC 4.75 5.00 5.25 V IOGND, DGND, TTLGND, VCOHGND, PLLGND, VCOGND, IRGND –0.05 0 0.05 V

• Digital input DIN (PECL) ∗1H level IOVCC – 1.1

DIN (PECL) ∗1L level IOVCC – 1.5 V DIN (TTL) ∗2H level 2.0 V DIN (TTL) ∗2L level 0.8 V

• SYNC, SYNCH, SYNCL input jitter 1.0 ns

• Operating temperature Ta –20 +75 °C

∗1

VCOH, VCOL, SYNCH, SYNCL

∗2

VCO, HOLD, SYNC, SENABLE, SCLK, SDATA, TLOAD, CS

– 3 –

CXA3106AQ

Block Diagram

TTLOUT

Polarity

Coarse

Delay

TTLOUT

1bit

on/off

1bit

on/off

1bit

on/off

DSYNC

(TTL)

DSYNC

(PECL)

CLK

(TTL)

NCLK

(TTL)

CLK

(PECL)

TTLOUT

1bit

on/off

1bit

on/off

CLK/2

(TTL)

NCLK/2

(TTL)

CLK/2

(PECL)

PECL

on/off

DIV1, 2, 4MUXVCO

Fine

Delay

Charge

Pump

Phase

Detector

PECLIN

TTLIN

PECLIN

TTLIN

Polarity

TTLIN

Programmable

Counter

whole chip

power save

synthesizer

power save

TTLINTTLOUTCONTROL REGISTERDAC

RESET

1/2

2bit

1bit5bit2bit

1bit

12bit

1/256 to 1/4096 CLK

1/16 to 20/16 CLK

1bit

CSTLOAD

DIVOUTSEROUT

SDATASCLKSENABLE

IREF

1bit2bit

Latch

logic

1bit

on/off

1bit

on/off

RC2RC1

VCO

(TTL)

VCO

(PECL)

SYNC

(TTL)

SYNC

(PECL)

HOLD

(TTL)

read out

TTLOUT

1 to 4 CLK

UNLOCK

VBB

PECLOUT

unlock

detect

– 4 –

CXA3106AQ

Pin No. Symbol Description Reference voltage level

1 IOVCC Digital power supply 5V 2 IOGND Digital GND 0V 3 VCOH External VCO input PECL 4 VCOL External inverted VCO input PECL 5 VCO External VCO input TTL 6 HOLD Phase detector disable signal input TTL 7 SYNCH Sync input PECL 8 SYNCL Inverted sync input PECL

9 SYNC Sync input TTL 10 SENABLE Control signal (enable) TTL 11 SCLK Control signal (clock) TTL 12 SDATA Control signal (data) TTL 13 TLOAD Programmable counter test input TTL 14 CS Chip select TTL 15 SEROUT Register read output TTL 16 DIVOUT Programmable counter test output TTL 17 UNLOCK Unlock signal output TTL 18 DVCC Digital power supply 5V 19 DGND Digital GND 0V 20 CLK/2N Inverted 1/2 clock output TTL 21 CLK/2 1/2 clock output TTL 22 CLKN Inverted clock output TTL 23 CLK Clock output TTL 24 DSYNC Delay sync signal output TTL 25 TTLGND TTL output GND 0V 26 TTLVCC TTL output power supply 5V 27 IOGND Digital GND 0V 28 PECLVCC PECL output power supply 5V 29 CLK/2L Inverted 1/2 clock output PECL 30 CLK/2H 1/2 clock output PECL 31 CLKL Inverted clock output PECL 32 CLKH Clock output PECL 33 DSYNCL Delay sync signal output PECL 34 DSYNCH Inverted delay sync signal output PECL 35 VBB PECL reference voltage PECLVCC – 1.3V 36 PECLVCC PECL output power supply 5V 37 IOGND Digital GND 0V 38 IOVCC Digital power supply 5V 39 PLLVCC PLL circuit analog power supply 5V 40 PLLGND PLL circuit analog GND 0V 41 VCOVCC VCO circuit analog power supply 5V 42 VCOGND VCO circuit analog GND 0V 43 VCOHGND VCO SUB analog GND 0V 44 IREF Charge pump current preparation 1.3V 45 RC2 External pin for LPF 1.7 to 4.4V 46 RC1 External pin for LPF 2.1V 47 IRGND IREF analog GND 0V 48 IRVCC IREF analog power supply 5V

– 5 –

CXA3106AQ

Pin Description and I/O Pin Equivalent Circuit

Digital power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

Digital GND. Digital power supply. Digital GND. TTL output GND. TTL output power supply.

Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

Digital GND. PECL output power supply.

Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

PECL output power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

Digital GND. Digital power supply.

Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

PLL circuit analog power supply. Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

PLL circuit analog GND. VCO circuit analog power supply.

Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

VCO circuit analog GND. VCO SUB analog GND. IREF analog GND. IREF analog power supply.

Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

1

2

18 19 25

26

27

28

36

37

38

39

40

41

42 43 47

48

IOVCC

IOGND DVCC DGND TTLGND

TTLVCC

IOGND

PECLVCC

IOGND

IOVCC

PLLVCC

PLLGND

VCOVCC

VCOGND VCOHGND IRGND

IRVCC

5V

0V 5V 0V 0V

5V

0V

5V

0V

5V

0V

5V

0V 0V 0V

5V

—

— — — —

—

— — —

—

Pin No.

Symbol I/O

Reference voltage level

Equivalent circuit Description

– 6 –

CXA3106AQ

External VCO input. Programmable counter test input (switchable by a control register). When using the VCO PECL input, open the Pin 5 VCO TTL input.

External inverted VCO input. When open, this pin goes to the PECL threshold voltage (IOVcc – 1.3V). Only the pin 3 VCOH input with VCOL input open can be also operated but complementary input is recommended in order to realize stable high-speed operation.

Sync input. When using the SYNCH PECL input, open the Pin 9 SYNC TTL input. The sync signal can be switched between positive/negative polarity by an internal register.

Inverted sync input. When open, this pin goes to the PECL threshold voltage (IOVcc – 1.3V). Only the Pin 7 SYNCH input with SYNCL input open can be also operated but complementary input is recommended in order to realize stable high-speed operation.

3

4

7

8

VCOH

VCOL

SYNCH

SYNCL

PECL

I

3 4

8

7

IOV

CC

IOGND

rr

Pin No.

Symbol I/O

Reference voltage level

Equivalent circuit Description

– 7 –

CXA3106AQ

External VCO input. Programmable counter test input (controlled by a control register). When using the VCO TTL input, open the Pin 3 VCOH and Pin 4 VCOL PECL inputs.

Phase detector disable signal. Active high. When this pin is high, the phase detector output is held. This pin goes to high level when open. (See the HOLD Timing Chart.)

Sync input. When using the SYNC TTL input, open the Pin 7 SYNCH and Pin 8 SYNCL PECL inputs. The sync signal can be switched between positive/negative polarity by a control register.

Control signal (enable) for setting the internal registers. When SENABLE is low, registers can be written; when high, registers can be read. (See the Control Register Table and Control Timing Chart.)

Control signal (clock) for setting the internal registers. When SENABLE is low, SDATA is loaded to the registers at the rising edge of SCLK. When SENABLE is high, the register contents are output from SEROUT at the falling edge of SCLK. (See the Control Register Table and Control Timing Chart.)

Control signal (data) for setting the internal registers. (See the Control Register Table and Control Timing Chart.)

Programmable counter test input. This pin is normally open status and high. Register contents can be loaded immediately to Programmable counter by setting TLOAD low during the programmable counter test mode.

5

6

9

10

11

12

13

VCO

HOLD

SYNC

SENABLE

SCLK

SDATA

TLOAD

TTL

I

5 6 9

10

12 13

r/2

r

2r

1.5V

IOVCC

IOGND

11

Pin No.

Symbol I/O

Reference voltage level

Equivalent circuit Description

– 8 –

CXA3106AQ

Chip select. When low, all circuits including the register circuit are set to the power save mode. When high, all circuits are set to operating mode.

Register read output. When SENABLE is high, the register contents are output from SEROUT at the falling edge of SCLK. (See the Control Register Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register.

Programmable counter test output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register.

Inverted 1/2 clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register.

1/2 clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register.

Inverted clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register.

Clock output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register.

Delay sync signal output. (See the I/O Timing Chart.) TTL output can be turned ON/OFF (high impedance) and switched between positive/negative polarity by a control register.

14

15

16

20

21

22

23

24

CS

SEROUT

DIVOUT

CLK/2N

CLK/2

CLKN

CLK

DSYNC

TTL

I

O

IOVCC

IOGND

14

IOVCC

IOGND

TTLV

CC

TTLGND

15

20

21

22 23 24

16

100k

Pin No.

Symbol I/O

Reference voltage level

Equivalent circuit Description

– 9 –

CXA3106AQ

Unlock signal output. This pin is an open collector output, and pulls in the current when a phase difference occurs. The UNLOCK sensitivity can be adjusted by connecting a capacitor and resistors to this output as appropriate. (See the UNLOCK Timing Chart.) TTL output can be turned ON/OFF (high impedance) by a control register.

Inverted 1/2 clock output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor.

1/2 clock output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor.

Inverted clock output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor.

Clock output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor.

Delay sync signal output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor.

Inverted delay sync signal output. (See the I/O Timing Chart.) This pin requires an external pulldown resistor. When not used, connect to PECLVCC without connecting a pull-down resistor.

17

29

30

31

32

33

34

UNLOCK

CLK/2L

CLK/2H

CLKL

CLKH

DSYNCL

DSYNCH

TTL

PECL

O

17

TTLVCC

IOGND

TTLGND

IOGND

IOVCC

29

30

34

31

32

33

PECLV

CC

Pin No.

Symbol I/O

Reference voltage level

Equivalent circuit Description

– 10 –

CXA3106AQ

PECL reference voltage. When used, ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

Charge pump current preparation. Connect to GND via an external resistor (1.6kΩ). Ground this pin to the ground pattern with a 0.1µF ceramic chip capacitor as close to the pin as possible.

External pin for LPF. See the Recommended Operating Circuit for the external circuits. Note that external resistors and capacitors should be metal film resistors and temperature compensation capacitors which are relatively unaffected by temperature change.

External pin for LPF. See the Recommended Operating Circuit for the external circuits.

VBB

IREF

RC2

RC1

O

PECLVCC

–1.3V

1.3V

1.7 to

4.4V

2.1V

35

44

45

46

Pin No.

Symbol I/O

Reference voltage level

Equivalent circuit Description

PECLVCC

IOGND

35

IRVCC

IRGND

44

IOGND

VCOVCC

VCOGND IOGND

IRGND

IRV

CC

45

46

100

– 11 –

CXA3106AQ

Control Register Table

Register No.

Register 1

Register 2

Register 3

Register 4

Register 5

Register 6

Register 7

Register Name

register read no

DIVREG1

register read no

DIVREG2

register read no

CENFREREG

register read no

DELAYREG

register read no

CPREG

register read no

TTLPOLREG

register read no

TESTPOWREG

DATA7

MSB1VCO

DIV

Bit 7

30

UNLOCK

Enable

DAT6

2

VCO

DIV

Bit 6

13

DIV 1, 2, 4

Bit 1

20

COARSE

DELAY

Bit 1

31

DSYNC

Enable

DATA5

3

VCO

DIV

Bit 5

14

DIV 1, 2, 4

Bit 0

21

COARSE

DELAY

Bit 0

32

NCLK/2

Enable

DATA4

4

VCO

DIV

Bit 4

15

N/A

∗

1

22

FINE

DELAY

Bit 4

33

CLK/2

Enable

DATA3

5

VCO

DIV

Bit 3

9

VCO

DIV

Bit 1116N/A

∗1

23

FINE

DELAY

Bit 3

34

NCLK

Enable

38

DIVOUT

Enable

DATA2

6

VCO

DIV

Bit 2

10

VCO

DIV

Bit 1017N/A

∗

1

24

FINE

DELAY

Bit 2

27

PD

POL

35

CLK

Enable

39

Read out

power

DATA1

7

VCO

DIV

Bit 1

11

VCO

DIV

Bit 9

18

N/A

∗

1

25

FINE

DELAY

Bit 1

28

C.Pump

Bit 1

36

DSYNC

POL

40

Synth

power

DATA0

8

VCO

DIV

Bit 0

12

VCO

DIV

Bit 8

19

N/A

∗

1

26

FINE

DELAY

Bit 0

29

C.Pump

Bit 0

37

SYNC

POL

41

VCO

By-pass

∗2

ADDR2

MSB

0

1

ADDR1

0

1

0

1

ADDR0

LSB

1

0

1

0

1

0

1

DATA ADDRESS

∗

1

Register read no. 15 to 19 are N/A.

∗2

VCO By-pass at register read no. 41 is a MUX control bit in Block Diagram.

– 12 –

CXA3106AQ

Electrical Characteristics (Ta = 25°C, VCC = 5V, GND = 0V)

Current consumption (excluding output current) Current consumption 1 Current consumption 2 Current consumption 3 Digital input Digital high level input

voltage (PECL) Digital low level input

voltage (PECL) VCOL, SYNCL input open

voltage (PECL) Digital high level input

current (PECL) Digital low level input

current (PECL) Digital high level input

voltage (TTL) Digital low level input

voltage (TTL) Digital high level input

current (TTL) Digital low level input

current (TTL) HOLD characteristics RC1 input pin leak current HOLD signal set-up time HOLD signal hold time Digital output Digital high level output

voltage (PECL) Digital low level output

voltage (PECL) PECL output reference

voltage Digital high level output

voltage (TTL) Digital low level output

voltage (TTL)

CS = H, Synth Power = 1 CS = H, Synth Power = 0 CS = L

VIH = IOVCC – 0.8V

VIL = IOVCC – 1.6V

VIH = 2.7V

VIL = 0.5V

RL = 330Ω

CL = 10pF

40

5 3

IOVCC

–1.15

–100

–200

2.0

–200

–500

20 20

PECLVCC

–1.1

2.7

70 19 14

IOVCC

–1.3

PECLVCC

–1.3

105

38 24

IOVCC

–1.5

100

0

0.8

–20

–100

1.0

PECLVCC

–1.6

0.5

mA mA mA

V

µA

V

µA

nA

ns ns

V

ICC1 ICC2 ICC3

VIH1

VIL1

VIO

IIH1

IIL1

VIH2

VIL2

IIH2

IIL2

Ileak Ths Thh

VOH1

VOL1

VBB

VOH2

VOL2

Item Symbol Conditions Min. Typ. Max. Unit

– 13 –

CXA3106AQ

UNLOCK output UNLOCK output current SYNC input SYNC input frequency range DSYNC output DSYNC output variable

coarse delay time setting resolution

DSYNC output variable coarse delay time

DSYNC output variable fine delay time setting resolution

DSYNC output variable fine delay time

VCO characteristics DIV output frequency

operation range 1 DIV output frequency

operation range 2 DIV output frequency

operation range 3 VCO lock range VCO gain 1 VCO gain 2 VCO gain 3

Charge pump current 1

Charge pump current 2

Charge pump current 3 VCO counter bits

DIV = 1/1

DIV = 1/2

DIV = 1/4

DIV = 1/1 DIV = 1/2 DIV = 1/4 C.Pump Bit = 00,

IREF = 1.6kΩ C.Pump Bit = 10,

IREF = 1.6kΩ C.Pump Bit = 11,

IREF = 1.6kΩ

–30

10

1

1/16

40

20

10

1.7 240 120

60 80

350

1350

2

5

400 200 100

100

400

1600

12

100

4

20/16

160

80

40

4.4 640 320 160

130

500

1800

mA

kHz

bit

CLK

bit

CLK

MHz

V Mrad/sv Mrad/sv Mrad/sv

µA

µA bit

Iunlock

Fin

Rdsync1

Td1

Rdsync2

Td2

FVCO1

FVCO2

FVCO3 Vlock

KVCO1 KVCO2 KVCO3

Kpd1

Kpd2

Kpd3 Rdiv2

Item Symbol Conditions Min. Typ. Max. Unit

– 14 –

CXA3106AQ

CLK (CLK, CLK/2) output CLK output (PECL)

frequency range 1 CLK output (PECL)

frequency range 2 CLK output (PECL)

frequency range 3 CLK, CLK/2 output (PECL)

rise time CLK, CLK/2 output (PECL)

fall time CLK output (TTL)

frequency range 1 CLK output (TTL)

frequency range 2 CLK output (TTL)

frequency range 3 CLK, CLK/2 output (TTL)

rise time CLK, CLK/2 output (TTL)

fall time CLK output (PECL, TTL)

duty SYNC input (PECL) and

CLK output (PECL) delay offset

CLK output (PECL) and DSYNC output (PECL) phase difference

CLK output (PECL) and CLK/2 output (PECL) phase difference

CLK output (PECL) and DIVOUT output (TTL) rise phase difference

CLK output (PECL) and DIVOUT output (TTL) fall phase difference

DSYNC, CLK, CLK/2 PECL output and TTL output phase difference

DIV = 1/1

DIV = 1/2

DIV = 1/4 10% to 90%,

RL = 330Ω 10% to 90%,

RL = 330Ω DIV = 1/1

DIV = 1/2

DIV = 1/4 10% to 90%,

CL = 10pF 10% to 90%,

CL = 10pF CL = 10pF

CL = 10pF

40

20

10

1.0

40

20

10

2.0

40

1.5

0.0

10

8

1.5

3.0

50

1

2.4

0.8

14

11

3.0

160

80

40

2.0

80

40

4.0

60

3.0

1.0

19

14

4.5

MHz

ns

MHz

ns

%

ns

Fclk1PECL

Fclk2PECL

Fclk3PECL

TrPECL

TfPECL

Fclk1TTL

Fclk2TTL

Fclk3TTL

TrTTL

TfTTL

Dclk2

Td3

Td4

Td5

Td6

Td7

Td8

Item Symbol Conditions Min. Typ. Max. Unit

– 15 –

CXA3106AQ

CLK (CLK, CLK/2) output

CLK vs. SYNC output jitter (NTSC)

CLK vs. SYNC output jitter (VGA)

CLK vs. SYNC output jitter (SVGA)

CLK vs. SYNC output jitter (XGA)

CLK vs. SYNC output jitter (SXGA)

CLK vs. DSYNC output jitter Control registers SCLK frequency SENABLE setup time SENABLE hold time SDATA setup time SDATA hold time SENABLE setup time SENABLE hold time

triggered at SYNC Fsync = 15.73kHz (Crystal) Fclk = 12.27MHz N = 780

triggered at SYNC Fsync = 31.47kHz (Crystal) Fclk = 25.18MHz N = 800

triggered at SYNC Fsync = 48.08kHz (Crystal) Fclk = 50.00MHz N = 1040

triggered at SYNC Fsync = 56.48kHz (Crystal) Fclk = 75.00MHz N = 1328

triggered at SYNC Fsync = 80kHz (Crystal) Fclk = 136.00MHz N = 1700

triggered at DSYNC

in write/read mode in write mode in write mode in write mode in read mode in read mode in read mode

3.0

1.0

0.9

0.8

0.6

3 0 3 0 3 0

5.0

2.0

1.6

1.5

1.0

8.0

3.0

2.5

2.0

1.4

0.1

12

ns

MHz

ns ns ns ns ns ns

Tj1p-p

Tj2p-p

Tj3p-p

Tj4p-p

Tj5p-p

Tj6p-p

SCLK TENS TENH TDS TDH TNENS TNENH

Item Symbol Conditions Min. Typ. Max. Unit

– 16 –

CXA3106AQ

Description of Block Diagram

Sync Input

Sync signals in the range of 10 to 100kHz can be input. Input supports both positive and negative polarity. PECL input can also be a single input. When SYNC is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal. When SYNC is negative polarity, the clock is regenerated in synchronization with the falling edge of the sync signal. VCO oscillation stops when there is no sync input.

Register: SYNC POL

SYNC input polarity

1

Positive

0

Negative

Phase Detector

The phase detector operates at the sync input frequency of 10 to 100kHz. The PD input polarity should be set to the default PD POL = 1. Phase comparison is performed at the edges. The input circuit of the phase detector does not contain a hysteresis circuit, so the waveform must be shaped at the front end of the CXA3106AQ when inputting a noisy signal.

The phase detector HOLD signal is supplied by TTL. (See the HOLD Timing Chart.)

The PLL UNLOCK signal is output by an open collector. (See the UNLOCK Timing Chart.)

Charge Pump

The gain (I, I/4, I/16) can be varied by changing the charge pump current using 2 bits of control register.

Register: C.Pump bit 1 Register: C.Pump bit 0

0 0

1 0

1 1

Charge pump current

100µA

400µA 1600µA

Register: DIV 1, 2, 4 bit 1 Register: DIV 1, 2, 4 bit 0

0 0

1 0

1 1

Counter frequency divisions

1/1

1/2 1/4

LPF

This is a loop filter comprised of the external capacitors and resistor. Be sure to use metal film resistors with little temperature variation and a temperature-compensated capacitor. In particular, the 0.33µF capacitor should be equivalent to high dielectric constant series capacitor type B or better. (electrostatic capacitance change ratio ±10%: T = –25 to +85°C)

VCO

The VCO oscillator frequency covers from 40 to 160MHz.

VCO Rear-end Counter

The VCO output is frequency divided to 1/1, 1/2 or 1/4 by switching 2 bits of control register. The operating range can be expanded to 10 to 160MHz by combining the counter with a VCO frequency divider.

– 17 –

CXA3106AQ

Feedback Programmable Counter

This counter can be set as desired from 256 to 4096 using 12 bits.

Frequency divisions = (m + 1) × 8 + n, n: 3 bits (VCO DIV bits 0 to 2), m: 9 bits (VCO DIV bits 3 to 11) When the register value is changed, the new setting is actually loaded to the counter when the counter value becomes "all 0".

Clock Output

When SYNC input is positive polarity, the clock is regenerated in synchronization with the rising edge of the sync signal. The clock output delay time can be changed in the range of 1/16 to 20/16 CLK using 5 bits of control register. (See the I/O Timing Chart.) Output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL output can also be turned off independently.

Register: Clock Enable

Clock output status

1

ON

0

OFF

Register: Clock Enable

Clock output status

1

ON

0

OFF

Register: DSYNC POL DSYNC output polarity

1

Positive

0

Negative

Lower delay line

FINE DELAY bits 0 to 4

Delay time

00000

1/16CLK

00001

2/16CLK

· · · · · · · · · · · ·

10011

20/16CLK

Upper delay line

COARSE DELAY bits 0 to 1

Delay time

00

1CLK

01

2CLK

10

3CLK

11

4CLK

Delay Sync Output

The front edge of the delay sync pulse is latched by the pulse obtained by frequency dividing the CLK regenerated by the PLL, so there is almost no jitter with respect to CLK. This front edge can be used as the reset signal for the system timing circuit. The rear edge of the delay sync pulse is latched by the CLK regenerated by the PLL. This relationship is undefined for one clock as shown in the Timing Chart. The delay sync output delay time can be varied in two stages. First, the delay time can be varied in the range of 1/16 to 20/16 CLK using 5 bits of control register, and then in the range of 1 to 4 CLK using 2 bits of control register. In other words, the total delay time is ((1/16 to 20/16) + (1 to 4)) CLK. (See the I/O Timing Chart.) DSYNC output is TTL and PECL (complementary), and supports both positive and negative polarity. Clock TTL output can also be turned off.

1/2 Clock Output

Reset is performed at the delay sync timing and the clock output is frequency divided by 1/2. (See the I/O Timing Chart.) Both odd and even output are TTL and PECL output. TTL output can also be turned off independently.

Register: Clock Enable

Clock output status

1

ON

0

OFF