Sony CXA3017R Datasheet

Decoder/Driver/Timing Generator for Color LCD Panels

Description

The CXA3017R is an IC designed to drive the color LCD panels LCX005BK/BKB, LCX009AK/AKB, LCX024AK/AKB, LCX027AK/AKB and DCX501BK.

This IC allows two-panel simultaneous and switching drive by simultaneously outputting the timing pulses for the LCX005BK/BKB, LCX009AK/AKB, LCX024AK/AKB, LCX027AK/AKB and DCX501BK.

This IC greatly reduces the number of peripheral circuits and parts by incorporating an RGB decoder, driver, and timing generator for video signals onto a single chip. This chip has a built-in serial interface circuit and electronic attenuators which allow various settings to be performed by microcomputer control, etc.

Features

• Color LCD panel LCX005BK/BKB, LCX009AK/AKB,

LCX024AK/AKB, LCX027AK/AKB and DCX501BK driver

• Supports two-panel simultaneous and switching

drive using the LCX005BK/BKB, LCX009AK/AKB,

LCX024AK/AKB, LCX027AK/AKB and the DCX501BK

• Supports NTSC and PAL systems

• Supports 16:9 wide display

(letter box and pulse elimination display)

• Supports composite inputs, Y/C inputs and Y/color

difference inputs

• Serial interface circuit

• Electronic attenuators (D/A converter)

• VCO

• BPF, trap and delay line

• Sharpness function

• 2-point γ correction circuit

• R, G, B signal delay time adjustment circuit

• Polarity inversion circuit (line inverted mode)

• Supports external RGB input

• D/A output pin (0 to 3V, 8 levels)

• Supports AC drive for LCD panel during no signal

Applications

• Compact LCD monitors

• LCD viewfinders

• Compact liquid crystal projectors, etc.

Structure

Bi-CMOS IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VCC1 – GND1 6 V

VCC2 – GND2 14 V VCC3 – GND3 14 V VDD1, 2 – VSS 4.5 V

• Analog input pin voltageVINA –0.3 to VCC1V

•Digital input pin voltage VIND –0.3 to VDD1 + 0.3V

• Operating temperature Topr –15 to +75 °C

• Storage temperature Tstg –40 to +125 °C

• Allowable power dissipation

∗1

PD (Ta ≤ 75°C)

Approximately 350mW

Operating Conditions

Supply voltage VCC1 – GND1 2.7 to 3.6 V

VCC2 – GND2 11.0 to 13.5 V VCC3 – GND3 11.0 to 13.5 V VDD1, 2 – VSS 2.7 to 3.6 V

∗1

With substrate Size: 30 × 30 × 1.6mm

Material: Glass fabric base epoxy

– 1 –

E98Y29-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA3017R

64 pin LQFP (Plastic)

For the availability of this product, please contact the sales office.

– 2 –

CXA3017R

Block Diagram

SIG.CENTER

POL SW

SUBBRIGHT

GAMMA

DEMOD

LPF

CONTRAST

EXT SW

BRIGHT

S/H

INT/EXT

VXO

HUE

PS

KILLER

FILT ADJ

COLOR CONT

BPF

PIC CONT

DL1

TRAP

CLAMP

ACC AMP

H.FILTER

REG

R G B

+12V

GND1

V

SS

+3.0V

Buf

EXT COLOR & BALANCE

HUE

COLOR

R-BRT B-BRT

γ -1

γ -2

D/A

VGATE

VJOG

VPAL

VWIN

WIDE

PALSW

D/A

HCNT H-PULSE

HAFC PLL-COUNTER & DECODER

HGATE H-SKEW DET

PD

CLP BGP

SBLK

+3V

MATRIX

Buf

POL SW

PSIGBRIGHT

PSIG-BRT

APC

ACC DET

HD

GND3

GND2

FRP

COLOR

PAL ID

CLAMP

DA OUT

VD

EN2

EN1

XEN1

VCK1

VCK2

VCK3

VCK4

VST

XVST

HD

PCG

XPCG

HCK1

HCK2

V

SS

XHST1

HST1

HST2

CLR

BLK

SCLK

DATA

LOAD

V

DD

1

TRAP

EXT B

EXT G

EXT R

TEST1

RPD

VCC1

VXO OUT

VXO IN

APC

R-Y IN

C OUT

V REG

C IN

RESET

Y IN

TEST2

SYNC IN

VSEP TC

GND1

F0 ADJ

B-Y IN

V

DD

2

DWN

RGT1

FB PSIG

GND3

PSIG

V

CC

3

B OUT

FB B

GND2

FB G

R OUT

FB R

V

CC

2

G OUT

BRIGHT

2

3

4

5

6

7

8

9

10

11

12

13

14 15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

40

39

38

37

36

35

34

31

32

33

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

63

64

61

62

1

Buf

BLKLIM WHTLIM

USER BRIGHT

+3V

I/F

HUE

COLOR

BRIGHT

CONT R-BRT B-BRT

γ-1

VCO

PSIG-BRT R-CONT B-CONT PICTURE USER-BRT BLKLIM

WHTLIM

γ-2

SERIAL BAS I/F

PALSW

INT/EXT

USERBRT

VCO

SYNC SEP

V SEP

PICTURE

SUB CONTRAST

R-CONT

B-CONT

CONT

– 3 –

CXA3017R

Pin Description

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

34

EXT R EXT G EXT B TRAP VDD1 LOAD DATA SCLK RPD TEST1 BLK CLR HST2 HST1 XHST1 VSS HCK2 HCK1 XPCG PCG HD XVST VST VCK4 VCK3 VCK2 VCK1 XEN1 EN1 EN2 VD DA OUT VDD2

DWN

Symbol

L

I I I

O

I I I

O

I O O O O O

O O O O O O O O O O O O O O O O

O

External digital R input External digital G input External digital B input External trap connection Digital 3V power supply for oscillation cell Serial interface load input Serial interface data input Serial interface clock input Phase comparator output Test (Connect to GND.) BLK pulse output CLR pulse output H start pulse 2 output H start pulse 1 output XH start pulse 1 output (reverse polarity of HST1) Digital 3V GND H clock pulse 2 output H clock pulse 1 output XPCG pulse output (reverse polarity of PCG) PCG (precharge) pulse output HD pulse output XV start pulse output (reverse polarity of VST) V start pulse output V clock pulse 4 output V clock pulse 3 output V clock pulse 2 output V clock pulse 1 output XEN pulse 1 output (reverse polarity of EN1) EN pulse 1 output EN pulse 2 output VD pulse output DAC output Digital 3V power supply DCX501BK up/down inverted display switching

(open collector output)

I/O Description

Input pin processing for open status

– 4 –

CXA3017R

Pin No.

35 36

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

62 63

64

L

RGT1 FB PSIG

GND3 PSIG VCC3 B OUT FB B GND2 G OUT FB G R OUT FB R VCC2 SIG.CENTER VCC1 VXO OUT VXO IN APC B-Y IN R-Y IN C OUT V REG C IN RESET Y IN TEST2 SYNC IN

VSEP TC F0 ADJ

GND1

Symbol

O

I

O

I

O

I

O

I

O

I

O

I

I O O

I

O

DCX501BK right/left inverted display switching (open collector output)

PSIG signal DC voltage feedback circuit capacitor connection Analog 12V GND for PSIG PSIG output Analog 12V power supply for PSIG B signal output B signal DC voltage feedback circuit capacitor connection Analog 12V GND G signal output G signal DC voltage feedback circuit capacitor connection R signal output R signal DC voltage feedback circuit capacitor connection Analog 12V power supply R, G, B and PSIG output DC voltage adjustment Analog 3V power supply VXO output VXO input APC detective filter connection B-Y color difference signal input R-Y color difference signal input Chroma signal output Constant voltage capacitor connection Chroma signal input System reset Y signal input Test (Connect to GND.) Video input for sync separation Capacitor connection for vertical sync separation

(or external VSYNC input) Internal filter adjusting resistor connection Analog 3V GND

I/O Description

Input pin processing for open status

∗

DWN: DOWN SCAN and UP SCAN RGT: RIGHT SCAN and LEFT SCAN

– 5 –

CXA3017R

Analog Block Pin Description

No.

Symbol Pin voltage Equivalent circuit Description

4

TRAP

1.0V

4

VCC1

GND1

200µA

1k

300

75µA

External trap connection. Connect the trap between this pin and GND to eliminate the chroma component. Leave this pin open when using Y/C and Y/color difference mode.

32

DA OUT

0.2 to 2.9V

VDD2

V

SS

50k

32

50k

DAC output. 8-level, 7-step DC voltage from approximately 0.2 to 2.9V is output from this pin.

34

35

DWN

—

RGT1

—

35

34

VCC2

GND2

500

DCX501BK up/down and right/left inversion switching. These pins are open collector outputs, so first connect a 100kΩ resistor between these pins and the panel V

DD (15.5V)

and then connect to the DCX501BK.

1 EXT-R

2 EXT-G

3 EXT-B

External digital signal inputs. There are two thresholds: Vth1 (= 1.0V) and Vth2 (= 2.0V). When one of the RGB signals exceeds Vth1, all of the RGB outputs go to black level; when an input exceeds Vth2, only the corresponding output goes to white level. Connect these pins to GND when not used.

VCC1

GND1

25µA

300

1.1V

2

3

1

50k

—

41 FB B

36 FB PSIG

44 FB G

46

FB R

Smoothing capacitor connection for the feedback circuit of R, G, B and PSIG output DC level control. Use a low-leakage capacitor because of high impedance.

VCC1

GND2

100k

36 41 44 46

1k

1.5V

37 GND3

0V

GND for the PSIG circuit.

– 6 –

CXA3017R

48

SIG. CENTER

VCC2

2

RGB/PSIG output DC voltage control. When used with a VCC2 or VCC3 of 12V or more, or when used with a signal center voltage of other than VCC2/2 or VCC3/2, apply voltage of 5.2 to

6.5V from an external source.

48

VCC2

GND2

150k 300

150k

10k

39

VCC3

12V

12V power supply for the PSIG circuit.

PSIG signal output.

VCC3

GND3

20

38

150

38

PSIG

VCC2

2

40

B OUT

43

G OUT

45

R OUT

VCC2

2

RGB signal outputs.

VCC2

GND2

40µA

20

40 43

45

42

GND2

0V

12V GND.

49 VCC1

3.0V

3.0V power supply.

47 VCC2

12V

12V power supply.

50

VXO OUT

1.2V

VXO output. Leave this pin open when using Y/color difference mode.

50

VCC1

GND1

200

370µA

51

VXO IN

1.6V

VXO input. Leave this pin open when using Y/color difference mode.

GND1

10k

1.6V

VCC1

500

51

3.5k

10p

3.5k

No.

Symbol Pin voltage Equivalent circuit Description

– 7 –

CXA3017R

Pin No.

Symbol Pin voltage Equivalent circuit Description

53 B-Y IN

54 R-Y IN

—

Y/color difference signal inputs. When using color difference input, the standard signal input level is 0.3Vp-p (75% color bar) and the clamp level is approximately 1.7V. During D-PAL, the COUT (Pin

55) chroma signal is U/V separated and then input. Input at low impedance (75Ω or less).

53

54

VCC1

GND1

40µA

4k

10k

5k

1k

30µA

55

C OUT

1.2V

Color adjusted chroma signal output during D-PAL. The output level is tripled in order to compensate for the attenuation of the external U/V separation delay line. The standard burst output level is approximately 200mVp-p. Leave this pin open in modes other than D-PAL.

50µA

VCC1

GND1

55

∗

D-PAL is a demodulation method that uses an external delay line during demodulation.

S-PAL is a demodulation method that internally processes chroma demodulation.

52 APC

1.7V

APC detective filter connection. Leave this pin open when using Y/color difference mode.

1k

GND1

VCC1

52

500

56 V REG

2.0V

Smoothing capacitor connection for the internally generated constant voltage source circuit. Connect a capacitor of 1µF or more.

VCC1

GND1

18.5k

30k

56

57

C IN —

Video signal input when using composite signal input. Chroma signal input when using Y/C signal input. Leave this pin open when using Y/color difference mode.

57

50k

V

CC1

GND1

15µA

50k

5p

10p

30µA

– 8 –

CXA3017R

No.

Symbol Pin voltage Equivalent circuit Description

58

RESET

—

TG block system reset pin. The system is reset when this pin is connected to GND. Connect a capacitor between this pin and GND.

1k

V

DD1

GND1

2µA

58

300

59

Y IN

Y signal input. The standard signal input level is 0.5Vp-p (100% white level from the sync tip). Input at low impedance (75Ω or less).

VCC1

GND1

59

20µA

1k

63

F0 ADJ

1.5V

Filter reference current generation. Connect resistance of 15 kΩ between this pin and GND1 to adjust the internal filters using the outflow current value. Leave this pin open when using Y/C or Y/color difference mode.

VCC1

GND1

200

500

5p

63

500

5p

62

VSEP TC

1.7V

Capacitor connection for vertical sync separation.

VDD1

GND1

20µA

500

1k

62

1k

1.6V

61 SYNC IN

1.6V

Sync input. Normally inputs the Y signal. The standard signal input level is 0.5Vp-p (100% white level from the sync tip). Input at low impedance (75Ω or less).

VDD1

GND1

12µA

1k

61

0.6µA

500

1k

64 GND1

0V

3.0V GND.

60

TEST2

0V

Test. Connect to GND.

– 9 –

CXA3017R

No.

Symbol Pin voltage Equivalent circuit Description

Digital Block Pin Description

VSS

1k

6 7 8

5 VDD1

6 LOAD

7 DATA

8 SCLK

9 33 10

RPD VDD2 TEST1

Power supply for VCO.

Serial bus inputs.

Phase comparator output. Power supply for digital block. Test. Connect to GND.

VDD2

V

SS

11 12 13 14 15

17 18 19 20

21

22 23

24

25 26 27 28 29

30

31

11 12 13 14 15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

BLK CLR HST2 HST1 XHST1 HCK2 HCK1 XPCG PCG HD XVST VST VCK4 VCK3 VCK2 VCK1 XEN1 EN1 EN2 VD

Digital block outputs.

– 10 –

CXA3017R

Setting Conditions for Measuring Electrical Characteristics

Use the Electrical Characteristics Measurement Circuit on page 30 while measuring electrical characteristics. Also, the TG (timing generator) block must be initialized by performing Settings 1 and 2 below.

Setting 1. System reset

After turning on the power, set SW58 to ON and start up V58 from GND in order to activate the TG block system reset. (See Fig. 1-1.) The serial bus is set to the default values.

Setting 2. Horizontal AFC adjustment

Input SIG5 (VL = 0mV) to (A) and adjust serial bus register VCO so that the TP9 phase comparison output waveform (near VSYNC) is horizontal. SW48 = OFF, SW58 = ON, V58 = 3.0V (See Fig. 1-2.)

Note) When measuring a band of 2MHz or more such as Y signal frequency response or sharpness characteristics

among the items being measured, the measurement must be made with the sample-and-hold circuit set to through (sample and hold not performed) by the serial bus.

VDD

TR

TR > 10µs

V58 (PWRST)

SIG5

TP9

approximately 1/2V

DD

VSYNC VSYNC

Adjust to a horizontal waveform.

Fig. 1-1. System reset

Fig. 1-2. Horizontal AFC adjustment

– 11 –

CXA3017R

Digital block I/O characteristics

Digital block input pins

∗

1

SW57 = A (A) = SIG4, (B) = SIG2

0.3V

DD

V

VIL

Low level input voltage

Digital block input pins

∗

1

SW57 = A (A) = SIG4, (B) = SIG2

0.7V

DD

V

VIH

High level input voltage

VDD = 3.0V IOH = –1.2mA

∗

2

SW57 = A (A) = SIG4, (B) = SIG2

2.8

V

VOH1

High level output voltage

VDD = 2.7V IOH = –1.2mA

∗

2

SW57 = A (A) = SIG4, (B) = SIG2

2.6

V

IOL = 1.2mA

∗

2

SW57 = A (A) = SIG4, (B) = SIG2

0.3

V

VOL1

Low level output voltage

∗1

Digital block input pins: SCLK, DATA, LOAD

∗2

Output pins except RPD: BLK, CLR, HST2, HST1, XHST1, HCK2, HCK1, XPCG, PCG, HD, XVST, VST,

VCK4, VCK3, VCK2, VCK1, XEN1, EN1, EN2, VD

Electrical Characteristics — DC Characteristics

Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 3.0V, VCC2 = VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS = 0V, Ta = 25°C SW1/SW2/SW3 = A, SW53/SW54/SW57 = B SW58 = ON, SW48 = OFF V58 = 3.0V Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified items should be set to the default settings.

Input SIG4 to (A) and SIG2 (0dB) to (B), and measure the I

CC1 current value. COMP input mode.

SW57 = A Input SIG4 to (A) and SIG2 (0dB) to (B), and measure

the I

CC1 current value. Y/C input mode.

SW57 = A Input SIG4 to (A), (D) and (E) and measure the I

CC1

current value. Y/color difference input mode. SW53 = SW54 = A

Input SIG4 to (A) and SIG2 (0dB) to (B), and measure the I

CC2 current value.

SW57 = A Input SIG4 to (A) and SIG2 (0dB) to (B), and measure

the I

DD3 and IDD4 current values.

I

DD1 = IDD3 + IDD4, LCX009AK/AKB

SW57 = A Input SIG4 to (A) and SIG2 (0dB) to (B), and measure

the I

DD3 and IDD4 current values.

I

DD2 = IDD3 + IDD4, LCX005BK/BKB

SW57 = A

27

24

19

6

8.5

7.5

34

30

25

8

11

10

41

37

30

10

13.5

12.5

mA

I

CC11

I

CC12

I

CC13

I

CC2

I

DD1

IDD2

Item

Current characteristics

Current consumption VCC1

Current consumption V

CC2, 3

Current consumption V

DD1, 2

Symbol Conditions Min. Typ. Max. Unit

– 12 –

CXA3017R

Electrical Characteristics — AC Characteristics

Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 3.0V, VCC2 = VCC3 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS = 0V, Ta = 25°C SW1, SW2, SW3 = A SW53, SW54, SW57 = B SW58 = ON SW48 = OFF V58 = 3.0V Set the serial bus registers to the "Serial Bus Register Initial Settings". Unspecified items should be set to the default settings. Unless otherwise specified, measure the non-inverted outputs for TP40, TP43 and TP45.

19

14

–3

5.0

2.5

3.0

21

16

1

23

18

3

dB

MHz

GV

GCNTTP

GCNTMN

FCYYC

FCYCMN

FCYCMP

Item

Y signal system

Video maximum gain

Contrast characteristics TYP

Contrast characteristics MIN

Y signal frequency response

11 14

–3 0

11 14

–1

2

dB

8

11

dB

–5

–2

dB

6

9

dB

–6

–3

dB

GSHP1X

GSHP1N

GSHP2X

GSHP2N

Picture quality adjustment variable amount 1 (Y/C input) LCX009AK/AKB

Picture quality adjustment variable amount 2 (Y/C input) LCX005BK/BKB

Symbol Conditions Min. Typ. Max. Unit

Y/C input

Composite input (NTSC)

Composite input (PAL)

2.5MHz MAX

2.5MHz MIN

1.8MHz MAX

1.8MHz MIN

1.8MHz MAX

1.8MHz MIN

2.5MHz MAX

2.5MHz MIN

Input SIG4 to (A) and measure the ratio between the output amplitude (white-black) and input amplitude at TP43.

Assume the output amplitude at TP43 when SIG1 (0dB, no burst, 100kHz) is input to (A) as 0dB. Vary the frequency of the input signal to obtain the frequency with an output amplitude of –3dB. CL = 400pF

Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Obtain the amount by which the output amplitude of SIG7 (2.5MHz or

1.8MHz) changes when PICTURE is set to the MAX and MIN values.

GSHP3X

GSHP3N

GSHP4X

GSHP4N

Picture quality adjustment variable amount 3 (composite input) LCX005BK/BKB

Picture quality adjustment variable amount 4 (composite input) LCX009AK/AKB

Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Obtain the amount by which the output amplitude of SIG7 (1.8MHz or

2.5MHz) changes when PICTURE is set to the MAX and MIN values.

– 13 –

CXA3017R

Input SIG2 (0dB) to (A). Using a spectrum analyzer, measure the input and the 3.58MHz or 4.43MHz component of TP43, and obtain

CRLEKY = 150mV × 10

∆CLK/20

using their difference ∆CLK.

CRLEKY 30 mV

Carrier leak (residual carrier)

TDYYC

TDYCMN

TDYCMP

TDYDEF

260

520

100

360

620

200

460

720

300

ns

Y signal I/O delay time

Y/C input Composite input

(NTSC) Composite input

(PAL) Y/color difference input

SW53 = SW54 = A

Input SIG9 to (A). Measure the delay time from the 2T pulse peak of the input signal to the 2T pulse peak of the non-inverted output at TP43.

–3

0

3 dB

–3 0 3

dB

–3

0

3

dB

–3

±500

Hz

±500 Hz

+3 +5 dB

–25

–20

dB

0

3

dB

ACC1

ACC2

FAPC

GCOLMX

GCOLMN

Item

Chroma signal block

ACC amplitude characteristics 1

ACC amplitude characteristics 2

APC pull-in range

Color adjustment characteristics MAX

Color adjustment characteristics MIN

–30 –40 deg

30 60 deg

HUEMX

HUEMN

HUE adjustment characteristics MAX

HUE adjustment characteristics MIN

Symbol Conditions Min. Typ. Max. Unit

NTSC

PAL

NTSC

PAL

NTSC

PAL

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB/+6dB/–20dB, 3.58MHz burst/chroma phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to (B). Measure the output amplitude at TP55, assuming the output corresponding to 0dB, +6dB and –20dB as V0, V1 and V2, respectively. ACC1 = 20 log (V1/V0) ACC2 = 20 log (V2/V0)

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz burst/chroma phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to (B). Vary the SIG2 burst frequency and measure the frequency f1 at which the TP40 output appears (the killer mode is canceled). NTSC: FAPCN = f1 – 3579545Hz PAL: FAPCP = f1 – 4433619Hz

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,

3.58MHz burst/chroma phase = 180°) to (B). Assume the chroma signal amplitude at TP55 when serial bus register COLOR = 128, 255 and 0 as V0, V1 and V2, respectively. GCOLMX = 20 log (V1/V0) GCOLMN = 20 log (V2/V0)

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, burst/chroma phase variable) to (B). Assume the phase at which the output amplitude at TP40 reaches a minimum when serial bus register HUE = 128, 255 and 0 as θ0, θ1 and θ2, respectively. HUEMX = θ1 – θ0 HUEMN = θ2 – θ0 SW57 = A

– 14 –

CXA3017R

Item Symbol Conditions Min. Typ. Max. Unit

θRBN

θGBN

VRBP

VGBP

99

230

109

242

119

254

deg

0.33

0.65

0.40

0.75

0.47

0.85

deg

θRBP

θGBP

80

23290244

100

256

deg

GEXCMX

+3

+5

dB

GEXCMN

Color difference input color adjustment characteristics MAX

Demodulation output phase difference (PAL)

Demodulation output amplitude ratio (PAL)

Demodulation output phase difference (NTSC)

Color difference input color adjustment characteristics MIN

Color difference balance

–20 –15 dB

VEXCBL 0.8 1.0 1.2

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,

3.58MHz) to (B) and vary the chroma phase. Assume the phase at which the amplitude at TP40, TP43 and TP45 reaches a maximum as θB, θG and θR, respectively. θRBN = θR – θB, θGBN = θG – θB SW57 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,

4.43MHz) to (B) and vary the chroma phase. Assume the maximum amplitude at TP40 as VB, the maximum amplitude at TP43 as VG, and the maximum amplitude at TP45 as VR. VRBP = VR/VB, VGBP = VG/VB SW57 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,

4.43MHz) to (B) and vary the chroma phase. Assume the phase at which the amplitude at TP40, TP43 and TP45 reaches a maximum as θB, θG and θR, respectively. θRBP = θR – θB, θGBP = θG – θB SW57 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP40 (100kHz) when serial bus register COLOR = 128 as VC0, when COLOR = 0 as VC2, and when SIG1 is set to –10dB and COLOR = 255 as VC1. GEXCMX = 20 log (VC1/VC0) + 10 GEXCMN = 20 log (VC2/VC0) SW53 = SW54 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP40 (100kHz) as VB and the output amplitude at TP45 (100kHz) as VR. VEXCBL = VR/VB SW53 = SW54 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (level variable, 3.58MHz burst/chroma phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to (B), and measure the output amplitude at TP40. Gradually reduce the SIG2 amplitude level and measure the level at which the killer operation is activated. SW57 = A

–36 –30 dB

–36

–30

dB

ACKN

ACKP

Killer operation input level

NTSC

PAL

VGBN

VRBN

0.25

0.53

0.32

0.63

0.39

0.73

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,

3.58MHz) to (B) and vary the chroma phase. Assume the maximum amplitude at TP40 as VB, the maximum amplitude at TP43 as VG, and the maximum amplitude at TP45 as VR. VRBN = VR/VB, VGBN = VG/VB SW57 = A

Demodulation output amplitude ratio (NTSC)

– 15 –

CXA3017R

Color difference input balance adjustment R

Color difference input balance adjustment B

GEXRMX

–5

–2

dB

GEXRMN

+2

+3

dB

GEXBMX

+2

+3 dB

GEXBMN –5 –2

dB

Input SIG5 (VL = 150mV) to (A) and SIG1 (–6dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP45 (100kHz) and TP40 (100kHz) when serial bus register HUE = 128 as VR0 and VB0, respectively, when HUE = 255 as VR1 and VB1, respectively, and when HUE = 0 as VR2 and VB2, respectively. GEXRMX = 20 log (VR1/VR0) GEXRMN = 20 log (VR2/VR0) GEXBMX = 20 log (VB1/VB0) GEXBMN = 20 log (VB2/VB0) SW53 = SW54 = A

Item Symbol Conditions Min. Typ. Max. Unit

VEXGBN 0.23 0.26 0.29

0.46 0.51 0.56

VEXGRN

5.85

5.2

6.00

0

6.15

100

6.5

V

mV

V

G-Y matrix characteristics (NTSC)

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP40 (100kHz) as VEXB and the output amplitude at TP43 (100kHz) as VEXBG. VEXGBN = VEXBG/VEXB SW53 = SW54 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (E). Assume the output amplitude at TP45 (100kHz) as VEXR and the output amplitude at TP43 (100kHz) as VEXRG. VEXGRN = VEXRG/VEXR SW53 = SW54 = A

VEXGBP 0.17 0.20 0.23

0.46 0.51 0.56

VEXGRP

G-Y matrix characteristics (PAL)

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP40 (100kHz) as VEXB and the output amplitude at TP43 (100kHz) as VEXBG. VEXGBP = VEXBG/VEXB SW53 = SW54 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (E). Assume the output amplitude at TP45 (100kHz) as VEXR and the output amplitude at TP43 (100kHz) as VEXRG. VEXGRP = VEXRG/VEXR SW53 = SW54 = A

VOUT

∆VOUT

Input SIG5 (VL = 0mV) to (A). Adjust serial bus registers BRIGHT and PSIG-BRT so that the output (black-black) at TP43 and TP38 is 9Vp-p and measure the DC voltage at TP40, TP43, TP45 and TP38.

Input SIG5 (VL = 0mV) to (A). Adjust serial bus registers BRIGHT and PSIG-BRT so that the output (black-black) at TP43 and TP38 is 9Vp-p, measure the DC voltage at TP40, TP43, TP45 and TP38, and obtain the maximum difference between each of these values.

RGB signal output block

RGB signal and PSIG output DC voltage

RGB signal and PSIG output DC voltage difference

VORNG

Set V48 to 5.2V or 6.5V in the VOUT measurement conditions and confirm that ∆VOUT in the preceding item is satisfied and that |V48 – VOUT| ≤ 0.15V. SW48 = ON

SIG center variable range

– 16 –

CXA3017R

Item Symbol Conditions Min. Typ. Max. Unit

±1.3

±1.7

V

–3.0

–2.5

V

2.5

3.0

V

SBBRT

Input SIG5 (VL = 0mV) to (A) and measure the difference between the outputs (black-black) at TP40 and TP45 and the output (black-black) at TP43 when serial bus registers R-BRT = B-BRT = 0 and when R-BRT = B-BRT = 255.

Amount of change in sub-brightness

–0.6

0

0.6

dB

∆GRGB

Input SIG4 to (A) and obtain the level difference between the maximum and minimum non-inverted output amplitudes (white-black) at TP40, TP43 and TP45.

Difference in gain between RGB output signals

±1.5

±2

dB

SBCNT

Input SIG4 to (A) and measure the difference between the non-inverted outputs (white-black) at TP40 and TP45 and the non-inverted output (white-black) at TP43 when serial bus registers R-CNT = B-CNT = 0 and when R-CNT = B-CNT = 255.

Amount of change in sub-contrast

–0.3

0

0.3

dB

∆GINV

Input SIG4 to (A) and obtain the difference between the non-inverted output amplitudes (white-black) and the inverted output amplitudes at TP40, TP43 and TP45.

Difference in RGB output inverted/ non-inverted gain

300 mV

∆VBL

Input SIG4 to (A) and obtain the level difference between the maximum and minimum black levels of both the inverted and non-inverted outputs at TP40, TP43 and TP45.

Difference in black level potential between RGB output signals

UBRTMX

UBRTMN

Input SIG3 to (A) and measure the amount of change in the black level output at TP40, TP43 and TP45 when serial bus register USER-BRT is changed from 128 to 255.

Input SIG3 to (A) and measure the amount of change in the white level output at TP40, TP43 and TP45 when serial bus register USER-BRT is changed from 128 to 0.

Amount of change in user brightness

–2.5

–2.0 V

2.0

2.5

V

BRTMX

BRTMN

Input SIG3 to (A) and measure the black level output at TP40, TP43 and TP45 when serial bus register BRIGHT is changed from 128 to 255.

Input SIG3 to (A) and measure the white level output at TP40, TP43 and TP45 when serial bus register BRIGHT is changed from 128 to 0.

Amount of change in brightness

PSIGMX

PSIGMN

Input SIG3 (VL = 0mV) to (A) and measure the output (black-black) at TP38 when serial bus register PSIG-BRT = 255.

Input SIG3 (VL = 0mV) to (A) and measure the output (black-black) at TP38 when serial bus register PSIG-BRT = 0.

Amount of change in PSIG output

VLIMMX

VLIMMN

Input SIG3 to (A). Vary BLKLIM and measure the maximum value VLIMMX and minimum value VLIMMN of the voltage range (black-black) over which the black limiter operates for the TP38, TP40, TP43 and TP45 outputs. Assume the value when BLKLIM = 0 as VLIMMX, and when BLKLIM = 255 as VLIMMN.

RGB and PSIG output black limiter operation voltage

9.0

7.0

1.5

Vp-p

– 17 –

CXA3017R

Input SIG8 to (A). Adjust the non-inverted output amplitude (black-white) at TP43 to 3.5Vp-p with serial bus register CONT and the black level at TP43 to 1.5V with serial bus register RBT. Measure VG1, VG2 and VG3. Gγ1 = 20 log (VG1/0.0375) Gγ2 = 20 log (VG2/0.0375) Gγ3 = 20 log (VG3/0.0375) (See Fig. 5 for definitions of VG1, VG2 and VG3.)

Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP43 is 9Vp-p (blackblack). Read the point where the gain of the non-inverted output at TP43 changes when serial bus register γ1 = 0 and 255 from the input signal IRE level. Vγ1MN when γ1 = 0, and Vγ 1MX when γ1 = 255.

Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP43 is 9Vp-p (blackblack). Read the point where the gain of the non-inverted output at TP43 changes when serial bus register γ2 = 0 and 255 from the input signal IRE level. Vγ2MN when γ2 = 0, and Vγ 2MX when γ2 = 255.

γ gain

γ1 adjustment

variable range

γ2 adjustment variable range

Gγ1

Gγ2

Gγ3

23.0

26.0

29.0 dB

12.0 15.0 18.0 dB

18.0 22.0

26.0

dB

Vγ1MN

Vγ1MX

Vγ2MN

Vγ2MX

0 IRE

100

IRE

100

IRE

0 IRE

Item Symbol Conditions Min. Typ. Max. Unit

0

100 mV

∆VWLIM

White limiter DC voltage difference

Input SIG5 (VL = 350mV) to (A). Measure the DC voltage at TP40, TP43 and TP45 and obtain the difference versus the RGB output voltage VOUT.

3.0

Vp-p

VDROFF

RGB output range when FRP polarity inversion is stopped

Input SIG8 to (A). Assume the black limiter level of the output at TP40, TP43 and TP45 when serial bus register BRIGHT = 0 as VDRB and the white limiter level when BRIGHT = 255 as VDRW. VDROFF = VDRW – VDRB

Input SIG4 to (A) and adjust serial bus register PSIGBRT so that the output at TP38 is 9Vp-p (black-black). Measure the time it takes to change to an amplitude of 9Vp-p.

tPSIGH: rise time, tPSIGL: fall time

Load: 20000pF

PSIG transition time

tPSIGH

tPSIGL

1.5

3.0 µs

1.5

3.0

µs

Input SIG3 to (A) and measure the potential difference between the white limiter level of the TP43 output and SIGCENTER. VWLIMX when WHITELIM = 0 VWLIMN when WHITELIM = 3

RGB output white limiter operation voltage

VWLIMX

VWLIMN

1.0

1.1

1.2

V

0.45

0.55

0.65

V

Input SIG5 (VL = 0mV) to (A) and adjust BLKLIM so that the output at TP43 is 9Vp-p (black-black). Measure the DC voltage at TP40, TP43 and TP45 and obtain the difference versus the RGB output voltage VOUT.

Black limiter DC voltage difference

∆VBLIM

0

100

mV

TDSY1

TDSY2

HPLLN

HPLLP

2.3 2.6 2.9 µs

4.3

4.6

4.9

µs

±500 ±1000 Hz

NTSC

PAL

WSSEP

VSSEP

2.0 µs

40

60

mV

Input sync signal width sensitivity

Sync separation input sensitivity

HD output delay time

Horizontal pull-in range

Sync separation, TG block

Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A) and confirm that it is synchronized with the HD output at TP21. Gradually narrow the WS of SIG5 from 4.7µs and obtain the WS at which synchronization with the HD output at TP21 is lost.

Input SIG5 (VL = 0mV, WS = 4.7µs, VS variable) to (A) and confirm that it is synchronized with the HD output at TP21. Gradually reduce the VS of SIG5 from 143mV and obtain the VS at which synchronization with the HD output at TP21 is lost.

Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV) to (A) and measure the delay time with the HD output at TP21. TDSY1 is from the falling edge of the input HSYNC to the rising edge of the HD output, and TDSY2 is from the falling edge of the input HSYNC to the falling edge of the HD output.

Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV, horizontal frequency variable) to (A) and confirm that it is synchronized with the HD output at TP21. Obtain the frequency f

H at which the input and

output are synchronized by changing the horizontal frequency of SIG5 from the non-synchronized condition. HPLLN = f

H – 15734, HPLLP = fH – 15625

– 18 –

CXA3017R

Item Symbol Conditions Min. Typ. Max. Unit

ATBPF

ATRAPN

ATRAPP

DEMLPF

–18

–12

dB

–16 –10 dB

–6 –2 dB

–6

–2 dB

–40 –30 dB

–40

–30

dB

0.9

1.2

1.5 MHz

NTSC 1.5MHz

PAL 2.0MHz

NTSC 5.5MHz

PAL 6.8MHz

NTSC

PAL

Amount of BPF attenuation

Amount of TRAP attenuation

R-Y and B-Y LPF characteristics

Filter characteristics

Assume the chroma amplitude at TP55 when SIG5 (VL = 0mV) is input to (A) and SIG1 (0dB at input center frequency (3.58MHz or 4.43MHz)) is input to (B) as 0dB. Obtain the amount by which the output at TP55 is attenuated when the frequencies noted on the right are input. SW57 = A

Input SIG2 (0dB, 3.58MHz and

4.43MHz) to (A) and measure the output at TP43 with a spectrum analyzer. Assume the amplitude at TP43 during Y/C input mode as 0dB, and obtain the amount of attenuation during COMP input mode.

Assume the amplitude of the 100kHz component of the output at TP43 when SIG5 (VL = 150mV) is input to (A) and SIG2 (0dB, 3.58MHz + 100kHz) is input to (B) as 0dB. Obtain the frequency which attenuates the beat component of the output by 3dB when the SIG2 frequency is increased with respect to 3.58MHz.

– 19 –

CXA3017R

Item Symbol Conditions Min. Typ. Max. Unit

tTLH tTHL

∆T

DTYHC

30

ns

30

ns

10

ns

47 50 53

%

Output transition time (page 11

∗

2

pins)

Cross-point time difference

HCK duty

Input SIG5 (VL = 0mV) to (A) and measure the transition time for each output. Load = 50pF (See Fig. 3.) SW57 = A

Input SIG5 (VL = 0mV) to (A) and measure HCK1/HCK2, VCK1/VCK2 and VCK3/VCK4. Load = 50pF (See Fig. 4.) SW57 = A

Input SIG5 (VL = 0mV) to (A) and measure the HCK1/HCK2 duty. Load = 50pF, SW57 = A

2.7

V

VBKLTH

DA OUT output voltage

Measure the output voltage at TP23 when DA OUT = 7. I

OH = –1mA

0.3

V

VBKLTL

Measure the output voltage at TP23 when DA OUT = 0. I

OH = 1mA

EXTWT

3.0

V

180

ns

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C). Measure the difference from the black level of the outputs at TP40, TP43 and TP45. SW1 = SW2 = SW3 = B

TEXMIN

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C). Measure the minimum pulse width at which each of the outputs at TP40, TP43 and TP45 reach the white limiter. SW1 = SW2 = SW3 = B

Output white level during external RGB input

Minimum pulse width during external RGB input

VTEXTB

VTEXTW

TD1EXT

TD2EXT

0.8 1.0 1.2

V

1.8

2.0 2.2

V

50 90

130

ns

50 100 140

ns

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C). Raise the SIG6 amplitude (VL) from 0V and assume the voltage where the outputs at TP40, TP43 and TP45 go to black level as VTEXTB. Then raise the amplitude further and assume the voltage where these outputs go to white level as VTEXTW. SW1 = SW2 = SW3 = B

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V) to (C). Measure the rise delay time TD1EXT and the fall delay time TD2EXT of the outputs at TP40, TP43 and TP45. (See Fig. 2.) SW1 = SW2 = SW3 = B

External I/O characteristics

External RGB input threshold voltage

Propagation delay time between external RGB input and output

EXTBK

0

V

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V) to (C). Measure the difference from the black level of the outputs at TP40, TP43 and TP45. SW1 = SW2 = SW3 = B

Output blanking level during external RGB input

– 20 –

CXA3017R

Item Symbol Conditions Min. Typ. Max. Unit

LOAD setup time, activated by the rising edge of SCLK. (See Fig. 6.)

DATA setup time, activated by the rising edge of SCLK. (See Fig. 6.)

LOAD hold time, activated by the rising edge of SCLK. (See Fig. 6.)

DATA hold time, activated by the rising edge of SCLK. (See Fig. 6.)

SCLK pulse width. (See Fig. 6.) SCLK pulse width. (See Fig. 6.) LOAD pulse width. (See Fig. 6.)

150

156 156

1

ns

ns ns µs

ts0

ts1

th0

th1

tw1L tw1H tw2

Serial transfer block

Data setup time

Data hold time

Minimum pulse width

– 21 –

CXA3017R

Setting 2

Current characteristics

Digital block I/O characteristics

Y signal block

Description of Electrical Characteristics Measurement Methods

Serial Bus Register Initial Settings

Item

Symbol

Serial bus

Mode settings

Input

System

Panel

S/H HUE COL BRT CNT

R-

BRT

B-

BRT

γ1

γ2

DAC settings

Low level input

voltage

High level input

voltage

High level output

voltage

Low level output

voltage

Video maximum

gain

Contrast

characteristics TYP

Contrast

characteristics MIN

I

CC11

ICC12

I

CC13ICC2IDD1

IDD2

VIL

VIH

VOH1

VOL1

GV

GCNTTP

GCNTMN

COMP

Y/C

Y/color

difference

COMP

NTSC

—

501

009

005

—

1

ALL

FRP

ON

128

255

128

0

128

0

VCO

ADJ

PIC

128

BLK

LIM

0

WHITE

LIM

3

USER

-BRT

128

R-

CNT

128

B-

CNT

128

PSIG

BRT

128

DA

OUT

—

(—: don't care, ADJ: adjustment, SET: setting)

VCO must be reset when the panel mode is changed.

Horizontal AFC

adjustment

Current

consumption V

CC1

Current

consumption V

CC2, 3

Current

consumption V

DD1, 2

– 22 –

CXA3017R

Y signal blockChroma signal block

Item

Symbol

Serial bus

Mode settings

Input

System

Panel

S/H HUE

COL BRT CNT

R-

BRT

B-

BRT

γ1

γ2

DAC settings

Y signal frequency

response

Carrier leak (Y block)

Y signal I/O delay

tim

e

ACC amplitude

characteristics 1

ACC amplitude

characteristics 2

APC pull-in range

FCYYC

FCYCMN

FCYCMP

GSHP1X

GSHP1N

GSHP2X

GSHP2N

GSHP3X

GSHP3N

GSHP4X

GSHP4N

CRLEKY

TDYYC

TDYCMN

TDYCMP

TDYDEF

ACC1

ACC2

FAPC

Y/C

COMP

Y/C

COMP

Y/C

COMP

Y/color

difference

COMP

NTSC

SPAL

NTSC

—

NTSC

SPAL

—

NTSC

SPAL

NTSC

SPAL

NTSC

SPAL

009

005

009

005

009

—

ALL

FRP

ON

128

180

128

0

VCO

ADJ

PIC

180

128

255

0

255

0

255

0

255

0

128

BLK

LIM

0

WHITE

LIM

3

USER

-BRT

128

R-

CNT

128

B-

CNT

128

PSIG

BRT

128

DA

OUT

—

(—: don't care, ADJ: adjustment, SET: setting)VCO must be reset when the panel mode is changed.

Picture quality

adjustment variable

amount 1

Picture quality

adjustment variable

amount 2

Picture quality

adjustment variable

amount 3

Picture quality

adjustment variable

amount 4

– 23 –

CXA3017R

Chroma signal block

Item

Symbol

Serial bus

Mode settings

Input

System

Panel

S/H HUE COL BRT CNT

R-

BRT

B-

BRT

γ1

γ2

DAC settings

Color adjustment

characteristics MAX

Color adjustment

characteristics MIN

HUE adjustment

characteristics MAX

HUE adjustment

characteristics MIN

Killer operation

input level

Color difference

input color

adjustment

Color difference

balance

GCOLMX

GCOLMN

HUEMX

HUEMN

ACKN

ACKP

VRBN

VGBN

θRBN

θGBN

VRBP

VGBP

θRBP

θGBP

GEXCMX

GEXCMN

VEXCBL

COMP

Y/color

difference

Y/color

difference

Y/color

difference

NTSC

SPAL

NTSC

SPAL

—

ALL

FRP

ON

128

255

0

128

255

0

128

255

0

128

150

128

0

VCO

ADJ

PIC

128

BLK

LIM

0

WHITE

LIM

3

USER

-BRT

128

R-

CNT

128

B-

CNT

128

PSIG

BRT

128

DA

OUT

—

(—: don't care, ADJ: adjustment, SET: setting)VCO must be reset when the panel mode is changed.

Demodulation

output amplitude

ratio (NTSC)

Demodulation

output phase

difference (NTSC)

Demodulation

output amplitude

ratio (PAL)

Demodulation

output phase

difference (PAL)

– 24 –

CXA3017R

RGB signal output block

Item

Symbol

Serial bus

Mode settings

Input

System

Panel

S/H HUE COL BRT CNT

R-

BRT

B-

BRT

γ1

γ2

DAC settings

Color difference

input balance

adjustment R

Color difference

input balance

adjustment B

G-Y matrix

characteristics

(NTSC)

G-Y matrix

characteristics

(PAL)

RGB/PSIG output

DC voltage

RGB/PSIG output

DC voltage difference

SIG center variable

range

Amount of change

in PSIG output

GEXRMX

GEXRMN

GEXBMX

GEXBMN

VEXGBN

VEXGRN

VEXGBP

VEXGRP

VOUT

∆

VOUT

VORNG

VLIMMX

VLIMMN

PSIGMX

PSIGMN

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

Y/color

difference

—

NTSC

SPAL

—

ALL

FRP

ON

255

0

255

0

128

ADJ

80

128

255

128

0

VCO

ADJ

PIC

128

BLK

LIM

0

255

0

WHITE

LIM

3

USER

-BRT

128

R-

CNT

128

B-

CNT

128

PSIG

BRT

128

255

0

DA

OUT

—

(—: don't care, ADJ: adjustment, SET: setting)VCO must be reset when the panel mode is changed.

RGB output/PSIG

black limiter

operation voltage

Chroma signal block

– 25 –

CXA3017R

RGB signal output block

Item

Symbol

Serial bus

Mode settings DAC settings

Amount of change

in user brightness

Amount of change

in brightness

Amount of change

in sub brightness

Difference in gain

between RGB signals

Amount of change

in sub-contrast

Difference in RGB

inverted/non-inverted

gain

Difference in black

level potential

between RGB signals

γ gain

γ1 adjustment

variable range

γ2 adjustment

variable range

PSIG transition time

UBRTMX

UBRTMN

BRTMX

BRTMN

SBBRT

∆GRGB

SBCNT

∆GINV

∆VBL

Gγ1

Gγ2

Gγ3

V

γ

1MN

V

γ

1MX

V

γ

2MN

V

γ

2MX

tPSIG

—

ALL

ON

128

255

0

160

128

ADJ

80

128

255

128

ADJ

60

128

SET

128

SET

128

0

140

0

255

0

128

0

230

0

255

128

ADJ

128

0

3

255

0

128

SET

128

SET

128

SET

—

(—: don't care, ADJ: adjustment, SET: setting)VCO must be reset when the panel mode is changed.

Input

System

Panel

S/H HUE COL BRT CNT

R-

BRT

B-

BRT

γ1

γ2

FRP

VCOPIC

BLK

LIM

WHITE

LIM

USER

-BRT

R-

CNT

B-

CNT

PSIG

BRT

DA

OUT