Sony CXA2504N Datasheet

– 1 –
CXA2504N
40 pin SSOP (Plastic)
E96652A82-PS
Sample-and-Hold Driver IC for LCD
Description
The CXA2504N comprises a 6-channel sample-
Features
Built-in sample-and-hold circuit for phase matching
Sample-and-hold circuit slew rate 280V/µs (Typ.)
Driver slew rate 190V/µs (Typ.)
(for 300pF load capacitance)
Sample-and-hold circuit slew rate adjustment function
Driver slew rate adjustment function
Structure
Bipolar silicon monolithic IC
Applications
Liquid crystal projectors
Liquid crystal viewfinders
Small liquid crystal monitors
Absolute Maximum Ratings (Ta = 25°C)
Supply voltage VCC117V
VCC217V VCC37V
Input pin voltage 1 VIN1
1
Vcc1 V
Input pin voltage 2 VIN2
2
Vcc3 V
Digital input pin voltage VP∗3–0.3 to Vcc3 + 0.3 V
Operating temperature Topr –25 to +75 °C
Storage temperature Tstg –55 to +150 °C
Allowable power dissipation (Ta 25°C)
PD 1.72
4
W
Reduction rate (Ta > 25°C) 13.8∗4mW/°C
Operating Conditions
Supply voltage VCC1 15.5 ± 0.8 V
VCC2 15.5 ± 0.8 V VCC3 5.0 ± 0.5 V
1
Applies to Pins 4, 5, 6, 7, 8, 13, 14, 15, 16, 24, 26, 28, 34, 36 and 38.
2
Applies to Pins 17 and 39.
3
Applies to Pins 1, 2, 3, 18, 19, 20, 21 and 40.
4
When mounted on 40 × 40mm2square epoxy board.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 2 –
CXA2504N
Block Diagram
Level Shifter
S/H S/H
DR
Current
Setting
S/H S/H
DR
S/H S/H
DR
Level Shifter
Level Shifter
Level Shifter
S/H S/H
DR
Level Shifter
S/H S/H
DR
Level Shifter
S/H S/H
DR
Current Setting
21
22
23
24
25
26
27
28
29
30
40
39
38
37
36
35
34
31
32
33
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
SH4
SH5
SH6
BIAS IN56
IN6
IN5
BIAS IN34
IN4
GND
GND
GND
V
CC1
IN3
BIAS IN12
IN2
IN1
I SH
SH1
SH2
SH3
GND
V
CC2
SH8
BIAS OUT6
I DR
BIAS OUT5
OUT6
BIAS OUT4
OUT5
OUT4
GND
GND
SH7
V
CC3
BIAS OUT3
BIAS OUT2
OUT3
BIAS OUT1
OUT2
OUT1
– 3 –
CXA2504N
Pin Description
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
1 2
3 18 19 20
21
40
4
7
14
5
6
8
13
15
16
17
39
SH4 SH5 SH6 SH1 SH2 SH3
SH7
SH8
BIAS IN56
BIAS IN34
BIAS IN12
IN6
IN5
IN4
IN3
IN2
IN1
I SH
I DR
CH4 sampling pulse input CH5 sampling pulse input CH6 sampling pulse input CH1 sampling pulse input CH2 sampling pulse input CH3 sampling pulse input Pulse input for simultaneous
resampling of CH1, 2, and 3 Pulse input for simultaneous
resampling of CH4, 5, and 6 Inputs IN5 and 6 signal center voltage
Inputs IN3 and 4 signal center voltage
Inputs IN1and 2 signal center voltage
CH6 input
1
CH5 input
1
CH4 input
1
CH3 input
1
CH2 input
1
CH1 input
1
Sets sample-and-hold circuit current. Sample-and-hold circuit slew rate changes.
Sets output driver circuit current. Output driver circuit slew rate changes.
GND
V
CC3
21 40
2
3 18 19 20
1
100
200
200µ
VCC1
4
7
14
GND
200
20µ
5
6
13 15 16
V
CC1
GND
200
100µ
8
0V
3.0 to 5.0V
2V
11.5V
VCC3
GND
200
10k
39
17
2k
1.2V
1.2V
1
Do not input a signal of 2V or less to IN1 to IN6.
– 4 –
CXA2504N
Pin
No.
Symbol
Pin voltage
Equivalent circuit
Description
23
25
27
33
35
37
24
26
28
34
36
38
12 22
32
9 10 11 29 30
31
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
BIAS OUT1
BIAS OUT2
BIAS OUT3
BIAS OUT4
BIAS OUT5
BIAS OUT6
Vcc1 Vcc3
Vcc2 GND GND GND GND GND
GND
CH1 output
2
CH2 output
2
CH3 output
2
CH4 output
2
CH5 output
2
CH6 output
2
Inputs OUT1 signal center voltage
Inputs OUT2 signal center voltage
Inputs OUT3 signal center voltage
Inputs OUT4 signal center voltage
Inputs OUT5 signal center voltage
Inputs OUT6 signal center voltage Power supply for level shifter and
S/H circuit 5V system power supply Output driver power supply GND
3
GND
3
GND
3
GND
3
GND
3
GND
3
GND
V
CC2
10
10
23 25 27
37
35
33
24
26
38
36
34
V
CC1
GND
200
20µ
28
15.5V
5.0V
15.5V
2
Power consumption varies depending on the output signal when driving load capacitance. Be careful not to go over the package allowable power dissipation.
3
Pins 9 to 11 and 29 to 31 must be connected to GND potential; they must not be open.
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