Sony CXA2503AR Datasheet

CXA2503AR

For the availability of this product, please contact the sales office.

Decoder/Driver/Timing Generator for Color LCD Panels

Description

The CXA2503AR is an IC designed exclusively to drive color LCD panels LCX005BK/BKB and LCX009AK/AKB.

This IC greatly reduces the number of circuits and parts required to drive LCD panels by incorporating RGB decoder functions for video signals, driver functions, and a timing generator for driving panels onto a single chip.

This chip has a built-in serial interface circuit and electronic attenuators which allow various mode settings and adjustments to be performed through direct control from an external microcomputer, etc.

Features

• Color LCD panels LCX005BK/BKB and LCX009AK/

AKB driver

• Supports NTSC and PAL systems

• Supports 16:9 wide display

• Supports composite inputs, Y/C inputs and Y/color

difference inputs

• Serial interface circuit

• Electronic attenuators (D/A converter)

• BPF, trap and delay line

• Sharpness function

• 2-point γ correction circuit

• R, G, B signal delay time adjustment circuit

• Polarity inversion circuit (line inverted mode)

• Supports external RGB input

• Supports AC drive for LCD panel during no signal

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VCC1 – GND1, 3 6 V

• Analog input pin voltage VINA –0.3 to VCC1V

•Digital input pin voltage VIND –0.3 to VDD1 + 0.3V

• Operating temperature Topr –15 to +75 °C

• Storage temperature Tstg –40 to +125 °C

• Allowable power dissipation

Operating conditions

Supply voltage VCC1 – GND1, 3 4.25 to 5.25 V

Note) With substrate

64 pin LQFP (Plastic)

VCC2 – GND2 14 V VDD1 – VSS1 4.5 V VDD2 – VSS2 4.5 V

PD (Ta ≤ 75°C) 350mW

VCC2 – GND2 11.0 to 13.5 V VDD1 – VSS1 2.7 to 3.6 V VDD2 – VSS2 2.7 to 3.6 V

Size: 114.3 × 76.1 × 1.5mm Material: Glass fabric base epoxy

Note)

Applications

• LCD viewfinders

• Compact liquid crystal projectors

• Compact LCD monitors

Structure

Bipolar CMOS IC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E97910-PS

Block Diagram

49

CC1

V

+4.5V

SIG.CENTER

48

47

+12V

CXA2503AR

2

CC

FB R

V

46

45

buf

R OUT

FB G

44

FB B

G OUT

43

buf buf

41

42

B OUT

40

GND2

TEST3

TEST4

RGT

39

37

38

36

TEST2

35

LOAD

SEREAL BAS I/F

34

DATA

33

SCLK

VSS2

32

SS2

V

B-Y IN

R-Y IN

C OUT

BLK LIM

APC

VXO OUT

VXO IN

V REG

START UP

C IN

F0 ADJ

GND3

Y IN

PIC

TEST0

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

REG.

GND3

EXT COLOR & BALANCE

CLAMP

COLOR HUE

APC

VXO HUE PS

HUE

COLOR

COLOR CONT

ACC DET

BPF

ACC AMP

CLAMP

1

2

VD IN

PWRST

PAL ID

FILT ADJ

TRAP

3

TRAP

KILLER

DL 1

GND1

4

PIC CONT

GND1

PAL SW

CONTRAST

H. FILTER

5

SYNC IN

DEMOD

INT/EXT

LPF

MATRIX

CNTRAST

RGB

EXT SW

6

H.FIL OUT

R-BRT

B-BRT

7

S.SEP IN

BRT

γ -1

γ -2

8

EXT R

POL SW

SUBBRIGHT

BRIGHT

S/H

GAMMA

9

EXT G

10

EXT B

VGATE VTST

VWIN

D/A

CLP BGP SBLK

V-SEP

SYNC SEP

PLL

VCO ADJ

11

VCO ADJ

12

RPD

WIDE

HAFC PLL-COUNTER & DECODER

HGATE H-SKEW DET

SS1

V 13

14 15

1

SS

CKI

V

PALSW

HCNT H-PULSE

CKO

VPAL

HD

PD

+3V

16

FRP

1

DD

V

+3V

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

VD2

VD1

EN

VCK1

VCK2

VST

TEST1

FLD IN

FLD OUT

HD

HCK1

HCK2

HST

CLR

DD2

V

– 2 –

Pin Description

CXA2503AR

Pin No.

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

Symbol

PWRST VD IN TRAP GND1 SYNC IN H.FIL OUT S.SEP IN EXT R EXT G EXT B VCO ADJ RPD VSS1 CKI CKO

I/O Description

—

System reset

I

External vertical sync input External trap connection Analog 4.5V GND

I

Video input for sync separation

O

Video output for sync input

I

Sync separation circuit input

I

External digital input R

I

External digital input G

I

External digital input B

O

VCO adjustment voltage output

O

Phase comparator output Digital 3V GND for oscillation cell

I

Oscillation cell input

O

Oscillation cell output

Input pin for open status

16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

VDD1 VDD2 CLR HST HCK2 HCK1 HD FLD OUT FLD IN TEST1 VST VCK2 VCK1 EN VD1 VD2 VSS2

Digital 3V power supply for oscillation cell Digital 3V power supply

O

CLR pulse output

O

H start pulse output

O

H clock pulse 2 output

O

H clock pulse 1 output

O

HD pulse output

O

Field identification output

I

Field identification input Test (Leave this pin open.)

O

V start pulse output

O

V clock pulse 2 output

O

V clock pulse 1 output

O

EN pulse output

O

VD1 pulse output

O

VD2 pulse output Digital 3V GND

– 3 –

CXA2503AR

No.

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

Symbol

SCLK DATA LOAD TEST2 TEST3 TEST4 RGT GND2 B OUT FB B G OUT FB G R OUT FB R VCC2

I/O Description

I

Serial interface clock input

I

Serial interface data input

I

Serial interface load input Test (Leave this pin open.) Test (Leave this pin open.) Test (Leave this pin open.)

I

Switches between Normal scan (H) and Reverse scan (L) Analog 12V GND

O

B output

O

B signal DC voltage feedback circuit capacitor connection

O

G output

O

G signal DC voltage feedback circuit capacitor connection

O

R output

O

R signal DC voltage feedback circuit capacitor connection Analog 12V power supply

Input pin for open status

H H H

H

48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

SIG.CENTER VCC1 B-Y IN R-Y IN C OUT BLK LIM APC VXO OUT VXO IN V REG START UP C IN F0 ADJ GND3 Y IN PIC TEST0

I

RGB output DC voltage adjustment Analog 4.5V power supply

I

B-Y demodulator input (or B-Y color difference signal input)

I

R-Y demodulator input (or R-Y color difference signal input)

O

Chroma signal output

I

Black peak limiter level adjustment

O

APC detective filter connection

O

VXO output

I

VXO input

O

Constant voltage capacitor connection

O

Startup time constant connection

I

Chroma signal input

O

Internal filter adjusting resistor connection Analog 4.5V GND

I

Y signal input

I

Y signal frequency response adjustment

I

Test (Leave this pin open.)

– 4 –

(H: Pull up)

Analog Block Pin Description

CXA2503AR

No.

Symbol Pin voltage Equivalent circuit Description

1 PWRST

2 VDIN —

—

VDD2

GND1

VDD2

GND1

2µA

1

1k

TG block system reset pin. The system is reset when this pin is connected to GND. Connect a capacitor between this pin and GND.

50k

2

50k

External vertical sync signal input.

3 TRAP 2.2V

5 SYNC IN 1.5V

VCC1

GND1

VDD1

GND1

VDD2

70µA

1k

300

3

130µA

1k

External trap connection. Connect the trap between this pin and GND to remove the chroma component.

Sync input. Normally inputs the Y signal.

5

1k 30µA

20k

2.1V

The standard signal input level is 0.5Vp-p (100% white level from the sync tip).

6 H.FIL OUT 2.5V

GND1

6

input to the sync separation circuit.

Outputs the video signal for

20k

– 5 –

CXA2503AR

Pin No.

7

Symbol Pin voltage Equivalent circuit Description

S.SEP IN

8 EXT-R

9 EXT-G

10 EXT-B

1.0V

—

VDD2

GND1

VCC1

GND1

10

17k

7

Sync separation circuit input. Input the H FILTER output signal.

1.8V10µA

2.8V

External digital signal inputs. There are two threshold

30µA

8

9

300

values: Vth1 (= 1.0V) and Vth2 (= 2.0V). When one of the RGB signals exceeds Vth1, all of the RGB outputs go to black level; when an

2.7V

50k

input exceeds Vth2, only the corresponding output goes to white level.

VCO ADJ

11

41 B OUT

43 G OUT

45 R OUT

42 FB B

44 FB G

46 FB R

—

VCC2

2

2.5V

VCC2

GND2

VCC2

41 43 45

GND2

VCC2

GND2

11

42 44

46

40µA

500

50

1k

VCO adjustment voltage output.

70µA

RGB signal outputs.

Smoothing capacitor connection for the feedback circuit of RGB output DC level control. Use a low-leakage capacitor because of high impedance.

– 6 –

CXA2503AR

No.

48

Symbol Pin voltage Equivalent circuit Description

SIG. CENTER

50 B-Y IN

51 R-Y IN

6.0V

—

VCC2

GND2

VCC1

50 51

GND1

48

150k

500

30µA

300

500

10k

50µA

RGB output DC voltage control. When used with a VCC2 of 12V or more, apply 6V from an external source.

Color difference demodulation circuit inputs. Color difference signal is input when using Y/color difference input. At this time, the clamp level is approximately 2.8V. Pin 52 signal is input in other modes. (except D-PAL∗1) At this time, the DC level is approximately 2.0V.

52 C OUT 1.3V

53

BLK LIM —

54 APC

2.7V

VCC1

GND1

VCC1

53

GND1

VCC1

54

52

350µA

50k

1k

Color adjusted chroma signal output. The burst level is approximately 140mVp-p (typ.). (420mVp-p during D-PAL.)

Sets the RGB output amplitude (black-black) clip level.

APC detective filter connection.

GND1

∗1

D-PAL is a demodulation method that uses an external delay line during demodulation; S-PAL is a demodulation

method that internally processes chroma demodulation.

– 7 –

CXA2503AR

Pin No.

55 VXO OUT

56 VXO IN 3.2V VXO input.

Symbol Pin voltage Equivalent circuit Description

VCC1

2.9V VXO output.

55

400µA

GND1

VCC1

500

56

3k

3.2V

GND1

57 V REG 3.6V

58

START UP

—

59 C IN —

VCC1

GND1

VCC1

GND1

VCC1

59

GND1

57

58

500

15p

20k

60k

30k

0.5µA 1k

30µA

Smoothing capacitor connection for the internally generated constant voltage source circuit. Connect a capacitor of 1µF or more.

Prevents output of the HST and VST pulses for driving LCD panels for a certain time during power-on. Connect a capacitor between this pin and GND. When not using this pin, connect to VCC1.

Video signal input when using composite signal input. Chroma signal input when using Y/C signal input. Leave this pin open when using Y/color difference input.

– 8 –

CXA2503AR

No.

60 F0 ADJ

Symbol Pin voltage Equivalent circuit Description

2.4V

62 Y IN 3.1V

VCC1

GND1

VCC1

GND1

60

62

1k

15µA

1k

70µA

Connect resistance of 82kΩ between this pin and GND1 to adjust the internal filters using the outflow current value.

Y signal input. The standard signal input level is 0.5Vp-p (100% white level from the sync tip). Input at low impedance (75Ω or less).

63 PIC

2.25V

VCC1

63

GND1

30k

50µA

10k

20k

50µA

2.25V

Adjusts frequency response of luminance signal. Increasing the voltage emphasizes contours.

– 9 –

CXA2503AR

Setting Conditions for Measuring Electrical Characteristics

When measuring the electrical characteristics, the TG (timing generator) block must be initialized by performing Settings 1 and 2 below.

Setting 1. System reset

After turning on the power, set SW1 to ON and start up V1 from GND in order to activate the TG block system reset. (See Fig. 1-1.)

Setting 2. Horizontal AFC adjustment

Input SIG5 (VL = 0mV) to (A) and adjust serial bus register PLL ADJ so that WL and WH of the TP12 output waveform are the same. (See Fig. 1-2.)

VDD

V1 (PWRST)

SIG5

WS

T

R

R > 10µs

T

TP12

WL

WH

WL = WH

Fig. 1-1. System reset Fig. 1-2. Horizontal AFC adjustment

– 10 –

CXA2503AR

Electrical Characteristics – DC Characteristics

Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 4.5V, VCC2 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25°C SW1, SW53, SW63 = ON SW8, SW9, SW10, SW59 = A SW50, SW51 = B V53 = 0V, V63 = 2.2V Set the serial bus registers to the "Serial Bus Register Initial Settings".

Item

Power supply characteristics

CC11

I

CC12

Current consumption V

CC1

Current consumption V

CC2

I

CC13

CC2

I

IDD1

Current consumption VDD

DD2

I

Symbol Conditions Min. Typ. Max. Unit

Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the I

CC1 current value.

20

27

34

mA

COMP input mode

Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the I

CC1 current value.

19

26

33

mA

Y/C input mode

Input SIG4 to (A), (D) and (E). Measure the I SW50, SW51 = A, SW59 = B

CC1 current value.

15

21

27

mA

Y/color difference input mode

Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the I

CC2 current value.

3

5

8

mA

Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the IDD current value.

4

6

8

mA

LCX009 mode

Input SIG4 to (A) and SIG2 (0dB) to (B). Measure the I

DD current value.

3.5

5

6.5

mA

LCX005 mode

– 11 –

CXA2503AR

Item

Symbol Conditions Min. Typ. Max. Unit

Digital block I/O characteristics

Input current FLDIN pin

Input current

High level input voltage Low level input voltage

II1

II2

VIH VIL

High level output voltage Output pins except CKO

VOH1

and RPD Low level output voltage

Output pins except CKO

VOL1

and RPD High level output voltage

CKO pin Low level output voltage

CKO pin High level output voltage

RPD pin

VOH2

VOL2

VOH3

Normal input pin

VIN = V VIN = VSS

DD

Input pin with pull-up resistor VIN = VSS

3

CMOS input cell CMOS input cell

IOH = –1mA

IOL = 1mA

∗

3

∗

2

∗

2

∗

IOH = –3mA

IOL = 3mA

IOH = –0.5mA

–10

1

∗

–145

0.7V

DD

–60

–24

0.3V

2.8

0.3

DD

0.5V

VDD – 1.2

10

DD

µA

V V

V

Low level output voltage RPD pin

Output off leak current RPD pin

∗1

Input pins with pull-up resistors: SCLK, DATA, LOAD, RGT

∗2

Output pins except CKO and RPD: CLR, HST, HCK1, HCK2, HD, VD1, VD2, FLDOUT, VST, VCK1, VCK2, EN

∗3

CMOS input cells: FLDIN, SCLK, DATA, LOAD, RGT

VOL3

IOFF

IOL = 0.7mA

High impedance status VOUT = V

SS or VOUT = VDD

–40

1.0

40

V

µA

– 12 –

CXA2503AR

Electrical Characteristics – AC Characteristics

Unless otherwise specified, Settings 1 and 2 and the following setting conditions are required. VCC1 = 4.5V, VCC2 = 12.0V, GND1 = GND2 = GND3 = 0V, VDD1 = VDD2 = 3.0V, VSS1 = VSS2 = 0V, Ta = 25°C SW1, SW53, SW63 = ON SW8, SW9, SW10 = A SW50, SW51, SW59 = B V53 = 0V, V63 = 2.2V Set the serial bus registers to the "Serial Bus Register Initial Settings". Unless otherwise specified, measure the non-inverted outputs for TP41, TP43 and TP45.

Item

Y signal system

Video maximum gain

Contrast characteristics TYP

Contrast characteristics MIN

Y signal frequency characteristics

Picture adjustment variable amount 1 (composite input, LCX005 mode)

Picture adjustment variable amount 2 (composite input, LCX009 mode)

Symbol Conditions Min. Typ. Max. Unit

GV

GCNTTP

GCNTMN

FCYYC

FCYCMN

FCYCMP

GSHP1X

GSHP1N

GSHP2X

GSHP2N

Input SIG4 to (A) and measure the ratio between the output amplitude (white – black) and input amplitude at TP43.

Assume the output amplitude at TP43 when SIG1 (0dB, no burst, 100kHz) is input to (A) as 0dB. Vary the frequency of the input signal to obtain the frequency with an output amplitude of –3dB.

Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 1.8MHz and measure GSHP1X and GSHP1N as the amounts by which the output amplitude at TP43 changes when V63 = 4V and 0V, respectively.

Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 2.0MHz and measure GSHP2X and GSHP2N as the amounts by which the output amplitude at TP43 changes when V63 = 4V and 0V, respectively.

Y/C input, V63 = 1.5V

Composite input (NTSC), V63 = 2.2V

Composite input (PAL), V63 = 2.2V

19

13

–9

5.0

2.5

3.0

812

69

22

17

–5

–3 1

–4 2

25

21

–1

dB

MHz

dB

Picture adjustment variable amount 3 (Y/C input, LCX005 mode)

Picture adjustment variable amount 4 (Y/C input, LCX009 mode)

Carrier leak (residual carrier)

Y signal I/O delay time

GSHP3X

GSHP3N

GSHP4X

GSHP4N

CRLEKY

TDYYC

TDYCMN

TDYCMP

Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 1.8MHz and measure GSHP3X and GSHP3N as the amounts by which the output amplitude at TP43 changes when V63 = 4V and 0V, respectively.

Assume the output amplitude at TP43 when SIG7 (100kHz) is input to (A) as 0dB. Set SIG7 to 2.5MHz and measure GSHP4X and GSHP4N as the amounts by which the output amplitude at TP43 changes when V63 = 4V and 0V, respectively.

Input SIG2 (0dB) to (A). Using a spectrum analyzer, measure the input and the 3.58MHz or 4.43MHz component of TP43, and obtain

CRLEKY = 150mV × 10

using their difference ∆CLK.

Input SIG9 (VL = 150mV) to (A). Measure the delay time from the 2T pulse peak of the input signal to the peak of the non-inverted output at TP43.

∆CLK/20

Y/C input Composite input

(NTSC) Composite input

(PAL)

10 15

10 14

230

430

– 13 –

–1 2

–2 0

330

530

30 mV

430

630

dB

ns

CXA2503AR

Item

Chroma signal block

ACC amplitude characteristics 1

ACC amplitude characteristics 2

APC pull-in range

Symbol Conditions Min. Typ. Max. Unit

ACC1

ACC2

FAPCN

FAPCP

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB/+6dB/–20dB, 3.58MHz burst/chroma phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to (B). Measure the output amplitude at TP52, assuming the output corresponding to 0dB, +6dB and –20dB as V0, V1 and V2, respectively. ACC1 = 20 log (V1/V0) ACC2 = 20 log (V2/V0) SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz burst/chroma phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to

(B). Changing the SIG2 burst frequency, measure the frequency fl at which the TP41 output appears (the killer mode is canceled). NTSC: FAPCN = fl – 3579545Hz PAL: FAPCP = fl – 4433619Hz SW59 = A

NTSC

PAL

NTSC

PAL

NTSC

PAL

–3

–3 0 3

–3

±500

±500 Hz

0

3dB

3

dB

Hz

Color adjustment characteristics MAX

Color adjustment characteristics MIN

HUE adjustment range MAX

HUE adjustment range MIN

Killer operation input level

GCOLMX

GCOLMN

HUEMX

HUEMN

ACKN

ACKP

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB,

3.58MHz burst/chroma phase = 180°) to (B). Assume the chroma output when serial bus register COLOR = 80H, 0FFH and 0H as V0, V1 and V2, respectively. GCOLMX = 20 log (V1/V0) GCOLMN = 20 log (V2/V0) SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, burst/chroma phase variable) to (B). Assume the phase at which the output amplitude at TP41 reaches a minimum when serial bus register HUE = 80H, 0FFH and 0H as θ0, θ1 and θ2, respectively. HUEMX = θ1 – θ0 HUEMN = θ2 – θ0 SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (level variable, 3.58MHz burst/chroma phase = 180°, or 4.43MHz burst/chroma phase = ±135°) to (B), and measure the output amplitude at TP41. Gradually reduce the SIG2 amplitude level and measure the level at which the killer operation is activated. SW59 = A

NTSC

PAL

46 dB

–25

–30 –40 deg

30 60 deg

–36 –30 dB

–34

–15

–28

dB

– 14 –

CXA2503AR

Item

Demodulation output amplitude ratio (NTSC)

Demodulation output phase difference (NTSC)

Demodulation output amplitude ratio (PAL)

Demodulation output phase difference (PAL)

Symbol Conditions Min. Typ. Max. Unit

VRBN

VGBN

θRBN

θGBN

VRBP

VGBP

θRBP

θGBP

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz) to B and change the chroma phase. Assume the maximum amplitude at TP41 as VB, the maximum amplitude at TP43 as VG, and the maximum amplitude at TP45 as VR. VRBN = VR/VB, VGBN = VG/VB SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 3.58MHz) to B and change the chroma phase. Assume the phase at which the amplitude at TP41, TP43 and TP45 reaches a maximum as θB, θG and θR, respectively. θRBN = θR – θB, θGBN = θG – θB SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz) to B and change the chroma phase. Assume the maximum amplitude at TP41 as VB, the maximum amplitude at TP43 as VG, and the maximum amplitude at TP45 as VR. VRBP = VR/VB, VGBP = VG/VB SW59 = A

Input SIG5 (VL = 150mV) to (A) and SIG2 (0dB, 4.43MHz) to B and change the chroma phase. Assume the phase at which the amplitude at TP41, TP43 and TP45 reaches a maximum as θB, θG and θR, respectively. θRBP = θR – θB, θGBP = θG – θB SW59 = A

0.53

0.25

99

230 242 254 deg

0.65

0.33

80 90 100

232

0.63

0.32

109

0.75

0.40

244

0.73

0.39

119

0.85

0.47

256

deg

Color difference input color adjustment characteristics MAX

Color difference input color adjustment characteristics MIN

Color difference balance

Color difference input balance adjustment R

Color difference input balance adjustment B

GEXCMX

GEXCMN

VEXCBL

GEXRMX

GEXRMN

GEXBMX

GEXBMN

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP41 when serial bus register COLOR = 80H as VC0, when COLOR = 0H as VC2, and when SIG1 is set to –10dB and COLOR = 0FFH as VC1. GEXCMX = 20 log (VC1/VC0) + 10 GEXCMN = 20 log (VC2/VC0) SW50, SW51 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP41 as VB and the output amplitude at TP45 as VR. VEXCBL = VR/VB SW50, SW51 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (–6dB, 100kHz, no burst) to (D) and (E). Assume the output amplitude at TP45 and TP41 when serial bus register HUE = 80H as VR0 and VB0, respectively, when HUE = 0FFH as VR1 and VB1, respectively, and when HUE = 0H as VR2 and VB2, respectively. GEXRMX = 20 log (VR1/VR0) GEXRMN = 20 log (VR2/VR0) GEXBMX = 20 log (VB1/VB0) GEXBMN = 20 log (VB2/VB0) SW50, SW51 = A

46 dB

0.8

23 dB

2

–20 –15 dB

1.0

1.2

–3

–2 dB

–3

–2 dB

3

dB

– 15 –

CXA2503AR

Item

VEXGB

G-Y matrix characteristics

VEXGR

RGB signal output block

RGB signal output DC voltage

RGB signal output DC voltage difference

RGB output limiter operation voltage

VOUT

∆VOUT

VLIMMX

VLIMMN

Symbol

Conditions

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (D). Assume the output amplitude at TP41 as VEXB and the output amplitude at TP43 as VEXBG. VEXGB = VEXBG/VEXB SW50, SW51 = A

Input SIG5 (VL = 150mV) to (A) and SIG1 (0dB, 100kHz, no burst) to (E). Assume the output amplitude at TP45 as VEXR and the output amplitude at TP43 as VEXRG. VEXGR = VEXRG/VEXR SW50, SW51 = A

Input SIG5 (VL = 0mV) to (A). Adjust serial bus register BRIGHT so that the output (black-black) at TP43 is 9Vp-p and measure the DC voltage at TP41, TP43 and TP45.

Input SIG5 (VL = 0mV) to (A). Adjust serial bus register BRIGHT so that the output (black-black) at TP43 is 9Vp-p, measure the DC voltage at TP41, TP43 and TP45, and obtain the maximum difference between these values.

Input SIG3 to (A). Vary V53 and measure the maximum value VLIMMX and minimum value VLIMMN of the voltage range (black – black) over which the black limiter operates for the TP41, TP43 and TP45 outputs. Assume the value when V53 = 0V as VLIMMX, and when V53 = 4.5V as VLIMMN.

NTSC

PAL

Min. Typ. Max. Unit

0.23

0.17

0.48 0.53 0.58

5.85

9.0 Vp-p

0.25

0.19

6.00

0

0.28

0.21

6.15

100

mV

5.2 Vp-p

V

Amount of change in brightness

Amount of change in sub-brightness

Difference in gain between RGB output signals

Difference in RGB output inverted/ non-inverted gain

Difference in black level potential between RGB output signals

BRTMX

BRTMN

SBBRT

∆GRGB

∆GINV

∆VBL

Input SIG5 (VL = 0mV) to (A) and measure the output (black – black) at TP41, TP43 and TP45 when serial bus register BRIGHT = 0H.

Input SIG5 (VL = 0mV) to (A) and measure the output (black – black) at TP41, TP43 and TP45 when serial bus register BRIGHT = 0FFH.

Input SIG5 (VL = 0mV) to (A) and measure the difference between the outputs (black-black) at TP41 and TP45 and the output (black – black) at TP43 when serial bus registers R-BRT = B-BRT = 0H and when R-BRT = B-BRT = 0FFH.

Input SIG4 to (A) and obtain the level difference between the maximum and minimum non-inverted output amplitudes (white – black) at TP41, TP43 and TP45.

Input SIG4 to (A) and obtain the level difference between the non-inverted output amplitudes (white – black) and the inverted output amplitudes at TP41, TP43 and TP45.

Input SIG4 to (A) and obtain the level difference between the maximum and minimum black levels of both the inverted and non-inverted outputs at TP41, TP43 and TP45.

9.0 Vp-p

±1.5

–0.5

±2.0

0

4.0

0.5

300

Vp-p

V

dB

mV

– 16 –

CXA2503AR

Item

γ gain

γ1 adjustment variable

range

γ2 adjustment variable range

Filter characteristics

Symbol Conditions Min. Typ. Max. Unit

Gγ1

Gγ2

Gγ3

Vγ1MN

Vγ1MX

Vγ2MN

Vγ2MX

Input SIG8 to (A). Adjust the non-inverted output black level at TP43 to 6 – 4.5V with serial bus register BRIGHT and the noninverted output amplitude (white – black) at TP43 to 3.5V with serial bus register CONTRAST. Measure VG1, VG2 and VG3. Gγ1 = 20 log (VG1/0.0357) Gγ2 = 20 log (VG2/0.0357) Gγ3 = 20 log (VG3/0.0357) (See Fig. 5 for definitions of VG1, VG2 and VG3.)

Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP43 is 9Vp-p (black – black). Read the point where the gain of the non-inverted output at TP43 changes when serial bus register γ1 = 0H and 0FFH from the input signal IRE level. Vγ1MN when γ1 = 0H, and Vγ1MX when γ1 = 0FFH.

Input SIG8 to (A) and adjust serial bus register BRIGHT so that the output at TP43 is 9Vp-p (black – black). Read the point where the gain of the non-inverted output at TP43 changes when serial bus register γ2 = 0H and 0FFH from the input signal IRE level. Vγ2MN when γ2 = 0H, and Vγ2MX when γ2 = 0FFH.

23.0

12.0

18.0

100 IRE

26.0 29.0

15.0 18.0

22.0 26.0

0 IRE

dB

Amount of BPF attenuation

Amount of TRAP attenuation

R-Y, B-Y and LPF characteristics

Sync separation, TG block

Input sync signal width sensitivity

ATBPF

ATRAPN

ATRAPP

DEMLPF

WSSEP

Assume the chroma amplitude at TP52 when SIG5 (VL = 0mV) is input to (A) and SIG1 (0dB at input center frequency (3.58MHz or 4.43MHz)) is input to (B) as 0dB. Obtain the amount by which the output at TP52 is attenuated when the frequencies noted on the right are input. SW59 = A

Input SIG2 (0dB, 3.58MHz or 4.43MHz) to (A) and measure the output at TP43. Assume the amplitude at TP43 during Y/C input mode as 0dB, and obtain the amount of attenuation during COMP input mode.

Assume the amplitude of the 100kHz component of the output at TP43 when SIG5 (VL = 150mV) is input to (A) and SIG2 (0dB, 3.58MHz + 100kHz) is input to (B) as 0dB. Obtain the frequency which attenuates the beat component of the output by 3dB when the SIG2 frequency is increased with respect to 3.58MHz.

Input SIG5 (VL = 0mV, VS = 143mV, WS variable) to (A) and confirm that it is synchronized with the HD output at TP22. Gradually narrow the WS of SIG5 from 4.7µs and obtain the WS at which synchronization with the HD output at TP22 is lost.

NTSC 1.5MHz

PAL 2.0MHz

NTSC 5.5MHz

PAL 6.8MHz

NTSC

PAL

0.8 1.0 1.3 MHz

2.0

–16 –10 dB

–7 –2 dB

–8 –3 dB

–40

–30 dB

–40 –30 dB

µs

Sync separation input sensitivity

VSSEP

Input SIG5 (VL = 0mV, WS = 4.7µs, VS variable) to (A) and confirm that it is synchronized with the HD output at TP22. Gradually reduce the VS of SIG5 from 143mV and obtain the VS at which synchronization with the HD output at TP22 is lost.

– 17 –

40 60 mV

CXA2503AR

Item

Sync separation output delay time

Horizontal pull-in range

Output transition time

∗

2

(

pins)

Cross-point time difference

HCK duty

Symbol Conditions Min. Typ. Max.

TDSYL

Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV) to (A) and measure the delay time with the RPD output at TP12. TDSYL is

430

630 830

from the falling edge of the input HSYNC to the falling edge of

TDSYH

the RPD output at TP12, and TDSYH is from the falling edge of the input HSYNC to the rising edge of the RPD output at TP12.

4.7

5.0 5.3

Input SIG5 (VL = 0mV, WS = 4.7µs, VS = 143mV,

HPLLN

horizontal frequency variable) to (A) and confirm that

NTSC

±500

it is synchronized with the HD output at TP22. Obtain the frequency fH at which the input and output are synchronized by changing the horizontal frequency

HPLLP

of SIG5 from the non-synchronized condition. HPLLN = fH – 15734

PAL

±500

HPLLP = fH – 15625

tTLH

Input SIG5 (VL = 0mV) to (A). Load = 30pF

tTHL

(See Fig. 3.) Input SIG5 (VL = 0mV) to (A).

∆T

Measure HCK1/HCK2 and VCK1/VCK2. Load = 30pF (See Fig. 4.)

Input SIG5 (VL = 0mV) to (A).

DTYHC

Measure the HCK1/HCK2 duty.

47 50 53

Load = 30pF

30 30

10

Unit

ns

µs

Hz

ns ns

ns

%

External I/O characteristics

VTEXTB

External RGB input threshold voltage

VTEXTW

Propagation delay time

TD1EXT between external RGB input and output

TD2EXT

Output blanking level during external RGB

EXTBK input

Output white level during external RGB input

EXTWT

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL variable) to (C). Raise the SIG6 amplitude (VL) from 0V and assume the

0.8 1.0 1.2

voltage where the outputs at TP41, TP43 and TP45 go to black level as VTEXTB. Then raise the amplitude further and assume the voltage where these outputs go to white level as VTEXTW.

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 3V) to (C). Measure the rise delay time TD1EXT and the fall delay

1.8 2.0 2.2

50 100 150

time TD2EXT of the outputs at TP41, TP43 and TP45. (See Fig. 2.)

50

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 1.7V) to (C). Measure the difference from the black level of the outputs at TP41, TP43 and TP45.

Input SIG5 (VL = 0mV) to (A) and SIG6 (VL = 2.7V) to (C). Measure the difference from the black level of the outputs

3.5

at TP41, TP43 and TP45.

100 150

0

V

ns

V

– 18 –

CXA2503AR

Item

Serial transfer block

Data setup time

Data hold time

Minimum pulse width

Other

AFC adjustment voltage output range

Symbol Conditions Min. Typ. Max. Unit

ts0

ts1

th0

th1

tw1L

tw1H

tw2

VPLLMN

VPLLTP

VPLLMX

LOAD setup time, activated by the rising edge of SCLK. (See Fig. 6.)

DATA setup time, activated by the rising edge of SCLK. (See Fig. 6.)

LOAD hold time, activated by the rising edge of SCLK. (See Fig. 6.)

DATA hold time, activated by the rising edge of SCLK. (See Fig. 6.)

SCLK pulse width. (See Fig. 6.) SCLK pulse width. (See Fig. 6.) LOAD pulse width. (See Fig. 6.)

Measure the DC voltage of the output at TP11 when serial bus register PLL ADJ = 0H, 80H and 0FFH as VPLLMN, VPLLTP and VPLLMX, respectively.

5.65

9.15

150

1

7.4

160 160

5.8

7.5

9.3

5.95

7.6

9.45

ns

ns ns µs

V

– 19 –

γ2

0H

γ1

0H

80H

B-BRT

80H

R-BRT

DAC settings

80H

CONTRAST

80H

BRIGHT

80H

COLOR

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

CXA2503AR

0H

80H

(—: don't care, ADJ: adjustment, SET: setting)

80H

Serial bus

Mode settings

80H

HUE

0H

HD-POSI

10H

H-POSI

S/H

SHS1

—

Panel

NTSC

System

Input

COMP

80H

0H

10H

SHS1

—

NTSC

COMP

ICC11

80H

0H

10H

SHS1

—

NTSC

Y/C

Y/color

ICC12

80H

0H

10H

SHS1

—

NTSC

COMP

difference

CC13

I

ICC2

80H

0H

10H

SHS1

LCX009

LCX005

NTSC

COMP

IDD1

IDD2

80H

0H

10H

SHS1

—

NTSC

COMP

II1

80H

0H

10H

SHS1

—

NTSC

COMP

II2

80H

0H

10H

SHS1

—

NTSC

COMP

VIH

80H

0H

10H

SHS1

—

NTSC

COMP

VIL

VOH1

80H

0H

10H

SHS1

—

NTSC

COMP

VOL1

80H

0H

10H

SHS1

—

NTSC

COMP

VOH2

VOL2

80H

0H

10H

SHS1

—

NTSC

COMP

VOH3

80H

0H

10H

SHS1

—

NTSC

COMP

VOL3

80H

0H

10H

SHS1

—

NTSC

COMP

IOFF

CC1

Item Symbol

Horizontal AFC adjustment

Current consumption V

Setting 2

Description of Electrical Characteristics Measurement Methods

Serial Bus Register Initial Values

Current consumption VCC2

Current consumption VDD

Input current

High level input voltage

Low level input voltage

Power supply characteristics

– 20 –

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

High level output voltage

Low level output voltage

Digital block I/O characteristics

Output off leak current

0H

γ1 γ2

0H

80H

B-BRT

80H

R-BRT

DAC settings

0FFH

CONTRAST

80H

BRIGHT

80H

COLOR

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

CXA2503AR

0H

80H

(—: don't care, ADJ: adjustment, SET: setting)

80H

Serial bus

Mode settings

80H

HUE

0H

HD-POSI

10H

H-POSI

S/H

Through

—

Panel

NTSC

System

Input

COMP

GV

80H

0H

10H

Through

—

NTSC

COMP

GCNTTP

80H

0H

10H

Through

—

LCX009

NTSC

Y/C

COMP

GCNTMN

FCYYC

80H

0H

10H

Through

LCX005

PAL

NTSC

COMP

FCYCMN

FCYCMP

80H

0H

10H

Through

LCX005

NTSC

COMP

GSHP1X

GSHP1N

80H

0H

10H

Through

LCX009

NTSC

COMP

GSHP2X

GSHP2N

80H

0H

10H

Through

LCX005

NTSC

Y/C

GSHP3X

GSHP3N

80H

0H

10H

Through

LCX009

NTSC

Y/C

GSHP4X

GSHP4N

80H

0H

10H

Through

—

Y/C

COMP

CRLEKY

TDYYC

80H

0H

10H

Through

—

PAL

NTSC

COMP

TDYCMN

TDYCMP

Item Symbol

Video maximum gain

Contrast characteristics

TYP

Contrast characteristics

MIN

Y signal frequency

response

Picture quality

adjustment variable

amount 1

Picture quality

adjustment variable

amount 2

Picture quality

adjustment variable

amount 3

Y signal block

– 21 –

Picture quality

adjustment variable

amount 4

Carrier leak

Y signal I/O delay time

0H

γ1 γ2

0H

80H

B-BRT

80H

R-BRT

DAC settings

80H

CONTRAST

80H

BRIGHT

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

0H

80H

96H

0H

80H

96H

0H

80H

96H

0H

80H

96H

0H

80H

96H

0H

80H

96H

0H

80H

96H

0H

80H

96H

0H

80H

96H

0H

80H

96H

CXA2503AR

0H

80H

96H

(—: don't care, ADJ: adjustment, SET: setting)

Serial bus

Mode settings

80H

COLOR

80H

HUE

0H

HD-POSI

10H

H-POSI

S/H

Through

—

Panel

NTSC

System

Input

COMP

80H

0H

10H

Through

—

PAL

NTSC

COMP

80H

0H

10H

Through

—

PAL

NTSC

COMP

80H

0FFH

80H

0H

10H

Through

—

PAL

NTSC

COMP

0H

80H

0H

10H

Through

—

NTSC

COMP

80H

0FFH

0H

10H

Through

—

NTSC

COMP

80H

0H

80H

0H

10H

Through

—

NTSC

COMP

80H

0H

10H

Through

—

PAL

NTSC

COMP

80H

0H

10H

Through

—

NTSC

COMP

80H

0H

10H

Through

—

PAL

NTSC

COMP

80H

0H

10H

Through

—

PAL

COMP

80H

0H

10H

Through

—

PAL

COMP

Item Symbol

ACC1

ACC2

ACC amplitude

characteristics 1

ACC amplitude

characteristics 2

ACC2

FAPCN

APC pull-in range

FAPCP

GCOLMX

Color adjustment

characteristics MAX

GCOLMN

HUEMX

Color adjustment

characteristics MIN

HUE adjustment

characteristics MAX

HUE adjustment

– 22 –

HUEMN

ACKN

ACKP

VRBN

characteristics MIN

Killer operation input

level

Demodulation

Chroma signal block

VGBN

θRBN

θGBN

output amplitude

ratio NTSC

Demodulation

output phase

difference NTSC

VRBP

VGBP

θRBP

Demodulation

output amplitude

ratio PAL

Demodulation

output phase

θGBP

difference PAL