Sony CXA2153S Datasheet
CXA2153S
Preamplifier for High Resolution Computer Display
Description
The CXA2153S is a bipolar IC developed for high
resolution computer displays.
Features
• Built-in wide-band amplifier: 180MHz@–3dB (Typ.)
• Input dynamic range: 1.0Vp-p (Typ.)
• High gain preamplifier (15dB)
• R, G and B incorporated in a single package
(SDIP 30 pins)
• I2C bus control
Contrast control
R/G/B drive control
Brightness control
OSD contrast control
4-channel DAC control output
• Built-in gamma function
• Built-in high-speed ABL blanking
• Built-in sync separator for Sync on Green
• Built-in blanking mixing function
(with blanking level fixed at 0.4V)
• Built-in OSD mixing function
• Video period detection function
• Built-in VBLK synchronous DAC refresh system
Applications
High resolution computer displays
Structure
Bipolar silicon monolithic IC
Absolute Maximum Ratings (Ta = 25°C, GND = 0V)
• Supply voltage Vcc12 13 V
Vcc5 5.5 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation
P
D 2.05 W
• Pin voltage Vcc5 + 0.3V
1, 3, 4, 6, 7, 8, 9, 10, 11,
12, 13, 14, 15, 16, 17 (Pin)
VREF (Pin 23) + 0.3V
18, 19, 20, 21, 25, 27,
29 (Pin)
Recommended Operating Conditions
Supply voltage Vcc12 12 ± 0.5 V
Vcc5 5 ± 0.25 V
– 1 –
E99X02A1Y-PS
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
30 pin SDIP (Plastic)
– 2 –
CXA2153S
Block Diagram
I
2
C Bus
Decoder
Clamp
BIN
GIN
RIN
ABL
SCL
SDA
Rch
Gch
Bch
Latch
LPF
D/A
Converter
Regulator
BRIGHTNESSRch
AMP
Blanking Mix
OSD/OSD_BLK
Mix
DRIVE
OSD GAIN
G2
B_BKG
G_BKG
R_BKG
V
CC12
VREF
SYNCIN
SHP GAIN/
SHP WIDTH
Contrast
Video
Detector
Gain Control
AMP
Gch (Same as Rch)
BLK
Bch (Same as Rch)
VDET LEVEL/VDET OFF
Sharpness
Clamp
Clamp
ROUT
BLK
GOUT
BOUT
OSD_BLK
OSD_R
OSD_G
OSD_B
VDET
CLP
SYNCOUT
BufferGamma
SYNC SEP.
SYNC OFF
ABL
GAMMA1/GAMMA2/GM OFF
POL1/POL2
18
19
20
21
22
23
4
12 29 14 27 25
8
9
10
11
15
13
63171716
– 3 –
CXA2153S
Pin Configuration
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VCC12
ROUT
GND_R
GOUT
GND_G
BOUT
GND_B
VREF
V
CC12
R_BKG
G_BKG
B_BKG
G2
SCL
SDA
RIN
V
CC5
GIN
SYNCIN
GND
BIN
ABL
OSD_BLK
OSD_R
OSD_G
OSD_B
SYNCOUT
CLP
BLK
VDET
– 4 –
CXA2153S
Pin Description
Pin
No.
Symbol Pin voltage Equivalent circuit Description
1
3
6
RIN
GIN
BIN
3.1V
(CLAMP)
RGB signal inputs.
Input via the capacitor.
7 ABL
2.5V
(when
open)
ABL input.
8 OSD_BLK
OSD_BLK control input.
VILMAX = 0.8V
VIHMIN = 2.8V
4 SYNCIN 2.9V
Sync-on-green signal input.
Input via the capacitor.
2 Vcc5 5V 5V power supply.
5 GND GND
1
6
3
VCC
VCC
VCC
1k
1k
1k
4
VCC
VCC
VCC
100
150
VCC
5V
20k
10k
10k
500 5002k
VCC VCCVCC
7
8
VCC
30k
5k
VCC
5k
– 5 –
CXA2153S
9
10
11
OSD_R
OSD_G
OSD_B
OSD control input.
VILMAX = 0.8V
VIHMIN = 2.8V
12 SYNCOUT
Sync separator output of Syncon-green signal.
I
2
C bus SOG off: Output at 0.
Typ.: High = 4.2V
Low = 0.2V
(positive polarity)
13 CLP
Clamp pulse (positive polarity)
input.
VILMAX = 0.8V
VIHMIN = 2.8V
14 BLK
Blanking pulse input.
Set the V blanking pulse width
to 300µs or more.
VILMAX = 1.2V
VIHMIN = 4.7V
10
9
11
VCC
30k
VCCVCC
5k5k
12
VCC
VCCVCC
100
200
20k
5k
VCC
200
13
VCC
30k
VCC
14
VCC
30k
VCCVCC
5k5k
Pin
No.
Symbol Pin voltage Equivalent circuit Description
– 6 –
CXA2153S
15 VDET
Video detector output.
I2C bus VDET off: Output at 0.
16
SDA
I
2
C bus standard SDA (serial
data) input/output.
VILMAX = 1.5V
VIHMIN = 3.5V
VOLMAX = 0.4V
15
VCC
VCCVREF
100
200
20k
10k
VCC
200
16
4k
VCC
17
SCL
I2C bus standard SCL (serial
clock) input.
VILMAX = 1.5V
VIHMIN = 3.5V
17
4k
10k
VCC
21
20
19
18
R_BKG
G_BKG
B_BKG
G2
BKG/G2 adjustment DAC
outputs.
The output DC is 1.5 to 5.5V.
22
30
Vcc12 12V
12V power supply
20
21
19
18
VCC
VREG VREG
1k100
1k100
Pin
No.
Symbol Pin voltage Equivalent circuit Description
– 7 –
CXA2153S
23 VREF 9V
9V regulator.
Connect with Vcc12 via a
resistor of around 220Ω.
It cannot be used as an
external power supply.
28
26
24
GND_R
GND_G
GND_B
0V GNDs
29
27
25
ROUT
GOUT
BOUT
R, G and B signal outputs.
VCC12
Band Gap
VCC12
23
27
29
25
VCC
VCC12 VREG
Pin
No.
Symbol Pin voltage Equivalent circuit Description
– 8 –
CXA2153S
I2C BUS Register Definitions
Slave Address
SLAVE RECEIVER: 40 (HEX)
Register Table
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
CONTRAST
BRIGHTNESS
R_BKG
G_BKG
B_BKG
OSD GAIN
G2
R_DRV
G_DRV
B_DRV
Sub Address BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
∗∗
SHP WIDTH SHP GAIN
POL1 GAMMA1 POL2 GAMMA2
∗∗
VDET LVL VDET OFF SOG OFF GAM OFF 0 D R OFF
∗: Don't Care
Sub Address 0000 CONTRAST (8) Controls the gain common to the R, G and B channels. Since control is
performed by multiplying with R/G/B DRIVE, the white balance can be
adjusted by R/G/B DRIVE and the luminance can be adjusted by
CONTRAST.
0: Output level minimum (0Vp-p)
255: Output level maximum (4.4Vp-p; with 0.7Vp-p input)
Sub Address 0001 BRIGHTNESS (8)Controls the black level common to the R, G and B channels.
0: Black level minimum (0.8V)
255: Black level maximum (2.9V)
Sub Address 0010 R_BKG (8) Controls Pin 21 (R BACKGROUND) output voltage.
0: Output voltage minimum (1.5V)
255: Output voltage maximum (5.5V)
Sub Address 0011 G_BKG (8) Controls Pin 20 (G BACKGROUND) output voltage.
0: Output voltage minimum (1.5V)
255: Output voltage maximum (5.5V)
Sub Address 0100 B_BKG (8) Controls Pin 19 (B BACKGROUND) output voltage.
0: Output voltage minimum (1.5V)
255: Output voltage maximum (5.5V)
Loading...