Sony CXA2094Q Datasheet

– 1 –

CXA2094Q

48 pin QFP (Plastic)

E97725A86

US Audio Multiplexing Decoder

Description

The CXA2094Q is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction. Various kinds of filters are built in while adjustment and mode control are all executed through I2C BUS.

Features

• Adjustment free of VCO and filter.

• Audio multiplexing decoder and dbx noise

reduction decoder are all included in a single chip.

Almost any sort of signal processing is possible

through this IC.

• All adjustments are possible through I2C BUS to

allow for automatic adjustment.

• Various built-in filter circuits greatly reduce external

parts.

• There are two systems for external inputs.

• There is an additional SAP output.

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VCC 11 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 0.6 W

Range of Operating Supply Voltage

9 ± 0.5 V

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

∗ A license of the dbx-TV noise reduction system is required for the use of this device.

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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25

2627

28

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40

39

38

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35

34

31

32

33

41 42

43 44 45 46 47 48

1

SDA

SCL

DGND

MANIN

NC

COMPIN

NC

PCINT2

PCINT1

VCATC

VCAIN

VEOUT

VETC

VEWGT

NC

VE

SAPIN

NC

SAPOUT

TVOUT-L

TVOUT-R

AUX2-L

TVOUT-S

AUX2-R

AUX1-L

AUX1-R

ESAPIN

SOUT

VCAWGT

NC

VGR

NC

GND

SAPTC

V

CC

SUBOUT

STIN

MAINOUT

PLINT

IREF

NC

NOISETC

NC

Standard I/O Level

• Input level

COMPIN (Pin 12) 100mVrms

245mVrms (Selected by INSW) AUX1-L/R (Pins 42 and 41) 490mVrms AUX2-L/R (Pins 45 and 44) 490mVrms

• Output level TVOUT-L/R (Pins 47 and 46) 490mVrms

Pin Configuration (Top View)

– 2 –

CXA2094Q

Block Diagram

VGR

IREF

DGND

SCL

SDA

SAPOUT

SAPIN

STIN

VE

VEWGT

VETC

VEOUT

VCAIN

VCAWGT

VCATC

MAININ

MAINOUT

SUBOUT

PLINT

PCINT1

COMPIN

V

CC

GND

NOISETC

SAPTC

AUX2-L

IREF

SW

LPF LPF

HPF

RMSDET

VCAVEDeEm

LOGIC

VCA

LPF

1/2

1/4VCOLFLT

STLPF

VCA LPF

BPF

SAPVCO

LPF

NOISE

DET

SAPIND

"PONRES"

STIND

"SAP"

"NOISE"

NRSW/FOMO/SAPC

WIDEBAND

SPECTRAL

"STEREO"

DeEm

FLT

AMP

(+4dB)

I

2

C BUS I/F

(+6dB)

AUX1-R AUX1-L

AUX2-R

PCINT2

TVSW

TVOUT-L

TVOUT-R

FEXT2

FEXT1

TVSW/EXT/M1

33 32

28

24

ATT/INSW

8

9

11

12

23

18

17

14

25

15

20

2

1

48

27

34

36

35

37

46

47

44

45

41 42

3

4

22

40

MATRIX

39

LPF

38

TVOUT-S

ESAPIN

SOUT

– 3 –

CXA2094Q

Pin Description (Ta = 25°C, VCC = 9V)

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

SCL

DGND

MAININ

—

4.0V

Serial clock input pin. VIH > 3.0V VIL < 1.5V

Digital block GND.

Input the (L + R) signal from MAINOUT (Pin 4).

1

2

3

MAINOUT

NC

4.0V

—

(L + R) signal output pin.

—

VCC

147

1k

15k

↓

200µ

V

CC

× 4

4

5

NC

—

6

NC

—

7

10.5k

VCC

7.5k

↓ 35µ

2.1V

× 4

4k

3k

1

2

VCC

10k

VCC

147

3

53k

4V

– 4 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit

Description

PCINT1

PCINT2

PLINT

4.0V

5.1V

Stereo block PLL loop filter integrating pin.

Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.)

VCC

147

20k

↓

26µ

20k

10k

20k

↓

50µ

20k

11

22k

VCC

30k

147

8

4k

VCC

× 2

10k

2k

147

9

8

9

11

COMPIN 4.0V

Audio multiplexing signal input pin.

12

VCC

12

24k

4V

34k

14k 147

24k 24k

NC

—

10

NC

—

13

– 5 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

VGR

IREF

GND

1.3V

—

Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.)

Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62kΩ (±1%) resistor between this pin and GND.)

Analog block GND.

Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.)

14

15

17

SAPTC

4.5V

18

8k

4k

3k

10k

VCC

↓ 50µ

1k

VCC

18

17

40k 40k 30k

30p

1.8k

16k

6.3k

147

30k 15k 30k

VCC

× 2

V

CC

15

× 4

11k

9.7k

19.4k

2.06k

3k

147

VCC

11k

14

NC

—

16

NC

—

19

VCC

—

Supply voltage pin.

20

NC

—

21

– 6 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

SUBOUT

STIN

NOISETC

4.0V

3.0V

(L-R) signal output pin.

Input the (L-R) signal from SUBOUT (Pin 22).

Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.)

22

23

SAPIN

4.0V

Input the (SAP) signal from SAPOUT (Pin 25).

27

24

2k

4k

1k

147

580

14.4k

580

4k

10P

2k2k

Vcc

22

23k

147

18k

20k

11.7k

23k

4V

147

18k

4V

VCC

23

27

3k

3.3k

4k

4V

Vcc

8k

× 2

10k

1k

2k

Vcc

200k

24

SAPOUT 4.0V

SAP FM detector output pin.

25

24k ↓ 10µ

580

Vcc

5P

580

4k ↓ 50µ

10k

147

25

– 7 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

VE

VETC

4.0V

1.7V

Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3kΩ resistor in series between this pin and GND.)

Determine the restoration time constant of the variable de-emphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3µF capacitor between this pin and GND.)

28

VEWGT

4.0V

Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047µF capacitor and a 3kΩ resistor in series between this pin and GND.)

32

33

Vcc

4V

36k

2.9V

580

147

580

8k

30k ↓ 8µ

4k ↓ 50µ

32

20k ↓ 7.5µ

4k ↓ 50µ

Vcc

× 4

33

7.5k

147

VCC

28

NC

—

26

NC

—

29

NC

—

30

NC

—

31

– 8 –

CXA2094Q

No.

Symbol

Pin voltage

Equivalent circuit

Description

VEOUT

VCAIN

VCAWGT

4.0V

Variable de-emphasis output pin. (Connect a 4.7µF non-polar capacitor between Pins 34 and 35.)

VCA input pin. Input the variable de-emphasis output signal from Pin 34 via a coupling capacitor.

Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.)

34

35

VCATC

1.7V

Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.)

36

37

Vcc

10k

580

5P

34

4k

VCC

30k

8k

36k

2.9V

3p

580

147

40k 40k

↓

50µ

↓

8µ

37

↓

50µ

VCC

4k

20k

× 4

↓

7.5µ

36

VCC

20k

VCC

47k

35

– 9 –

CXA2094Q

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

ESAPIN

4.0V

Additional SAP output pin.

Input the signal from SOUT (Pin 38).

SOUT

4.0V

38

39

VCC

15k

VCC

× 4

1k

38

↓

200µ

VCC

4V

147

47k

10k

39

AUX1-R

4.0V

Right channel external input 1 pin.

41

AUX1-L

4.0V

Left channel external input 1 pin.

42

AUX2-R

4.0V

Right channel external input 2 pin.

44

AUX2-L

4.0V

Left channel external input 2 pin.

45

VCC

4V

27.5k

47k

10k

41 42 44 45

TVOUT-S

4.0V

Optional output pin. From this pin monaural or additional SAP is output.

40

TVOUT-R

4.0V

TVOUT right channel output pin.

46

TVOUT-L

4.0V

TVOUT left channel output pin.

47

3k

580

VCC

46 47

40

43

NC

—

43

– 10 –

CXA2094Q

No.

Symbol

Pin voltage

Equivalent circuit Description

7.5k

4.5k

× 5

4k

3k

7.5k

V

CC

↓ 35µ

2.1V

× 2

48

SDA

—

Serial data I/O pin. VIH > 3.0V VIL < 1.5V

48