Sony CXA2069Q Datasheet
—1—
E96Y05B81
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage VCC 12 V
• Operating temperature
Topr –20 to +75 °C
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation
PD 1300 mW
Operating Conditions
Supply voltage 9±0.5 V
Description
The CXA2069Q is a 7-input, 3-output audio/video
switch featuring I2C bus compatibility for TVs. This
IC has input pins that are compatible with S2
protocol.
Features
• 4 inputs that are compatible with S2 protocol
• Serial control with I2C bus
• 7 inputs, 3 outputs
• The desired inputs can be selected independently
for each of the 3 outputs
• Wide band video amplifier (20 MHz, –3 dB)
• Y/C MIX circuit
• Slave address can be changed (90H/92H)
• Audio muting from external pin
• High impedance maintained by I2C bus lines (SDA,
SCL) even when power is OFF
• Wide audio dynamic range (3 Vrms typ.)
Applications
Audio/video switch featuring I2C bus compatibility
for TVs
Structure
Bipolar silicon monolithic IC
S2-Compatible 7-Input 3-Output Audio/Video Switch
64 pin QFP (Plastic)
CXA2069Q
—2—
CXA2069Q
Block Diagram
TV
V1
V2
V3
V4
V5
V6
8
15
30
22
60
63
1
53
6dB
6dB
6dB
6dB
6dB
6dB
6dB
6dB
6dB
3
10
17
24
Y1
Y2
Y3
Y4
5
12
19
26
C1
C2
C3
C4
39
37
49
47
46
44
41
58
56
55
51
VOUT1
YIN1
YOUT1
TRAP1
COUT1
CIN1
V/YOUT2
TRAP2
COUT2
VOUT3
YOUT3
COUT3
BIAS
57
50
VGND
BIAS
2
9
16
29
23
59
62
6dB
0dB
6dB
0dB
6dB
6dB
4
11
18
31
25
61
64
6dB
6dB
35
42
52
54
40
38
45
43
V
CC
AGND
LOUT1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
Logic
6
7
20
14
13
28
27
21
36
34
33
32
48
DC OUT
SCL
SDA
ADR
S-1
S-2
S-3
S-4
S2-1
S2-2
S2-3
S2-4
MUTE
LTV
LV1
LV2
LV3
LV4
LV5
LV6
RTV
RV1
RV2
RV3
RV4
RV5
RV6
Audio system is attenuated by 6dB at input,
and a total gain is 0dB (LOUT1 and ROUT1
can be changed to –6dB).
—3—
CXA2069Q
Pin Configuration
6 7 8 9
10 11 12 13 14 15 16 17 18 19
42 31 5
ADR
RV5
V5
LV5
S-4
S2-4
C4
RV4
Y4
LV4
V4
S-3
S2-3
LOUT1
VOUT1
ROUT1
TRAP1
YOUT1
VGND
COUT1
LV6
V6
RV6
LTV
TV
RTV
CXA2069Q
21
22
23
24
20
26
27
28
29
25
30
31
32
42 41 40 39 38 37 36 35 34 3351 50 49 48 47 46 45 44 43
63
62
61
60
64
58
57
56
55
59
54
53
52
V1
LV1
Y1
RV1
C1
S2-1
S-1
V2
LV2
Y2
RV2
C2
S-2
V3
LV3
Y3
RV3
C3
S2-2
CIN1
BIAS
YIN1
MUTE
COUT2
TRAP2
ROUT2
LOUT2
V
CC
VOUT3
ROUT3
YOUT3
LOUT3
COUT3
DC OUT
AGND
SDA
SCL
V/YOUT2
—4—
CXA2069Q
Pin Description
Pin
Symbol
Pin
Equivalent circuit Description
No. voltage
63
1
8
15
22
30
60
3
10
17
24
49
5
12
19
26
51
62, 2
9, 16
23, 29
59, 64
4, 11
18, 25
31, 61
53
41
TV
V1
V2
V3
V4
V5
V6
Y1
Y2
Y3
Y4
YIN1
C1
C2
C3
C4
CIN1
LTV, LV1
LV2, LV3
LV4, LV5
LV6, RTV
RV1, RV2
RV3, RV4
RV5, RV6
VOUT1
VOUT3
4.0 V
4.0 V
4.5 V
4.5 V
3.9 V
VCC
8
60
1
30
22
63
150
15
3µA
VCC
24
17
10
150
3µA
49
3
VCC
26
19
12
150
51
5
27k
20k
VCC
25
18
11
31
4
15k
33k
61
64
23
16
9
29
2
59
62
27k
VCC
VCC
53
41
27k
23.5k
30k
250
Video signal inputs.
Input composite video signals.
Y/C separation signal inputs.
Input luminance signals.
The YIN1 pin inputs the signal
obtained by Y/C separating the
VOUT1 pin output.
Y/C separation signal inputs.
Input chrominance signals.
The CIN1 pin inputs the signal
obtained by Y/C separating the
VOUT1 pin output.
Audio signal inputs.
Video signal outputs.
Output composite video signals.
—5—
CXA2069Q
Pin
Symbol
Pin
Equivalent circuit Description
No. voltage
44
56
39
58
47
37
52
43
38
54
45
40
6
13
20
27
V/YOUT2
YOUT1
YOUT3
COUT1
COUT2
COUT3
LOUT1
LOUT2
LOUT3
ROUT1
ROUT2
ROUT3
S2-1
S2-2
S2-3
S2-4
3.8 V
3.3 V
3.8 V
4.5 V
4.5V
—
44
VCC
VCC VCC VCC
VCC
VCC VCC VCC
39
56
VCC
VCC VCC VCC
37
58
47
VCC VCC
40 38
45 43
5254
56
20k
20k
VCC
VCC VCC
6
20
13
27
147
100k
Video signal output.
Either composite video signal output
or luminance signal output can be
selected by I2C bus control.
Video signal outputs.
Output luminance signals.
Video signal outputs.
Output chrominance signals.
Audio signal outputs.
Zo=50 Ω (within DC ±2 mA)
Detects the S2-compatible DC
superimposed onto the C signal.
4 : 3 video signal at 1.3 V or less
4 : 3 letter-box signal at 1.3 V or more
to 2.5 V or less
16 : 9 picture squeezed signal at 2.5 V
or more
This pin is pulled down to GND by a
100 kΩ resistor, so the 4 : 3 video
signal is selected when open.
—6—
CXA2069Q
Pin
Symbol
Pin
Equivalent circuit Description
No. voltage
7
14
21
28
32
33
34
S-1
S-2
S-3
S-4
ADR
SCL
SDA
—
—
—
—
VCC
VCC VCC
50k
7
14
28
21
100k
100k
50k
5V
VCC
147 72k
28k
32
VCC
10.5k
4k
33
VCC
4k
34
Composite video/S selector.
The detection results are written
to the status register.
S signal at 3.5 V or less
Composite video signal at 3.5 V
or more
This pin is pulled up to 5 V by a 100 kΩ
resistor, so the composite video signal
is selected when open.
Selects the slave address
for the I2C bus.
90H at 1.5 V or less
92H at 2.5 V or more
90H when open.
I2C bus signal input
VILmax=1.5 V
VIHmin=3.0 V
I2C bus signal input
VILmax=1.5 V
VIHmin=3.0 V
VOLmax=0.4 V
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