Sony CXA2064M Datasheet

US Audio Multiplexing Decoder

Description

The CXA2064M is an IC designed as a decoder for the Zenith TV Multi-channel System. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction.

Features

• Adjustment free of VCO and filter.

• Audio multiplexing decoder and dbx noise

reduction decoder are all included in a single chip.

Almost any sort of signal processing is possible

through this IC.

• Various built-in filter circuits greatly reduce external

parts.

• This IC is near pin to pin compatible with the

CXA2020M.

Applications

TV, VCR and other decoding systems for US audio multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage VCC 11 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 1000 mW

• STID, SAPID drive current IO 2 (max.) mA

Range of Operating Supply Voltage

9 ± 0.5 V

∗

This device is available only to the licensees of the dbx-TV noise reduction system.

– 1 –

E98513-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA2064M

30 pin SOP (Plastic)

Standard I/O Level

• Input level

COMPIN (Pin 7) 100mVrms (MONO 100Hz 100% mod.)

• Output level TVOUT-L/R (Pins 23 and 22) 490mVrms (MONO 100Hz 100% mod.)

Pin Configuration (Top View)

STIN

2

3

4

5

6

7

8

9

10

11

12

13

14 15

1

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SUBOUT

NOISETC

V

CC

IREF

GND

COMPIN

SAPTC

VGR

PLINT

STID

SAPID

PCINT2

PCINT1

MAINOUT

VE

VEWGT

SAPOUT

SAPIN

VETC

VEOUT

VCAIN

TVOUT-L

TVOUT-R

VCATC

VCAWGT

MUTE

M1

FOMO

MAININ

– 2 –

CXA2064M

Block Diagram

9

5

IREF

11

12

DETECTION

MODE_DISPLAY

NOISE

DET

SAPVCO

STIND

SAPIND

BPF

LPF

LPF DeEm LPF

LPF

1/21/4VCOLFLT

FLT

LPF LPF RMSDET

VCAVEDeEm

AMP

(+4dB)

SW

HPF

MATRIX

RMSDET

2

3

4

6

7

8

10

13 14 15

16

17

18

19

20

21

22

23

24 25 26

2728

29 30

1

COMPIN

V

CC

GND

NOISETC

SAPTC

VGR

IREF

SAPID

STID

FOMO

M1

MUTE

SAPOUT

SAPIN

STIN

VE

VEWGT

VETC

VEOUT

VCAIN

VCAWGT

VCATC

TVOUT-L

TVOUT-R

MAININ

MAINOUT

SUBOUT

PLINT

PCINT2 PCINT1

–

+6dB

– 3 –

CXA2064M

Pin Description (Ta = 25°C, VCC = 9V)

Pin No.

Symbol

Pin voltage

Equivalent circuit Description

VCC

SUBOUT

STIN

NOISETC

—

4.0V

3.0V

Supply voltage pin.

(L–R) signal output pin.

Input the (L-R) signal from SUBOUT (Pin 2).

Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.)

4

2

1

SAPIN

4.0V

Input the (SAP) signal from SAPOUT (Pin 28).

27

3

4

12k

4k

147

580

Vcc

2

23k

147

18k

20k

11.7k

23k

4V

147

18k

4V

VCC

27

1

3k

3.3k

4k

4V

Vcc

8k

× 2

10k

1k

2k

Vcc

200k

3

– 4 –

CXA2064M

Pin No.

Symbol

Pin voltage

Eqivalent circuit Description

COMPIN

IREF

GND

4.0V

1.3V

—

Audio multiplexing signal input pin.

Set the filter and VCO reference current. (Connect a 68kΩ (±1%) resistor between this pin and GND.)

Analog block GND.

Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.)

7

5

6

SAPTC

4.5V

8

VCC

24k

4V

50k

147

24k 24k

7

8k

4k

3k

10k

V

CC

↓ 50µ

1k

VCC

8

6

40k 40k 30k

30p 1.8k

16k

6.3k

147

34k 15k 30k

VCC

× 2

V

CC

5

CXA2064M

– 5 –

Pin No.

Symbol

Pin voltage

Eqivalent circuit Description

PLINT

5.1V

Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.)

VCC

147

20k

↓

26µ

20k

10k

20k

↓

50µ

20k

10

STID

—

Stereo detection pin. Open collector output. Drive current is 2mA (Max.).

11

SAPID —

SAP detection pin. Open collector output. Drive current is 2mA (Max.).

12

68k

10.5k

11

12

15k

VGR

1.3V

Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.)

9

× 4

11k

9.7k

19.4k

2.06k

3k

147

VCC

11k

9

– 6 –

CXA2064M

No.

Symbol

Pin voltage

Eqivalent circuit Description

MAININ

4.0V

Input the (L + R) signal from MAINOUT (Pin 15).

16

MAINOUT 4.0V

(L + R) signal output pin.

VCC

147

1k

15k

↓

200µ

V

CC

× 4

15

FOMO

—

Mode control switch pin. This pin has 3 ranges for input voltage. Sets forced monoral mode and also control ST.ID.

17

MUTE —

Mode control switch pin. When this pin is set to H level, TVOUT output is muted.

19

50k

70k

10.5k

17 19

PCINT1

PCINT2

4.0V

Stereo block PLL loop filter integrating pin.

22k

VCC

30k

147

14

4k

VCC

× 2

10k

2k

147

13

14

13

16

VCC

147

VCC

10k

47k

4V

– 7 –

CXA2064M

Pin No.

Symbol

Pin voltage

Eqivalent circuit Description

VCATC

1.7V

Determine the restoration time constant of the VCA control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.)

21

↓ 50µ

VCC

4k

20k

× 4

↓

7.5µ

21

TVOUT-R

4.0V

TVOUT right channel output pin.

22

TVOUT-L

4.0V

TVOUT left channel output pin.

23

3k

580

VCC

22

23

VCAWGT

4.0V

Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.)

20

4k

VCC

30k

8k

36k

2.9V

3p

580

147

40k 40k

↓

50µ

↓

8µ

20

M1

—

Mode control switch pin. This pin has 3 ranges for input voltage. Stereo, BOTH, SAP selection are available.

18

10.5k

40k

18

24k

4V

VCC

25k