Sony CXA2056Q Datasheet

Digital CCD Camera Head Amplifier

Description

The CXA2056Q is a bipolar IC developed as a head amplifier for digital CCD cameras. This IC provides the following functions: correlated double sampling, AGC for the CCD signal, GCA for the lowband chroma signal, AMP for high-band chroma and line signals, A/D sample and hold, blanking, A/D reference voltage, and an output driver.

Features

• High sensitivity made possible by a high-gain AGC

amplifier

• Blanking function provided for the purpose of

calibrating the CCD output signal black level

• Regulator output pin provided for A/D converter

reference voltage

• Built-in GCA and AMP for amplifying video signals

(chroma and line signals) from external sources

• Built-in sample-and-hold circuits for camera signals

required by external A/D converters

Absolute Maximum Ratings

• Supply voltage VCC 11 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 1160 mW

Operating Conditions

Supply voltage VCC1, 2, 3 3 to 3.3 V

Applications

Digital CCD cameras

Structure

Bipolar silicon monolithic IC

– 1 –

E96119A8X-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXA2056Q

32 pin QFP (Plastic)

– 2 –

CXA2056Q

Block Diagram and Pin Configuration

DC

SHIFT

BUF

SH1 SH2

SH3

VIDC

SHIFT

VREF

DMSW1

DMSW2

VSI

CH SW

CAM

SH

OBSW

VS2

VCENT

MODE CONTROL

&

POWER SAVE CONTROL

LOSW

VB

VRT

OFFSET

VRB

CVSW

VCENT VB

VB

BLK SW

26

27

28

29

30

31

32

25

9

10

11

12

13

14

15

16

2

3

4

5

6

7

8

1

17

18

19

20

21

22

23

24

PBRFC

DIN

V

CC2

ICONT

LIN/CH

GND2

RFCONT

AGCCLP

V

CC3

CLPOB

XRS

PBLK

OFFSET

VRT

VRB

MODE1

DRVOUT

MODE2

MODE3

PS

N.C

GND3

LOUTCLP

CLPDM

N.C

GND1

SHD

SHP

V

CC

1

CCDLEVEL

AGCCONT

VISW

LISW

1

2

3

CDS

CLP1

CDS

CLP2

LIN

CLP

LIN

CH AMP

CL

GCA

CAM DRV

VIDEO

DRV

LOUT

CLP

V

RT

DRV

VRB

DRV

AGC

CLP

AGC

– 3 –

CXA2056Q

Pin Description (VCC1, 2, 3 = 3V)

Pin No.

Symbol Pin voltage Equivalent circuit Description

1 MODE1

Camera and video signal selector. Composite video signal and high-band chroma/low-band chroma signal selector of the video signal. For details on the selection conditions for each mode, refer to the diagram of the Electrical Characteristics Measurement Circuit.

2 MODE2

3 MODE3

4 PS

Power saving mode.

5

17

N.C

No connection; normally ground.

6 23 30

GND3 GND1 GND2

Ground.

7

LOUTCLP

Capacitor connection for LOUTCLP which clamps the output minimum level in modes which pass the composite video signal. (Recommended value: 0.1µF)

VTH = 1.5V

GND

Approx. 1.1V

145

75k

50k

10µA

2 3 4

1

1.5V

7

2µA

100µA 100µA

38k 1k

90k22k

12k

145

1.1V

– 4 –

CXA2056Q

No.

Symbol Pin voltage Equivalent circuit Description

8

DRVOUT

Driver output for A/D converter capable of DC coupling.

Dynamic range = 1Vp-p

• Camera mode (CAM) VRB to VRB + 100mV

• Composite video mode (LIN) VRB + 50mV = approx.

1.4V

• Chroma mode (CH, CL) Center voltage = (VRT – VRB)/2 = approx.

1.85V

10 VRB

1.35V regulator output.

Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF)

9 20 27

VCC3 VCC1 VCC2

Power supply.VCC

1.35V

2.35V11 VRT

2.35V regulator output.

Be sure to decouple this pin near the IC pins to prevent the oscillation and external noise when this pin is not used. (Recommended capacitor value: 4.7µF)

100µA

5090

4072

509

30k

10p

1.4

1.85V

30k

SW3

SW1

SW2

2.4mA

CAM signal

VIDEO signal

48

50µA

SW1

145

ICONT

3.2 to 6.4mA

200µA

50µA

25µA25µA

2k

IOFFSET

0 to 50µA

SW1

VRT = 2.35V

V

RB = 1.35V

8

SW1SW2

Mode

1 0 0

0 1 1

SW3

0 1 0

CAM

LIN CH, CL 0: Open

1: Closed

200

30k

16.5k

13.5k

145

1.35V

110µA

10

30k

6.5k

23.5k

145

2.35V

220µ

11

55µ

200

– 5 –

CXA2056Q

Pin No.

Symbol Pin voltage Equivalent circuit Description

12 OFFSET

Controls the output offset during camera mode.

When 3V: VRB When 1.5V:

VRB + 100mV When 0V (preset mode):

VRB + 35mV

1.5 to 3V &

0V

2k

30k

50k 50k

1.5k 3k 25k

VRB

145

50µA

50µA 50µA

12

1.85V

13 PBLK

Camera signal preblanking pulse input.

Active when Low only during camera mode. Calibrates the black level of the AGC output waveform. When PBLK is Low, the DRVOUT potential is forced to VRB.

VTH = 1.85V

13

145

50µA

30k

1.85V

30k

14 XRS

Camera signal sample-and-hold pulse input.

VTH = 0.68V

24k

7k

0.68V

770µA

40µA

97µ

145

14

15 CLPOB

Clamp pulse used to clamp the optical black portion of the camera signal after it passes through the AGC amplifier.

VTH = 1.5V

145

50µA

30k

1.5V

30k

15

Active: Low

Sampling

Active: Low

– 6 –

CXA2056Q

Pin No.

Symbol Pin voltage Equivalent circuit Description

16 AGCCLP

AGC clamp capacitor. (Recommended value: 0.1µF)

Approx. 1.3V

18

AGCCONT

AGC gain control. When 1.5V: –1dB

(Minimum gain)

When 3.0V: +31.5dB

(Maximum gain)

1.5 to 3.0V

50k

145

5k5k

3k

16

145

18

200µA

3.4k 3.4k

200µA

2.14V

100µA300µA

300µA 100µA

2.29V

ICONT

3.4k

3.3k

19

CCDLEVEL

Enables monitoring of the SH3 output camera signal.

DIN input CCD signal black level: approx. 2.2V

21 SHP

Preset level sampleand-hold pulse input.

22 SHD

Data level sampleand-hold pulse input.

VTH = 0.65V

500

19

340

100µA

36k

10k

0.65V

365µA

20µA

145

21 22

Sampling

– 7 –

CXA2056Q

Pin No.

Symbol Pin voltage Equivalent circuit Description

24 CLPDM

Clamp pulse used to clamp the dummy pixel portion of the input CCD signal.

VTH = 1.5V

145

50µA

30k

1.5V

24

25 26

28

PIN DIN

ICONT

CCD signal input.

DRVOUT output waveform rise time control.

When 1.5V:

Maximum rise time

When 3V:

Minimum rise time

Black level: approx. 2.1V

1.5 to 3V

145

200µA

50µA

23k

26

25

7k14k

2k

15µA

145

100µA

15k

45k

28

6k

2.25V

29

LIN/CH

Common input for the composite video signal (LIN) and highband chroma signal (CH).

Clamp potential during LIN mode: approx. 1.46V

During CH mode: approx. 1.85V

145

50µA

25µA

200µA

11.5k

18.5k

1.85V

CH mode

100µA

LIN mode

2µA

10k

30k

VRB + 50mV

29

54k

Active: Low

– 8 –

CXA2056Q

No.

Symbol Pin voltage Equivalent circuit Description

31 RFCONT

Gain control for the low-band chroma signal (CL).

When 0.3V: –4dB

(Minimum gain)

When 2.7V: +12.5dB

(Maximum gain)

0.3 to 2.7V

54k145

42k27k

27k

31

32 PBRFC

Low-band chroma signal (CL) input.

Approx. 1.9V

32

145

200µA

100µA

7.8k

2k

58k

10k

200µA

38k

1.9V

22k

25µA

2.9V