Sony CXA2054S Datasheet

—1—

E96Y15B86-TE

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

US Audio Multiplexing Decoder

48 pin SDIP (Plastic)

CXA2054S

Absolute Maximum Ratings (Ta=25 °C)

• Supply voltage VCC 11 V

• Operating temperature Topr –20 to +75 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation

PD 2.2 W

Range of Operating Supply Voltage

9±0.5 V

Applications

TV, VCR and other decoding systems for US audio

multiplexing TV broadcasting

Structure

Bipolar silicon monolithic IC

Description

The CXA2054S is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built in while adjustment, mode control and sound processor control are all executed through I2C BUS.

Features

• Audio multiplexing decoder, dbx noise reduction

decoder and sound processor (surround, volume

limiter, bass · treble, volume) are all included in a

single chip. Almost any sort of signal processing is

possible through this IC.

• All adjustments are possible through I2C BUS to

allow for automatic adjustment.

• Various built-in filter circuits greatly reduce external

parts.

• There are two channel external inputs for LSOUT

outputs.

• Automatic volume control between input sources is

possible through volume limiter.

Standard I/O Level

• Input level

COMPIN (Pin 19) 245 mVrms

AUX1-L/R (Pins 40 and 39) 490 mVrms

AUX2-L/R (Pins 42 and 41) 490 mVrms

SURRIN (Pin 4) 490 mVrms

Pin Configuration (Top View)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

38 37 36 35 34 33 32 31 30 29 28 27 26 2548 46 45 44 43 42 41 40 3947

BASSL2

TRER

TREL

SURRIN

SURROUT

LSOUT-R

LSOUT-L

NC

SDA

SCL

DGND

SAD

MAININ

MAINOUT

NC

PCINT1

PCINT2

PLINT

COMPIN

VGR

IREF

GND

SAPTC

V

CC

BASSL1

BASSR2

BASSR1

SURRTC

TVOUT-L

TVOUT-R

AUX2-L

AUX2-R

AUX1-L

AUX1-R

VLTC

VLDC

VCAWGT

VCATC

VCAIN

VEOUT

VETC

VEWGT

VE

SAPIN

SAPOUT

NOISETC

STIN

SUBOUT

• Output level TVOUT-L/R (Pins 44 and 43) 490 mVrms LSOUT-L/R (Pins 7 and 6) 490 mVrms SURROUT (Pin 5) 490 mVrms

∗A license of the dbx-TV noise reduction system is required for the use this device.

—2—

CXA2054S

1/4 1/2

STLPF

“FILTER”

VCA

VCA LPF DeEm LPF

WIDEBAND

LFLT VCO

STIND

FLT LPF

“STEREO”

(+6dB)

ATT

BPF

SAPVCO

LPF

NOISE

DET

“NOISE”

“SAP”

SAPIND

19

22

24

27

23

VCO

FILTER

COMPIN

V

CC

GND

NOISETC

SAPTC

IREF

I

2

C BUS I/F

“PONRES”

LOGIC

NRSW/FOMO/SAPC

LPF LPF

SW

DeEm VE

RMSDETHPF

AMP

(+4dB)

SPECTRAL

VCA

RMSDET

MATRIX

SW1

16 17 25 1418 13 40 39

SW2

VOLLIM

PREVOL

SURROUND

PR-VOLSURR

BASS

TREB

TREBLE

VOL-L

VOL-R

VOL-S

MATRIX

SW3

VOL-SURR

(L-R)

44

43

42

41

37

38

45

1

46

47

3482

4

SURRSW

TVOUT-L

TVOUT-R

AUX2-L

AUX2-R

VLDC

VLTC

SURRTC

BASSL1

BASSL2

BASSR1

BASSR2

TREL

TRER

SURRIN

VOL-RVOL-L

VGR

IREF

SAD

DGND

SCL

SDA

SAPOUT

SAPIN

STIN

VE

VEWGT

VETC

VEOUT

VCAIN

VCAWGT

VCATC

LSOUT-R

LSOUT-L

SURROUT

20 21 12 11 10

9

28 29 26 30 33 34 3631 32 35

7 6 5

PCINT1

PCINT2

SUBOUT

MAINOUT

PLINT

MAININ

AUX1-L

AUX1-R

FEXT1

EXT1/EXT2/M1

VL

FEXT2

M2

Block Diagram

—3—

CXA2054S

Pin Description (Ta=25 °C, VCC=9 V)

Symbol

Equivalent circuit Description

No. voltage

1

48

47

46

2

3

4

BASSL2

BASSL1

BASSR2

BASSR1

TRER

TREL

SURRIN

4.0 V

48

47

1

13.2k

10.7k

8.57k

6.89k

5.66k

4.44k

3.67k

15.3k

46

4V

3k

VCC

580

V

CC

3

2

VCC

4.2k

3.42k

2.73k

2.2k

1.8k

1.42k

1.17k

4.88k

580

VCC

3k

10k

4

VCC

20k 20k

27.5k

47k

4V

BASS filter pin. (Left channel) (Connect a 15 nF capacitor between Pins 1 and 48.) The cutoff frequency is determined by the built-in resistor and the external capacitance.

BASS filter pin. (Right channel) (Connect a 15 nF capacitor between Pins 47 and 46.) The cutoff frequency is determined by the built-in resistor and the external capacitance.

TREBLE filter pin. (Right channel) (Connect a 6.8 nF capacitor between this pin and GND.)

TREBLE filter pin. (Left channel) (Connect a 6.8 nF capacitor between this pin and GND.)

Surround external input pin.

—4—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

5

6

7

8

9

10

11

SURROUT

LSOUT-R

LSOUT-L

NC

SDA

SCL

DGND

4.0 V

—

6 7

5

VCC

580

7.5k

×2

4.5k

×5

9

4k

3k

2.1V

↓ 35µ

7.5k

V

CC

10.5k

×4

4k

3k

2.1V

↓ 35µ

7.5k

V

CC

10

(L-R) signal output pin.

LSOUT right channel output pin.

LSOUT left channel output pin.

—

Serial data I/O pin. VIH > 3.0 V VIL < 1.5 V

Serial clock input pin. VIH > 3.0 V VIL < 1.5 V

Digital block GND.

8

11

—5—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

12

13

14

15

16

17

SAD

MAININ

MAINOUT

NC

PCINT1

PCINT2

—

4.0 V

—

4.0 V

12

80k

10k

40k

2V

V

CC

13

4V

53k

147

10k

V

CC

VCC

14

VCC

147

V

CC

×4

15k

1k

↓

200µ

16

147

30k

22k

VCC

17

147

4k

V

CC

2k

10k 10k

×2

Slave address control switch. The slave address is selected by changing the voltage applied to this pin.

Input the (L+R) signal from MAINOUT (Pin 14).

(L+R) signal output pin.

—

Stereo block PLL loop filter integrating pin.

15

—6—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

18

19

20

21

PLINT

COMPIN

VGR

IREF

5.1 V

4.0 V

1.3 V

15k 15k

20k 20k

20k 10k

↓

26µ

↓

50µ

147

18

VCC

147

19

3k

50k

16k4k

VCC

9.7k 19.4k

2.06k

×4

20

3k 147

VCC

11k

40k 40k

30p1.8k

16k

30k 30k

21

147

VCC

Pilot cancel circuit loop filter integrating pin. (Connect a 1 µF capacitor between this pin and GND.)

Audio multiplexing signal input pin.

Band gap reference output pin. (Connect a 10 µF capacitor between this pin and GND.)

Set the filter and VCO reference current. The reference current is adjusted with the BUS DATA based on the current which flows to this pin. (Connect a 62 kΩ (±1 %) resistor between this pin and GND.)

—7—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

22

23

24

25

26

29

GND

SAPTC

VCC

SUBOUT

STIN

SAPIN

—

4.5 V

—

4.0 V

22

24

8k

VCC

23

10k

1k

3k

VCC

4k ↓ 50µ

2k

2k 2k

2k

4k

14.4k

580

10P

4k

1k

147

25

VCC

26

147

18k

4V

23k

11.7k

20k

23k

4V

147

29

VCC

18k

Analog block GND.

Set the time constant for the SAP carrier detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.)

Supply voltage pin.

(L-R) signal output pin.

Input the (L-R) signal from SUBOUT (Pin 25).

Input the (SAP) signal from SAPOUT (Pin 28).

—8—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

27

28

30

31

NOISETC

SAPOUT

VE

VEWGT

3.0 V

4.0 V

8k

×2

2k

10k

1k

27

3k

200k

V

CC 3k

4k

4V

3.3k

VCC

24k ↓ 10µ

5P

4k ↓ 50µ

580

580 10k

147

28

V

CC

30

147

7.5k

VCC

31

147

580

8k

30k ↓ 8µ

4V

36k

2.9V

4k ↓ 50µ

V

CC

Set the time constant for the noise detection circuit. (Connect a 4.7 µF capacitor between this pin and GND.)

SAP FM detector output pin.

Variable de-emphasis integrating pin. (Connect a 2700 pF capacitor and a 3.3 kΩ resistor in series between this pin and GND.)

Weight the variable deemphasis control effective value detection circuit. (Connect a 0.047 µF capacitor and a 3 kΩ resistor in series between this pin and GND.)

—9—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

32

33

34

35

VETC

VEOUT

VCAIN

VCATC

1.7 V

4.0 V

1.7 V

4k

↓ 50µ

×4

20k ↓ 7.5µ

32

VCC

33

VCC

580

10k

5P

VCC

47k 47k

34

20k

VCC

35

VCC

↓

50µ

4k

×4

20k

↓

7.5µ

Determine the restoration time constant of the variable deemphasis control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 3.3 µF capacitor between this pin and GND.)

Variable de-emphasis output pin. (Connect a 4.7 µF non-polar capacitor between Pins 33 and 34.)

VCA input pin. Input the variable deemphasis output signal from Pin 33 via a coupling capacitor.

Determine the restoration time constant of the VCA control effective value detection circuit. (The specified restoration time constant can be obtained by connecting a 10 µF capacitor between this pin and GND.)

—10—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

36

37

38

39

40

41

42

VCAWGT

VLDC

VLTC

AUX1-R

AUX1-L

AUX2-R

AUX2-L

4.0 V

0.7 V

4.0 V

40k 40k

30k

36k

2.9V

4k

↓

50µ

↓

8µ

8k

3P

580

147

36

VCC

147

3k

37

VCC

147

38

200 200

100k 100k

10k

20k 20k

27.5k

47k

4V

39 40 41 42

V

CC

Weight the VCA control effective value detection circuit. (Connect a 1 µF capacitor and a 3.9 kΩ resistor in series between this pin and GND.)

Volume limiter detection circuit bias pin. (Connect a 1 MΩ resistor between pins 37 and 38.)

Set the time constant for the volume limiter detection circuit.

Right channel external input 1 pin.

Left channel external input 1 pin.

Right channel external input 2 pin.

Left channel external input 2 pin.

—11—

CXA2054S

Symbol

Equivalent circuit Description

No. voltage

43

44

45

TVOUT-R

TVOUT-L

SURRTC

4.0 V

44

43

580

3k

VCC

147

10k

20k

45

20k

24k

580

40k

V

CC

VCC

TVOUT right channel output pin.

TVOUT left channel output pin.

Set the central frequency of the SURROUND circuit phase shifter. The frequency is determined by the built-in resistor and the external capacitance. (Connect a 0.022 µF capacitor between this pin and GND.)

—12—

CXA2054S

Electrical Characteristics

COMP IN input level

(100 % modulation level)

(Ta=25 °C, VCC=9 V)

Main (L+R) (Pre-Emphasis : OFF)

SUB (L–R) (dbX-TV : OFF)

Pilot

SAP Carrier

f

H

=245 mVrms

=490 mVrms

=49 mVrms

=147 mVrms

=15.734 kHz

No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Item

Current consumption

Main output level

Main de-emphasis frequency

characteristic

Main LPF frequency

characteristic

Main distortion

Main overload distortion

Main S/N

Sub output level

Sub LPF frequency

characteristic

Sub distortion

Sub overload distortion

Sub S/N

ST

→

SAP

Cross talk

Sub pilot leak

Symbol

I

CC

Vmain

FCdeem

FCmain

THDm

THDmmax

SNmain

Vsub

FCsub

THDsub

THDsmax

SNsub

CTst

PCsub

Mode

MONO

ST

SAP

ST

Input pin

19

Input signal

No signal

Mono 1 kHz 100 % mod.

Pre-em. on

Mono 5 kHz 30 % mod.

Pre-em. on

Mono 12 kHz 30 % mod.

Pre-em.on

Mono 1 kHz 100 % mod.

Pre-em. on

Mono 1 kHz 200 % mod.

Pre-em off

Mono 1 kHz,

Pre-em on

SUB (L-R), 1 kHz,

100 % mod., NR OFF

SUB (L-R) 12 kHz,

30 % mod., NR OFF

SUB (L-R) 1 kHz,

100 % mod., NR OFF

SUB (L-R), 1 kHz,

200 % mod., NR OFF

SUB (L-R) 1 kHz,

NR OFF

SUB (L-R) 1 kHz,

100 % mod., NR ON

SAP Carrier (5 f

H

)

PILOT (f

H

) 0 dB

Measurement

conditions

20 log ('5 k'/'1 k')

20 log

('12 k'/'1 k')

20 log

('100 %'/'0 %')

20 log

('12 k'/'1 k')

20 log

('100 %'/'0 %')

20 log

('NRSW=0'/

'NRSW=1')

20 log

('out'/'in')

Filter

15 kLPF

1 kBPF

f

H

BPF

Output

43/44

25

44

25

Min.

37

440

–1.2

–3.0

—

61

150

–3.0

—

56

60

—

Typ.

47

490

0

–1.0

0.1

0.15

69

190

–0.5

0.1

0.2

64

70

–42

Max.

57

540

1.0

0.5

—

230

1.0

2.0

—

–30

Unit

mA

mVrms

dB

%

dB

mVrms

dB

%

dB