Sony CXA2000Q Datasheet

CXA2000Q

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Y/C/RGB/D for PAL/NTSC Color TVs

Description

The CXA2000Q is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for NTSC/PAL system color TVs onto a single chip. This IC includes deflection processing functions for wide-screen TVs, and is also equipped with a SECAM decoder interface, making it possible to construct a TV system that supports multiple color systems.

Features

• I2C bus compatible

• Compatible with both PAL and NTSC systems

(also compatible with SECAM if a SECAM decoder is connected)

• Built-in deflection compensation circuit capable of supporting various wide modes

• Countdown system eliminates need for H and V oscillator frequency adjustment

• Automatic identification of 50/60Hz vertical frequency (forced control possible)

• Non-interlace display support (even/odd selectable)

• Automatic identification of PAL, NTSC, and SECAM color systems (forced control possible)

• Automatic identification of 4.43MHz/3.58MHz crystal (forced control possible)

• Non-adjusting Y/C block filter

• One CV input, one set of Y/C inputs, two sets of analog RGB inputs (one set of which can serve as both

analog and digital inputs)

• Built-in AKB circuit

• Support for forcing YS1 off

64 pin QFP (Plastic)

Applications

Color TVs (4:3, 16:9)

Structure

Bipolar silicon monolithic IC

Absolute Maximum Ratings (Ta = 25°C, SGND, DGND = 0V)

• Supply voltage SVCC1, 2, DVCC1, 2 –0.3 to 12 V

• Operating temperature Topr –20 to +65 °C

• Storage temperature Tstg –65 to +150 °C

• Allowable power dissipation PD 1.7 W

(when mounted on 50mm × 50mm board)

• Voltages at each pin –0.3 to SVCC1, SVCC2,

DVCC1, DVCC2 + 0.3 V

Operating Conditions

Supply voltage SVCC1, 2 9.0 ± 0.5 V

DVCC1, 2 9.0 ±0.5 V

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96103-ST

CXA2000Q

Block Diagram

CC2DVCC1

DV

44

36

L2FIL

39

HOFF AFCPIN/

38

PHASE

CERA

41

32fH

AFCFIL

40

HSIN

47

H SYNC

VSIN

46

VSFIL

45

BLHOLD

52

DCTRAN

54

VM

49

SCL

50

51

48

56

VM OFF

2Vp-p

SDA

SYNCOUT

EXT SYNC IN

DET

VCO

SEP

6dB

DGND 42

V SYNC

EXT

HD OUT

37

H.DRIVE

SHIFT

PHASE

1/32

2fH

DET.

PHASE

GATE

SEP

CV/YC

SYNC

VAGCSH

VTIM

SCPOUT

34

10

30

VPOSI, VOFF,

SCP BGR/BGF

Sand

Castle

AFC

H POSI

C MODE

50/60 ID

V FREQ

D PICAGING

DC

TRAN

SHARP

DL

TRAP OFF

SUB CONT

S

SEP

STATUS

53

CVIN

SAWOSC

VD+OUT

32

35

WIDE

VSIZE

Count Down

D PIC

CLP

TRAN

NESS

DL

TRAP

SUB

CONT

SW

VIDEO

1Vp-p

55

YIN

VD–OUT

/VPROT

31

VLIN, SCORR

Gen.

Sawtooth

525/625

GATE

INTER

PRE/OVER

TOT

TRAP F0

ACC

57

CIN

E-WOUT

33

GB CUT

Gen.

WIDE

Parabola

GB DRV

BRT

γ

D-COL

PIC

INTERLACE

-LACE

YS1 OFF

1Vp-p

DET

KILLER

TOT

SUB COLOR

DET

ACC

GOUT

ROUT

24

22

BLK

OFF

CUT

GB

DRV

BRT

γ

D-

COL

MIX

OSD

PIC

SW

YS/YM

YS

SW

Y/C

MIX

DEM

ID

fsc

ID

PAL

PAL/

NTSC

COLOR SW

APC

59

20

CC1SVCC2

SV

BOUT

26

2

SGND1

IKIN

27

HV

COMP

DIG

COLOR

fsc R-Y

HUE

9

SGND2

AKB OFF

AKB

ABL

CLP

& AXIS

fsc B-Y

DEM

AXIS

HUE

VCO

IREF

25 23

21

EHT H, V

28

29

19 18

17 16 15

14 13

12 11

COL

8 7 6 5 4 3

64

XTAL

61 62 1

60

43

BSH

YM

YS2

YS1

GSH RSH

ABLIN/

ABLFIL

B2IN

G2IN

R2IN

B1IN

G1IN

R1IN

YRET

YOUT

X443 X358

IREF

VCOMP

–(B-Y) IN

–(R-Y) IN

–(B-Y) OUT –(R-Y) OUT

SECAMREF

FSCOUT

APCFIL

– 2 –

Pin Configuration

CXA2000Q

BLHOLD

CVIN

DCTRAN

YIN

EXT SYNC IN

CIN

TEST

SV

CC1

APCFIL

X443 X358

NC

FSCOUT

52 53

54

55

56 57 58

59

60 61 62 63 64

51

1

SDA

50

2

SCL

VM

49

3

HSIN

SYNCOUT

48

47

5

4

46

6

VSIN

45

7

VSFIL

44

8

2

CC

DV

43

9

IREF

10

DGND

4142

11

CERA

40

12

L2FIL

AFCFIL

39

13

AFCPIN/HOFF

HDOUT

37

38

14 15

36

16

1

CC

DV

35

17

VAGCSH

SAWOSC

33

34

19

18

E-WOUT

32

30

24 23

20

VD+OUT/VPROT VD–OUT/VPROT

31

VTIM ABLFIL

29

ABLIN/VCOMP

28

IKIN

27

BOUT

26

BSH

25

GOUT GSH ROUT

22

RSH

21

SV

CC2

SGND1

SECAMREF

–(R-Y) OUT

YRET

YOUT

–(B-Y) OUT

–(B-Y) IN

–(R-Y) IN

SGND2

SCPOUT

YS1

R1IN

G1IN

B1IN

YS2

YM

R2IN

G2IN

B2IN

– 3 –

Pin Description

CXA2000Q

Pin No.

Symbol Equivalent circuit Description

20p

6k

SECAM decoder interface. This pin

SECAMREF

1

SGND1 GND for Y/C block.

2

1

250µA

7.2V

—

serves as both a 4.43MHz output and as a SECAM identification input/output pin.

Color difference signal outputs. Go to

3 4

–(R-Y) OUT –(B-Y) OUT

200µA

3 4

high impedance when the SECAM system is detected.

Standard output levels for 75% CB:

B-Y: 0.665Vp-p R-Y: 0.525Vp-p

5

6

7 8

YOUT

YRET

–(R-Y) IN –(B-Y) IN

500

Luminance signal output. Black level is 3.5VDC.

5

30k

400µA

Standard output level for 100 IRE input:

1Vp-p

Luminance signal input.

6

1.5k

Clamped to 4.8V at the burst timing.

Standard input level for 100 IRE input:

1Vp-p

70k

Color difference signal inputs. Clamped to 5.5V at the burst timing.

7 8

1.5k

70k

Standard input levels for 75% CB:

B-Y: 1.33Vp-p R-Y: 1.05Vp-p

SGND2 GND for the RGB block.

9

– 4 –

CXA2000Q

Pin No.

10

11

Symbol Equivalent circuit Description

SCPOUT

YS1

11

10

40k

10k

1k

100µA

Sand castle pulse output. The 0 to 5V BGP pulse, the phase of which is controlled through the bus, is superimposed with the 0 to 2V H and VBLK pulse for output.

YSSW control input. When YS is high, the RGB1 block signal is selected; when YS is low, the Y/C block is selected. This function can be disabled by the YS1OFF setting for the I2C bus.

VILMAX = 0.4V VIHMIN = 1.0V

12 13 14

15

16

R1IN G1IN B1IN

YS2

YM

12 13 14

15

16

40k

30k

100µA

Analog R, G and B signal inputs.

200

Input a 0.7Vp-p (no sync, 100 IRE) signal via a capacitor. The signal is clamped to 5.7V at the burst timing of the signal input to the HSIN input pin (Pin 47).

YS/YMSW YS control input. When YS is high, the RGB2 block signal is selected; when YS is low, the YSSW output signal is selected.

VILMAX = 0.4V VIHMIN = 1.0V

YS/YMSW YM control input. When YM is high, the YSSW output signal is attenuated by 9.6dB.

VILMAX = 0.4V VIHMIN = 1.0V

– 5 –

CXA2000Q

Pin No.

17 18 19

20

21 23 25

R2IN G2IN B2IN

SVCC2

RSH GSH BSH

Symbol Equivalent circuit Description

Analog/digital (dual-purpose) RGB signal inputs. The input signals are input via capacitors.

100µA

200 17 18 19

30k

When using analog input, input a 0.7Vp-p signal (no sync, 100 IRE); when using digital input, input a signal of at least

1.5Vp-p (Vth = 1.2V). The display level is 67 IRE. When using digital input, digital input is selected regardless of the YS setting. In addition, the VM output is turned off. These pins are clamped to 5.7V at the burst timing of the signal input to the sync input pin (Pin 47).

Power supply for RGB block.

200 21 23 25

Sample-and-hold for R, G and B AKB. Connect to GND via a capacitor. When not using AKB (manual CUTOFF mode), R, G and B cut-off voltage can be controlled by applying a control voltage to each pin. The control voltage is 4.5 ± 1V.

22 24 26

27

ROUT GOUT BOUT

IKIN

27

22 24 26

200

1.1mA

1k

12k

50µA

R, G and B signal outputs.

2.5Vp-p is output during 100% white input.

Input the signal converted from the CRT beam current (cathode current Ik) to a voltage via a capacitor. The V blanking part is clamped to 2.7V at the V retrace timing. The input for this pin is the reference pulse return, and the loop operates so that the Rch is 1Vp-p and the G and Bch are 0.81Vp-p. The G and Bch can be varied by ±0.5V by the bus CUTOFF control. When not using AKB, this pin should be open.

– 6 –

CXA2000Q

Pin No.

ABLIN/VCOMP

28

ABLFIL

29

Symbol Equivalent circuit Description

ABL control signal input and VSAW high voltage fluctuation compensation signal input.

1.5V

High voltage compensation has linear control characteristics for the pin voltage range of about 8V to 1V. The control

28

147

characteristics can be varied through EHT-V control of the bus. ABL begins to have effect below a threshold voltage of about 1.2V. ABL functions as PIC/BRT-ABL (average value type).

100k

29

1.2k

Connect a capacitor to form the LPF of the ABL control signal.

VTIM

30

VD–OUT/VPROT

31

32

VD+OUT/VPROT

31

32

30

700

400µA

700

400µA

10k

30k

1k

24k

V timing pulse output. Outputs the timing pulse from V sync identification to the end of V blanking. Pulses are positive polarity from 1 to 6V. During zoom mode, the V blanking pulse which has been expanded before and after the V sync is superimposed and output as the 1 to 3V pulse.

V sawtooth wave output and V protect signal input. When a large current (3mA) is drawn from this pin, the RGB outputs are all blanked and "1" is output to the status register VNG.

Serves as both a V sawtooth wave output with the reverse polarity of VD–OUT, and a Vprotect signal input. The Vprotect function can even be applied to this pin.

– 7 –

CXA2000Q

Pin No.

33

34

Symbol Equivalent circuit Description

E-WOUT

VAGCSH

33

34

1.4k

800µA

1.2k

15k

V parabola wave output.

78k

Sample-and-hold for AGC which maintains the V sawtooth wave at a constant amplitude. Connect to GND via a capacitor.

Connect a capacitor to generate the V

SAWOSC

35

36

DVCC1 Power supply for the V deflection block.

HD OUT

37

35

37

300

100

147

20k

sawtooth wave. For the capacitor, use an MPS (metalized polyester capacitor), etc., with a small tan δ.

H drive signal output. This signal is output with the open collector.

H deflection pulse input for H AFC. Input an about 5Vp-p pulse via a capacitor. Set the pulse width to 10 to 12µs. This pin is also used as the hold-

38

AFCPIN/HOFF

38

147

10k

68k

down signal input for the HD output, and if this pin is 1V or less for a 7V cycle or

4.2V

longer, the hold-down function operates

10k

and the HD output is held to 9VDC. In addition, the RGB outputs are all blanked. Outputs "1" to the status register XRAY.

– 8 –

CXA2000Q

Pin No.

39

40

L2FIL

AFCFIL

Symbol Equivalent circuit Description

Filter for H AFC. Connect to GND via a capacitor. The H phase can also be controlled from

39

100

this pin by leading current in and out of this capacitor. As the pin voltage rises, the picture shifts to the left; as the pin voltage drops, the picture shifts to the right.

40

1.2k 46k

CR connection for the AFC lag-lead filter.

10k

41

42

CERA

DGND

41

400µA

Connect the 32 × FH VCO ceramic oscillator.

GND for the deflection block.

Internal reference current setting.

43

IREF

43

147

20k

Connect to GND via a resistor with an error of less than 1% (such as a metal film resistor).

44

DVCC2 Power supply for the H deflection block.

45

VSFIL

45

1k

– 9 –

Filter for V sync separation. Connect to GND via a capacitor.

CXA2000Q

Pin No.

46

47

VSIN

HSIN

Symbol Equivalent circuit Description

15k

Sync signal input for V sync separation. Input a 2Vp-p Y signal (or a 0.6Vp-p sync signal).

46

147

20µA

14k

4.1V

Sync signal input for H sync separation.

47

147

10µA

3.2V

Input a 2Vp-p Y signal (or a 0.6Vp-p sync signal).

48

49

50

SYNCOUT

VM

SCL

49

50

48

147

1.2k

240µA

500

1.2k

400µA

4k

40k

30k

Sync signal output for VSIN and HSIN. The output can be selected from the internal sync signals (Pin 53 or Pin 55) or the external sync signal (Pin 56) by the I2C bus.

Output signal level: 2Vp-p

(0.6Vp-p sync only)

Input/output gain: 6dB

Outputs the differential waveform of the VM (Velocity Modulation) Y signal. (6.6VDC, 1.1Vp-p) The signal advanced for 200ns from YOUT is output. The delay time versus YIN is determined by the DL setting of the I2C bus. This output can be turned off through the I2C bus. This output can also be turned off by YS1, YM, and YS2.

I2C bus protocol SCL (Serial Clock) input.

VILMAX = 1.5V VIHMIN = 3.5V

– 10 –

CXA2000Q

Pin No.

51

52

SDA

BLHOLD

Symbol Equivalent circuit Description

51

4k

I2C bus protocol SDA (Serial Data) I/O.

VILMAX = 1.5V VIHMIN = 3.5V VOLMAX = 0.4V

9µA

4.6V

20k

1.2k

Capacitor connection for black peak hold of the dynamic picture (black expansion).

4k

52

53

54

55

CVIN

DCTRAN

YIN

54

53

55

4k

1µA

2k

2V

4.6V

1.2k

Composite video signal input. Input the 1Vp-p (100% white including sync) CV signal via a capacitor. The sync level of the input signal is clamped to 3.8V. In addition, this pin detects input video signal HSYNC, and outputs the status via the status register CVSYNC.

Connect a capacitor that determines the DC transmission ratio to GND.

Y signal input. Input a 1Vp-p (100% white including sync) Y signal via a capacitor. The sync level of the input signal is clamped to 3.8V.

– 11 –

CXA2000Q

Pin No.

56

57

Symbol Equivalent circuit Description

EXT SYNC IN

CIN

57

56

1µA

30k

50k

4.6V

External sync signal input. Input a 0.3Vp-p sync signal (or a 1Vp-p CV signal or Y signal) via a capacitor. The sync level of the input signal is clamped to 3.8V.

Chroma signal input. Input a C signal with a burst level of 300mVp-p via a capacitor. Input signal is

5.2V

biased to 4.5V internally.

1k

Test pin.

TEST

58

59

SVCC1 Power supply for Y/C block.

60

APCFIL

58

15k

4.6V

1.2k

60

1.2k

4k

Outputs a 0 to 3V V-SYNC SEP with positive polarity. If not used, leave this pin open.

CR connection for the chroma APC laglead filter.

61

X443

61

Connect a 4.433619MHz crystal oscillator.

500

200µA

– 12 –

CXA2000Q

Pin No.

X358 Connect a 3.579545MHz crystal oscillator.

62

Symbol Equivalent circuit Description

4k

62

500

200µA

Not connected.

63

NC

Normally connected to GND to prevent interference with other pins.

1.2k

64

FSCOUT

64

147

280µA

Subcarrier output.

Output level: 5.2VDC, 0.4Vp-p

– 13 –

CXA2000Q

mA

86

65

mA

65

48

kHz

15.90

15.734

42

30

C Bus Register Initial Settings".

2

Measurement contents Min. Typ. Max. Unit

Measure the pin inflow current.

15.55

HDRIVE output frequency

Hz

400

—

–400

C status register

2

H is shifted from

HLOCK is 1 (the pull-in range

when f

Confirm that I

µs

26.5

25.5

24.5

15.734kHz).

Measure the pulse width for the section

where the HDRIVE output is high.

µs

12.6

12.1

11.6

VBGPh

µs

3.3

2.9

2.5

VBLKh

V

1.1

1.0

0.9

VSp-p

46: VSIN in

V

3.1

3.0

2.9

VDRIVE+

Measure the VDRIVE output Vp-p.

VSdc

10.79ms

20, 59

36, 44

37

—

Measurement pins

C bus register as shown in "I

2

Measurement conditions

CC = 9.0V,

V

CC = 9.0V,

Bus data = center

V

Bus data = center

AFC MODE = 0h

SYNCIN: composite sync

Symbol

SICC

DICC

fHFR

∆fHR

• Measures the following after setting the I

37

SYNCIN: composite sync

HDw

10

SCP

Measure the pulse width for the

VBLKh

10

section where the BLK output is high.

SCP

Measure the pulse width for the section

where the BGP output is high.

VBGPh

31, 32

VSp-p

31, 32

SYNCIN: composite sync

VSdc

Signal block current

consumption

Sync block current

consumption

1

2

Electrical Characteristics

Setting conditions • Ta = 25°C, SVCC1, 2 = DVCC1, 2 = 9V, SGND1, 2 = DGND = 0V

No. Item

Sync deflection block items

Horizontal free-running

frequency

3

Horizontal sync pull-in

range

4

– 14 –

HD output pulse width 5

SCP

BLK output pulse width

SCP

6

7

BGP output pulse width

VDRIVE output

amplitude

8

VDRIVE output center

potential

9

CXA2000Q

Unit

V

0.62

0.52

0.42

VEWp-p

Measurement contents Min. Typ. Max.

Measure the EWDRIVE output

Vp-p.

46: VSIN in

V

4.1

3.95

3.8

VEW dc

10.79ms

V

2.85

2.5

2.25

Output amplitude when a video

signal with an amplitude of

0.7Vp-p/100 IRE is input.

V1

V2

%

104

100

96

× 100

V1

Lin =

V2 × 2

dB

—

–30

—

f = 3.58MHz

Input fsc to CVIN.

Ratio of the fsc component of the

Yout amplitude when CTRAP = 1

against the Yout amplitude when

CTRAP = 0.

33

Measurement pins

Measurement conditions

SYNCIN: composite sync

VEWp-p

33

VEWdc

22, 24, 26

0.7Vp-p

/100 IRE

CVIN:

VRout1

22, 24, 26

100 IRE

50 IRE

CVIN:

Lin

22

CVIN:

fsc, 50 IRE

C-Trap3.58

TRAPOFF = 0/1

TRAP-F0 = 7h

No. Item Symbol

EWDRIVE output

amplitude

10

EWDRIVE output

center potential

11

Signal block items

R, G and B output

amplitude

12

– 15 –

R, G and B output

linearity

13

C-TRAP attenuation

(3.58MHz)

14