Sony CXA1866Q Datasheet
6-bit 140MSPS Flash A/D Converter
For the availability of this product, please contact the sales office.
Description
The CXA1866Q is a 6-bit ultra-high-speed flash
A/D converter IC capable of digitizing analog
signals at the maximum rate of 140MSPS. The
digital input level is compatible with ECL
100K/10KH/10K.
Features
• Ultra-high-speed operation with maximum
conversion rate of 140MSPS
• Low input capacitance: 7pF
• Wide analog input bandwidth: 210MHz
• Low power consumption: 325mW
• Low error rate
• Excellent temperature characteristics
• 1 : 2 demultiplexed output (TTL level)
CXA1866Q
48 pin QFP (Plastic)
Structure
Bipolar silicon monolithic IC
Applications
• Magnetic recording (PRML)
• Communications (QPSK, QAM)
• Liquid crystal display
Block Diagram
V
INV
CCLK
NCCLK
DCLK
NDCLK
RBS
V
15
RB
16
27
26
CD
25
11
CD
12
Reference Resistance Chain
COMPARATOR
6bit Latch
CLatchA
6
TTLOUT
6
CLatchB
IN
RTS
V
V
19
22
21
VRT
41
EE
DV
AVEE
23
AGND
20
46
DGND1
DGND2
45
DGND3
42
DVCC1
6
47
48
DVCC2
CD; Clock Driver
5
6
7
P2D4
P2D5 (MSB)
P2D3
4
3
P2D2
2
P2D1
P2D0 (LSB)
35
33
34
P1D3
P1D4
P1D5 (MSB)
32
31
P1D2
30
P1D1
P1D0 (LSB)
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E93Z35B77
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage AVEE, DVEE –7.0 to +0.5 V
∗1
DVCC
0.5 to +7.0 V
• Analog input voltage VIN –2.7 to +0.5 V
• Reference input voltage VRT, VRB –2.7 to +0.5 V
I VRT – VRB I 2.5 V
• Digital input voltage DIN
∗2
I
CCLK – NCCLKI, I DCLK – NDCLK
–4.0 to +0.5 V
I 2.5 V
• Digital output current ID0 to ID6 –30 to +30 mA
• Storage temperature Tstg –65 to +150 °C
• Ambient operating temperature Ta –20 to +75 °C
• Allowable power dissipation PD 750 mW
Recommended Operating Conditions Min. Typ. Max.
• Supply voltage AVEE, DVEE –5.5 –5.2 –4.75 V
AVEE – DVEE –0.05 0 0.05 V
AGND – DGND
∗1
DVCC
∗3
–0.05 0 0.05 V
4.75 5.0 5.25 V
• Reference input voltage VRT –0.1 0 0.1 V
VRB –2.2 –2.0 –0.8 V
• Analog input voltage VIN VRB VRT
• Digital input voltage DIN (H) –1.1 V
DIN (L) –1.5 V
• CCLK, NCCLK frequency Fcclk 140 MHz
• DCLK, NDCLK frequency Fdclk 70 MHz
• CCLK, NCCLK duty Dcclk 40 50 60 %
• DCLK, NDCLK duty Ddclk 40 50 60 %
• CCLK-DCLK time difference
∗4
tdcd –TPWL + 2 0 TPWH + 1 ns
• Operating temperature Ta –20 +75 °C
CXA1866Q
∗1
DVCC = DVCC1, DVCC2
∗2
DIN = CCLK, NCCLK, DCLK, NDCLK, INV
Pin Configuration.
Pins without names are NC pins
(not connected).
DV
CC2
37
DV
CC1
38
DGND1
39
DGND2
40
EE
DV
41
DGND3
42
DVCC2
43
DVEE
44
DGND2
45
DGND1
46
DV
CC1
47
DV
CC2
48
DGND3
36
1
DGND3
P1D4
P1D5 (MSB)
35
34
2
3
P2D1
P2D0 (LSB)
∗3
DGND = DGND1, DGND2, DGND3
∗4
Refer to the Timing Chart 1 for TPWL, TPWH.
2
CC
33
4
P1D3
32
5
P2D2
P1D2
P2D3
P1D0 (LSB)
P1D1
31
30
CXA1866Q
(Top View)
6
7
P2D4
P2D5 (MSB)
DGND3
29
8
DGND3
DV
2728
9
10
2
CC
DV
INV
26
11
CCLK
25
12
DCLK
NCCLK
NDCLK
24
AVEE
23
VRTS
22
RT
V
21
AGND
20
V
IN
19
18
AGND
17
VRB
16
VRBS
15
AVEE
14
13
– 2 –
Pin Description and I/O Pin Equivalent Circuit
Pin
Symbol
No.
21
VRT
22 VRTS
16
VRB
15 VRBS
I/O
I
O
O
I
Standard
voltage
level
0V
0V
–2V
–2V
Equivalent circuit
VRT
VRTS
VRBS
VRB
Comparator 1
Comparator 2
Comparator 31
Comparator 32
Comparator 63
CXA1866Q
Description
Top reference voltage input (= 0V).
This is the top reference voltage supplied
to the internal resistance chain. The
external input can be set in accordance
with the peak value on the plus side of
the input analog signal amplitude.
VRT sense output.
This is the voltage sense pin for VRT.
Bottom reference voltage input (= –2V).
This is the bottom reference voltage
supplied to the internal resistance
chain. The external input can be set in
accordance with the peak value on the
minus side of the input analog signal
amplitude.
VRB sense output.
This is the voltage sense pin for VRB.
19
26
25
11
12
VIN
CCLK
NCCLK
DCLK
NDCLK
AGND
VRTS
I
to
VRBS
VIN
Analog input.
The input range is 2Vp-p.
AVEE
CCLK clock input.
I
ECL
This is the conversion clock, and is an
ECL level input.
CCLK inversion clock input.
This is an ECL level input. When left
I
ECL
DGND1
CCLK
(DCLK)
NCCLK
(NDCLK)
500
500
r
r
r
r
open, this input goes to the ECL
threshold potential (–1.3V). Only
CCLK input can be used for operation
with the NCCLK input left open,but
complementary input is recommended
to attain fast and stable operation.
DCLK clock input.
This is the 1:2 DMPX latch clock; input
a clock of 1/2 frequency of CCLK.
I
ECL
Data are output from DMPX port 1
and port 2 synchronously with the
rising edge of this signal. This is an
r
DV
r
EE
ECL level input.
1.3V
DCLK inversion clock input.
This is an ECL level input. When left
open, this input goes to the ECL
I
ECL
threshold potential (–1.3V). Only
DCLK input can be used for operation
with the NDCLK input left open, but
complementary input is recommended
to attain fast and stable operation.
– 3 –
CXA1866Q
Pin
Symbol I/O
No.
INV
27
30 P1D0
31 P1D1
32 P1D2
33 P1D3
34 P1D4
35 P1D5
2 P2D0
I
O
Standard
voltage
level
ECL
TTL
DGND1
DVCC1
Equivalent circuit
500
DV
INV
EE
Description
r
r
r
1.3V
Digital output polarity inversion input.
This is an ECL level input.
This input inverts the polarity of the
digital outputs P1D0 to P1D5, and
P2D0 to P2D5. (Refer to the Output
Code Table.)
When left open, this signal is
r
1.3V
maintained at the low level.
These pins are for the 6 bits of digital
DVCC2
output data for DMPX port 1. P2D5 is
the MSB, and P2D0 is the LSB.
These are TTL level outputs.
P1D0 to D5
P2D0 to D5
3 P2D1
4 P2D2
5 P2D3
6 P2D4
7 P2D5
38, 47
9, 28, 37,
43, 48
DVCC1
DVCC2
39, 46 DGND1
40, 45
1, 8, 29,
17, 20
41, 44
36, 42
DGND2
DGND3
AGND
DVEE
—
—
—
—
—
—
—
+5.0V
+5.0V
0V
0V
0V
0V
–5.2V
DGND2
100K
DGND3
These pins are for the 6 bits of digital
output data for DMPX port 2. P2D5 is
the MSB, and P2D0 is the LSB.
These are TTL level outputs.
+5V power supply for TTL level
internal circuit.
+5V power supply for TTL level
output buffers (P1D0 to P2D5).
Ground for DVEE digital circuit.
Ground for DVcc1 digital circuit.
Ground for DVcc2 digital circuit.
Ground for AVEE analog circuit .
Used as the ground for the
comparator input buffers, latches, etc.
Separated from DGND.
–5.2V power supply for digital circuit.
Connected internally with AVEE.
(Resistance is 4 to 6Ω.)
14, 23
AVEE
—
–5.2V
–5.2V power supply for analog circuit.
Connected internally with DVEE.
(Resistance is 4 to 6Ω.)
– 4 –
CXA1866Q
Electrical Characteristics
Item
Resolution
DC characteristics
Integral linearity error
Differential linearity error
No missing code
Analog input
Analog input capacitance
Analog input resistance
Input bias current
Reference input
Reference resistance
Reference resistance
current
Offset voltage VRT
VRB
Digital input
Logic high level
Logic low level
Logic high current
Logic low current
Input capacitance
Symbol
n
EIL
EDL
CIN
RIN
IIN
RREF
Iref
EOT
EOB
VIH
VIL
IIH
IIL
(Ta = 25°C, AVEE = DVEE = –5.2V, DVCC = 5V, VRT = 0V, VRB = –2V)
Conditions
Min.
Typ.
Max.
6
Fc = 140MHz
Fc = 140MHz
±0.2
±0.2
Guaranteed
VIN = –1V + 0.07Vrms, DC ≤ VIN ≤ 70MHz
–2V≤VIN≤0V
–2V≤VIN≤0V
200
7
110
225
9
25
25
–1.13
–1.50
VIH = –0.8V
VIL = –1.6V
0
–50
50
50
3.5
Unit
bits
LSB
LSB
pF
kΩ
µA
Ω
mA
mV
mV
V
V
µA
µA
pF
Switching characteristics
Maximum conversion
frequency
Aperture jitter
Sampling delay
Digital output
Logic high level
Logic low level
Output delay
Output rising time
Output falling time
Dynamic characteristics
Analog amplitude
input bandwidth
S/N ratio
Error rate
Power supply
Supply current
Power consumption
∗1
TPS: Times Per Sample
FC
Taj
Tds
VOH
VOL
tdo
tr
tf
Finb
SNR1
SNR2
SNR3
ICC
IEE
Pd
Error rate1E-9 TPS
∗1
IOUT = –2mA
IOUT = 1mA
ZL = 25pF
ZL = 25pF, 0.5V to 2.4V
ZL = 25pF, 0.5V to 2.4V
VIN = 2Vp-p,
p-p value = 3dB down input frequenc
y
Fc = 140MHz, Fin = 1MHz
Fc = 140MHz, Fin = 35MHz
Fc = 140MHz, Fin = 70MHz
Fc = 140MHz, error > 4LSB
DVCC = +5V
AVEE = DVEE = –5.2V
140
2.7
2.0
210
–60
5.0
1.0
1.2
1.2
36
34
32
10
20
–40
325
MSPS
ps
ns
V
0.5
8.0
V
ns
ns
ns
MHz
dB
dB
dB
–9
32
TPS
mA
∗1
mA
mW
– 5 –
Output Code Table
CXA1866Q
VIN
0V
STEP
0
1
D5 D0
0 0 0 0 0 0
0 0 0 0 0 1
D5 D0
1 1 1 1 1 1
1 1 1 1 1 0
:
INV = 0
–1V
31
32
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 0 0 0
0 1 1 1 1 1
:
1 1 1 1 1 0
–2V
∗
INV = 0: low level; INV = 1: high level
63
1 1 1 1 1 1
0 0 0 0 0 1
0 0 0 0 0 0
Timing Chart 1
V
CCLK
tds
IN
N – 1
N
tr
tf
–1.1V
INV = 1
:
:
N + 1
–1.5V
N + 2
Dcclk
N + 3
N + 4
TPWH
TPWL
–1.3V
NCCLK
DCLK
NDCLK
P1D0-5
P2D0-5
tdcd
tdo
tdo
–1.3V
tf
2.0V
1.0V
2.0V
1.0V
tr
–1.1V
–1.5V
N – 2 NN – 4
N – 1 N + 1N – 3
Ddclk
–1.3V
–1.3V
– 6 –
Timing Chart 2
CXA1866Q
VIN
CCLK
DCLK
VIN
CCLK
6
COMPARATOR
N – 1N N + 1N + 2N + 3N + 4N + 5
6bit Latch
CLatchA CLatchB
6
6
66
TTLout
TTLout
6
P1D0 to D5
P2D0 to D5
COMPARATOR
(master)
COMPARATOR
(slave)
6bit Latch
CLatchA
CLatchB
DCLK
N
– 1
N – 1 N N + 1 N + 2 N + 3 N + 4 N + 5
N
– 3
N
– 4
NN
N – 1 N N + 1 N + 2 N + 3 N + 4N – 2
N – 1
N – 2
+ 1 N + 2 N + 3 N + 4 N + 5
N N + 1 N + 2 N + 3
N – 1 N N + 1 N + 2N – 3N – 2
TTLout
(P2D0 to D5)
TTLout
(P1D0 to D5)
N – 1 N + 1N – 3
N – 2NN – 4
– 7 –
Electrical Characteristics Measurement Circuit
Maximum conversion rate measurement circuit
6
IN
Signal Source
fCLK
–1kHz
4
2Vp-p Sin Wave
Signal Source
CLK
f
V
Amp
DUT
CXA1866Q
1/2
Latch
6
DCLKCCLK
Data 4
CXA1866Q
A
Comparator
A > B
B
+
Latch
Pulse
Counter
Integral linearity error measurement circuit
Differential linearity error measurement circuit
S1
S2
(P1D0 to D5)
6
VIN
DVM Controller
DUT
CXA1866Q
CCLK DCLK
6
(P2D0 to D5)
+V
S1: ON when A < B
S2: ON when A > B
–V
A < B A > B
Comparator
SW
A6 B6
to to
A1 B1
A0 B0
"0" "1"
6
Buffer
000000
to
6
111110
– 8 –
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