0.1COPYRIGHT NOTICE AND DISCLAIMER................................................................................................................................0-3
0.2WELCOME TO THE AR-B1474 SERIAL CPU BOARD.............................................................................................................0-3
0.3BEFORE YOU USE THIS GUIDE...............................................................................................................................................0-3
0.4RETURNING YOUR BOARD FOR SERVICE............................................................................................................................0-3
0.5TECHNICAL SUPPORT AND USER COMMENTS...................................................................................................................0-3
2.3.1I/O Port Address Map..........................................................................................................................................................2-3
2.3.2Real-Time Clock and Non-Volatile RAM ............................................................................................................................2-4
2.3.4ISA Bus Pin Assignment .....................................................................................................................................................2-5
2.3.5ISA Bus Signal Description.................................................................................................................................................2-6
3.SETTING UP THE SYSTEM............................................................................................................................ 3-1
3.2.2Hard Disk (IDE) Connector (CN1).......................................................................................................................................3-3
3.2.4FDD Port Connector (CN2).................................................................................................................................................3-4
3.2.5Parallel Port Connector (CN3)............................................................................................................................................3-4
3.2.14CRT Display Type Select (JP13)..................................................................................................................................3-11
4.3.3Enable the Software Write Protect......................................................................................................................................4-5
4.3.4Disable the Software Write Protect.....................................................................................................................................4-5
5.SOLID STATE DISK ....................................................................................................................................... 5-1
5.3.2SSD Memory Type Setting (M1 ~ M3 & JP5).....................................................................................................................5-6
0-1
AR-B1474 User¡¦s Guide
5.4ROM DISK INSTALLATION........................................................................................................................................................5-6
5.4.5Combination of ROM and RAM Disk................................................................................................................................5-12
6.6AUTO-DETECT HARD DISKS....................................................................................................................................................6-7
6.8.1Auto Configuration with Optimal Setting.............................................................................................................................6-7
6.8.2Auto Configuration with Fail Safe Setting...........................................................................................................................6-7
6.9.1Save Settings and Exit........................................................................................................................................................6-8
6.9.2Exit Without Saving .............................................................................................................................................................6-8
Acrosser Technology makes no representations or warranties with respect to the contents hereof and specifically
disclaims any implied warranties of merchantability or fitness for any particular purpose. Furthermore, Acrosser
Technology reserves the right to revise this publication and to make changes from time to time in the contents
hereof without obligation of Acrosser Technology to notify any person of such revisions or changes.
Possession, use, or copying of the software described in this publication is authorized only pursuant to a valid
written license from Acrosser or an authorized sublicensor.
(C) Copyright Acrosser Technology Co., Ltd., 1995. All rights Reserved.
No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated
into any language or computer language, in any form or any means, electronic, mechanical, magnetic, optical,
chemical, manual or otherwise, without the prior written consent of Acrosser Technology.
Acrosser, IBM, INTEL, AMD, CYRIX, AMI, MS-DOS, PC-DOS, DR-DOS, X-DOS…are registered trademarks.
All other trademarks and registered trademarks are the property of their respective holders.
This document was produced with Adobe Acrobat 3.01.
0.2 WELCOME TO THE AR-B1474 SERIAL CPU BOARD
This guide introduces the Acrosser AR-B1474 serial CPU board.
Use the information describes this card’ s functions, features, and how to start, set up and operate your AR-B1474
serial CPU board. You also could find general system information here.
0.3 BEFORE YOU USE THIS GUIDE
If you have not already installed this AR-B1474, refer to the Chapter 3, “Setting Up the System” in this guide.
Check the packing list, make sure the accessories in the package.
AR-B1474 diskette provides the newest information about the card. Please refer to the README.DOC file ofthe enclosed utility diskette. It contains the modification and hardware & software information, and adding the
description or modification of product function after manual published.
0.4 RETURNING YOUR BOARD FOR SERVICE
If your board requires servicing, contact the dealer from whom you purchased the product for service information.
If you need to ship your board to us for service, be sure it is packed in a protective carton. We recommend that
you keep the original shipping container for this purpose.
You can help assure efficient servicing of your product by following these guidelines:
1. Include your name, address, telephone and facsimile number where you may be reached during the day.
2. A description of the system configuration and/or software at the time is malfunction.
3. A brief description is in the symptoms.
0.5 TECHNICAL SUPPORT AND USER COMMENTS
User’ s comments are always welcome as they assist us in improving the usefulness of our products and the
understanding of our publications. They form a very important part of the input used for product enhancement
and revision.
We may use and distribute any of the information you supply in any way we believe appropriate without incurring
any obligation. You may, of course, continue to use the information you supply.
If you have suggestions for improving particular sections or if you find any errors, please indicate the manual title
and book number.
Please send your comments to Acrosser Technology Co., Ltd. or your local sales representative.
Internet electronic mail to: webmaster@acrosser.com
0-3
AR-B1474 User¡¦s Guide
0.6 ORGANIZATION
This information for users covers the following topics (see the Table of Contents for a detailed listing):
l Chapter 1, “Overview”, provides an overview of the system features and packing list.
l Chapter 2, “System Controller” describes the major structure.
l Chapter 3, “Setting Up the System”, describes how to adjust the jumper, and the connectors setting.
l Chapter 4, “Installation”, describes setup procedures including information on the utility diskette.
l Chapter 5, “Solid State Disk,” describes the various type SSD’ s installation steps.
l Chapter 6, “BIOS Console”, providing the BIOS options setting.
l Chapter 7, Specifications
l Chapter 8, Placement & Dimensions
l Chapter 9, Memory Banks & Programming RS-485
l Chapter 10, SSD Types Supported & Index
0.7 STATIC ELECTRICITY PRECAUTIONS
Before removing the board from its anti-static bag, read this section about static electricity precautions.
Static electricity is a constant danger to computer systems. The charge that can build up in your body may be
more than sufficient to damage integrated circuits on any PC board. It is, therefore, important to observe basic
precautions whenever you use or handle computer components. Although areas with humid climates are much
less prone to static build-up, it is always best to safeguard against accidents may result in expensive repairs. The
following measures should generally be sufficient to protect your equipment from static discharge:
• Touch a grounded metal object to discharge the static electricity in your body (or ideally, wear a grounded
wrist strap).
• When unpacking and handling the board or other system component, place all materials on an antic static
surface.
• Be careful not to touch the components on the board, especially the “golden finger” connectors on the bottom
of every board.
0-4
AR-B1474 User¡¦s Guide
1. OVERVIEW
This chapter provides an overview of your system features and capabilities. The following topics are covered:
l Introduction
l Packing List
l Features
1.1 INTRODUCTION
The AR-B1474 is a half size industrial grade CPU card that has been designed to withstand continuous operation
in harsh environments. The total on-board memory for the AR-B1474 can be configured from 1MB to 32MB by
using all 72-pin type DRAM devices.
The 8 layers PCB CPU card is equipped with a IDE HDD interface, a floppy disk drive adapter, 1 parallel port, 2
serial ports, a watchdog timer and a solid state disk. Its dimensions are as compact as 122mm x 185mm. It’ s
highly condensed features make it an ideal cost/performance solution for high-end commercial and industrial
applications where CPU speed and mean time between failure is critical.
The AR-B1474 provides 2 bus interfaces, ISA bus and PC/104 compatible expansion bus. Based on the PC/104
expansion bus, you could easy install thousands of PC/104 module from hundreds venders around the world. You
could also directly connect the power supply to the AR-B1474 on-board power connector in stand alone
applications.
A watchdog timer, which has a software programmable time-out interval, is also provided on this CPU card. It
ensures that the system will not hang-up if a program can not execute normally.
For diskless application, the AR-B1474 provides up to 3MB of bootable ROM, FLASH, or SRAM disk space by
using 64K x 8 to 1M x 8 memory chips.
The AR-B1474 is implemented with M1429 and M1431 chipset incorporate a memory controller, parity generation
and checking, two 8237 DMA controllers, two 8259 interrupt controllers, one 8254 timer/counter, an address buffer
and a data buffer.
A super I/O chip (SMC37C669) is embedded in the AR-B1474 card. It combines functions of a floppy disk drive
adapter, a hard disk drive (IDE) adapter, two serial (with 16C550 UART) adapters and 1 parallel adapter.
The I/O port configurations can be done by setting the BIOS setup program.
As an UART, the chip supports serial to parallel conversion on data characters received from a peripheral device
or a MODEM , and parallel to serial conversion on data character received from the CPU. The UART includes a
programmable baud rate generator, complete MODEM control capability and a processor interrupt system. As a
parallel port, the SMC37C669 provides the user with a fully bi-directional parallel centronics-type printer interface.
This manual has been written to assist you in installing, configuring and running the AR-B1474 CPU card. Each
section is intended to guide you through it’ s procedures clearly and concisely, allowing you to continue to the next
chapters without any difficulty.
1-1
AR-B1474 User¡¦s Guide
1.2 PACKING LIST
The accessories are included with the system. Before you begin installing your AR-B1474 card, take a moment to
make sure that the following items have been included inside the AR-B1474 package.
l The quick setup manual
l 1 AR-B1474 all-in-one CPU card
l 1 Keyboard adapter cable
l 1 Parallel port interface cable
l 1 Hard disk drive interface cable
l 1 Floppy disk drive interface cable
l 1 40-pin header for PC/104 adapter
l 1 64-pin header for PC/104 adapter
l 1 Software utility diskettes
NOTE: If there are any discrepancies, please contact your Acrosser distributor immediately.
1.3 FEATURES
The system provides a number of special features that enhance its reliability, ensure its availability, and improve its
expansion capabilities, as well as its hardware structure.
l All-in-one designed 486DX/DX2/DX4 CPU card
l Support 3.3V/5V CPU with voltage regulator
l Support ISA bus and PC/104 bus
l Support 128KB to 512KB second level cache on-board
l Support up to 32MB DRAM on-board
l Support shadow memory and EMS
l Legal AMI BIOS
l IDE hard disk drive interface
l Floppy disk drive interface
l Bi-direction parallel interface
l 2 serial ports with 16C550 UART
l DS12887 or compatible RTC
l Programmable watchdog timer
l Up to 3MB solid state disk (SSD)
l On-board build-in buzzer
l 8 layers PCB
1-2
AR-B1474 User¡¦s Guide
2. SYSTEM CONTROLLER
This chapter describes the major structure of the AR-B1474 serial CPU board. The following topics are covered:
l DMA Controller
l Keyboard Controller
l Interrupt Controller
l Serial Port
l Parallel Port
2.1 DMA CONTROLLER
The equivalent of two 8237A DMA controllers are implemented in the AR-B1474 card. Each controller is a fourchannel DMA device that will generate the memory addresses and control signals necessary to transfer
information directly between a peripheral device and memory. This allows high-speed information transfer with less
CPU intervention. The two DMA controllers are internally cascaded to provide four DMA channels for transfers to
8-bit peripherals (DMA1) and three channels for transfers to 16-bit peripherals (DMA2). DMA2 channel 0 provides
the cascade interconnection between the two DMA devices, thereby maintaining IBM PC/AT compatibility.
Following is the system information of DMA channels:
The 8042 processor is programmed to support the serial keyboard serial interface. The keyboard controller
receives serial data from the keyboard, checks its parity, translates scan codes, and presents it to the system as a
byte data in its output buffer. The controller can interrupt the system when data is placed in its output buffer, or
wait for the system to poll its status register to determine when data is available.
Data can be written to the keyboard by writing data to the output buffer of the keyboard controller.
Each byte of data is sent to the keyboard controller in series with an odd parity bit automatically inserted. The
keyboard controller is required to acknowledge all data transmissions. Therefore, another byte of data will not be
sent to keyboard controller until acknowledgment is received for the previous byte sent. The “output buffer full”
interrupt may be used for both send and receive routines.
2-1
AR-B1474 User¡¦s Guide
2.3 INTERRUPT CONTROLLER
The equivalent of two 8259 Programmable Interrupt Controllers (PIC) are included on the AR-B1474 card. They
accept requests from peripherals, resolve priorities on pending interrupts in service, issue interrupt requests to the
CPU, and provide vectors which are used as acceptance indices by the CPU to determine which interrupt service
routine to execute.
Following is the system information of interrupt levels:
InInterrupt Level
NMI
CTRL1
IRQ 0
IRQ 1
IRQ 2
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
Description
Parity check
CTRL2
System timer interrupt from timer 8254
Keyboard output buffer full
IRQ8 : Real time clock
IRQ9 : Rerouting to INT 0Ah from hardware IRQ2
IRQ10 : Spare
IRQ11 : Spare
IRQ12 : Spare
IRQ13 : Math. coprocessor
IRQ14 : Hard disk adapter
IRQ15 : Spare (Watchdog Timer)
Serial port 2
Serial port 1
Parallel port 2
Floppy disk adapter
Parallel port 1
394-395Watchdog
3A0-3AFBisynchronous 1
3B0-3BFMonochrome display and printer port 1 (LPT 1)
3C0-3CFEGA/VGA adapter
3D0-3DFColor/graphics monitor adapter
3E8-3EFSerial port 3 (COM 3)
3F0-3F7Diskette controller
3F8-3FFSerial port 1 (COM 1)
Table 2-2 I/O Port Address Map
AR-B1474 User¡¦s Guide
2-3
AR-B1474 User¡¦s Guide
2.3.2 Real-Time Clock and Non-Volatile RAM
The AR-B1474 contains a real-time clock compartment that maintains the date and time in addition to storing
configuration information about the computer system. It contains 14 bytes of clock and control registers and 114
bytes of general purpose RAM. Because of the use of CMOS technology, it consumes very little power and can be
maintained for long period of time using an internal Lithium battery. The contents of each byte in the CMOS RAM
are listed as follows:
AddressDescription
00Seconds
01Second alarm
02Minutes
03Minute alarm
04Hours
05Hour alarm
06Day of week
07Date of month
08Month
09Year
0AStatus register A
0BStatus register B
0CStatus register C
0DStatus register D
0EDiagnostic status byte
0FShutdown status byte
10Diskette drive type byte, drive A and B
11Fixed disk type byte, drive C
12Fixed disk type byte, drive D
13Reserved
14Equipment byte
15Low base memory byte
16High base memory byte
17Low expansion memory byte
18High expansion memory byte
19-2DReserved
2E-2F2-byte CMOS checksum
30Low actual expansion memory byte
31High actual expansion memory byte
32Date century byte
33Information flags (set during power on)
34-7FReserved for system BIOS
Table 2-3 Real-Time Clock & Non-Volatile RAM
2.3.3 Timer
The AR-B1474 provides three programmable timers, each with a timing frequency of 1.19 MHz.
Timer 0The output of this timer is tied to interrupt request 0. (IRQ 0)
Timer 1This timer is used to trigger memory refresh cycles.
Timer 2This timer provides the speaker tone.
Application programs can load different counts into this timer to generate various sound frequencies.
2-4
2.3.4 ISA Bus Pin Assignment
I/O Pin Signal Name Input/Output I/O Pin Signal Name Input/Output
BUSCLK [Output] The BUSCLK signal of the I/O channel is asynchronous to
the CPU clock.
RSTDRV [Output]This signal goes high during power-up, low line-voltage or
hardware reset
SA0 - SA19
[Input / Output]
LA17 - LA23
[Input/Output]
SD0 - SD15
[Input/Output]
BALE [Output]The Buffered Address Latch Enable is used to latch SA0 -
-IOCHCK [Input]The I/O Channel Check is an active low signal which
IOCHRDY
[Input, Open
collector]
IRQ 3-7, 9-12, 14, 15
-IOR
[Input/Output]
-IOW [Input/Output] The I/O write signal is an active low signal which instructs
-SMEMW [Output] The System Memory Read is low while any of the low 1
-MEMR
[Input/Output]
-SMEMW [Output] The System Memory Write is low while any of the low 1
-MEMW
[Input/Output]
DRQ 0-3, 5-7
[Input]
-DACK 0-3, 5-7
[Output]
AEN [output]The DMA Address Enable is high when the DMA
-REFRESH
[Input/Output]
TC [Output]Terminal Count provides a pulse when the terminal count
SBHE
[Input/Output]
The System Address lines run from bit 0 to 19. They are
latched onto the falling edge of "BALE"
The Unlatched Address line run from bit 17 to 23
System Data bit 0 to 15
SA19 onto the falling edge. This signal is forced high
during DMA cycles
indicates that a parity error exist on the I/O board
This signal lengthens the I/O, or memory read/write cycle,
and should be held low with a valid address
The Interrupt Request signal indicates I/O service request
[Input]
attention. They are prioritized in the following sequence :
(Highest) IRQ 9, 10, 11, 12, 13, 15, 3, 4, 5, 6, 7 (Lowest)
The I/O Read signal is an active low signal which instructs
the I/O device to drive its data onto the data bus
the I/O device to read data from the data bus
mega bytes of memory are being used
The Memory Read signal is low while any memory
location is being read
mega bytes of memory is being written
The Memory Write signal is low while any memory
location is being written
DMA Request channels 0 to 3 are for 8-bit data transfers.
DMA Request channels 5 to 7 are for 16-bit data
transfers. DMA request should be held high until the
corresponding DMA has been completed. DMA request
priority is in the following sequence:(Highest) DRQ 0, 1, 2,
3, 5, 6, 7 (Lowest)
The DMA Acknowledges 0 to 3, 5 to 7 are the
corresponding acknowledge signals for DRQ 0 to 3 and 5
to 7
controller is driving the address bus. It is low when the
CPU is driving the address bus
This signal is used to indicate a memory refresh cycle and
can be driven by the microprocessor on the I/O channel
for any DMA channel is reached
The System Bus High Enable indicates the high byte SD8
- SD15 on the data bus
2-6
AR-B1474 User¡¦s Guide
NameDescription
-MASTER [Input]The MASTER is the signal from the I/O processor which
gains control as the master and should be held low for a
maximum of 15 microseconds or system memory may be
lost due to the lack of refresh
-MEMCS16
[Input, Open
collector]
-IOCS16
[Input, Open
collector]
OSC [Output]The Oscillator is a 14.31818 MHz signal
ZWS
[Input, Open
collector]
The Memory Chip Select 16 indicates that the present
data transfer is a 1-wait state, 16-bit data memory
operation
The I/O Chip Select 16 indicates that the present data
transfer is a 1-wait state, 16-bit data I/O operation
The Zero Wait State indicates to the microprocessor that
the present bus cycle can be completed without inserting
additional wait cycle
Table 2-6 ISA Bus Signal Description
2.4 SERIAL PORT
The ACEs (Asynchronous Communication Elements ACE1 to ACE2) are used to convert parallel data to a serial
format on the transmit side and convert serial data to parallel on the receiver side. The serial format, in order of
transmission and reception, is a start bit, followed by five to eight data bits, a parity bit (if programmed) and one,
one and half (five-bit format only) or two stop bits. The ACEs are capable of handling divisors of 1 to 65535, and
produce a 16x clock for driving the internal transmitter logic.
Provisions are also included to use this 16x clock to drive the receiver logic. Also included in the ACE a completed
MODEM control capability, and a processor interrupt system that may be software tailored to the computing time
required handle the communications link.
The following table is summary of each ACE accessible register
0base + 1Interrupt enable
Xbase + 2Interrupt identification (read only)
Xbase + 3Line control
Xbase + 4MODEM control
Xbase + 5Line status
Xbase + 6MODEM status
Xbase + 7Scratched register
1base + 0Divisor latch (least significant byte)
1base + 1Divisor latch (most significant byte)
Table 2-7 ACE Accessible Registers
(1) Receiver Buffer Register (RBR)
Bit 0-7: Received data byte (Read Only)
(2) Transmitter Holding Register (THR)
Bit 0-7: Transmitter holding data byte (Write Only)
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AR-B1474 User¡¦s Guide
Word Length
(3) Interrupt Enable Register (IER)
Bit 0: Enable Received Data Available Interrupt (ERBFI)
Bit 1: Enable Transmitter Holding Empty Interrupt (ETBEI)
Bit 2: Enable Receiver Line Status Interrupt (ELSI)
Bit 3: Enable MODEM Status Interrupt (EDSSI)
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(4) Interrupt Identification Register (IIR)
Bit 0: “0” if Interrupt Pending
Bit 1: Interrupt ID Bit 0
Bit 2: Interrupt ID Bit 1
Bit 3: Must be 0
Bit 4: Must be 0
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(5) Line Control Register (LCR)
Bit 0: Word Length Select Bit 0 (WLS0)
Bit 1: Word Length Select Bit 1 (WLS1)
WLS1WLS0
005 Bits
016 Bits
107 Bits
118 Bits
Bit 2: Number of Stop Bit (STB)
Bit 3: Parity Enable (PEN)
Bit 4: Even Parity Select (EPS)
Bit 5: Stick Parity
Bit 6: Set Break
Bit 7: Divisor Latch Access Bit (DLAB)
(6) MODEM Control Register (MCR)
Bit 0: Data Terminal Ready (DTR)
Bit 1: Request to Send (RTS)
Bit 2: Out 1 (OUT 1)
Bit 3: Out 2 (OUT 2)
Bit 4: Loop
Bit 5: Must be 0
Bit 6: Must be 0
Bit 7: Must be 0
(7) Line Status Register (LSR)
Bit 0: Data Ready (DR)
Bit 1: Overrun Error (OR)
Bit 2: Parity Error (PE)
Bit 3: Framing Error (FE)
Bit 4: Break Interrupt (BI)
Bit 5: Transmitter Holding Register Empty (THRE)
Bit 6: Transmitter Shift Register Empty (TSRE)
Bit 7: Must be 0
2-8
(8) MODEM Status Register (MSR)
Bit 0: Delta Clear to Send (DCTS)
Bit 1: Delta Data Set Ready (DDSR)
Bit 2: Training Edge Ring Indicator (TERI)
Bit 3: Delta Receive Line Signal Detect (DSLSD)
Bit 4: Clear to Send (CTS)
Bit 5: Data Set Ready (DSR)
Bit 6: Ring Indicator (RI)
Bit 7: Received Line Signal Detect (RSLD)
(9) Divisor Latch (LS, MS)
LSMS
Bit 0:Bit 0Bit 8
Bit 1:Bit 1Bit 9
Bit 2:Bit 2Bit 10
Bit 3:Bit 3Bit 11
Bit 4:Bit 4Bit 12
Bit 5:Bit 5Bit 13
Bit 6:Bit 6Bit 14
Bit 7:Bit 7Bit 15
AR-B1474 User¡¦s Guide
Table 2-8 Serial Port Divisor Latch
2.5 PARALLEL PORT
(1) Register Address
Table 2-9 Registers’ Address
Desired Baud RateDivisor Used to Generate 16x Clock
300384
600192
120096
180064
240048
360032
480024
960012
144008
192006
288004
384003
576002
1152001
Port AddressRead/WriteRegister
base + 0WriteOutput data
base + 0ReadInput data
base + 1ReadPrinter status buffer
base + 2WritePrinter control latch
(2) Printer Interface Logic
The parallel portion of the SMC37C669 makes the attachment of various devices that accept eight bits of parallel
data at standard TTL level.
2-9
AR-B1474 User¡¦s Guide
(3) Data Swapper
The system microprocessor can read the contents of the printer’ s Data Latch through the Data Swapper by reading
the Data Swapper address.
(4) Printer Status Buffer
The system microprocessor can read the printer status by reading the address of the Printer Status Buffer. The bit
definitions are described as follows:
12345670
XXX
-ERROR
SLCT
PE
-ACK
-BUSY
Figure 2-2 Printer Status Buffer
NOTE: X presents not used.
Bit 7: This signal may become active during data entry, when the printer is off-line during printing, or when the
print head is changing position or in an error state. When Bit 7 is active, the printer is busy and can not
accept data.
Bit 6: This bit represents the current state of the printer’ s ACK signal. A 0 means the printer has received the
character and is ready to accept another. Normally, this signal will be active for approximately 5
microseconds before receiving a BUSY message stops.
Bit 5: A 1 means the printer has detected the end of the paper.
Bit 4: A 1 means the printer is selected.
Bit 3: A 0 means the printer has encountered an error condition.
(5) Printer Control Latch & Printer Control Swapper
The system microprocessor can read the contents of the printer control latch by reading the address of printer
control swapper. Bit definitions are as follows:
12345670
XX
STROBE
AUTO FD XT
INIT
SLDC IN
IRQ ENABLE
DIR(write only)
Figure 2-3 Bit’ s Definition
NOTE: X presents not used.
Bit 5: Direction control bit. When logic 1, the output buffers in the parallel port are disabled allowing data driven
from external sources to be read; when logic 0, they work as a printer port. This bit is write only.
Bit 4: A 1 in this position allows an interrupt to occur when ACK changes from low state to high state.
Bit 3: A 1 in this bit position selects the printer.
Bit 2: A 0 starts the printer (50 microseconds pulse, minimum).
Bit 1: A 1 causes the printer to line-feed after a line is printed.
Bit 0: A 0.5 microsecond minimum highly active pulse clocks data into the printer. Valid data must be present
for a minimum of 0.5 microseconds before and after the strobe pulse.
2-10
AR-B1474 User¡¦s Guide
3. SETTING UP THE SYSTEM
This section describes pin assignments for system’ s external connectors and the jumpers setting.
l Overview
l System Setting
3.1 OVERVIEW
The AR-B1474 is a half size industrial grade CPU card that has been designed to withstand continuous operation
in harsh environments. The total on-board memory for the AR-B1474 can be configured from 1MB to 32MB by
using all 72-pin type DRAM devices.
CN4
U27
CN3
U8
U12
U18
H7
H15
JP13
J4J3
JP3
JP11
J8
H19H18
J2J1
H4
SIMM1DB1
JP8
1
H16
CN1CN2
U13
JP15
JP1
JP12
J7
CN6
JP14
JP2
U20
BUS1BUS2
LED1LED2
H6
U7
JP9
JP10
H14
CN6
U17
U26
JP6
P5
P6
JP5
P7
P8
JP7
P9
P10
SW1
JP4
H5
J5
J6
DB2
CN5
Figure 3-1 AR-B1474 Placement
3-1
AR-B1474 User¡¦s Guide
3.2 SYSTEM SETTING
Jumper pins allow you to set specific system parameters. Set them by changing the pin location of jumper blocks.
(A jumper block is a small plastic-encased conductor that slips over the pins.) To change a jumper setting, remove
the jumper from its current location with your fingers or small needle-nosed pliers. Place the jumper over the two
pins designated for the desired setting. Press the jumper evenly onto the pins. Be careful not to bend the pins.
We will show the locations of the AR-B1474 jumper pins, and the factory-default setting.
CAUTION: Do not touch any electronic component unless you are safely grounded. Wear a grounded wrist strap
or touch an exposed metal part of the system unit chassis. The static discharges from your fingers can
permanently damage electronic components.
3.2.1 Serial Port
(1) RS-485 Adapter Select (JP3 & JP11)
JP3 and JP11 can be set independently. JP3 selects COM-A port and JP11 selects COM-B port.
JP3 -- COM-A
1
2
3
Reserved for Acrosser's
RS-485 adapter used only
Figure 3-2 JP3: RS-485 Adapter Select for COM-A
1
2
3
RS-232C
(Factory Preset)
JP11 -- COM-B
1 2 3
Reserved for Acrosser's
RS-485 adapter used only
Figure 3-3 JP11: RS-485 Adapter Select—COM-B
1 2 3
RS-232C
(Factory Preset)
(2) RS-232 Connector (DB1 & DB2)
There are two serial ports with EIA RS-232C interface on the AR-B1474. COM-A and COM-B use two on-board Dtype 9-pin male connectors (DB1 & DB2). If you want to configure the serial port, please refer to the BIOS
configuration.
DB1 (COM A)
DB2 (COM B)
3-2
5 GND
5 GND
9-RI
4-DTR
4-DTR
8-CTS
3 TXD
3 TXD
7-RTS
2 RXD
2 RXD
6-DSR
1-DCD
Figure 3-4 DB1 & DB2: RS-232 Connector
1-DCD
9-RI
8-CTS
7-RTS
6-DSR
AR-B1474 User¡¦s Guide
6 +12VDC
3.2.2 Hard Disk (IDE) Connector (CN1)
A 40-pin header type connector (CN1) is provided to interface with up to two embedded hard disk drives (IDE AT
bus). This interface, through a 40-pin cable, allows the user to connect up to two drives in a “daisy chain” fashion.
To enable or disable the hard disk controller, please use BIOS Setup program to select. The following table
illustrates the pin assignments of the hard disk drive’ s 40-pin connector.