SONY KE-32TS2U, 32LG710H Service Manual

KE-32TS2U/32TS2E

UC Model

PANEL MODULE SERVICE MANUAL

AEP Model

PDP Module Name

FPF32C106128UA-7X

UK Model

Koria Model

FLAT PANEL COLOR TV

1. Out line

The module is a plasma display module which can be designed in there is no fan in addition to a general

feature of the plasma display such as a flat type, lightness, and high-viewing-angle and terrestrial

magnetism.

1.1 Out view

448

399.36

784

715.68

Pixel pitch(horizontal)

0.84mm

RGB

Pixelpitch(Vertical)

RGB

0.39 mm

-1-

RGB

Sub- pixel pitch(horizontal)

0.28mm

RGB

1.2 Feature

1. For high definition television by ALIS method

2. For FAN Less design(Low consumption electric power)

3. Thin Depth and Lightness

4. Customizing of module equipped with communication function

1.3

Specification

1.3.1 Functional specification

Item NO

Module size 1 784 x 448 x 65.5 mm ← ← Externals Weight 2 13 kg ← ←

Display panel

Color Grayscale (standard) 8 RGB each color

BrightNess White (display load

Chromaticity Coordinates Contrast Contrast in Darkroom (60Hz) 11 500:1 (TYP.)

Powersupply

Noise Shade noise at 18dB(A) or less 18 25dB(A) orless ← ← Guarantee environment

Display size 3 715.68 x 399.36 mm

Aspect ratio 4 16:9 ← ← Resolution 5 852 x 1024 pixel ← ← Pixel pitch 6 0.84(H) x 0.39(V) mm ← ← Sub pixel pitch 7 0.28(H) x 0.39(V) mm ← ←

Ratio 1%, standard) (x,y), white 10% 10 (0.300, 0.290) (TYP.)

Video signal (RGB each color) Dot clock (max) 13 52 MHz

Horizontal Sync Signal (max) 14 50KHz (LVDS)

Vertical Sync Signal 15 50Hz ± 19/60 ± 1.7Hz

Input voltage/current 16 100-120/200-240VAC

Standby electric power (max) 17 1W ← ←

Temperature (operation) 19 0 - 55°C ← ← Temperature (storage) 20 0 - 55°C ← ← Humidity (operation) 21 20 - 85%RH (no condensation) ← ← Humidity (storage) 22 20 - 80%RH (no condensation) ← ←

(32inch: 16:9)

256 Grayscale

9 650 cd/㎡ (TYP.)

12 LVDS (8bit)

(LVDS)

4.0-1.7A 50/60Hz

UA-1x UA-6x ＵＡ－7x

Specification

← ←

←

+3.3/+5/+70-90/+ 30-70V

DC

0.05/6/ 2.5 /2A

900cd/㎡

(typ.)

(0.300,0.300)

(typ.)

900:1

(typ.)

50Hz±1.9／60±

/70Hz±1.5Hz

(LVDS) +3.3/+5/+70-90/ +30-65V

0.05/6/ 2.5 /2A

← Data signal

←

← Sync Signal

1.7

DC

※ It is made to give priority when there is a delivery specification according to the customer.

-2-

1.3.2 Display quality specification

Item NO

Non-lighting cell defect

ing cell defect

Flickering cell defect

High intensity cell defect

variation

Color variation White block of 10% load

Total number (subpixel) 1 15 or less ← ← Density (subpixel/cm2) 2 2 or less

Size(HxV) (subpixel) 3 1x2 or less,

Total number (subpixel) 4 6 or less

Density (subpixel/ cm

Flickering lighting cell defect (sub pixel/ cm Flickering non-extinguishing cell defect Twice or more bright point 8 0 ← ←

White block of 10% load [9 point](%) In area adjacent 20mm [White](%)

[9 point]

2

) 5 Each color 2 cells max

2

)

6 5 or less ← ←

7 Number on inside of

9 20 or less ← ← Brightness

10 10 or less ← ←

11 X: Average ±0.015

Specification

UA-1x UA-6x UA-7x

(However,1 continuousness or less)

Or 2x1 or less

(each color 2 or less)

(However,1 continuousness or less)

Non-extinguishing cell defect

y: Average ±0.015

← ←

← ← Non-extinguish

← ←

Note: It is made to give priority when there is a delivery specification according to the customer.

-3-

1.3.3 I/0 Interface Specification

(1) I/O signal

No. Item Signal Name

Reflection signal Timing Signal

Display

1

Data

Clock

Power down Signal

MPU Comm

2

unicati on/ Control

Communication

Control

RXIN0RXIN0+ RXIN1RXIN1+ RXIN2RXIN2+ RXIN3RXIN3+

RXCLKINRXCLKIN+

PDWN 1 Input LVTTL

SDA 1 I/O

SCL 1 I/O

CPUGO 1 Input LVTTL

PDPGO 1 Input LVTTL

IRQ 1 Output LVTTL

Number

of

signals

1 1 1 1 1 1 1 1

1 1

I/O Form Content of definition

Differential serial data signal.

Input video and timing signals after differential serial conversion using a dedicated transceiver.

The serial data signal is transmitted seven times faster than the base signal.

Input

LVDS Differe ntial

Differential clock signal.

Input the clock signal after

Input

LVDS Differe ntial

differential conversion using a dedicated transceiver.

The clock signal is transmitted at the same speed as the base signal.

Low: LVDS receiver

outputs are all L.

High: Input signals are

active.

I2C bus serial data

LVTTL

2

C)

(I

communication signal. Communication with the

control MPU of this product is enabled. Low power consumption mode of the control MPU of this product is released.

“High”:

This product is started.

(CPUGO=“High” Effective) It changes into "Low" Î "High" when this product enters the undermentioned state.

1.Vcc/Va/Vs output decrease

2.Circuit abnormality detection

-4-

(2) LVDS Signal Definition and Function

A video signal (display data signal and control signal) is converted from parallel data to serial data with the LVDS transmitter and further converted into four sets of differential signals before input to this product.

These signals are transmitted seven times faster than dot clock signals.

The dot clock signal is converted into one set of differential signals by the transmitter before input to this product.

The LVDS signal definition and function are summarized below:

Signal name

Video signal

Timing signal

Transmission line

Clock transmission line RXCLKIN-

Symbol

RXIN0-

RXIN0+

RXIN1-

RXIN1+

RXIN2-

RXIN2+

RXIN3-

RXIN3+

RXCLKIN+

Number

of signals

1 1

Signal definition and function

Display data signal

R0,R1,R2,R3,R4,R5,G0

Display data signal

G1,G2,G3,G4,G5,B0,B1

Display data signal, Sync Signal, Control signal

B2,B3,B4,B5 _____ _____ _______ Hsync, Vsync, BLANK

Display data signal, Control signal

R6,R7,G6,G7,B6,B7,PARITY

Clock signal _____ DCLK

-5-

(3) Video Signal Definition and Function

The table below summarizes the definitions and functions of input video signals before LVDS conversion.

Item Signal name

Original Display signal (before LVDS transmitta nce)

Video signal (digital RGB)

Data Clock

Horizontal sync

signal

Vertical sync

signal

Parity signal PARITY 1 Input

Blanking signal BLANK 1 Input

DATA-R DATA-G DATA-B

DCLK

_____ Hsync

_____ Vsync

Number

of

signals

8 8 8

1 Input

Input/

output

Input

Display data signal R7/G7/B7 is the highest intensity bit. R0/G0/B0 is the lowest intensity bit. Display data timing signal: Data are read when DCLK is low. DCLK is continuously input.

Regulates one horizontal line of data: Begins control of the next screen when Hsync is lowered. Screen starts up control timing signal: Begins control of the next screen when Vsync is lowered. Input the same frequency in both odd-numbered and even-numbered fields.

This signal specifies the display field.

H: Odd-numbered field

L: Even-numbered field Parity signal should be alternated in every Vsync cycle. This signal is arbitrarily reversed internally when there is no reversing signal.

Display period timing signal.

H indicates the display period and L indicates

the non display period.

Note:

Set this timing properly like followings, as is

used internally for signal processing.

・Set the blanking period so that the number

of effective display data items in one

horizontal period is 852.

・Set the number of blanking signals in one

vertical period to 512, which is one half the

number of effective scan lines.

If the BLANK changes when the Vsync

frequency is switched, the screen display may

be disturbed or brightness may change.

The screen display is restored to the normal

state later when the BLANK length is

constant again.

Signal definition and function

-6-

(4) Connector Specifications

The connector specification is shown below.

Please do not connect anything with the terminal NC.

(I) Signal connector CN1: DF13-20DP-1.25 V (tin-plated) (Maker: HIROSE DENKI)

1 RXIN0- 2 GND

3 RXIN0+ 4 SCL

5 RXIN1- 6 GND

7 RXIN1+ 8 SDA

9 RXIN2- 10 GND

11 RXIN2+ 12 CPUGO

13 RXCLKIN- 14 PDPGO

15 RXCLKIN+ 16 IRQ

17 RXIN3- 18 PDWN

19 RXIN3+ 20 GND

Pin No. Signal name Pin No. Signal name

[Conforming connector] Housing: DF13-20DS-1.25C

Contact: DF-2630SCF

(II) Power Source Connectors for power supply(jig)

(a) Power input connector (b) Power supply output connector for system

CN61: B06P-VH CN62:B03P-VH

(Maker: JST) (Maker: JST)

Pin No. Symbol

1 AC(L) 2 N.C 3 AC(N) 4 N.C

5

6 F.G

[Conforming connector]

Housing: VHR-06N (or M) Contact: SVH-21T-P1.1

N.C

Pin No. Symbol

1 V 2 N.C 3 GND

[Conforming connector]

Housing: VHR-03N (or M) Contact: SVH-21T-P1.1

AUX

(c) Power supply output connector for system

CN63: B5B-XH-A

(Maker: JST)

Pin No. Symbol

1 Vpr1 2 N.C. 3 Vpr2 4 N.C. 5 GND

[Conforming connector]

Housing: XHP-5 Contact: SXH-001T-P0.6

-7-

Power Source Connectors

(III)

Power supply output (b)Power supply output (c)Power supply output

(a)

connector for system

connector for system connector for system

CN6: B6B-PH-SM3-TB(JST) CN23: B10PS-VH(JST) CN33: B9PS-VH(JST)

Pin No. Symbol Pin No. Symbol

1 Vpr2 1 Va 1 Vcc

2 N.C. 2 N.C. 2 GND

3 GND 3 Vcc 3 GND

4 GND 4 GND 4 GND

5 N.C. 5 GND 5 GND

6 Vcc 6 GND 6 N.C.

[Conforming connector]

Housing: PHR-6 Contact: SPH-002T-P0.5L

10 Vs

7 N.C. 7 Vs 8 Vs 9 Vs 9 Vs

[Conforming connector]

Housing: VHR-10N Contact: SVH-21T-

P1.1

Pin No. Symbol

8 Vs

[Conforming connector]

Housing: VHR-9N Contact: SVH-21T-P1.1

Power supply output (e)Power supply output

(d)

connector for system

CN42: B7B-PH-SM3-TB(JST) CN52: B7B-PH-SM3-TB(JST)

Pin No. Symbol Pin No. Symbol

1 Va 1 Va

2 N.C. 2 N.C.

3 N.C. 3 N.C.

4 GND 4 GND

5 GND 5 GND

6 N.C. 6 N.C.

7 Vcc 7 Vcc

[Conforming connector]

Housing: PHR-7 Contact: SPH-002T-P0.5L

[Conforming connector]

Housing: PHR-7 Contact: SPH-002T-P0.5L

-8-

Power supply output

(f)

connector for system

CN7: 00 6200 520 330 000 [ZIF Right Angle Connector](kyousera elco)

Pin No. Symbol Pin No. Symbol

1 N.C. 11 GND 2 N.C. 12 Vra

3 N.C. 13 GND 4 N.C. 14 Vrs 5 GND 15 GND 6 VSAGO 16 Iak 7 GND 17 GND 8 VCEGO 18 Vak 9 GND 19 GND

10 PFCGO 20 Vsk

-9-

2. Notes on safe handling of the plasma display

2. 1 Notes to follow during servicing

 The work procedures shown with the Note indication are important for ensuring the safety of the

product and the servicing work. Be sure to follow these instructions.

 Before starting the work, secure a sufficient working space.

 At all times other than when adjusting and checking the product, be sure to turn OFF the main

POWER switch and disconnect the power cable from the power source of the display (jig or the display itself) during servicing.

 To prevent electric shock and breakage of PC board, start the servicing work at least 30 seconds after the

main power has been turned off. Especially when installing and removing the power supply PC board and the SUS PC board in which high voltages are applied, start servicing at least 2 minutes after the main power has been turned off.

 While the main power is on, do not touch any parts or circuits other than the ones specified.

The high voltage power supply block within the PDP module has a floating ground. If any connection other than the one specified is made between the measuring equipment and the high voltage power supply block, it can result in electric shock or activation of the leakage-detection circuit breaker.



When installing the PDP module in, and removing it from the packing carton, be sure to have at least two persons perform the work while being careful to ensure that the flexible printed-circuit cable of the PDP module does not get caught by the packing carton.

 When the surface of the panel comes into contact with the cushioning materials, be sure to confirm

that there is no foreign matter on top of the cushioning materials before the surface of the panel comes into contact with the cushioning materials. Failure to observe this precaution may result in the surface of the panel being scratched by foreign matter.

 When handling the circuit PC board, be sure to remove static electricity from your body before

handling the circuit PC board.

 Be sure to handle the circuit PC board by holding the such large parts as the heat sink or transformer.

Failure to observe this precaution may result in the occurrence of an abnormality in the soldered areas.

 Do not stack the circuit PC boards.

Failure to observe this precaution may result in problems resulting from scratches on the parts, the deformation of parts, and short-circuits due to residual electric charge.

 Routing of the wires and fixing them in position must be done in accordance with the original routing

and fixing configuration when servicing is completed.

All the wires are routed far away from the areas that become hot (such as the heat sink). These wires are fixed in position with the wire clamps so that the wires do not move, thereby ensuring that they are not damaged and their materials do not deteriorate over long periods of time. Therefore, route the cables and fix the cables to the original position and states using the wire clamps.

 Perform a safety check when servicing is completed.

Verify that the peripherals of the serviced points have not undergone any deterioration during servicing. Also verify that the screws, parts and cables removed for servicing purposes have all been returned to their proper locations in accordance with the original setup.

-10-

g

3. Name and Function

3.1 Configuration

Scan module

⑦Ps cable

⑩PSU

Si

Panel chassis

Serial Id label

nal cable

ADM1

ADM2

③Y-SUS board

ADM3

ADM4

⑥PSU board *1

ADM5

ADM6

Product label

②X-SUS board

ADM7

Address module(ADM)

⑧Signal

cable

XBB

④ABUSL board ⑤ABUSR board

①LOGIC board

The figure shows the article number in the parts information table of clause 7.

*1:Power supply(jig)

-11-

Y

/

3.2 Block Diagrams

3.2.1 Signal Diagrams

Y----SUS

SUS B.

SUSSUS

Y-SUS

Y-SCAN

Y-SUS

ODD SW

Y-SCAN

ODD SW

B.

B. B.

Y

EVEN SW

POS /NEG

RESET SW

MMMM

DDDD

MMMM

SSSS DDDD

SSSS

XXXX----SUS

SUS B.

B.

SUSSUS

XXXX BBBB BBBB

XXXX BBBB

ADM1 ADM2 ADM3 ADM4 ADM5 ADM6 ADM7

ABUSR B.

ABUSL

ABUSL BBBB．

ABUSLABUSL

CN51 CN41

．

．．

ABUSR B.

ABUSR B.ABUSR B.

BBBB

B. B.

X-SUS

EVEN SW

X-SCAN

EVEN SW

X-SUS

ODD SW

X-SCAN

ODD SW

POS

RESET SW

SIGNAL

INPU T

CN31

LOGIC

LOGIC B.

TIMMING ROM

CN3 CN2

LOGICLOGIC

B.

B.B.

SCAN CONTROLLER

OSC

24MHz

CN1

LVDS

I2C

Analog SW

OSC

8MHz

DATA PROCESSOR

SCI.

FLASH

RGB GAIN

γ comp.

V-SYNC cont.

Ｆailure DET.

DITHER

ERR DIF.

MPU

APC cont.

I/O

DATA CONVERTER

SUB FIELD

PRC.

OSC

50MHz

EEPROM

D/A

OSC

80MHz

Vrs Vra Vrw Vrx

MEMORY

CONTROLLER

FRAME

MEMORY

CN21

CN5

CN4

CN7

-12-

PFCgo Vsago Vcego

Y

g

p

3.2.2 Power Diagrams

Y----SUS

SUS B.

B.

SUSSUS

Y

EVEN SW

POS/NEG

RESET SW

B. B.

Y-SUS

Y-SCAN

Y-SUS

ODD SW

Y-SCAN

ODD SW

SSSS

DDDD

MMMM

SSSS

DDDD

MMMM

XXXX----SUS

SUS B.

B.

SUSSUS

XXXX BBBB

BBBB

XXXX

ADM1 ADM2 ADM3 ADM4 ADM5 ADM6 ADM7

ABUSL

ABUSL BBBB．

ABUSLABUSL

．

．．

ABUSR B.

ABUSR B.ABUSR B.

BBBB BBBB

B. B.

X-SUS

EVEN SW

X-SCAN

EVEN SW

X-SUS

ODD SW

X-SCAN

ODD SW

POS

RESET SW

YFVCC1 YFVCC2 FVE5H

5V 5V 17V

FVE1 YFVE2 VE

Y

17V 17V 17V

DC/DC

CONVERTER

Vcc 5V

CN33

AC100 -

240V

Vw 160V Vb -5V

10A

CN61

Va

CN32 CN22

Vra Vrs Vrw Vrx

CPUgo PDPgo

D/A

CN42CN52

Vxwgo

MPU

Vrst

RST

LOGIC

Servce

PFC

SW

o

PFC

V V

380V

r2 3.3V

r1 5V

LOGIC B.

LOGICLOGIC

CN6

B.

B. B.

Vsago

Vcego

55V

5V

80V

CN65

CN68

CN67

CN66

Vb Vx

-5V 45V

DC/DC

CONVERTER

Vs 80V

XFVCC1 XFVCC2 VEW

5V 5V 17V

FVE1 XFVE2 VE

X

17V 17V 17V

DC/DC

CONVERTER

CN23

Vsa

PFCgo

Vsago

o

Vce

Control

o

PSU

PSU B.

B. *1

PSUPSU

B. B.

*1

*1 *1

Vra Vrs

-13-

CN64

*1:Power supply (jig)

3.3 Function

3.3.1 Logic board Function

(1) Data Processor

z γadjustment (1/2.2/2.4/2.6/2.8) z NTSC/EBU format（Color matrix）Switch z RGB gain Control（White balance adjustment、Amplitude limitation）

z Error Diffusion Technology (Grayscale adjustment)

z Dithering (Grayscale adjustment)

z Burn-in Pattern generation

(2) Scan Controller

z Address driver control signal generator (ADM)

z Scan driver control signal generator (SDM)

z X/Y sustain control signal generator

(3) Waveform ROM

z Waveform Pattern for drive / Timing memory

(4) MPU

z Synchronous detection

z System control

z Driving voltage (Va,Vs,Vr,Vw) adjustment and tuning

z Abnormal watching (breakdown detection) / abnormal processing

z Is (sustain) current control (sustain pulse control)

z Ia (address) current control (sub-field control)

z External communication control

z Waveform ROM pattern writing

(5) EEPROM

z Control parameter memory

z The accumulation energizing time (Every hour).

z Abnormal status memory (16 careers)

-14-

Sub

Address

Data

bit

00

7-0

01

4-0

02 7-0 ERRC Error Code

Symbol Item Function

MAPVER

7 ERRF update of Error

6 OHRF

PSDF

5

CNDC Condition Code Indicates status of the module. -

address MAP Version

Flag

update of Operation Hours Flag

Power Shut

Down Flag

Indicates the version number of the address map.

Indicates that an error has occurred.

It can be cleared with the ErrRST setting.

If this flag is set,

• Error code is written.

• Cannot enter the PDP-ON mode.

Indicates that the drive hours are counted.

Indicates that shutdown of the AC power is detected and the PDP has executed the OFF-sequence. It can be cleared with the PSDRST setting.

Indicates error code.

The error codes of as many as 16 errors in the past can be retrieved with the ERRS setting.

continuously.

03

04

20

OHRH

7-0

OHRL

7-0

PATSEL

7

PATON

6

ADEN

5

- -

4

- -

3

3 DSPPRT

Operation Hours Higher bits

Operation Hours Lower bits

Selecting patterns

Built-in pattern display is set to ON.

Address data enable

DiSPlay PaRiTy

Indicates the higher 8 bits of the module driving hours. *1)

Indicates the lower 8 bits of the module driving hours. *1)

It selects the built-in test pattern signals of this display. This setting is valid when the PATON setting is 1.

Display of the built-in pattern signal in this product is turned ON/OFF.

The black screen is displayed.

0 is set when the input video signal has disturbance.

Be sure to use the display with the setting fixed to 0.

Be sure to use the display with the setting fixed to 1.

Input reflection polarity setting

. Same error code is not stored

Setting [hex]

RANGE INITIAL value

00 ~ FF

0: Not updated

1: Updated

0: Not updated

1: Updated

0: Not detected

1: Detected

00~FF 00

00~FF

0: The single

color display is switched every 2 seconds. A total of 8 colors are displayed.

1: All white

(Different from actual white.)

0: Displaying

the input signal

1: Displaying

the built-in pattern

0: Blank

1: Displaying

the input signal

0~1

0:Emits light by

LOW

1:Emits light by

High

01【UA1x/6x】

02【UA7x 】

0

-

00

0

1

0

1【UA1x/6x】

1【UA7x 】

-15-

Sub

Address

Data

bit

Symbol Item Function

Setting [hex]

RANGE INITIAL value

20

2 IFON

1 PDPON

0

Interface power supply ON

High voltage power supply

ON

*1) It is not the one to guarantee brightness.

Sub

Address

21

22

Sub Data

Data

bit

7-5

7-6

5-3

Symbol Item Function

- -

4

CCFMD

3 DCBON

2 HAON

1

- -

0 DSETEN

7

CCFON Color correction

6 CCFORM

- -

Symbol

Color correction mode

Dynamic Color Balance

Heat APC function

Data set enable

Color correction format

Item

Switches the interface power ON/OFF.

Use this item when you want turn ON the main power of the interface side only when the PDPON is set to 0. This setting is invalid when PDPON is set to 1.

Switches ON/OFF the high voltage power supply of PDP.

Be sure to use the display with the setting fixed to 1.

Be sure to use the display with the setting fixed to 0.

Selecting the color correction modes. Valid when the CCFON setting is 1

Tracking correction of white balance between the high luminance and the low luminance.

When a picture with high luminance/small area is displayed for about 3 minutes or longer, the number of pulses is reduced to about 20% at a maximum. This item can be used to reduce panel temperature/extend useful life when the display is used to show a still image.

Be sure to use the display with the setting fixed to 0.

Whether the register value is reflected to the operating status of this product, selected by this item.

The following switch is executed.

0: The received register value is reflected

from the next field.

1: The received register value is stored so

that the DSET setting is reflected from the next field. (DSET setting: Setting bit 0 of address FF)

Color collection process is turned

ON/OFF.

Color collection process is switched.

This item is valid when CCFON setting is

1.

Be sure to use the display with the setting fixed to 0.

Function

0: Power OFF

1: Power ON

0: Power OFF

1: Power ON

0~1 1

Setting[hex]

RANGE INITIAL value

0~7

0: Luminance

has priority.

1: Gradation

has priority

0: OFF 1: ON

0: OFF

1: ON

0~1

0: Invalid

1: Valid

0: OFF 1: ON

0: NTSC

1: EBU

0~7

Setting [hex]

0【UA1x/6x】

0【UA7x】

0

1

0

-16-

Addre

22 2-0 GAMSEL

23 7-0

24

25 7-0 G-RATIO G ratio 00~FF FF

bit

ss

7-0 R-RATIO

Reverse γ correction level is set.

The setup 7 is the test mode. Do not select the setup 7.

CONTRAS T

Selecting the reverse γ correction

Peak luminance

R ratio

When the setup 6 is selected, setting of the addressed in the range of 31~51 become valid.

Peak luminance is adjusted.

When the display picture load is heavy, the peak luminance is automatically limited.

White balance is adjusted.

Use the display with at least one item being set to FF (hex).

RANGE

0: OFF 1: 1.0 th power 2: 2.2 nd

power 3: 2.4 th power 4: 2.6 th power 5: 2.8 th power 6: USER 7: TEST

00~FF FF

INITIAL

value

2

26

7-0 B-RATIO B ratio

7 IRQRST

6 ERRRST

5 - - Be sure to use the display with the setting

5 OHRRST

27

4 PSDRST Clearing the

3-0 ERRS Error code

28

7-6 -

7

Sub Data

PWMP

Symbol

Clearing the IRQ output signal

Clearing the ERRF flag

Clearing the OHRF flag

PSDF flag

selection

-

Power Maximam peek control

Item

This item implements control to return the IRQ signal from "HIGH" to "Low" level when an error occurs. When this item is set to 1, the IRQ signal is returned to "Low" level.

This item implements control to return the ERRF flag to 0 when an error occurs.

When this item is set to 1, this setting automatically returns to 0 after returning the ERRF flag to 0.

fixed to 0.

The control by which the OHRF flag is returned to 0 is done. This setting automatically returns to the state of 0 after returning 0 the ERRF flag when this setting is set to one.

This item exercise control to return the PSDF flag to 0 when this machine performs the OFF sequence at AC power shutdown. When this item is set to 1, this setting automatically returns to 0 after returning the PSDF flag to 0.

When this setting is changed and the ERRC setting is read out, the error contents (as many as 16 errors) of the module that have occurred in the past can be checked.

If more than 16 errors have occurred, the error code is updated starting from the oldest error.

Be sure to use the display with the setting fixed to 0.

The PWMAX setting is switched to constant brightness (peak electric power) control. The password setting is necessary to turn on this setting.

Function

00~FF

0: Normal

1: IRQ signal

clear

0: Normal

1: ERRF

flag clear

0~1 0【UA1x/6x】

0: Normal

1: OHRF

flag clear

0: Normal

1: PSDF

flag clear

0: Latest error

1: Previous

error

2:

|

E:

F:Oldest error

0~3 0【UA1x/6x】

When password

is set

0:OFF 1:ON

Setting [hex]

FF

0

0【UA7x】

0

0【UA7x】

-17-

Addre

28

29

2C

2D 7-0 PsTTM Ps-Tank TiMe

31

32

33 7-0

34

35

Sub Data

bit

ss

6 -

5-4 PWMAX

- -

3-0

PWM

7-0

PASS

7-0 PsTPW

7-0 GAM00

7-2 - <no use> -

GAM01

1-0

[9: 8]

GAM01 [7: 0]

7-3 - <no use> -

GAM02

2-0

[10: 8]

GAM02

7-0

[7: 0]

Symbol

-

Maximum power consumption

Password of peak electric power setting

Ps-Tank PoWer

Reverse γ correction DC

Reverse γ coefficient 01

Reverse γ correction 02

Item

Be sure to use the display with the setting fixed to 0.

Sets the maximum power consumption.

Set this item in accordance with the status of the machine.

Make sure that the respective parts' temperature/panel temperature stays within the specifications. If the setting is set to 3, power consumption increases to a level exceeding the standard consumption. Be sure to execute the heat dissipation design so that respective parts' temperature/panel temperature stays within the specifications.

PWMP =0

PWMP =1

Be sure to use the display with the setting fixed to 0.

Password of peak electric power setting.The password is described to the delivery specifications. When the password setting is normally done, the reading value of the real thing ground becomes 51.

The maximum electric power setting:

The maximum over electric power from +10W

Time which can operate by the maximum over electric power (*10sec)

Sets the input level that implements the forced 0 [LSB] output.

Reverse γ coefficient value is set.

Input Output value of 8 [LSB]

Reverse γ coefficient value is set.

Input Output value of 16 [LSB]

Function

Setting of the maximum electric power.

Setting of peak electric power. Electric power by which electric power is permitted in addition to improve practical brightness to the maximum electric power set 3:+10W

When the amount of an over electric power becomes PsTPW×PsTTM or less at PWMP=1, the control by which brightness is lowered is done.

RANGE

0-3 0【UA7x】

0: −20W

1: −10W

2: ±0W

3: +10W

0: 0W

1: +10W

2: +20W

3: +30W

0: −20W

1: −10W

2: ±0W

3: +10W

0-F 0

51: Permission

of PWMP ON

Another:

Prohibition

00-FF 1E【UA7x】

00-FF 3C【UA7x】

00~FF 1F

00~FF 00

00~FF 04

00~FF 00

00~FF

Setting [hex]

INITIAL

value

2【UA1x/6x】

2【UA7x】

FF【UA7x】

24

-18-

Addre

36

37

38

39

3A

3B

3C

3D

3E

3F

40

41

42

43

Sub Data

bit

ss

7-4 - <no use> -

GAM03

3-0

[11:8]

GAM03

7-0

7-4 - <no use> -

3-0

7-0

7-5 - <no use> -

4-0

7-1

0

7-5 - <no use> -

4-0

7-1

0

7-5 - <no use> -

4-0

7-2

1-0

7-5 - <no use> -

4-0

7-2

1-0

7-6 - <no use> -

5-0

7-4

3-0

[7: 0]

GAM04

[11: 8]

GAM04

[7: 0]

GAM05

[12: 8]

GAM05

[7: 1]

- <no use> -

GAM06

[12: 8]

GAM06

[7: 1]

- <no use> -

GAM07

[12: 8]

GAM07

[7: 2]

- <no use> -

GAM08

[12: 8]

GAM08

[7: 2]

- <no use> -

GAM09

[13: 8]

GAM09

[7: 4]

- <no use> -

Symbol

Reverse γ correction 03

Reverse γ correction 04

Reverse γ correction 05

Reverse γ correction 06

Reverse γ correction 07

Reverse γ correction 08

Reverse γ correction 09

Item

Reverse γ coefficient value is set.

Input Output value of 24 [LSB]

00~FF 58

Reverse γ coefficient value is set. Input Output value of 32 [LSB]

Reverse γ coefficient value is set. Input Output value of 40 [LSB]

Reverse γ coefficient value is set. Input Output value of 48 [LSB]

Reverse γ coefficient value is set. Input Output value of 56 [LSB]

Reverse γ coefficient value is set. Input Output value of 64 [LSB]

Reverse γ coefficient value is set. Input Output value of 80 [LSB]

Function

RANGE

00-FF 00

00~FF 00

00~FF A7

00~FF 01

00~FF 12

00~FF 01

00~FF 9A

00~FF 02

00~FF 40

00~FF 03

00~FF 04

00~FF F0

Setting [hex]

INITIAL

value

-19-

Addre

44

45

46

47

48

49

bit

ss

7-6 - <no use> -

GAM10

5-0

[13: 8]

GAM10

7-4

[7: 4]

3-0

- <no use> -

7-6 - <no use> -

GAM11

5-0

[13: 8]

GAM11

7-4

[7: 4]

3-0

- <no use> -

7-6 - <no use> -

GAM12

5-0

[13: 8]

GAM12

7-4

[7: 4]

Reverse γ correction 10

Reverse γ correction 11

Reverse γ correction 12

Reverse γ coefficient value is set. Input Output value of 96 [LSB]

Reverse γ coefficient value is set. Input Output value of 112 [LSB]

Reverse γ coefficient value is set. Input Output value of 128 [LSB]

RANGE

00~FF 07

00~FF 60

00~FF 0A

00~FF 50

00~FF 0D

00~FF D0

INITIAL

value

3-0

7-6 - <no use> -

4A

5-0

7-4

4B

3-0 - <no use> -

7-6 - <no use> -

4C

5-0

4D

Sub Data

7-4

3-0

7-6 - <no use> -

4E

5-0

7-4

4F

3-0

7 - <no use> -

50

6-0

7-5

51

4-0

- <no use> -

[1

GAM13

3: 8]

GAM13

4]

GAM14

3: 8]

GAM14

4]

- <no use> -

GAM15

3: 8]

GAM15

4]

- <no use> -

GAM16

4: 8]

GAM16

5]

- <no use> -

Symbol

[7:

[1

[7:

[1

[7:

[1

[7:

Reverse γ correction 13

Reverse γ correction 14

Reverse γ correction 15

Reverse γ correction 16

Item

Reverse γ coefficient value is set. Input Output value of 160 [LSB]

Reverse γ coefficient value is set. Input Output value of 192 [LSB]

Reverse γ coefficient value is set. Input Output value of 224 [LSB]

Reverse γ coefficient Input Output value of 256 [LSB]

Function

00~FF 16

00~FF A0

00~FF 21

00~FF E0

00~FF 2F

00~FF 90

00~FF 40

00~FF 00

Setting [hex]

-20-

Addre

E5 7-0 UVrs USER Vrs

E6

FE

bit

ss

7-0 UVra USER Vra

7-3 － <no use>

２

RCLVr

UVrs/UVra RECALL

Setting Vrs voltage Standard equation: Vrs=2.99*UVrs/255 Setting Vra voltage Standard equation: Vra=2.99*UVra/255

Be sure to use the display with the setting

Resetting the UVrs, UVra in both of register and EEPROM to the initial value by setting RCLVr to 1. This setting automatically returns to 0 after resetting the UVrs,Uvra.

fixed to 0.

RANGE

~AA

00

~AA

00

0 0

0:Normal 1:UVrs,UVra

initialized

INITIAL

value

Adjusted in

factory

Adjusted in

factory

0

１ EWRVr

０

7-1 - -

FF

0 DSET Data setup

- -

UVrs/UVra Write

Storing the UVrs,UVra in register to EEPROM by setting EWRVr to 1. This setting automatically returns to 0 after resetting the UVrs,Uvra. Be sure to use the display with the setting fixed to 0. Be sure to use the display with the setting fixed to 0. When the DSETEN setting is 1, setting this bit causes all the register setups that have been set up to now, to be reflected to the operation status of this product. They are reflected from the next field after this bit is accepted.

0:Normal 1:UVrs,UVra

stored in EEPROM

0 0

0: Normal 1: Execute

0

-21-

SONY KE-32TS2U, 32LG710H Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

1. Out line

1.1 Out view

1.2 Feature

1.3.1 Functional specification

Specification

1.3.2 Display quality specification

1.3.3 I/0 Interface Specification

(1) I/O signal

(2) LVDS Signal Definition and Function

(3) Video Signal Definition and Function

(4) Connector Specifications

2. Notes on safe handling of the plasma display

2. 1 Notes to follow during servicing

3. Name and Function

3.1 Configuration

3.2 Block Diagrams

3.2.1 Signal Diagrams

3.2.2 Power Diagrams

3.3 Function

3.3.1 Logic board Function