Page 1
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 1 Version 0.9
SN8PC20
USER’S MANUAL
Version 0.9
SSO
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
Page 2
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 2 Version 0.9
AMENDENT HISTORY
Version
Date
Description
VER 0.1
Oct. 2007
First issue.
VER 0.2
Nov. 2007
1. Modify 455KHz crystal application circuit.
2. Add “@GreenMode” macro to control system green mode.
3. Modify IR application circuit.
VER 0.3
Jan. 2008
1. Add “Development Tool” section.
2. Modify internal low RC frequency to 10KHz @3V.
VER 0.4
May 2009
1. Modify some formals.
2. Add IHRC frequency curves.
VER 0.5
Jun. 2011
1. Add external low clock crystal type 32KHz.
VER 0.6
Sep. 2011
1. Add SN8PC2016S and SN8PC2014S package type.
VER 0.7
Mar. 2014
1. Modify “ELECTRICAL CHARACTERISTIC” operating temperature range from 0~70
℃ to -20~70℃.
VER 0.8
Dec. 2014
1. Modify “ELECTRICAL CHARACTERISTIC” Supply voltage
VER 0.9
May 2018
1. Modify “IR APPLICATION CIRCUIT“ section.
2. Modify ” ICE and EV-KIT APPLICATION NOTIC” section.
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SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version 0.9
Table of Content
AMENDENT HISTORY ................................................................................................................................ 2
1
1
1
PRODUCT OVERVIEW ......................................................................................................................... 6
1.1 FEATURES ........................................................................................................................................ 6
1.2 SYSTEM BLOCK DIAGRAM .......................................................................................................... 7
1.3 PIN ASSIGNMENT ........................................................................................................................... 8
1.4 PIN DESCRIPTIONS ......................................................................................................................... 9
1.5 PIN CIRCUIT DIAGRAMS ............................................................................................................. 10
2
2
2
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 11
2.1 PROGRAM MEMORY (ROM) ....................................................................................................... 11
2.1.1 RESET VECTOR (0000H) ...................................................................................................... 12
2.1.2 INTERRUPT VECTOR (0008H) ............................................................................................. 13
2.1.3 LOOK-UP TABLE DESCRIPTION ........................................................................................ 15
2.1.4 JUMP TABLE DESCRIPTION ............................................................................................... 17
2.1.5 CHECKSUM CALCULATION............................................................................................... 19
2.2 DATA MEMORY (RAM) ................................................................................................................ 20
2.2.1 SYSTEM REGISTER .............................................................................................................. 20
2.2.1.1 SYSTEM REGISTER TABLE ............................................................................................ 20
2.2.1.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 20
2.2.1.3 BIT DEFINITION of SYSTEM REGISTER ....................................................................... 21
2.2.2 ACCUMULATOR ................................................................................................................... 22
2.2.3 PROGRAM FLAG ................................................................................................................... 23
2.2.4 PROGRAM COUNTER........................................................................................................... 24
2.2.5 H, L REGISTERS..................................................................................................................... 27
2.2.6 Y, Z REGISTERS..................................................................................................................... 28
2.2.7 R REGISTER ........................................................................................................................... 29
2.3 ADDRESSING MODE .................................................................................................................... 30
2.3.1 IMMEDIATE ADDRESSING MODE .................................................................................... 30
2.3.2 DIRECTLY ADDRESSING MODE ....................................................................................... 30
2.3.3 INDIRECTLY ADDRESSING MODE ................................................................................... 30
2.4 STACK OPERATION ...................................................................................................................... 31
2.4.1 OVERVIEW ............................................................................................................................. 31
2.4.2 STACK REGISTERS ............................................................................................................... 32
2.4.3 STACK OPERATION EXAMPLE.......................................................................................... 33
2.5 CODE OPTION TABLE .................................................................................................................. 34
2.5.1 Reset_Pin code option .............................................................................................................. 34
2.5.2 Security code option ................................................................................................................. 34
3
3
3
RESET ..................................................................................................................................................... 35
3.1 OVERVIEW ..................................................................................................................................... 35
3.2 POWER ON RESET ......................................................................................................................... 36
3.3 WATCHDOG RESET ...................................................................................................................... 36
3.4 BROWN OUT RESET ..................................................................................................................... 37
3.4.1 THE SYSTEM OPERATING VOLTAGE .............................................................................. 38
3.4.2 LOW VOLTAGE DETECTOR (LVD) ................................................................................... 38
3.4.3 BROWN OUT RESET IMPROVEMENT............................................................................... 39
3.5 EXTERNAL RESET ........................................................................................................................ 40
3.6 EXTERNAL RESET CIRCUIT ....................................................................................................... 40
3.6.1 Simply RC Reset Circuit .......................................................................................................... 40
3.6.2 Diode & RC Reset Circuit ........................................................................................................ 41
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 4 Version 0.9
3.6.3 Zener Diode Reset Circuit ........................................................................................................ 41
3.6.4 Voltage Bias Reset Circuit ....................................................................................................... 42
3.6.5 External Reset IC ...................................................................................................................... 42
4
4
4
SYSTEM CLOCK .................................................................................................................................. 43
4.1 OVERVIEW ..................................................................................................................................... 43
4.2 FCPU (INSTRUCTION CYCLE) ...................................................................................................... 43
4.3 SYSTEM HIGH-SPEED CLOCK .................................................................................................... 44
4.3.1 HIGH_CLK CODE OPTION ................................................................................................... 44
4.3.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC) ............................................. 44
4.3.3 EXTERNAL HIGH-SPEED OSCILLATOR ........................................................................... 44
4.3.4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT ....................................................... 45
4.4 SYSTEM LOW-SPEED CLOCK ..................................................................................................... 46
4.5 OSCM REGISTER ........................................................................................................................... 47
4.6 SYSTEM CLOCK MEASUREMENT ............................................................................................. 47
4.7 SYSTEM CLOCK TIMING ............................................................................................................. 48
5
5
5
SYSTEM OPERATION MODE ........................................................................................................... 50
5.1 OVERVIEW ..................................................................................................................................... 50
5.2 NORMAL MODE ............................................................................................................................ 51
5.3 SLOW MODE .................................................................................................................................. 51
5.4 POWER DOWN MDOE .................................................................................................................. 51
5.5 GREEN MODE ................................................................................................................................ 52
5.6 OPERATING MODE CONTROL MACRO .................................................................................... 53
5.7 WAKEUP ......................................................................................................................................... 54
5.7.1 OVERVIEW ............................................................................................................................. 54
5.7.2 WAKEUP TIME ...................................................................................................................... 54
5.7.3 P1W WAKEUP CONTROL REGISTER ................................................................................ 55
6
6
6
INTERRUPT ........................................................................................................................................... 56
6.1 OVERVIEW ..................................................................................................................................... 56
6.2 INTEN INTERRUPT ENABLE REGISTER ................................................................................... 56
6.3 INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 57
6.4 GIE GLOBAL INTERRUPT OPERATION .................................................................................... 57
6.5 PUSH, POP ROUTINE..................................................................................................................... 58
6.6 EXTERNAL INTERRUPT OPERATION (INT0) ........................................................................... 59
6.7 T0 INTERRUPT OPERATION........................................................................................................ 60
6.8 MULTI-INTERRUPT OPERATION ............................................................................................... 61
7
7
7
I/O PORT ................................................................................................................................................ 62
7.1 OVERVIEW ..................................................................................................................................... 62
7.2 I/O PORT MODE ............................................................................................................................. 63
7.3 I/O PULL UP REGISTER ................................................................................................................ 64
7.4 I/O PORT DATA REGISTER .......................................................................................................... 65
8
8
8
TIMERS .................................................................................................................................................. 66
8.1 WATCHDOG TIMER ...................................................................................................................... 66
8.2 TIMER 0 (T0) ................................................................................................................................... 68
8.2.1 OVERVIEW ............................................................................................................................. 68
8.2.2 T0 Timer Operation .................................................................................................................. 68
8.2.3 T0M MODE REGISTER ......................................................................................................... 69
8.2.4 T0C COUNTING REGISTER ................................................................................................. 69
8.2.5 T0 TIMER OPERATION SEQUENCE ................................................................................... 70
9
9
9
IR OUTPUT ............................................................................................................................................ 71
9.1 OVERVIEW ..................................................................................................................................... 71
9.2 IR CONTROL REGISTER ............................................................................................................... 71
9.2.1 IRM MODE REGISTER .......................................................................................................... 71
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 5 Version 0.9
9.2.2 IRC COUNTING REGISTER.................................................................................................. 72
9.2.3 IRR AUTO-LOAD REGISTER ............................................................................................... 72
9.2.4 IRD IR DUTY CONTROL REGISTER .................................................................................. 73
9.3 IR OUTPUT OPERATION SEQUENCE......................................................................................... 74
9.4 IR APPLICATION CIRCUIT .......................................................................................................... 75
1
1
1
0
0
0
INSTRUCTION TABLE ................................................................................................................... 76
1
1
1
1
1
1
ELECTRICAL CHARACTERISTIC .............................................................................................. 77
11.1 ABSOLUTE MAXIMUM RATING ................................................................................................ 77
11.2 ELECTRICAL CHARACTERISTIC ............................................................................................... 77
11.3 CHARACTERISTIC GRAPHS ................................................................................................................. 78
1
1
1
2
2
2
DEVELOPMENT TOOL .................................................................................................................. 79
12.1 SN8PC20 EV-KIT ............................................................................................................................. 79
12.2 ICE AND EV-KIT APPLICATION NOTIC ...................................................................................... 80
1
1
1
3
3
3
OTP PROGRAMMING PIN ............................................................................................................. 81
13.1 THE PIN ASSIGNMENT OF EASY WRITER TRANSITION BOARD SOCKET: .............................................. 81
13.2 PROGRAMMING PIN MAPPING: .......................................................................................................... 82
1
1
1
4
4
4
MARKING DEFINITION ................................................................................................................. 83
14.1 INTRODUCTION ............................................................................................................................ 83
14.2 MARKING INDETIFICATION SYSTEM ...................................................................................... 83
14.3 MARKING EXAMPLE ................................................................................................................... 84
14.4 DATECODE SYSTEM .................................................................................................................... 84
1
1
1
5
5
5
PACKAGE INFORMATION ........................................................................................................... 85
15.1 P-DIP 20 PIN .................................................................................................................................... 85
15.2 SOP 20 PIN ....................................................................................................................................... 86
15.3 SSOP 20 PIN ..................................................................................................................................... 87
15.4 SOP 16 PIN ....................................................................................................................................... 88
15.5 SOP 14 PIN ....................................................................................................................................... 89
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SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 6 Version 0.9
1
1
1
PRODUCT OVERVIEW
1.1 FEATURES
Features Selection Table
CHIP
ROM
RAM
Stack
T0
Oscillator
I/O
IR
Output
Wakeup
Pin No.
Package
Ext.
455K
Ext.
4M
Int.
8M
SN8PC01
0.5K*16
32 4 - V - - 16
Fix 38KHz,
Normal current
9
PDIP20/SOP20
SN8PC13
2K*16
48 4 V - V - 16
Duty/cycle programmable,
Normal current
15
PDIP20/SOP20/
SSOP20
SN8PC20
2K*16
56 4 V V V V 18
Duty/cycle programmable,
400mA sink current
16
PDIP20/SOP20/
SSOP20
SN8PC2016
2K*16
56 4 V V V V 14
Duty/cycle programmable,
400mA sink current
12
SOP16
SN8PC2014
2K*16
56 4 V V V V 12
Duty/cycle programmable,
400mA sink current
10
SOP14
Memory configuration
2 interrupt sources
OTP ROM size: 2K * 16 bits.
1 internal interrupts: T0
RAM size: 56 * 8 bits.
1 external interrupts: INT0
4 levels stack buffer.
One 8-bit timer. (T0).
T0: Basic timer.
I/O pin configuration
Bi-directional: P0, P1, P5.
One channel duty/cycle programmable IR output.
400mA IR output pin: P5.4/IROUT
Wakeup: P0, P1 level change trigger.
Five system clocks
Pull-up resisters: P0, P1, P5.
External high clock: RC type up to 8 MHz
External Interrupt trigger edge: P0.0
External high clock: Crystal type up to 8 MHz
controlled by PEDGE register.
External low clock: Crystal type 32KHz and 455KHz
Internal high clock: RC type 8MHz
1-Level LVD.
Internal low clock: RC type 10KHz(3V)
Fcpu (Instruction cycle)
Four operating modes
Fcpu = Fosc/1, Fpsc/2, Fosc/4, Fosc/8
Normal mode: Both high and low clock active
Slow mode: Low clock only
Powerful instructions
Sleep mode: Both high and low clock stop
One clocks per instruction cycle (1T)
Green mode: Periodical wakeup by timer
Most of instructions are one cycle only.
All ROM area JMP instruction.
Package (Chip form support)
All ROM area CALL address instruction.
PDIP 20 pin
All ROM area lookup table function (MOVC).
SOP 20 pin
SSOP 20 pin
SOP 16 pin
SOP 14 pin
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 7 Version 0.9
1.2 SYSTEM BLOCK DIAGRAM
INTERRUPT
CONTROL
EXTERNAL
HIGH OSC.
ACC
INTERNAL
LOW RC
TIMING GENERATOR
RAM
SYSTEM REGISTERS
1-Level LVD
(Low Voltage Detector)
WATCHDOG TIMER
TIMER & COUNTER
P0 P5P1
IR Generator
ALU
PC
FLAGS
IR
OTP
ROM
INTERNAL HIGH
RC 8MHz
IR Output
Page 8
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 8 Version 0.9
1.3 PIN ASSIGNMENT
SN8PC20P (PDIP 20 pins)
SN8PC20S (SOP 20 pins)
SN8PC20X (SSOP 20 pins)
VDD
1 U 20
VSS
P0.0/INT0
2 19
P5.4/IROUT
P0.1
3 18
P5.0
P0.2/RST/VPP
4 17
P1.7
P0.3/XIN
5 16
P1.6
P0.4/XOUT
6 15
P1.5
P0.5
7 14
P1.4
P0.6
8 13
P1.3
P0.7
9 12
P1.2
P1.0
10 11
P1.1
SN8PC2016S (SOP 16 pins)
VDD
1 U 16
VSS
P0.0/INT0
2 15
P5.4/IROUT
P0.1
3 14
P5.0
P0.2/RST/VPP
4 13
P1.5
P0.3/XIN
5 12
P1.4
P0.4/XOUT
6 11
P1.3
P0.5
7 10
P1.2
P1.0
8 9
P1.1
SN8PC2014S (SOP 14 pins)
VDD
1 U 14
VSS
P0.0/INT0
2 13
P5.4/IROUT
P0.1
3 12
P5.0
P0.2/RST/VPP
4 11
P1.3
P0.3/XIN
5 10
P1.2
P0.4/XOUT
6 9
P1.1
P0.5
7 8
P1.0
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SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 9 Version 0.9
1.4 PIN DESCRIPTIONS
PIN NAME
TYPE
DESCRIPTION
VDD, VSS
P
Power supply input pins for digital and analog circuit.
P0.2/RST/
VPP
I, P
RST: System external reset input pin. Schmitt trigger structure, active “low”, normal stay to
“high”.
VPP: OTP power input pin in programming mode.
P0.2: Input only pin with Schmitt trigger structure and no pull-up resistor.
XIN/P0.3
I/O
XIN: Oscillator input pin while external oscillator enable (crystal and RC).
P0.3: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors and level change
wake-up function as input mode.
XOUT/P0.4
I/O
XOUT: Oscillator output pin while external crystal enable.
P0.4: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors and level change
wake-up function as input mode.
P0.0/INT0
I/O
P0.0: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors and level change
wake-up function as input mode.
INT0: External interrupt 0 input pin.
P0.1,
P0[7:5]
I/O
P0: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors and level change wake-up
function as input mode.
P1[7:0]
I/O
P1: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors and level change wake-up
function controlled by P1W register as input mode.
P5.0
I/O
P5.0: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors as input mode.
P5.4/IROUT
I/O
P5.4: Bi-direction pin. Schmitt trigger structure. Built-in pull-up resistors as input mode.
IROUT: Duty/cycle programmable IR signal output pin.
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 10 Version 0.9
1.5 PIN CIRCUIT DIAGRAMS
I/O with Schmitt-trigger (ViH=0.7*Vdd, ViL=0.3*Vdd) and Pull-up Resistor(200KΩ@3V):
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
Input Only with Schmitt-trigger (ViH=0.7*Vdd, ViL=0.3*Vdd) and Vpp High Voltage:
Pin
OTP Program Mode
Input Bus
OTP Vpp Input
Reset Pin Code Option
Reset Trigger
Oscillator shared I/O with Schmitt-trigger (ViH=0.7*Vdd, ViL=0.3*Vdd) and Pull-up Resistor(200KΩ@3V):
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
Oscillator
Code Option
Oscillator
IR output shared I/O with Schmitt-trigger (ViH=0.7*Vdd, ViL=0.3*Vdd) and Pull-up Resistor(200KΩ@3V):
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
IREN
IR Signal
Page 11
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 11 Version 0.9
2
2
2
CENTRAL PROCESSOR UNIT (CPU)
2.1 PROGRAM MEMORY (ROM)
2K words ROM
ROM
0000H
Reset vector
User reset vector
Jump to user start address
0001H
General purpose area
. .
0007H
0008H
Interrupt vector
User interrupt vector
0009H
General purpose area
User program
. . 000FH
0010H
0011H . . . . .
07FCH
End of user program
07FDH
Reserved
07FEH
07FFH
The ROM includes Reset vector, Interrupt vector, General purpose area and Reserved area. The Reset vector is
program beginning address. The Interrupt vector is the head of interrupt service routine when any interrupt occurring.
The General purpose area is main program area including main loop, sub-routines and data table.
Page 12
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 12 Version 0.9
2.1.1 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
Power On Reset (NT0=1, NPD=0).
Watchdog Reset (NT0=0, NPD=0).
External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
Example: Defining Reset Vector
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
10H START:
; 0010H, The head of user program.
…
; User program
…
ENDP
; End of program
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 Version 0.9
2.1.2 INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
PUSH
; Save ACC and PFLAG register to buffers.
… …
POP
; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine
…
START:
; The head of user program.
…
; User program
…
JMP
START
; End of user program
…
ENDP
; End of program
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 14 Version 0.9
Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
JMP
MY_IRQ
; 0008H, Jump to interrupt service routine address.
ORG
10H START:
; 0010H, The head of user program.
…
; User program.
…
…
JMP
START
; End of user program.
…
MY_IRQ:
;The head of interrupt service routine.
PUSH
; Save ACC and PFLAG register to buffers.
…
…
POP
; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine.
…
ENDP
; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.
Page 15
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 15 Version 0.9
2.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
Example: To look up the ROM data located “TABLE1”.
B0MOV
Y, #TABLE1$M
; To set lookup table1’s middle address
B0MOV
Z, #TABLE1$L
; To set lookup table1’s low address.
MOVC
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
INCMS
Z
; Z+1
JMP
@F
; Z is not overflow.
INCMS
Y
; Z overflow (FFH 00), Y=Y+1
NOP
;
;
@@:
MOVC
; To lookup data, R = 51H, ACC = 05H.
… ; TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must be take care such situation to avoid look-up table errors. If Z register is
overflow, Y register must be added one. The following INC_YZ macro shows a simple method to process
Y and Z registers automatically.
Example: INC_YZ macro.
INC_YZ
MACRO
INCMS
Z
; Z+1
JMP
@F
; Not overflow
INCMS
Y
; Y+1
NOP
; Not overflow
@@:
ENDM
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 16 Version 0.9
Example: Modify above example by “INC_YZ” macro.
B0MOV
Y, #TABLE1$M
; To set lookup table1’s middle address
B0MOV
Z, #TABLE1$L
; To set lookup table1’s low address.
MOVC
; To lookup data, R = 00H, ACC = 35H
INC_YZ
; Increment the index address for next address.
;
@@:
MOVC
; To lookup data, R = 51H, ACC = 05H.
… ; TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV
Y, #TABLE1$M
; To set lookup table’s middle address.
B0MOV
Z, #TABLE1$L
; To set lookup table’s low address.
B0MOV
A, BUF
; Z = Z + BUF.
B0ADD
Z, A
B0BTS1
FC
; Check the carry flag.
JMP
GETDATA
; FC = 0
INCMS
Y
; FC = 1. Y+1.
NOP
GETDATA:
;
MOVC
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
Page 17
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 17 Version 0.9
2.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
Example: Jump table.
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
PCL, A
; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP
A0POINT
; ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A
MACRO
VAL
IF
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP
($ | 0XFF)
ORG
($ | 0XFF)
ENDIF
B0ADD
PCL, A
ENDM
Note: “VAL” is the number of the jump table listing number.
Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV
A, BUF0
; “BUF0” is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
JMP
A0POINT
; ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
JMP
A4POINT
; ACC = 4, jump to A4POINT
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Remote Control 8-Bit Micro-Controller
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If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A” macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
Example: “@JMP_A” operation.
; Before compiling program.
ROM address
B0MOV
A, BUF0
; “BUF0” is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
0X00FD
JMP
A0POINT
; ACC = 0, jump to A0POINT
0X00FE
JMP
A1POINT
; ACC = 1, jump to A1POINT
0X00FF
JMP
A2POINT
; ACC = 2, jump to A2POINT
0X0100
JMP
A3POINT
; ACC = 3, jump to A3POINT
0X0101
JMP
A4POINT
; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
B0MOV
A, BUF0
; “BUF0” is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
0X0100
JMP
A0POINT
; ACC = 0, jump to A0POINT
0X0101
JMP
A1POINT
; ACC = 1, jump to A1POINT
0X0102
JMP
A2POINT
; ACC = 2, jump to A2POINT
0X0103
JMP
A3POINT
; ACC = 3, jump to A3POINT
0X0104
JMP
A4POINT
; ACC = 4, jump to A4POINT
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 19 Version 0.9
2.1.5 CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
MOV
A,#END_USER_CODE$L
B0MOV
END_ADDR1, A
; Save low end address to end_addr1
MOV
A,#END_USER_CODE$M
B0MOV
END_ADDR2, A
; Save middle end address to end_addr2
CLR
Y
; Set Y to 00H
CLR
Z
; Set Z to 00H
@@:
MOVC
B0BSET
FC
; Clear C flag
ADD
DATA1, A
; Add A to Data1
MOV
A, R
ADC
DATA2, A
; Add R to Data2
JMP
END_CHECK
; Check if the YZ address = the end of code
AAA:
INCMS
Z
; Z=Z+1
JMP
@B
; If Z != 00H calculate to next address
JMP
Y_ADD_1
; If Z = 00H increase Y
END_CHECK:
MOV
A, END_ADDR1
CMPRS
A, Z
; Check if Z = low end address
JMP
AAA
; If Not jump to checksum calculate
MOV
A, END_ADDR2
CMPRS
A, Y
; If Yes, check if Y = middle end address
JMP
AAA
; If Not jump to checksum calculate
JMP
CHECKSUM_END
; If Yes checksum calculated is done.
Y_ADD_1:
INCMS
Y
; Increase Y
NOP
JMP
@B
; Jump to checksum calculate
CHECKSUM_END:
…
…
END_USER_CODE:
; Label of program end
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Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 20 Version 0.9
2.2 DATA MEMORY (RAM)
56 X 8-bit RAM
Address
RAM Location
BANK 0
000h
General Purpose Area
RAM Bank 0
“ “
“ 037h
080h
System Register
080h~0FFh of Bank 0 store system
registers (128 bytes).
“
“ “ 0FFh
End of Bank 0
Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1, b0bset…) to control Bank 0 RAM directly.
2.2.1 SYSTEM REGISTER
2.2.1.1 SYSTEM REGISTER TABLE
0 1 2 3 4 5 6 7 8 9 A B C D E F
8
L H R Z Y - PFLAG - - - - - - - -
- 9 - - - - - - - - - - - - - - -
- A - - - - - - - - - - - - - - -
- B - - - - - - - - P0M - - - -
-
-
PEDGE
C
P1W
P1M - - - P5M - -
INTRQ
INTEN
OSCM
-
WDTR
IRR
PCL
PCH
D
P0
P1 - - - P5 - -
T0M
T0C
IRM
IRC - - - STKP
E
P0UR
P1UR - - - P5UR
@HL
@YZ
IRD - - - - - -
-
F
- - - - - - - - STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
2.2.1.2 SYSTEM REGISTER DESCRIPTION
H, L =
Working, @HL addressing register.
Y, Z =
Working, @YZ and ROM addressing register.
R =
Working register and ROM look-up data buffer.
PFLAG =
ROM page and special flag register.
PnM =
Port n input/output mode register.
PEDGE =
P0.0 edge direction register.
INTRQ =
Interrupt request register.
INTEN =
Interrupt enable register.
OSCM =
Oscillator mode register.
WDTR =
Watchdog timer clear register.
IRR =
IR counter auto-reload data buffer.
PCH, PCL =
Program counter.
Pn =
Port n data buffer.
T0M =
T0 mode register.
T0C =
T0 counting register.
IRM =
IR mode register.
IRC =
IR counting register.
STKP =
Stack pointer buffer.
PnUR =
Port n pull-up resister control register.
@HL =
RAM HL indirect addressing index pointer.
@YZ =
RAM YZ indirect addressing index pointer.
IRD =
IR duty control register.
STK0~STK3 =
Stack 0 ~ stack 3 buffer.
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Remote Control 8-Bit Micro-Controller
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2.2.1.3 BIT DEFINITION of SYSTEM REGISTER
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Remarks
080H
LBIT7
LBIT6
LBIT5
LBIT4
LBIT3
LBIT2
LBIT1
LBIT0
R/W L 081H
HBIT7
HBIT6
HBIT5
HBIT4
HBIT3
HBIT2
HBIT1
HBIT0
R/W H 082H
RBIT7
RBIT6
RBIT5
RBIT4
RBIT3
RBIT2
RBIT1
RBIT0
R/W R 083H
ZBIT7
ZBIT6
ZBIT5
ZBIT4
ZBIT3
ZBIT2
ZBIT1
ZBIT0
R/W Z 084H
YBIT7
YBIT6
YBIT5
YBIT4
YBIT3
YBIT2
YBIT1
YBIT0
R/W
Y
086H
NT0
NPD C
DC
Z
R/W
PFLAG
0B8H
P07M
P06M
P05M
P04M
P03M
P01M
P00M
R/W
P0M
0BFH P00G1
P00G0 R/W
PEDGE
0C0H
P17W
P16W
P15W
P14W
P13W
P12W
P11W
P10W W P1W
0C1H
P17M
P16M
P15M
P14M
P13M
P12M
P11M
P10M
R/W
P1M
0C5H P54M P50M
R/W
P5M
0C8H T0IRQ P00IRQ
R/W
INTRQ
0C9H T0IEN P00IEN
R/W
INTEN
0CAH CPUM1
CPUM0
CLKMD
STPHX
R/W
OSCM
0CCH
WDTR7
WDTR6
WDTR5
WDTR4
WDTR3
WDTR2
WDTR1
WDTR0 W WDTR
0CDH
IRR7
IRR6
IRR5
IRR4
IRR3
IRR2
IRR1
IRR0 W IRR
0CEH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
R/W
PCL
0CFH PC10
PC9
PC8
R/W
PCH
0D0H
P07
P06
P05
P04
P03
P02
P01
P00
R/W
P0
0D1H
P17
P16
P15
P14
P13
P12
P11
P10
R/W
P1
0D5H P54 P50
R/W
P5
0D8H
T0ENB
T0rate2
T0rate1
T0rate0
R/W
T0M
0D9H
T0C7
T0C6
T0C5
T0C4
T0C3
T0C2
T0C1
T0C0
R/W
T0C
0DAH
IREN
CREN
R/W
IRM
0DBH
IRC7
IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
R/W
IRC
0DFH
GIE STKPB1
STKPB0
R/W
STKP
0E0H
P07R
P06R
P05R
P04R
P03R
P01R
P00R W P0UR
0E1H
P17R
P16R
P15R
P14R
P13R
P12R
P11R
P10R W P1UR
0E5H P54R P50R W P5UR
0E6H
@HL7
@HL6
@HL5
@HL4
@HL3
@HL2
@HL1
@HL0
R/W
@HL
0E7H
@YZ7
@YZ6
@YZ5
@YZ4
@YZ3
@YZ2
@YZ1
@YZ0
R/W
@YZ
0E8H
IRD7
IRD6
IRD5
IRD4
IRD3
IRD2
IRD1
IRD0 W IRD
0F8H
S3PC7
S3PC6
S3PC5
S3PC4
S3PC3
S3PC2
S3PC1
S3PC0
R/W
STK3L
0F9H S3PC10
S3PC9
S3PC8
R/W
STK3H
0FAH
S2PC7
S2PC6
S2PC5
S2PC4
S2PC3
S2PC2
S2PC1
S2PC0
R/W
STK2L
0FBH S2PC10
S2PC9
S2PC8
R/W
STK2H
0FCH
S1PC7
S1PC6
S1PC5
S1PC4
S1PC3
S1PC2
S1PC1
S1PC0
R/W
STK1L
0FDH S1PC10
S1PC9
S1PC8
R/W
STK1H
0FEH
S0PC7
S0PC6
S0PC5
S0PC4
S0PC3
S0PC2
S0PC1
S0PC0
R/W
STK0L
0FFH S0PC10
S0PC9
S0PC8
R/W
STK0H
Note:
1. To avoid system error, make sure to put all the “0” and “1” as it indicates in the above table.
2. All of register names had been declared in SN8ASM assembler.
3. One-bit name had been declared in SN8ASM assembler with “F” prefix code.
4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers.
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2.2.2 ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
Example: Read and write ACC value.
; Read ACC data and store in BUF data memory.
MOV
BUF, A
; Write a immediate data into ACC.
MOV
A, #0FH
; Write ACC data from BUF data memory.
MOV
A, BUF
; or
B0MOV
A, BUF
The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to
other data memories. “PUSH”, “POP” save and load ACC, PFLAG data into buffers.
Example: Protect ACC and working registers.
INT_SERVICE:
PUSH
; Save ACC and PFLAG to buffers.
…
…
POP
; Load ACC and PFLAG from buffers.
RETI
; Exit interrupt service vector
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2.2.3 PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.
NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and
watchdog reset. C, DC, Z bits indicate the result status of ALU operation.
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFLAG
NT0
NPD - - - C
DC
Z
Read/Write
R/W
R/W - - - R/W
R/W
R/W
After reset
- - - - - 0 0
0
Bit [7:6] NT0, NPD: Reset status flag.
NT0
NPD
Reset Status
0
0
Watch-dog time out
0
1
Reserved
1
0
Reset by LVD
1
1
Reset by external Reset Pin
Bit 2 C: Carry flag
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result
≥ 0.
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison
result < 0.
Bit 1 DC: Decimal carry flag
1 = Addition with carry from low nibble, subtraction without borrow from high nibble.
0 = Addition without carry from low nibble, subtraction with borrow from high nibble.
Bit 0 Z: Zero flag
1 = The result of an arithmetic/logic/branch operation is zero.
0 = The result of an arithmetic/logic/branch operation is not zero.
Note: Refer to instruction set table for detailed information of C, DC and Z flags.
Page 24
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2.2.4 PROGRAM COUNTER
The program counter (PC) is a 11-bit binary counter separated into the high-byte 3 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 10.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC
- - - - -
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
After
reset
- - - - - 0 0 0 0 0 0 0 0 0 0
0
PCH
PCL
ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
B0BTS1
FC
; To skip, if Carry_flag = 1
JMP
C0STEP
; Else jump to C0STEP.
…
…
C0STEP:
NOP
B0MOV
A, BUF0
; Move BUF0 value to ACC.
B0BTS0
FZ
; To skip, if Zero flag = 0.
JMP
C1STEP
; Else jump to C1STEP.
…
… C1STEP:
NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
CMPRS
A, #12H
; To skip, if ACC = 12H.
JMP
C0STEP
; Else jump to C0STEP.
… … C0STEP:
NOP
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If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
INCS
BUF0
JMP
C0STEP
; Jump to C0STEP if ACC is not zero.
…
…
C0STEP:
NOP
INCMS instruction:
INCMS
BUF0
JMP
C0STEP
; Jump to C0STEP if BUF0 is not zero.
…
… C0STEP:
NOP
If the destination decreased by 1, which results underflow of 0x01 to 0x00, the PC will add 2 steps to skip next
instruction.
DECS instruction:
DECS
BUF0
JMP
C0STEP
; Jump to C0STEP if ACC is not zero.
…
… C0STEP:
NOP
DECMS instruction:
DECMS
BUF0
JMP
C0STEP
; Jump to C0STEP if BUF0 is not zero.
… … C0STEP:
NOP
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MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate
multi-address jumping function. Program Counter supports “ADD M,A”, ”ADC M,A” and “B0ADD M,A” instructions
for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value
by the three instructions and don’t care PCL overflow problem.
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
Example: If PC = 0323H (PCH = 03H, PCL = 23H)
; PC = 0323H
MOV
A, #28H
B0MOV
PCL, A
; Jump to address 0328H
…
; PC = 0328H
MOV
A, #00H
B0MOV
PCL, A
; Jump to address 0300H
…
Example: If PC = 0323H (PCH = 03H, PCL = 23H)
; PC = 0323H
B0ADD
PCL, A
; PCL = PCL + ACC, the PCH cannot be changed.
JMP
A0POINT
; If ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
… …
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2.2.5 H, L REGISTERS
The H and L registers are the 8-bit buffers. There are two major functions of these registers.
Can be used as general working registers
Can be used as RAM data pointers with @HL register
081H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H
HBIT7
HBIT6
HBIT5
HBIT4
HBIT3
HBIT2
HBIT1
HBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
- - - - - - -
- 080H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
L
LBIT7
LBIT6
LBIT5
LBIT4
LBIT3
LBIT2
LBIT1
LBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
- - - - - - -
-
Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode
to access data as following.
B0MOV
H, #00H
; To set RAM bank 0 for H register
B0MOV
L, #20H
; To set location 20H for L register
B0MOV
A, @HL
; To read a data into ACC
Example: Clear general-purpose data memory area of bank 0 using @HL register.
CLR
H
; H = 0, bank 0
B0MOV
L, #07FH
; L = 7FH, the last address of the data memory area
CLR_HL_BUF:
CLR
@HL
; Clear @HL to be zero
DECMS
L
; L – 1, if L = 0, finish the routine
JMP
CLR_HL_BUF
; Not zero
CLR
@HL
END_CLR:
; End of clear general purpose data memory area of bank 0
…
…
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2.2.6 Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
Can be used as general working registers
Can be used as RAM data pointers with @YZ register
Can be used as ROM data pointer with the MOVC instruction for look-up table
084H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Y
YBIT7
YBIT6
YBIT5
YBIT4
YBIT3
YBIT2
YBIT1
YBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
- - - - - - -
- 083H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Z
ZBIT7
ZBIT6
ZBIT5
ZBIT4
ZBIT3
ZBIT2
ZBIT1
ZBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
- - - - - - -
-
Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.
B0MOV
Y, #00H
; To set RAM bank 0 for Y register
B0MOV
Z, #25H
; To set location 25H for Z register
B0MOV
A, @YZ
; To read a data into ACC
Example: Uses the Y, Z register as data pointer to clear the RAM data.
B0MOV
Y, #0
; Y = 0, bank 0
B0MOV
Z, #07FH
; Z = 7FH, the last address of the data memory area
CLR_YZ_BUF:
CLR
@YZ
; Clear @YZ to be zero
DECMS
Z
; Z – 1, if Z= 0, finish the routine
JMP
CLR_YZ_BUF
; Not zero
CLR
@YZ
END_CLR:
; End of clear general purpose data memory area of bank 0
…
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2.2.7 R REGISTER
R register is an 8-bit buffer. There are two major functions of the register.
Can be used as working register
For store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
082H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
RBIT7
RBIT6
RBIT5
RBIT4
RBIT3
RBIT2
RBIT1
RBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
- - - - - - -
-
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
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2.3 ADDRESSING MODE
2.3.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.
Example: Move the immediate data 12H to ACC.
MOV
A, #12H
; To set an immediate data 12H into ACC.
Example: Move the immediate data 12H to R register.
B0MOV
R, #12H
; To set an immediate data 12H into R register.
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.
2.3.2 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.
Example: Move 0x12 RAM location data into ACC.
B0MOV
A, 12H
; To get a content of RAM location 0x12 of bank 0 and save in
ACC.
Example: Move ACC data into 0x12 RAM location.
B0MOV
12H, A
; To get a content of ACC and save in RAM location 12H of
bank 0.
2.3.3 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (H/L, Y/Z).
Example: Indirectly addressing mode with @HL register
B0MOV
H, #0
; To clear H register to access RAM bank 0.
B0MOV
L, #12H
; To set an immediate data 12H into L register.
B0MOV
A, @HL
; Use data pointer @HL reads a data from RAM location
; 012H into ACC.
Example: Indirectly addressing mode with @YZ register
B0MOV
Y, #0
; To clear Y register to access RAM bank 0.
B0MOV
Z, #12H
; To set an immediate data 12H into Z register.
B0MOV
A, @YZ
; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
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2.4 STACK OPERATION
2.4.1 OVERVIEW
The stack buffer has 4-level. These buffers are designed to push and pop up program counter’s (PC) data when
interrupt service routine and “CALL” instruction are executed. The STKP register is a pointer designed to point active
level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program
counter (PC) data.
RET /
RETI
CALL /
INTERRUPT
STKP = 3
STKP = 2
STKP = 1
STKP = 0
STACK Level
STK3H
STK2H
STK1H
STK0H
STACK Buffer
High Byte
PCH
STKP
STK3L
STK2L
STK1L
STK0L
STACK Buffer
Low Byte
PCL
STKP
STKP - 1STKP + 1
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2.4.2 STACK REGISTERS
The stack pointer (STKP) is a 2-bit register to store the address used to access the stack buffer, 9-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses.
The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push
operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to
the top address of stack buffer and write the last program counter value (PC) into the stack buffer.
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
0DFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STKP
GIE - - - -
-
STKPB1
STKPB0
Read/Write
R/W - - - - - R/W
R/W
After reset
0 - - - - - 1
1
Bit[2:0] STKPBn: Stack pointer (n = 0 ~ 1)
Bit 7 GIE: Global interrupt control bit.
0 = Disable.
1 = Enable. Please refer to the interrupt chapter.
Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the
beginning of the program.
MOV
A, #00000011B
B0MOV
STKP, A
0F0H~0F8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STKnH
- - - - -
SnPC10
SnPC9
SnPC8
Read/Write
- - - - -
R/W
R/W
R/W
After reset
- - - - - 0 0
0
0F0H~0F8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STKnL
SnPC7
SnPC6
SnPC5
SnPC4
SnPC3
SnPC2
SnPC1
SnPC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
STKn = STKnH , STKnL (n = 3 ~ 0)
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2.4.3 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
Stack Level
STKP Register
Stack Buffer
Description
STKPB1
STKPB0
High Byte
Low Byte
0
1 1 Free
Free
-
1
1 0 STK0H
STK0L
-
2
0 1 STK1H
STK1L
-
3
0 0 STK2H
STK2L
-
4
1 1 STK3H
STK3L
-
> 4
1 0 -
-
Stack Over, error
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
STKP Register
Stack Buffer
Description
STKPB1
STKPB0
High Byte
Low Byte
4
1 1 STK3H
STK3L
-
3
0 0 STK2H
STK2L
-
2
0 1 STK1H
STK1L
-
1
1 0 STK0H
STK0L
-
0
1 1 Free
Free
-
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2.5 CODE OPTION TABLE
The code option is the system hardware configurations including oscillator type, watchdog timer operation, reset pin
option and OTP ROM security control. The code option items are as following table:
Code Option
Content
Function Description
High_Clk
IHRC_8M
High speed internal 8MHz RC. XIN/XOUT pins are bi-direction GPIO
mode.
RC
Low cost RC for external high clock oscillator. XIN pin is connected to RC
oscillator. XOUT pin is bi-direction GPIO mode.
455K X’tal
Low frequency 32KHz and 455KHz, power saving crystal for external high
clock oscillator.
32KHz: XIN connects 20pF capacitor, XOUT connects 20pF
capacitor.
455KHz: XIN connects 47pF capacitor, XOUT connects 20pF
capacitor.
8M X’tal
High speed crystal/resonator (e.g. 8MHz) for external high clock
oscillator.
4M X’tal
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
Fcpu
Fhosc/1
Instruction cycle is oscillator clock.
Fhosc/2
Instruction cycle is 2 oscillator clocks.
Fhosc/4
Instruction cycle is 4 oscillator clocks.
Fhosc/8
Instruction cycle is 8 oscillator clocks.
Watch_Dog
Always_On
Watchdog timer is always on enable even in power down and green
mode.
Enable
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
Disable
Disable Watchdog function.
Reset_Pin
Reset
Enable External reset pin.
P02
Enable P0.2 input only without pull-up resister.
Security
Enable
Enable ROM code Security function.
Disable
Disable ROM code Security function.
2.5.1 Reset_Pin code option
The reset pin is shared with general input only pin controlled by code option.
Reset: The reset pin is external reset function. When falling edge trigger occurring, the system will be reset.
P02: Set reset pin to general input only pin (P0.2). The external reset function is disabled and the pin is input pin.
2.5.2 Security code option
Security code option is OTP ROM protection. When enable security code option, the ROM code is secured and not
dumped complete ROM contents.
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3
3
3
RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
Power on reset
Watchdog reset
Brown out reset
External reset (only supports external reset pin enable situation)
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFLAG
NT0
NPD - - - C
DC
Z
Read/Write
R/W
R/W - - - R/W
R/W
R/W
After reset
- - - - - 0 0
0
Bit [7:6] NT0, NPD: Reset status flag.
NT0
NPD
Condition
Description
0
0
Watchdog reset
Watchdog timer overflow.
0
1
Reserved
- 1 0
Power on reset and LVD reset.
Power voltage is lower than LVD detecting level.
1
1
External reset
External reset pin detect low level status.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
VDD
VSS
VDD
VSS
Watchdog Normal Run
Watchdog Stop
System Normal Run
System Stop
LVD Detect Level
External Reset
Low Detect
External Reset
High Detect
Watchdog
Overflow
Watchdog
Reset Delay
Time
External
Reset Delay
Time
Power On
Delay Time
Power
External Reset
Watchdog Reset
System Status
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3.2 POWER ON RESET
The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising
curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.
Power-up: System detects the power voltage up and waits for power stable.
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
3.3 WATCHDOG RESET
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.
Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer
overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and
returns normal mode. Watchdog reset sequence is as following.
Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.
Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer
overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and
returns normal mode. Watchdog reset sequence is as following.
Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
Watchdog timer application note is as following.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.
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3.4 BROWN OUT RESET
The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external
factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well
or executing program error.
VDD
VSS
V1
V2
V3
System Work
Well Area
System Work
Error Area
Brown Out Reset Diagram
The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power
range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset
diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate
the system working area. The above area is the system work well area. The below area is the system work error area
called dead-band. V1 doesn’t touch the below area and not effect the system operation. But the V2 and V3 is under the
below area and may induce the system error occurrence. Let system under dead-band includes some conditions.
DC application:
The power source of DC application is usually using battery. When low battery condition and MCU drive any loading,
the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system
reset voltage. That makes the system under dead-band.
AC application:
In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC
noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating
induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power
situation.
The power on duration and power down duration are longer in AC application. The system power on sequence protects
the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power,
the VDD drops slowly and through the dead-band for a while.
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3.4.1 THE SYSTEM OPERATING VOLTAGE
To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system
executing rate and power level. Different system executing rates have different system minimum operating voltage.
The electrical characteristic section shows the system voltage to executing rate relationship.
Vdd (V)
System Rate (Fcpu)
System Mini.
Operating Voltage.
System Reset
Voltage.
Dead-Band Area
Normal Operating
Area
Reset Area
Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is
decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even
higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system
reset voltage.
3.4.2 LOW VOLTAGE DETECTOR (LVD)
VDD
VSS
System Normal Run
System Stop
LVD Detect Voltage
Power On
Delay Time
Power
System Status
Power is below LVD Detect
Voltage and System Reset.
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD can’t be the protection and need to other reset methods. More detail LVD information
is in the electrical characteristic section.
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3.4.3 BROWN OUT RESET IMPROVEMENT
How to improve the brown reset condition? There are some methods to improve brown out reset as following.
LVD reset
Watchdog reset
Reduce the system executing rate
External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)
Note:
1. The “ Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can completely
improve the brown out reset, DC low battery and AC slow power down conditions.
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use
external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset IC”). The
structure can improve noise effective and get good EFT characteristic.
Watchdog reset:
The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear
at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the
watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t
be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of
watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method
also can improve brown out reset condition and make sure the system to return normal mode.
If the system reset by watchdog and the power is still in dead-band, the system reset sequence won’t be successful
and the system stays in reset status until the power return to normal range.
Reduce the system executing rate:
If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band.
The lower system rate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue
and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue.
This way needs to modify whole program timing to fit the application requirement.
External reset circuit:
The external reset methods also can improve brown out reset and is the complete solution. There are three external
reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External
reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under
power dropping and under dead-band. The external reset information is described in the next section.
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3.5 EXTERNAL RESET
External reset function is controlled by “Reset_Pin” code option. Set the code option as “Reset” option to enable
external reset function. External reset pin is Schmitt Trigger structure and low level active. The system is running when
reset pin is high level voltage input. The reset pin receives the low voltage and the system is reset. The external reset
operation actives in power on and normal running mode. During system power-up, the external reset pin must be high
level input, or the system keeps in reset status. External reset sequence is as following.
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
The external reset can reset the system during power on duration, and good external reset circuit can protect the
system to avoid working at unusual power condition, e.g. brown out reset in AC power application…
3.6 EXTERNAL RESET CIRCUIT
3.6.1 Simply RC Reset Circuit
MCU
VDD
VSS
VCC
GND
R
S
T
R1
47K ohm
C1
0.1uF
R2
100 ohm
This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into
reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from
the timing difference.
Note: The reset circuit is no any protection against unusual power or brown out reset.
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3.6.2 Diode & RC Reset Circuit
MCU
VDD
VSS
VCC
GND
R
S
T
R1
47K ohm
C1
0.1uF
DIODE
R2
100 ohm
This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal.
The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct
higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can
improve slight brown out reset condition.
Note: The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to
limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due
to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).
3.6.3 Zener Diode Reset Circuit
MCU
VDD
VSS
VCC
GND
R
S
T
R1
33K ohm
R3
40K ohm
R2
10K ohm
Vz
Q1
E
C
B
The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition
completely. Use zener voltage to be the active level. When VDD voltage level is above “Vz + 0.7V”, the C terminal of
the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of
the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener
specification. Select the right zener voltage to conform the application.
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3.6.4 Voltage Bias Reset Circuit
MCU
VDD
VSS
VCC
GND
R
S
T
R1
47K ohm
R3
2K ohm
R2
10K ohm
Q1
E
C
B
The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely.
The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When
VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high
voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor
outputs low voltage and MCU is in reset mode.
Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the
circuit diagram condition, the MCU’s reset pin level varies with VDD voltage variation, and the differential voltage is
0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the
reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external
reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power
system, the current must be considered to whole system power consumption.
Note: Under unstable power condition as brown out reset, “Zener diode rest circuit” and “Voltage bias
reset circuit” can protects system no any error occurrence as power dropping. When power drops below
the reset detect voltage, the system reset would be triggered, and then system executes reset sequence.
That makes sure the system work well under unstable power situation.
3.6.5 External Reset IC
MCU
VDD
VSS
VCC
GND
R
S
T
Reset
IC
VDD
VSS
RST
Bypass
Capacitor
0.1uF
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good
effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can
improve all power variation.
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4
4
4
SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system including high-speed and low-speed clocks. The high-speed clock includes
internal high-speed oscillator and external oscillators selected by “High_CLK” code option. The low-speed clock is from
internal low-speed oscillator controlled by “CLKMD” bit of OSCM register. Both high-speed clock and low-speed clock
can be system clock source through a divider to decide the system clock rate.
High-speed oscillator
Internal high-speed oscillator is 8MHz RC type called “IHRC”.
External high-speed oscillator includes crystal/ceramic (4MHz, 8MHz, 455KHz) and RC type.
Low-speed oscillator
Internal low-speed oscillator is 10KHz @3V RC type called “ILRC”.
System clock block diagram
Fhosc. Fcpu = Fhosc/1 ~ Fhosc/8
Flosc. Fcpu = Flosc/4
CPUM[1:0]
XIN
XOUT
STPHX HOSC
Fcpu Code Option
Fosc
Fosc
CLKMD
Fcpu
HOSC: High_Clk code option.
Fhosc: External high-speed clock / Internal high-speed RC clock.
Flosc: Internal low-speed RC clock (about 10KHz@3V).
Fosc: System clock source.
Fcpu: Instruction cycle.
4.2 FCPU (INSTRUCTION CYCLE)
The system clock rate is instruction cycle called “Fcpu” which is divided from the system clock source and decides the
system operating rate. Fcpu rate is selected by Fcpu code option and the range is Fhosc/1~Fhosc/8 under system
normal mode. If the system high clock source is external 4MHz crystal, and the Fcpu code option is Fhosc/4, the Fcpu
frequency is 4MHz/4 = 1MHz. Under system slow mode, the Fcpu is fixed Flosc/4, 10KHz/4=2.5KHz @3V.
In high noisy environment, below “Fhosc/4” of Fcpu code option is the strongly recommendation to reduce
high frequency noise effect.
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4.3 SYSTEM HIGH-SPEED CLOCK
The system high-speed clock has internal and external two-type. The external high-speed clock includes 4MHz, 8MHz,
455KHz crystal/ceramic and RC type. These high-speed oscillators are selected by “High_CLK” code option.
4.3.1 HIGH_CLK CODE OPTION
For difference clock functions, Sonix provides multi-type system high clock options controlled by “High_CLK” code
option. The High_CLK code option defines the system oscillator types including IHRC_8M, RC, 455K X’tal, 8M X’tal
and 4M X’tal. These oscillator options support different bandwidth oscillator.
IHRC_8M: The system high-speed clock source is internal high-speed 8MHz RC type oscillator. In the mode, XIN
and XOUT pins are bi-direction GPIO mode, and not to connect any external oscillator device.
RC: The system high-speed clock source is external low cost RC type oscillator. The RC oscillator circuit only
connects to XIN pin, and the XOUT pin is bi-direction GPIO mode.
455K X’tal: The system high-speed clock source is external low-speed crystal. The option support 32KHz and
455KHz crystals.
8M X’tal: The system high-speed clock source is external high-speed crystal/ceramic. The oscillator bandwidth is
4MHz~8MHz.
4M X’tal: The system high-speed clock source is external high-speed crystal/resonator. The oscillator bandwidth
is 1MHz~4MHz.
4.3.2 INTERNAL HIGH-SPEED OSCILLATOR RC TYPE (IHRC)
The internal high-speed oscillator is 8MHz RC type. The accuracy is ±2% under commercial condition. When the
“High_CLK” code option is “IHRC_8M”, the internal high-speed oscillator is enabled.
IHRC_8M: The system high-speed clock is internal 8MHz oscillator RC type. XIN/XOUT pins are general purpose
I/O pins.
4.3.3 EXTERNAL HIGH-SPEED OSCILLATOR
The external high-speed oscillator includes 4MHz, 8MHz, 455KHz and RC type. The 4MHz, 8MHz and 455KHz
oscillators support crystal and ceramic types connected to XIN/XOUT pins with 20pF capacitors to ground. The RC
type is a low cost RC circuit only connected to XIN pin. The capacitance is not below 100pF, and use the resistance to
decide the frequency.
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4.3.4 EXTERNAL OSCILLATOR APPLICATION CIRCUIT
4M/8M CRYSTAL/CERAMIC
RC Type
MCU
VCC
GND
C
20pF
XIN
X
O
U
T
VDD
VSS
C
20pF
CRYSTAL
R
MCU
VCC
GND
XIN
X
O
U
T
V
D
D
VSS
C
455KHz CRYSTAL/CERAMIC
32KHz CRYSTAL/CERAMIC
MCU
VCC
GND
C
47pF
XIN
XOUT
VDD
VSS
C
20pF
455KHz
X’tal
455K code option crystal’s capacitors are 47pF to
XIN pin and 20pF to XOUT pin.
MCU
VCC
GND
C
20pF
XIN
XOUT
VDD
VSS
C
20pF
32KHz
X’tal
455K code option crystal’s capacitors are 20pF to
XIN pin and 20pF to XOUT pin.
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of
micro-controller. Connect the R and C as near as possible to the VDD pin of micro-controller.
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4.4 SYSTEM LOW-SPEED CLOCK
The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator
uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common
condition, the frequency of the RC oscillator is about 10KHz at 3V. The relation between the RC frequency and voltage
is as the following figure.
The internal low RC supports watchdog clock source and system slow mode controlled by “CLKMD” bit of OSCM
register.
Flosc = Internal low RC oscillator (about 10KHz @3V).
Slow mode Fcpu = Flosc / 4
There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 455K
mode and watchdog disable. If system is in 455K mode and watchdog disable, only 455K oscillator actives and system
is under low power consumption.
Example: Stop internal low-speed oscillator by power down mode.
B0BSET
FCPUM0
; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1
(455K, watchdog disable) bits of OSCM register.
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4.5 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
0CAH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCM
0 0 0
CPUM1
CPUM0
CLKMD
STPHX
0
Read/Write
- - -
R/W
R/W
R/W
R/W
-
After reset
- - - 0 0 0 0
-
Bit 1 STPHX: External high-speed oscillator control bit.
0 = External high-speed oscillator free run.
1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running.
Bit 2 CLKMD: System high/Low clock mode control bit.
0 = Normal (dual) mode. System clock is high clock.
1 = Slow mode. System clock is internal low clock.
Bit[4:3] CPUM[1:0]: CPU operating mode control bits.
00 = normal.
01 = sleep (power down) mode.
10 = green mode.
11 = reserved.
“STPHX” bit controls internal high speed RC type oscillator and external oscillator operations. When “STPHX=0”, the
external oscillator or internal high speed RC type oscillator active. When “STPHX=1”, the external oscillator or internal
high speed RC type oscillator are disabled. The STPHX function is depend on different high clock options to do
different controls.
IHRC_8M: “STPHX=1” disables internal high speed RC type oscillator.
RC, 4M, 8M, 455K: “STPHX=1” disables external oscillator.
4.6 SYSTEM CLOCK MEASUREMENT
Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is
useful in RC mode.
Example: Fcpu instruction cycle of external oscillator.
B0BSET
P0M.0
; Set P0.0 to be output mode for outputting Fcpu toggle signal.
@@:
B0BSET
P0.0
; Output Fcpu toggle signal in low-speed clock mode.
B0BCLR
P0.0
; Measure the Fcpu frequency by oscilloscope.
JMP
@B
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
frequency.
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4.7 SYSTEM CLOCK TIMING
Parameter
Symbol
Description
Typical
Hardware configuration time
Tcfg
2048*F
ILRC
64ms @ F
ILRC
= 32KHz
128ms @ F
ILRC
= 16KHz
Oscillator start up time
Tost
The start-up time is depended on oscillator’s material,
factory and architecture. Normally, the low-speed
oscillator’s start-up time is lower than high-speed
oscillator. The RC type oscillator’s start-up time is faster
than crystal type oscillator.
-
Oscillator warm-up time
Tosp
Oscillator warm-up time of reset condition.
2048*F
hosc
(Power on reset, LVD reset, watchdog reset, external
reset pin active.)
64ms @ F
hosc
= 32KHz
512us @ F
hosc
= 4MHz
256us @ F
hosc
= 8MHz
Oscillator warm-up time of power down mode wake-up
condition.
2048*F
hosc
……Crystal/resonator type oscillator, e.g.
32768Hz crystal, 4MHz crystal, 16MHz crystal…
32*F
hosc
……RC type oscillator, e.g. external RC type
oscillator, internal high-speed RC type oscillator.
64ms @ F
hosc
= 32KHz
512us @ F
hosc
= 4MHz
256us @ F
hosc
= 8MHz
Power On Reset Timing
Vdd
Power On Reset
Flag
Oscillator
Fcpu
(Instruction Cycle)
Tcfg Tost
Tosp
Vp
External Reset Pin Reset Timing
External Reset Pin
Oscillator
Fcpu
(Instruction Cycle)
Tcfg Tost
Tosp
Reset pin falling edge trigger system reset.
Reset pin returns to high status.
System is under reset
status.
External Reset
Flag
Watchdog Reset Timing
Watchdog Reset
Flag
Oscillator
Fcpu
(Instruction Cycle)
Tcfg Tost
Tosp
Watchdog timer overflow.
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Power Down Mode Wake-up Timing
Wake-up Pin
Rising Edge
Oscillator
Fcpu
(Instruction Cycle)
Tosp
Tost
Wake-up Pin
Falling Edge
System inserts into power down mode.
Edge trigger system wake-up.
Green Mode Wake-up Timing
Wake-up Pin
Rising Edge
Oscillator
Fcpu
(Instruction Cycle)
Wake-up Pin
Falling Edge
System inserts into green mode.
Edge trigger system wake-up.
0x000xFF0xFE 0x01 0x02 ...0xFD... ... ... ... ...Timer
Timer overflow.
Oscillator Start-up Time
The start-up time is depended on oscillator’s material, factory and architecture. Normally, the low-speed oscillator’s
start-up time is lower than high-speed oscillator. The RC type oscillator’s start-up time is faster than crystal type
oscillator.
Low Speed Crystal
(32K, 455K)
Tost
Crystal
Tost
External RC
Tost
Ceramic/Resonator
Tost
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5
5
5
SYSTEM OPERATION MODE
5.1 OVERVIEW
The chip builds in four operating mode for difference clock rate and power saving reason. These modes control
oscillators, op-code operation and analog peripheral devices’ operation.
Normal mode: System high-speed operating mode.
Slow mode: System low-speed operating mode.
Power down mode: System power saving mode (Sleep mode).
Green mode: System ideal mode.
Operating Mode Control Block
Power Down Mode
Slow Mode
CLKMD = 1
CLKMD = 0
CPUM1, CPUM0 = 01.
Wake-up condition:
P0, P1 input status is level changing.
T0 timer counter is overflow.
CPUM1, CPUM0 = 10.
Normal Mode
Green Mode
Wake-up condition:
P0, P1 input status is level changing.
T0 timer counter is overflow.
Wake-up condition:
P0, P1 input status is level changing.
Reset Control Block
One of reset trigger sources actives.
One of reset trigger sources actives.
One of reset trigger sources actives.
Operating Mode Clock Control Table
Operating
Mode
Normal Mode
Slow Mode
Green Mode
Power Down
Mode
EHOSC
Running
By STPHX
By STPHX
Stop
IHRC
Running
By STPHX
By STPHX
Stop
ILRC
Running
Running
Running
Stop
CPU instruction
Executing
Executing
Stop
Stop
T0 timer
By T0ENB
By T0ENB
By T0ENB
Inactive
Watchdog timer
By Watch_Dog
Code option
By Watch_Dog
Code option
By Watch_Dog
Code option
By Watch_Dog
Code option
Internal interrupt
All active
All active
T0
All inactive
External interrupt
All active
All active
All active
All inactive
Wakeup source
-
-
P0, P1, T0, Reset
P0, P1, Reset
EHOSC: External high-speed oscillator (XIN/XOUT).
IHRC: Internal high-speed oscillator RC type.
ILRC: Internal low-speed oscillator RC type.
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5.2 NORMAL MODE
The Normal Mode is system high clock operating mode. The system clock source is from high speed oscillator. The
program is executed. After power on and any reset trigger released, the system inserts into normal mode to execute
program. When the system is wake-up from power down mode, the system also inserts into normal mode. In normal
mode, the high speed oscillator actives, and the power consumption is largest of all operating modes.
The program is executed, and full functions are controllable.
The system rate is high speed.
The high speed oscillator and internal low speed RC type oscillator active.
Normal mode can be switched to other operating modes through OSCM register.
Power down mode is wake-up to normal mode.
Slow mode is switched to normal mode.
Green mode from normal mode is wake-up to normal mode.
5.3 SLOW MODE
The slow mode is system low clock operating mode. The system clock source is from internal low speed RC type
oscillator. The slow mode is controlled by CLKMD bit of OSCM register. When CLKMD=0, the system is in normal
mode. When CLKMD=1, the system inserts into slow mode. The high speed oscillator won’t be disabled automatically
after switching to slow mode, and must be disabled by SPTHX bit to reduce power consumption. In slow mode, the
system rate is fixed Flosc/4 (Flosc is internal low speed RC type oscillator frequency).
The program is executed, and full functions are controllable.
The system rate is low speed (Flosc/4).
The internal low speed RC type oscillator actives, and the high speed oscillator is controlled by STPHX=1. In slow
mode, to stop high speed oscillator is strongly recommendation.
Slow mode can be switched to other operating modes through OSCM register.
Power down mode from slow mode is wake-up to normal mode.
Normal mode is switched to slow mode.
Green mode from slow mode is wake-up to slow mode.
5.4 POWER DOWN MDOE
The power down mode is the system ideal status. No program execution and oscillator operation. Whole chip is under
low power consumption status under 1uA. The power down mode is waked up by P0, P1 hardware level change trigger.
P1 wake-up function is controlled by P1W register. Any operating modes into power down mode, the system is waked
up to normal mode. Inserting power down mode is controlled by CPUM0 bit of OSCM register. When CPUM0=1, the
system inserts into power down mode. After system wake-up from power down mode, the CPUM0 bit is disabled (zero
status) automatically.
The program stops executing, and full functions are disabled.
All oscillators including external high speed oscillator, internal high speed oscillator and internal low speed
oscillator stop.
The power consumption is under 1uA.
The system inserts into normal mode after wake-up from power down mode.
The power down mode wake-up source is P0 and P1 level change trigger.
Note: If the system is in normal mode, to set STPHX=1 to disable the high clock oscillator. The system is
under no system clock condition. This condition makes the system stay as power down mode, and can
be wake-up by P0, P1 level change trigger.
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5.5 GREEN MODE
The green mode is another system ideal status not like power down mode. In power down mode, all functions and
hardware devices are disabled. But in green mode, the system clock source keeps running, so the power consumption
of green mode is larger than power down mode. In green mode, the program isn’t executed, but the timer with wake-up
function actives as enabled, and the timer clock source is the non-stop system clock. The green mode has 2 wake-up
sources. One is the P0, P1 level change trigger wake-up. The other one is internal timer with wake-up function
occurring overflow. That’s mean users can setup one fix period to timer, and the system is waked up until the time out.
Inserting green mode is controlled by CPUM1 bit of OSCM register. When CPUM1=1, the system inserts into green
mode. After system wake-up from green mode, the CPUM1 bit is disabled (zero status) automatically.
The program stops executing, and full functions are disabled.
Only the timer with wake-up function actives.
The oscillator to be the system clock source keeps running, and the other oscillators operation is depend on
system operation mode configuration.
If inserting green mode from normal mode, the system insets to normal mode after wake-up.
If inserting green mode from slow mode, the system insets to slow mode after wake-up.
The green mode wake-up sources are P0, P1 level change trigger and unique time overflow.
PWN and buzzer output functions active in green mode, but the timer can’t wake-up the system as overflow.
Note: Sonix provides “GreenMode” macro to control green mode operation. It is necessary to use
“GreenMode” macro to control system inserting green mode.
The macro includes three instructions. Please take care the macro length as using BRANCH type
instructions, e.g. bts0, bts1, b0bts0, b0bts1, ins, incms, decs, decms, cmprs, jmp, or the routine would
be error.
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5.6 OPERATING MODE CONTROL MACRO
Sonix provides operating mode control macros to switch system operating mode easily.
Macro
Length
Description
SleepMode
1-word
The system insets into Sleep Mode (Power Down Mode).
GreenMode
3-word
The system inserts into Green Mode.
SlowMode
2-word
The system inserts into Slow Mode and stops high speed oscillator.
Slow2Normal
5-word
The system returns to Normal Mode from Slow Mode. The macro
includes operating mode switch, enable high speed oscillator, high
speed oscillator warm-up delay time.
Example: Switch normal/slow mode to power down (sleep) mode.
SleepMode
; Declare “SleepMode” macro directly.
Example: Switch normal mode to slow mode.
SlowMode
; Declare “SlowMode” macro directly.
Example: Switch slow mode to normal mode (The external high-speed oscillator stops).
Slow2Normal
; Declare “Slow2Normal” macro directly.
Example: Switch normal/slow mode to green mode.
GreenMode
; Declare “GreenMode” macro directly.
Example: Switch normal/slow mode to green mode and enable T0 wake-up function.
; Set T0 timer wakeup function.
B0BCLR
FT0IEN
; To disable T0 interrupt service
B0BCLR
FT0ENB
; To disable T0 timer
MOV
A,#20H
; B0MOV
T0M,A
; To set T0 clock = Fcpu / 64
MOV
A,#74H
B0MOV
T0C,A
; To set T0C initial value = 74H (To set T0 interval = 10 ms)
B0BCLR
FT0IEN
; To disable T0 interrupt service
B0BCLR
FT0IRQ
; To clear T0 interrupt request
B0BSET
FT0ENB
; To enable T0 timer
; Go into green mode
GreenMode
; Declare “GreenMode” macro directly.
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5.7 WAKEUP
5.7.1 OVERVIEW
Under power down mode (sleep mode) or green mode, program doesn’t execute. The wakeup trigger can wake the
system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0 level change) and
internal trigger (T0 timer overflow).
Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0 level change)
Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger (P0
level change) and internal trigger (T0 timer overflow).
5.7.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power
down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit.
After the wakeup time, the system goes into the normal mode.
Note: Wakeup from green mode is no wakeup time because the clock doesn’t stop in green mode.
The value of the wakeup time is as the following.
The Wakeup time = 1/Fosc * 2048 (sec) + high clock start-up time
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system goes
into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz)
The total wakeup time = 0.512 ms + oscillator start-up time
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5.7.3 P1W WAKEUP CONTROL REGISTER
Under power down mode (sleep mode) and green mode, the I/O ports with wakeup function are able to wake the
system up to normal mode. The wake-up trigger edge is level changing. When wake-up pin occurs rising edge or falling
edge, the system is waked up by the trigger edge. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function
always enables, but the Port 1 is controlled by the P1W register.
0C0H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1W
P17W
P16W
P15W
P14W
P13W
P12W
P11W
P10W
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
Bit[7:0] P10W~P17W: Port 1 wakeup function control bits.
0 = Disable P1n wakeup function.
1 = Enable P1n wakeup function.
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6
6
6
INTERRUPT
6.1 OVERVIEW
This MCU provides three interrupt sources, including one internal interrupt (T0) and one external interrupt (INT0). The
external interrupt can wake-up the chip while the system is switched from power down mode to high-speed normal
mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt
request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. All
of the interrupt request signals are stored in INTRQ register.
INTEN Interrupt Enable Register
Interrupt
Enable
Gating
INTRQ
3-Bit
Latchs
P00IRQ
T0IRQ
Interrupt Vector Address (0008H)
Global Interrupt Request Signal
INT0 Trigger
T0 Time Out
Note: The GIE bit must enable during all interrupt operation.
6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack i s
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
0C9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTEN
- - -
T0IEN - -
-
P00IEN
Read/Write
- - -
R/W - - - R/W
After reset
- - - 0 - - -
0
Bit 0 P00IEN: External P0.0 interrupt (INT0) control bit.
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
Bit 4 T0IEN: T0 timer interrupt control bit.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
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6.3 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
0C8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTRQ
- - -
T0IRQ - -
-
P00IRQ
Read/Write
- - -
R/W - - - R/W
After reset
- - - 0 - - -
0
Bit 0 P00IRQ: External P0.0 interrupt (INT0) request flag.
0 = None INT0 interrupt request.
1 = INT0 interrupt request.
Bit 4 T0IRQ: T0 timer interrupt request flag.
0 = None T0 interrupt request.
1 = T0 interrupt request.
6.4 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and
the stack add 1 level.
0DFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STKP
GIE - - - -
-
STKPB1
STKPB0
Read/Write
R/W - - - - - R/W
R/W
After reset
0 - - - - - 1
1
Bit 7 GIE: Global interrupt control bit.
0 = Disable global interrupt.
1 = Enable global interrupt.
Example: Set global interrupt control bit (GIE).
B0BSET
FGIE
; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
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6.5 PUSH, POP ROUTINE
When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save
ACC, PFLAG data. The chip includes “PUSH”, “POP” for in/out interrupt service routine. The two instructions save and
load ACC, PFLAG data into buffers and avoid main routine error after interrupt service routine finishing.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is
an unique buffer and only one level.
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine
executed.
ORG
0
JMP
START
ORG
8
JMP
INT_SERVICE
ORG
10H START:
…
INT_SERVICE:
PUSH
; Save ACC and PFLAG to buffers.
… …
POP
; Load ACC and PFLAG from buffers.
RETI
; Exit interrupt service vector
…
ENDP
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6.6 EXTERNAL INTERRUPT OPERATION (INT0)
INT0 is external interrupt trigger source and builds in edge trigger configuration function. When the external edge
trigger occurs, the external interrupt request flag will be set to “1” no matter the external interrupt control bit enabled or
disable. When external interrupt control bit is enabled and external interrupt edge trigger is occurring, the program
counter will jump to the interrupt vector (ORG 8) and execute interrupt service routine.
The external interrupt builds in wake-up latch function. That means when the system is triggered wake-up from power
down mode, the wake-up source is external interrupt source (P0.0), and the trigger edge direction matches interrupt
edge configuration, the trigger edge will be latched, and the system executes interrupt service routine fist after
wake-up.
0BFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEDGE
- - -
P00G1
P00G0 - -
-
Read/Write
- - -
R/W
R/W - -
-
After reset
- - - 1 0 - -
-
Bit[4:3] P00G[1:0]: INT0 edge trigger select bits.
00 = reserved,
01 = rising edge,
10 = falling edge,
11 = rising/falling bi-direction.
Example: Setup INT0 interrupt request and bi-direction edge trigger.
MOV
A, #18H
B0MOV
PEDGE, A
; Set INT0 interrupt trigger as bi-direction edge.
B0BSET
FP00IEN
; Enable INT0 interrupt service
B0BCLR
FP00IRQ
; Clear INT0 interrupt request flag
B0BSET
FGIE
; Enable GIE
Example: INT0 interrupt service routine.
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FP00IRQ
; Check P00IRQ
JMP
EXIT_INT
; P00IRQ = 0, exit interrupt vector
B0BCLR
FP00IRQ
; Reset P00IRQ
… ; INT0 interrupt service routine
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.7 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the
T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the
trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the
operation under multi-interrupt situation.
Example: T0 interrupt request setup.
B0BCLR
FT0IEN
; Disable T0 interrupt service
B0BCLR
FT0ENB
; Disable T0 timer
MOV
A, #20H
; B0MOV
T0M, A
; Set T0 clock = Fcpu / 64
MOV
A, #74H
; Set T0C initial value = 74H
B0MOV
T0C, A
; Set T0 interval = 10 ms
B0BSET
FT0IEN
; Enable T0 interrupt service
B0BCLR
FT0IRQ
; Clear T0 interrupt request flag
B0BSET
FT0ENB
; Enable T0 timer
B0BSET
FGIE
; Enable GIE
Example: T0 interrupt service routine.
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FT0IRQ
; Check T0IRQ
JMP
EXIT_INT
; T0IRQ = 0, exit interrupt vector
B0BCLR
FT0IRQ
; Reset T0IRQ
MOV
A, #74H
B0MOV
T0C, A
; Reset T0C.
… ; T0 interrupt service routine
… EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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6.8 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
Interrupt Name
Trigger Event Description
P00IRQ
P0.0 trigger controlled by PEDGE
T0IRQ
T0C overflow
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
Example: Check the interrupt request under multi-interrupt operation
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
INTP00CHK:
; Check INT0 interrupt request
B0BTS1
FP00IEN
; Check P00IEN
JMP
INTT0CHK
; Jump check to next interrupt
B0BTS0
FP00IRQ
; Check P00IRQ
JMP
INTP00
INTT0CHK:
; Check T0 interrupt request
B0BTS1
FT0IEN
; Check T0IEN
JMP
INT_EXIT
; End of interrupt request checking
B0BTS0
FT0IRQ
; Check T0IRQ
JMP
INTT0
; Jump to T0 interrupt service routine
… INT_EXIT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
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7
7
7
I/O PORT
7.1 OVERVIEW
The micro-controller builds in 16 pin I/O. Some of the I/O pins are mixed with analog pins and special function pins.
The I/O shared pin list is as following.
I/O Pin
Shared Pin
Shared Pin Control Condition
Name
Type
Name
Type
P0.0
I/O
INT0
DC
P00IEN=1
P0.2
I
RST
DC
Reset_Pin code option = Reset
VPP
HV
OTP Programming
P0.4
I/O
XOUT
AC
High_CLK code option = 455K, 4M, 8M
P0.3
I/O
XIN
AC
High_CLK code option = RC, 455K, 4M, 8M
P5.4
I/O
IROUT
DC
IREN = 1.
* DC: Digital Characteristic. AC: Analog Characteristic. HV: High Voltage Characteristic.
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7.2 I/O PORT MODE
The port direction is programmed by PnM register. When the bit of PnM register is “0”, the pin is input mode. When the
bit of PnM register is “1”, the pin is output mode.
0B8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0M
P07M
P06M
P05M
P04M
P03M
-
P01M
P00M
Read/Write
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
After reset
0 0 0 0 0 - 0
0 0C1H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1M
P17M
P16M
P15M
P14M
P13M
P12M
P11M
P10M
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0C5H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P5M
- - -
P54M - - - P50M
Read/Write
- - -
R/W - - - R/W
After reset
- - - 0 - - -
0
Bit[7:0] PnM[7:0]: Pn mode control bits. (n = 0~5).
0 = Pn is input mode.
1 = Pn is output mode.
Note:
1. Users can program them by bit control instructions (B0BSET, B0BCLR).
2. P0.2 input only pin, and the P0M.2 is undefined.
Example: I/O mode selecting
CLR
P0M
; Set all ports to be input mode.
CLR
P1M
CLR
P5M
MOV
A, #0FFH
; Set all ports to be output mode.
B0MOV
P0M, A
B0MOV
P1M,A
B0MOV
P5M, A
B0BCLR
P1M.0
; Set P1.0 to be input mode.
B0BSET
P1M.0
; Set P1.0 to be output mode.
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7.3 I/O PULL UP REGISTER
The I/O pins build in internal pull-up resistors and only support I/O input mode. The port internal pull-up resistor is
programmed by PnUR register. When the bit of PnUR register is “0”, the I/O pin’s pull-up is disabled. When the bit of
PnUR register is “1”, the I/O pin’s pull-up is enabled.
0E0H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0UR
P07R
P06R
P05R
P04R
P03R
-
P01R
P00R
Read/Write
W W W W W - W
W
After reset
0 0 0 0 0 - 0
0 0E10H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1UR
P17R
P16R
P15R
P14R
P13R
P12R
P11R
P10R
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
0E5H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P5UR
- - -
P54R - - - P50R
Read/Write
- - - W - - -
W
After reset
- - - 0 - - -
0
Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 is undefined.
Example: I/O Pull up Register
MOV
A, #0FFH
; Enable Port 0, 1, 5 Pull-up register,
B0MOV
P0UR, A
;
B0MOV
P1UR,A
B0MOV
P5UR, A
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7.4 I/O PORT DATA REGISTER
0D0H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0
P07
P06
P05
P04
P03
P02
P01
P00
Read/Write
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0D1H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1
P17
P16
P15
P14
P13
P12
P11
P10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0D5H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P5
- - -
P54 - - - P50
Read/Write
- - -
R/W - - - R/W
After reset
- - - 0 - - -
0
Note: The P02 keeps “1” when external reset enable by code option.
Example: Read data from input port.
B0MOV
A, P0
; Read data from Port 0
B0MOV
A, P1
; Read data from Port 4
B0MOV
A, P5
; Read data from Port 5
Example: Write data to output port.
MOV
A, #0FFH
; Write data FFH to all Port.
B0MOV
P0, A
B0MOV
P1, A
B0MOV
P5, A
Example: Write one bit data to output port.
B0BSET
P1.0
; Set P1.0 and P5.3 to be “1”.
B0BSET
P5.3
B0BCLR
P1.0
; Set P1.0 and P5.3 to be “0”.
B0BCLR
P5.3
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8
8
8
TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator (10KHz @3V).
Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).
VDD
Internal Low RC Freq.
Watchdog Overflow Time
3V
10KHz
819.2ms
The watchdog timer has three operating options controlled “WatchDog” code option.
Disable: Disable watchdog timer function.
Enable: Enable watchdog timer function. Watchdog timer actives in normal mode and slow mode. In power down
mode and green mode, the watchdog timer stops.
Always_On: Enable watchdog timer function. The watchdog timer actives and not stop in power down mode and
green mode.
In high noisy environment, the “Always_On” option of watchdog operations is the strongly recommendation
to make the system reset under error situations and re-start again.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTR
WDTR7
WDTR6
WDTR5
WDTR4
WDTR3
WDTR2
WDTR1
WDTR0
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
MOV
A, #5AH
; Clear the watchdog timer.
B0MOV
WDTR, A
…
CALL
SUB1
CALL
SUB2
… JMP
MAIN
Example: Clear watchdog timer by “@RST_WDT” macro of Sonix IDE.
Main:
@RST_WDT
; Clear the watchdog timer.
…
CALL
SUB1
CALL
SUB2
…
JMP
MAIN
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Watchdog timer application note is as following.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the
main routine of the program.
Main:
… ; Check I/O.
…
; Check RAM
Err:
JMP $
; I/O or RAM error. Program jump here and don’t
; clear watchdog. Wait watchdog timer overflow to reset IC.
Correct:
; I/O and RAM are correct. Clear watchdog timer and
; execute program.
MOV
A, #5AH
; Clear the watchdog timer.
B0MOV
WDTR, A
…
CALL
SUB1
CALL
SUB2
… … …
JMP
MAIN
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8.2 TIMER 0 (T0)
8.2.1 OVERVIEW
The T0 timer is an 8-bit binary up basic timer. If T0 timer occurs an overflow (from 0xFF to 0x00), it will continue
counting and issue a time-out signal to indicate T0 time out event. The T0 builds in green mode wake-up function.
When T0 timer overflow occurs under green mode, the system will be waked-up to last operating mode. The main
purposes of the T0 timer are as following.
8-bit programmable up counting timer: Generate time-out at specific time intervals based on the selected clock
frequency.
Interrupt function: T0 timer function supports interrupt function. When T0 timer occurs overflow, the T0IRQ
actives and the system points program counter to interrupt vector to do interrupt sequence.
Green mode function: T0 keeps running in green mode and can wake-up from green mode as T0ENB = 1.
System will be wake-up when T0IRQ actives after T0 timer overflow occurrence.
Fcpu
T0 Rate
(Fcpu/2~Fcpu/256)
T0ENB
CPUM0,1
T0C 8-Bit Binary Up Counting Counter
T0 Time Out
Load
Internal Data Bus
8.2.2 T0 Timer Operation
T0 timer is a basic 8-bit timer. T0 timer clock source is Fcpu. T0 unit time of Fcou clock source is decided by T0rate
register including Fcpu/2, Fcpu/4, Fcpu/8, Fcpu/16, Fcpu/32, Fcpu/64, Fcpu/128 and Fcpu/256. When T0ENB=1, T0
timer starts to count. If the T0 counter is from 0xFF to 0x00, the T0 timer overflow occurs and T0IRQ sets as “1”. If T0
interrupt function is enabled (T0IEN=1), the program counter is pointed to interrupt vector (ORG 8) to execute interrupt
service routine after T0 timer overflow occurrence. T0 timer builds in green mode wake-up function. T0 timer keeps
counting in green mode. When T0 timer overflow occurs, the system will be waked-up from green mode to last
operating mode. T0 counter doesn’t build in auto-reload function. Set the T0 interval time through setting T0C by
program and have to set again when T0 timer overflows, or T0 timer counts from 0x00 to 0xFF 256 counts. Not keep
the correct interval time.
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8.2.3 T0M MODE REGISTER
0D8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0M
T0ENB
T0rate2
T0rate1
T0rate0 - - - -
Read/Write
R/W
R/W
R/W
R/W - - - -
After reset
0 0 0 0 - - -
-
Bit [6:4] T0RATE[2:0]: T0 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7 T0ENB: T0 counter control bit.
0 = Disable T0 timer.
1 = Enable T0 timer.
8.2.4 T0C COUNTING REGISTER
T0C is an 8-bit counter register for T0 interval time control.
0D9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0C
T0C7
T0C6
T0C5
T0C4
T0C3
T0C2
T0C1
T0C0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
The equation of T0C initial value is as following.
T0C initial value = 256 - (T0 interrupt interval time * input clock)
Example: To set 10ms interval time for T0 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select
T0RATE=010 (Fcpu/64).
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10-2 * 4 * 106 / 4 / 64)
= 100
= 64H
The basic timer table interval time of T0.
T0RATE
T0CLOCK
High speed mode (Fcpu = 4MHz / 4)
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval
One step = max/256
Max overflow interval
One step = max/256
000
Fcpu/256
65.536 ms
256 us
8000 ms
31250 us
001
Fcpu/128
32.768 ms
128 us
4000 ms
15625 us
010
Fcpu/64
16.384 ms
64 us
2000 ms
7812.5 us
011
Fcpu/32
8.192 ms
32 us
1000 ms
3906.25 us
100
Fcpu/16
4.096 ms
16 us
500 ms
1953.125 us
101
Fcpu/8
2.048 ms
8 us
250 ms
976.563 us
110
Fcpu/4
1.024 ms
4 us
125 ms
488.281 us
111
Fcpu/2
0.512 ms
2 us
62.5 ms
244.141 us
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8.2.5 T0 TIMER OPERATION SEQUENCE
T0 timer operation sequence of setup T0 timer is as following.
Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag.
B0BCLR
FT0ENB
; T0 timer.
B0BCLR
FT0IEN
; T0 interrupt function is disabled.
B0BCLR
FT0IRQ
; T0 interrupt request flag is cleared.
Set T0 timer rate.
MOV
A, #0xxx0000b
;The T0 rate control bits exist in bit4~bit6 of T0M. The
; value is from x000xxxxb~x111xxxxb.
B0MOV
T0M,A
; T0 timer is disabled.
Set T0 interrupt interval time.
MOV
A,#7FH
B0MOV
T0C,A
; Set T0C value.
Set T0 timer function mode.
B0BSET
FT0IEN
; Enable T0 interrupt function.
Enable T0 timer.
B0BSET
FT0ENB
; Enable T0 timer.
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9
9
9
IR OUTPUT
9.1 OVERVIEW
IR signal is generated by IR timer. The IR output pin is 400mA @Vss+0.5V sink type. When IREN bit of IRM is set as
logic “1”, IROUT pin exchanges from GPIO to IR output mode. If CREN = 0 or system is in power down mode, IROUT
pin is tied to high status. The IR timer is an 8-bit binary up counting timer for IR signal generator. The IR signal is
duty/cycle changeable type controlled by IRR and IRD. IRR decides IR’s cycle and IRD decides IR’s duty. IR counter
clock source is only from Fhosc (system high clock source), eg. IHRC_8M, 4MHz or 455KHz crystal. If Fhosc is 4MHz,
the IR counter clock rate is 4MHz. IR timer only generate IR output and no interrupt function. When enable IR output
function (CREN=1), IR output status is low level. IRC initial value is IRR and starts to count. When IRC=IRD, IR output
status change to high level and finishes low duty operation. When IRC overflow occurs (IRC changes from 0xFF to
0x00), IR output high duty operation stops. System loads IRR into IRC automatically and next cycle starts.
Fhosc
CREN
CPUM0
IRC
8-Bit Binary Up
Counting Counter
IRR Reload
Data Buffer
Up Counting
Reload Value
Compare
R
S
Output Low
IROUT pin
IR Signal
IREN
Load
IRD
Data Buffer
IRC Overflow
9.2 IR CONTROL REGISTER
9.2.1 IRM MODE REGISTER
0DAH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRM
- - - - - - IREN
CREN
Read/Write
- - - - - - R/W
R/W
After reset
- - - - - - 0
0
Bit 1 IREN: IROUT pin control bit.
0 = Disable. IROUT pin is P5.4 GPIO mode.
1 = Enable. IROUT pin is output high status.
Bit 0 CREN: IR carry signal output control bit.
0 = Disable. IROUT pin is output high status.
1 = Enable. IROUT pin outputs IR carry signal.
Note: IR carry output condition is IREN=1 and CREN=1. If CREN=1 and IREN=0, the IROUT pin is P5.4
GPIO mode.
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9.2.2 IRC COUNTING REGISTER
IRC is an 8-bit counter register for IR interval time control.
0DBH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRC
IRC7
IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
Note: Set IRC=IRR before IR output enable to make sure the first cycle correct.
9.2.3 IRR AUTO-LOAD REGISTER
IRR decides IR signal frequency. IR timer is with auto-load function. When IRC overflow occurs, IRR value will load
to IRC. It is easy to generate an accurate time for IR signal cycle, and users don’t reset IRC during interrupt service
routine.
IR is double buffer design. If new IRR value is set by program, the new value is stored in 1st buffer. Until IR overflow
occurs, the new value moves to real IRR buffer.
0CDH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRR
IRR7
IRR6
IRR5
IRR4
IRR3
IRR2
IRR1
IRR0
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
The equation of IRRinitial value is as following.
IRR initial value = 256 - (IR interrupt interval time * input clock)
Note: The input clock is 4MHz of external 4MHz oscillator.
Example: Set IR cycle frequency is 38KHz. Input clock is 4MHz.
IRR initial value = 256 - (IR interrupt interval time * input clock)
IR interval time = 1/38KHz = 26.3us
Input clock = external oscillator 4MHz.
IRR = 256 - (26.3us * 4MHz)
= 150.8
≈ 151
= 97h
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9.2.4 IRD IR DUTY CONTROL REGISTER
The IR signal is duty changeable by IRD. IRD decides the IR output signal low pulse width length. When IRC=IRD, the
IR signal changes from low pulse to high pulse. The low pulse stops when IRC overflow. The low pulse width is
IRD-IRR, and the high pulse width is 256-IRD. It is easy to modulate IR duty/cycle by IRR and IRD registers.
0E8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRD
IRD7
IRD6
IRD5
IRD4
IRD3
IRD2
IRD1
IRD0
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
The equation of IRD initial value is as following.
IRD initial value = IRR + (256-IRR) / (1/IR duty)
Example: Set IRD for 38KHz IR and duty is 1/3. Input clock is 4MHz.
IRD initial value = IRR + (256-IRR) / (1/IR duty)
IRR of 38KHz = 151
IRD = 151 + (256-151)/(1/ (1/3))
= 186
= BAh
Common IR signal table. System clock is 4MHz.
IR Freq.
(KHz)
IRC
IRR
IRD
Freq. Error
Rate
1/2 duty
1/3 duty
1/4duty
DEC
HEX
DEC
HEX
DEC
HEX
DEC
HEX
32
131
83
193.50
C1
172.67
AC
162.25
A2
0.00%
36
145
91
200.50
C8
182.00
B6
172.75
AC
0.10%
38
151
97
203.50
CB
186.00
BA
177.25
B1
0.25%
39.2
154
9A
205.00
CD
188.00
BC
179.50
B3
0.04%
40
156
9C
206.00
CE
189.33
BD
181.00
B5
0.00%
56
185
B9
220.50
DC
208.67
D0
202.75
CA
0.60%
Page 74
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 74 Version 0.9
9.3 IR OUTPUT OPERATION SEQUENCE
Set IRC and IRR for IR cycle.
MOV
A, #IRCYCVAL
;IRC, IRR value for IR cycle.
MOV
IRC, A
MOV
IRR, A
Set IRD for IR duty.
MOV
A, #IRDUTYVAL
;IRD value for IR duty.
MOV
IRD, A
Enable IR output.
BSET
FIREN
; Set IROUT pin to IR carry output function.
BSET
FCREN
; Set IR carry signal output.
Page 75
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 75 Version 0.9
9.4 IR APPLICATION CIRCUIT
The IR sink current is 400mA @Vss+1.5V.
Crystal type, Max. 56 keys:
VCC
S7
S2 S51
S50S1
S55
S56
S6
C1
47uF
BT1
3V
KI3
KI2
KI1
KI5
KI4
KO1
KI7
KI6
KO4KO3KO2 KO6KO5
...
KO7 KO8
...
...
...
R1 3.75 ohm D1 IR
Y1 4MHz
C5
20pF
C4
20pF
R3
47k ohm
C2
0.1uF
VDD
VSS
U
U1
SN8PC20
VDD
1
P0.0
2
P0.1
3
P0.2/RST
4
P0.3/XIN
5
P0.4/XOUT
6
P0.5
7
P0.6
8
P0.7
9
P1.0
10
VSS
20
P5.4/IROUT
19
P5.0
18
P1.7
17
P1.6
16
P1.5
15
P1.4
14
P1.3
13
P1.2
12
P1.1
11
VDD
VSS
XOUT
XIN
VSS
VSSVDD
XIN
XOUT
IHRC_8M type, Max. 72 keys:
VCC
S9
S2 S66
S65S1
S71
S72
S8
C1
47uF
BT1
3V
KI1
KI5
KI3
KI2
KI7
KI6
KO2KO1
KI8
KO5KO4KO3 KO8KO6
...
...
KO7
...
...
R1 3.75 ohm D1 IR
R3
47k ohm
C2
0.1uF
VSS
VDD
U
U1
SN8PC20
VDD
1
P0.0
2
P0.1
3
P0.2/RST
4
P0.3/XIN
5
P0.4/XOUT
6
P0.5
7
P0.6
8
P0.7
9
P1.0
10
VSS
20
P5.4/IROUT
19
P5.0
18
P1.7
17
P1.6
16
P1.5
15
P1.4
14
P1.3
13
P1.2
12
P1.1
11
VSS
VDD
VDD VSS
KI4
KI4
Page 76
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 76 Version 0.9
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INSTRUCTION TABLE
Field
Mnemonic
Description
C
DC Z Cycle
MOV
A,M
A M
-
- 1 M MOV
M,A
M A
- - - 1 O
B0MOV
A,M
A M (bank 0)
-
- 1
V
B0MOV
M,A
M (bank 0) A
- - - 1 E
MOV
A,I
A I
- - - 1
B0MOV
M,I
M I, “M” only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z…)
- - - 1
XCH
A,M
A M
- - -
1+N
B0XCH
A,M
A M (bank 0)
- - -
1+N
MOVC
R, A ROM [Y,Z]
- - -
2
ADC
A,M
A A + M + C, if occur carry, then C=1, else C=0
1 A ADC
M,A
M A + M + C, if occur carry, then C=1, else C=0
1+N
R
ADD
A,M
A A + M, if occur carry, then C=1, else C=0
1 I ADD
M,A
M A + M, if occur carry, then C=1, else C=0
1+N
T
B0ADD
M,A
M (bank 0) M (bank 0) + A, if occur carry, then C=1, else C=0
1+N
H
ADD
A,I
A A + I, if occur carry, then C=1, else C=0
1 M SBC
A,M
A A - M - /C, if occur borrow, then C=0, else C=1
1 E SBC
M,A
M A - M - /C, if occur borrow, then C=0, else C=1
1+N
T
SUB
A,M
A A - M, if occur borrow, then C=0, else C=1
1 I SUB
M,A
M A - M, if occur borrow, then C=0, else C=1
1+N
C
SUB
A,I
A A - I, if occur borrow, then C=0, else C=1
1 AND
A,M
A A and M
-
- 1 L AND
M,A
M A and M
-
- 1+N
O
AND
A,I
A A and I
-
- 1 G OR
A,M
A A or M
-
- 1 I OR
M,A
M A or M
-
- 1+N
C
OR
A,I
A A or I
-
- 1
XOR
A,M
A A xor M
-
- 1 XOR
M,A
M A xor M
-
- 1+N
XOR
A,I
A A xor I
-
- 1
SWAP
M
A (b3~b0, b7~b4) M(b7~b4, b3~b0)
- - -
1
P
SWAPM
M
M(b3~b0, b7~b4) M(b7~b4, b3~b0)
- - -
1+N
R
RRC
M
A RRC M
- - 1
O
RRCM
M
M RRC M
- - 1+N
C
RLC
M
A RLC M
- - 1 E RLCM
M
M RLC M
- - 1+N
S
CLR
M
M 0
- - -
1
S
BCLR
M.b
M.b 0
- - -
1+N
BSET
M.b
M.b 1
- - -
1+N
B0BCLR
M.b
M(bank 0).b 0
- - -
1+N
B0BSET
M.b
M(bank 0).b 1
- - -
1+N
CMPRS
A,I
ZF,C A - I, If A = I, then skip next instruction
-
1 + S
B
CMPRS
A,M
ZF,C A – M, If A = M, then skip next instruction
-
1 + S
R
INCS
M
A M + 1, If A = 0, then skip next instruction
- - -
1+ S
A
INCMS
M
M M + 1, If M = 0, then skip next instruction
- - -
1+N+S
N
DECS
M
A M - 1, If A = 0, then skip next instruction
- - -
1+ S
C
DECMS
M
M M - 1, If M = 0, then skip next instruction
- - -
1+N+S
H
BTS0
M.b
If M.b = 0, then skip next instruction
- - -
1 + S
BTS1
M.b
If M.b = 1, then skip next instruction
- - -
1 + S
B0BTS0
M.b
If M(bank 0).b = 0, then skip next instruction
- - -
1 + S
B0BTS1
M.b
If M(bank 0).b = 1, then skip next instruction
- - -
1 + S
JMP
d
PC15/14 RomPages1/0, PC13~PC0 d
- - - 2
CALL
d
Stack PC15~PC0, PC15/14 RomPages1/0, PC13~PC0 d
- - -
2
M
RET
PC Stack
- - - 2 I
RETI
PC Stack, and to enable global interrupt
- - -
2
S
PUSH
To push ACC and PFLAG (except NT0, NPD bit) into buffers.
- - -
1
C
POP To pop ACC and PFLAG (except NT0, NPD bit) from buffers.
1
NOP
No operation
- - -
1
Note:
1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1.
2. If branch condition is true then “S = 1”, otherwise “S = 0”.
Page 77
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 77 Version 0.9
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ELECTRICAL CHARACTERISTIC
11.1 ABSOLUTE MAXIMUM RATING
Supply voltage (Vdd)…………………………………………………………………………………………………………………….……………… - 0.3V ~ 4.0V
Input in voltage (Vin)…………………………………………………………………………………………………………………….… Vss – 0.2V ~ Vdd + 0.2V
Operating ambient temperature (Topr)
SN8PC20P, SN8PC20S, SN8PC20X, SN8PC2016S, SN8P2014S..……………………………………………….………………….. -20C ~ + 70C
Storage ambient temperature (Tstor) ………………………………………………………………….………………………………………… –40C ~ + 125C
11.2 ELECTRICAL CHARACTERISTIC
DC CHARACTERISTIC
(All of voltages refer to Vss, Vdd = 3.0V, fosc = 4MHz, fcpu=1MHZ, ambient temperature is 25C unless otherwise note.)
PARAMETER
SYM.
DESCRIPTION
MIN.
TYP.
MAX.
UNIT
Operating voltage
Vdd
Normal mode, Vpp = Vdd, 25C, Fcpu = 2mips.
1.8
3.0
3.6
V
RAM Data Retention voltage
Vdr 1.5 - - V Vdd rise rate
Vpor
Vdd rise rate to ensure internal power-on reset
0.05 - -
V/ms
Input Low Voltage
ViL1
All input ports
Vss - 0.3Vdd
V
ViL2
Reset pin
Vss - 0.2Vdd
V
Input High Voltage
ViH1
All input ports
0.7Vdd - Vdd V ViH2
Reset pin
0.9Vdd - Vdd V Reset pin leakage current
Ilekg
Vin = Vdd
- - 2
uA
I/O port pull-up resistor
Rup
Vin = Vss , Vdd = 3V
100
200
300
K
I/O port input leakage current
Ilekg
Pull-up resistor disable, Vin = Vdd
- - 2
uA
I/O output source current
sink current
IoH
Vop = Vdd – 0.5V
8
10
-
mA
IoL1
Vop = Vss + 0.5V
8
12 - IoL2
Vop = Vss + 1.5V, IR output pin
300
400 - mA
INTn trigger pulse width
Tint0
INT0 interrupt request pulse width
2/fcpu - -
cycle
Supply Current
Idd1
Run Mode
(No loading,
Fcpu = Fosc/4)
Vdd= 3V, 4Mhz
- 1 2
mA
Idd2
Slow Mode
(Internal low RC, Stop
high clock)
Vdd= 3V, 10Khz
- 5 10
uA
Idd3
Sleep Mode
Vdd= 3V, 25C
- 1 2
uA
Idd4
Green Mode
(No loading,
Fcpu = Fosc/4
Watchdog Disable)
Vdd= 3V, 4Mhz
-
0.25
0.5
mA
Vdd=3V, ILRC 10Khz ,
- 3 6
uA
Internal High Oscillator Freq.
Fihrc
Internal Hihg RC (IHRC)
25C,
Vdd= 3V,
Fcpu = 1MHz
7.84 8 8.16
Mhz
LVD Voltage
Vdet0
Low voltage reset level.
- - 1.8
V
“ *” These parameters are for design reference, not tested.
Page 78
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 78 Version 0.9
11.3 CHARACTERISTIC GRAPHS
The graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data
presented are outside specified operating range. This is for information only and devices are guaranteed to
operate properly only within the specified range.
Internal High RC Oscillator (MHz)
(Fcpu = IHRC/1~IHRC/8)
7.60
7.70
7.80
7.90
8.00
8.10
8.20
8.30
2.0V 2.5V 3.0V 3.5V 4.0V
VDD (V)
Freq. (MHz)
10℃
70℃
25℃
0℃
50℃
Internal High RC Oscillator (MHz)
(Fcpu=IHRC/1~IHRC/8)
7.75
7.80
7.85
7.90
7.95
8.00
8.05
8.10
8.15
8.20
8.25
8.30
0 10 25 50 70
Tem peture (℃ )
Freq. (MHz)
VDD=2V
VDD=3V
Page 79
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 79 Version 0.9
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2
DEVELOPMENT TOOL
SONIX provides ICE (in circuit emulation), IDE (Integrated Development Environment) and EV-kit for SN8PC20
development. ICE and EV-kit are external hardware devices, and IDE is a friendly user interface for firmware
development and emulation. These development tools’ version is as following.
ICE: SN8ICE2K
EV-kit: SN8PC20 EV-kit V1.0.
IDE: SONiX IDE M2IDE_V115.
Writer: MPIII WRITER-LV.
12.1 SN8PC20 EV-KIT
SN8PC20 EV-kit includes ICE interface , GPIO interface and IR driver module. The schematic of SN8PC20 EV-kit is as
following.
CON1: ICE interface connected to SN8ICE2K .
JP1: EV-Kit power connector between VCC and VDD. VCC is the power source from SN8ICE2K. VDD is the
power of KV-kit.
JP2: GPIO connector for test.
U1: SN8PC20 DIP and SSOP type connector for connecting to user’s target board.
U2/U3: Internal short connector. Don’t care them as emulating.
S1~S72: Remote key map.
D1/R1/R2/Q1: IR driving circuit for ICE emulation.
D2/R3: IR driving circuit for SN8PC20 real chip test. The two devices aren’t set on SN8PC20 EV-kit.
Page 80
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 80 Version 0.9
SN8PC20 EV-kit Circuit
P1.2
P0.0
P0.1
P0.4
S51
S59
P0.6
P0.7
S35
S3
S11
S19
P0.3
P1.2
JP2
HEADER 36X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
343633
35
P0.0
P0.1
P0.3
P0.2
S43
P0.5
S46S44
P0.5P0.5
P0.4
S45
P0.5 P0.5
S48S47
P1.7P0.5P1.4 P1.5 P1.6P1.2 P1. 3P1.0 P1. 1
S41
P0.5
S42
P0.5
P0.0
P1.3
P0.3
P0.2
P0.1
P0.0
S30
P0.3
P0.4
P0.2
S28
P0.0
S38
S22
P1.3
S61
P0.1
S37
S62
P1.5
P0.4
S54
S5
P0.0
P0.4P0.4
P1.4
P1.5
S13
S52
P0.7
S60
CON1
HEADER 30X2
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
P0.6
S21
P0.2
S6
P1.4
P0.7
P0.6
S36
S53
S4
S14
S29
S12
P0.1
P0.2
P0.6
P0.1
P1.5
S20
P0.7
P0.3
JP3
VDD
1
2
3
P1.3
P0.3
P1.4
VSSVDD
S32
P1.7
S15
S64
P0.4
P0.2
P1.6
S8
P0.3
P0.6
S7
S56
S31
P1.7
S23
P0.1
P0.7
P0.2
S63
P0.0
S16
S40
P0.0
S55
P0.4
P0.6
P0.7
P0.3
P1.6
S39
P1.7
P0.1
P1.6
S24
P1.7
P1.7
P1.7
P1.7
P1.6
P1.6
P1.6
P1.6
P1.5
P1.5
P1.5
P1.5
C4 20pF
R1 1K
P1.4
R2
330
P1.4
P1.4
C2
0.1uF
P1.4
P1.3
P1.3
P1.3
P1.3
C1
47uF
P1.2
P1.2
P1.2
P1.2
VDD
P1.1
P1.1
P1.1
P1.1
P1.0
P1.0
P1.0
P1.0
JP1
2 HEADER
1 2
VSS1
Y1
4MHz
VCC
C5 20pF
P5.0
P5.4
P0.3
P0.4
VSS2
S67
P5.0
P0.0
P1.0
P1.4
S69
P0.4
P1.2
P0.2
P1.6
S70
P5.0
S68
P5.0 P5.0
S72
P5.0
S71
P1.7P5.0P1.5 P1. 6P1.2 P1. 3 P1. 4
VSS
P1.0 P1. 1
S65
P0.6
P5.0P5.0
S66
P0.5
P1.3
VSS
P1.7
P0.1
P1.5
P0.7
P1.1
VCC
P0.3
S73 Reset
VDDVCC
P5.4
VDD2
P0.0
P0.1
P0.2
P0.3
VSS
P0.6
P0.5
P0.4
P0.7
P1.0
VSS2
U2
Short
112
2
P5.0
P5.4
P1.4
P1.5
P1.6
P1.7
U3
Short
112
2
P1.1
P1.2
P1.3
VDD1
Q1
PNP
D1 IR
C6 0.1uF
D2 IR R3 330
P5.4
R4
47k
C3
0.1uF
VDD
P5.4
VDD2
P5.4
P0.2
S1
S9
P0.6
S17
S25
JP4
VDD
1
2
3
S33
S49
P1.1
P0.7
P1.0
S57
P1.7
P1.2
P5.0
P1.4
P1.6
P1.5
P1.3
P0.0
P0.1
P0.2
P0.3
P0.4
P0.6
P0.5
P0.7
VSS
P5.0
P0.7
P1.0
P0.6
P1.6
P1.3
P1.7
P1.1
P1.2
P1.4
P1.5
P1.0
P1.0
P0.5
P1.0 P0. 2
P1.1
S26
P1.1
P0.1
P0.0
P0.4
S50
S58
P0.7
P0.6
S34
S2
S10
S18
P1.1
P0.3
U
U1
SN8PC20
VDD
1
P0.0
2
P0.1
3
P0.2/RST
4
P0.3/XIN
5
P0.4/XOUT
6
P0.5
7
P0.6
8
P0.7
9
P1.0
10
VSS
20
P5.4/IR OUT
19
P5.0
18
P1.7
17
P1.6
16
P1.5
15
P1.4
14
P1.3
13
P1.2
12
P1.1
11
P1.2
P0.2
S27
12.2 ICE AND EV-KIT APPLICATION NOTIC
SN8PC20 EV-kit includes matrix type key map and IR driving circuit module.
The IR driving circuit module includes two types. One is for ICE emulation to drive IR carry signal. The other one
is for SN8PC20 real chip test and disconnected with ICE. The EV-kit is like a real remote controller.
If the SN8PC20 real chip is set as 455KHz oscillator mode, the C4 (XIN) capacitance must be 47pF and C5
(XOUT) capacitance must be 20pF.
Page 81
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 81 Version 0.9
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OTP PROGRAMMING PIN
13.1 THE PIN ASSIGNMENT OF EASY WRITER TRANSITION
BOARD SOCKET:
Easy Writer JP1/JP2 Easy Writer JP3 (Mapping to 48-pin text tool)
VSS
2
1
VDD DIP1
1
48
DIP48
CE
4 3 CLK/PGCLK
DIP2
2
47
DIP47
OE/ShiftDat
6 5 PGM/OTPCLK
DIP3
3
46
DIP46
D0
8 7 D1 DIP4
4
45
DIP45
D2
10 9 D3 DIP5
5
44
DIP44
D4
12
11
D5 DIP6
6
43
DIP43
D6
14
13
D7 DIP7
7
42
DIP42
VPP
16
15
VDD DIP8
8
41
DIP41
RST
18
17
HLS DIP9
9
40
DIP40
ALSB/PDB
20
19 -
DIP10
10
39
DIP39
DIP11
11
38
DIP38
JP1 for MP transition board
DIP12
12
37
DIP38
DIP13
13
36
DIP36
DIP14
14
35
DIP35
DIP15
15
34
DIP34
DIP16
16
33
DIP33
DIP17
17
32
DIP32
DIP18
18
31
DIP31
DIP19
19
30
DIP30
DIP20
20
29
DIP29
DIP21
21
28
DIP28
DIP22
22
27
DIP27
DIP23
23
26
DIP26
DIP24
24
25
DIP25
JP3 for MP transition board
Page 82
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 82 Version 0.9
13.2 PROGRAMMING PIN MAPPING:
Programming Information of SN8PC20
Chip Name
SN8PC20P/S/X
SN8PC2016S
SN8PC2014S
EZ Writer
Connector
OTP IC / JP3 Pin Assignment
Number
Name
Number
Pin
Number
Pin
Number
Pin 1 VDD
1
VDD
1
VDD
1
VDD 2 GND
20
VSS
16
VSS
14
VSS 3 CLK
12
P1.2
10
P1.2
10
P1.2 4 CE
- - - - - - 5
PGM
10
P1.0
8
P1.0
8
P1.0
6
OE
13
P1.3
11
P1.3
11
P1.3
7
D1
- - - - - - 8
D0
- - - - - - 9
D3
- - - - - - 10
D2
- - - - - - 11
D5
- - - - - -
12
D4
- - - - - -
13
D7
- - - - - - 14
D6
- - - - - - 15
VDD
- - - - - - 16
VPP
4
RST
4
RST
4
RST
17
HLS
- - - - - -
18
RST
- - - - - -
19 - - - - - - -
20
ALSB/PDB
6, 11
P0.4/
P1.1
6, 9
P0.4/
P1.1
6, 9
P0.4/
P1.1
Note: It is necessary to connect a diode between P0.4/XOUT (Pin 6) and P1.1 (Pin 11) of the writer’s
transition board. The direction of diode is P0.4/XOUT to P1.1 as below graphic.
P0.4/XOUT P1.1
Page 83
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 83 Version 0.9
1
1
1
4
4
4
Marking Definition
14.1 INTRODUCTION
There are many different types in Sonix 8-bit MCU production line. This note listed the production definition of all 8-bit
MCU for order or obtain information. This definition is only for Blank OTP MCU.
14.2 MARKING INDETIFICATION SYSTEM
Title
SONiX 8-bit MCU Production
ROM Type
P=OTP
A=MASK
Material
B = PB-Free Package
G = Green Package
Temperature
Range
- = -20℃ ~ 70℃
Shipping
Package
W = Wafer
H = Dice
P = P-DIP
S = SOP
X = SSOP
Device
Device Part No.
SN8 X Part No. X X X
Note: SN8PC20 doesn’t support -40ºC~85ºC temperature range.
Page 84
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 84 Version 0.9
14.3 MARKING EXAMPLE
Name
ROM Type
Device
Package
Temperature
Material
SN8PC20PG
OTP
C20
P-DIP
-20℃~70℃
Green Package
SN8PC20SG
OTP
C20
SOP
-20℃~70℃
Green Package
SN8PC20XG
OTP
C20
SSOP
-20℃~70℃
Green Package
SN8PC2016SG
OTP
C20
SOP
-20℃~70℃
Green Package
SN8PC2014SG
OTP
C20
SOP
-20℃~70℃
Green Package
SN8PC20W
OTP
C20
Wafer
-20℃~70℃
-
SN8PC20H
OTP
C20
Dice
-20℃~70℃
-
14.4 DATECODE SYSTEM
X X X X XXXXX
Year
Month
1=January
2=February
. . . .
9=September
A=October
B=November
C=December
SONiX Internal Use
Day
1=01
2=02
. . . .
9=09
A=10
B=11
. . . .
03= 2003
04= 2004
05= 2005
06= 2006
. . . .
Page 85
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 85 Version 0.9
1
1
1
5
5
5
PACKAGE INFORMATION
15.1 P-DIP 20 PIN
SYMBOLS
MIN
NOR
MAX
MIN
NOR
MAX
(inch)
(mm)
A - -
0.210 - -
5.334
A1
0.015 - -
0.381 - -
A2
0.125
0.130
0.135
3.175
3.302
3.429
D
0.980
1.030
1.060
24.892
26.162
26.924
E
0.300
7.620
E1
0.245
0.250
0.255
6.223
6.350
6.477
L
0.115
0.130
0.150
2.921
3.302
3.810
ｅ
B
0.335
0.355
0.375
8.509
9.017
9.525
θ°
0°
7°
15°
0°
7°
15°
Page 86
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 86 Version 0.9
15.2 SOP 20 PIN
SYMBOLS
MIN
NOR
MAX
MIN
NOR
MAX
(inch)
(mm)
A
0.093
0.099
0.104
2.362
2.502
2.642
A1
0.004
0.008
0.012
0.102
0.203
0.305
D
0.496
0.502
0.508
12.598
12.751
12.903
E
0.291
0.295
0.299
7.391
7.493
7.595
H
0.394
0.407
0.419
10.008
10.325
10.643
L
0.016
0.033
0.050
0.406
0.838
1.270
θ°
0°
4°
8°
0°
4°
8°
Page 87
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 87 Version 0.9
15.3 SSOP 20 PIN
SYMBOLS
MIN
NOR
MAX
MIN
NOR
MAX
(inch)
(mm)
A
0.053
0.063
0.069
1.350
1.600
1.750
A1
0.004
0.006
0.010
0.100
0.150
0.250
A2 - -
0.059 - -
1.500
b
0.008
0.010
0.012
0.200
0.254
0.300
c
0.007
0.008
0.010
0.180
0.203
0.250
D
0.337
0.341
0.344
8.560
8.660
8.740
E
0.228
0.236
0.244
5.800
6.000
6.200
E1
0.150
0.154
0.157
3.800
3.900
4.000
[e]
0.025
0.635
h
0.010
0.017
0.020
0.250
0.420
0.500
L
0.016
0.025
0.050
0.400
0.635
1.270
L1
0.039
0.041
0.043
1.000
1.050
1.100
ZD
0.059
1.500
Y - -
0.004 - -
0.100
θ°
0° - 8°
0° - 8°
Page 88
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 88 Version 0.9
15.4 SOP 16 PIN
SYMBOLS
MIN
NOR
MAX
MIN
NOR
MAX
(inch)
(mm)
A
0.053
-
0.069
1.346
-
1.753
A1
0.004
-
0.010
0.102
-
0.254
D
0.386
-
0.394
9.804
-
10.008
E
0.150
-
0.157
3.810
-
3.988
H
0.228
-
0.244
5.791
-
6.198
L
0.016
-
0.050
0.406
-
1.270
θ°
0° - 8°
0° - 8°
Page 89
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 89 Version 0.9
15.5 SOP 14 PIN
SYMBOLS
MIN
NOR
MAX
MIN
NOR
MAX
(inch)
(mm)
A
0.058
0.064
0.068
1.4732
1.6256
1.7272
A1
0.004
-
0.010
0.1016
-
0.254
B
0.013
0.016
0.020
0.3302
0.4064
0.508
C
0.0075
0.008
0.0098
0.1905
0.2032
0.2490
D
0.336
0.341
0.344
8.5344
8.6614
8.7376
E
0.150
0.154
0.157
3.81
3.9116
3.9878 e -
0.050 - -
1.27 - H
0.228
0.236
0.244
5.7912
5.9944
6.1976
L
0.015
0.025
0.050
0.381
0.635
1.27
θ°
0° - 8°
0° - 8°
Page 90
SN8PC20
Remote Control 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 90 Version 0.9
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or
design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed,
intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a
situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such
unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries,
affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use
even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.
Main Office:
Address: 10F-1, No.36, Taiyuan Street, Chupei City, Hsinchu, Taiwan.
Tel: 886-3-5600 888
Fax: 886-3-5600 889
Taipei Office:
Address: 15F-2, No.171 Song Ted Road, Taipei, Taiwan
Tel: 886-2-2759 1980
Fax: 886-2-2759 8180
Hong Kong Office:
Unit 1519, Chevalier Commercial Centre, NO.8 Wang Hoi Road, Kowloon Bay,
Hong Kong.
Tel: 852-2723-8086
Fax: 852-2723-9179
Technical Support by Email:
Sn8fae@sonix.com.tw
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