Page 1
SN8P275X Series
USER’S MANUAL
Version 0.7
SN8P2754
SN8P2755
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
SN8P2758
S
O
Nii
S
O
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
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SONiX TECHNOLOGY CO., LTD Page 1 Version 0.7
Page 2
AMENDENT HISTORY
Version Date Description
VER 0.1 Nov. 2008 1. Preliminary Version first issue
VER 0.2 Nov. 2008 1. Modify Package information.
VER 0.3 Nov. 2008 1. Modify ICE MSP emulation.
VER 0.4 Feb. 2008 1. Modify MSP,Package information.
VER 0.5 Apr. 2009 1. Modify SOP32 Package size.
VER 0.6 Jun. 2009 1. Update code option table.
VER 0.7 Nov. 2009 1. Modify LQFP48 marking name
2. Add AVDD pin descriptment
3. Modify DAO as 7bit DAC output in 1.4 Pin Description
4. Fix typing error
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page 2 Version 0.7
Page 3
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1
1
PRODUCT OVERVIEW......................................................................................................................... 9
1.1 FEATURES........................................................................................................................................ 9
1.2 SYSTEM BLOCK DIAGRAM........................................................................................................ 10
1.3 PIN ASSIGNMENT......................................................................................................................... 11
1.4 PIN DESCRIPTIONS....................................................................................................................... 13
1.5 PIN CIRCUIT DIAGRAMS............................................................................................................. 14
2
2
2
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 15
2.1 MEMORY MAP............................................................................................................................... 15
2.1.1 PROGRAM MEMORY (ROM)............................................................................................... 15
2.1.1.1 RESET VECTOR (0000H) .................................................................................................. 16
2.1.1.2 INTERRUPT VECTOR (0008H)......................................................................................... 16
2.1.1.3 LOOK-UP TABLE DESCRIPTION.................................................................................... 19
2.1.1.4 JUMP TABLE DESCRIPTION ........................................................................................... 21
2.1.1.5 CHECKSUM CALCULATION........................................................................................... 23
2.1.2 CODE OPTION TABLE.......................................................................................................... 24
2.1.3 DATA MEMORY (RAM) ....................................................................................................... 25
2.1.4 SYSTEM REGISTER .............................................................................................................. 26
2.1.4.1 SYSTEM REGISTER TABLE ............................................................................................ 26
2.1.4.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 26
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER....................................................................... 27
2.1.4.4 ACCUMULATOR ............................................................................................................... 31
2.1.4.5 PROGRAM FLAG............................................................................................................... 32
2.1.4.6 PROGRAM COUNTER....................................................................................................... 33
2.1.4.7 H, L REGISTERS................................................................................................................. 35
2.1.4.8 Y, Z REGISTERS................................................................................................................. 37
2.1.4.9 X REGISTERS..................................................................................................................... 37
2.1.4.10 R REGISTERS..................................................................................................................... 38
2.2 ADDRESSING MODE .................................................................................................................... 39
2.2.1 IMMEDIATE ADDRESSING MODE.................................................................................... 39
2.2.2 DIRECTLY ADDRESSING MODE ....................................................................................... 39
2.2.3 INDIRECTLY ADDRESSING MODE................................................................................... 39
2.3 STACK OPERATION...................................................................................................................... 40
2.3.1 OVERVIEW............................................................................................................................. 40
2.3.2 STACK REGISTERS............................................................................................................... 41
SONiX TECHNOLOGY CO., LTD Page 3 Version 0.7
Page 4
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
2.3.3 STACK OPERATION EXAMPLE.......................................................................................... 42
3
3
3
RESET..................................................................................................................................................... 43
3.1 OVERVIEW..................................................................................................................................... 43
3.2 POWER ON RESET......................................................................................................................... 44
3.3 WATCHDOG RESET...................................................................................................................... 44
3.4 BROWN OUT RESET ..................................................................................................................... 45
3.4.1 BROWN OUT DESCRIPTION............................................................................................... 45
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION................................................... 46
3.4.3 BROWN OUT RESET IMPROVEMENT .............................................................................. 46
3.5 EXTERNAL RESET........................................................................................................................ 48
3.6 EXTERNAL RESET CIRCUIT ....................................................................................................... 48
3.6.1 Simply RC Reset Circuit.......................................................................................................... 48
3.6.2 Diode & RC Reset Circuit........................................................................................................ 49
3.6.3 Zener Diode Reset Circuit........................................................................................................ 49
3.6.4 Voltage Bias Reset Circuit ....................................................................................................... 50
3.6.5 External Reset IC...................................................................................................................... 51
4
4
4
SYSTEM CLOCK.................................................................................................................................. 52
4.1 OVERVIEW..................................................................................................................................... 52
4.2 CLOCK BLOCK DIAGRAM .......................................................................................................... 52
4.3 OSCM REGISTER........................................................................................................................... 53
4.4 SYSTEM HIGH CLOCK ................................................................................................................. 54
4.4.1 INTERNAL HIGH RC............................................................................................................. 54
4.4.2 EXTERNAL HIGH CLOCK.................................................................................................... 54
4.4.2.1 CRYSTAL/CERAMIC......................................................................................................... 55
4.4.2.2 RC......................................................................................................................................... 55
4.4.2.3 EXTERNAL CLOCK SIGNAL........................................................................................... 56
4.5 SYSTEM LOW CLOCK.................................................................................................................. 57
4.5.1 SYSTEM CLOCK MEASUREMENT .................................................................................... 58
5
5
5
SYSTEM OPERATION MODE........................................................................................................... 59
5.1 OVERVIEW..................................................................................................................................... 59
5.2 SYSTEM MODE SWITCHING....................................................................................................... 60
5.3 WAKEUP......................................................................................................................................... 62
5.3.1 OVERVIEW............................................................................................................................. 62
5.3.2 WAKEUP TIME ...................................................................................................................... 62
5.3.3 P1W WAKEUP CONTROL REGISTER................................................................................ 63
6
6
6
INTERRUPT........................................................................................................................................... 64
6.1 OVERVIEW..................................................................................................................................... 64
SONiX TECHNOLOGY CO., LTD Page 4 Version 0.7
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
6.2 INTEN INTERRUPT ENABLE REGISTER................................................................................... 65
6.3 INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 66
6.4 GIE GLOBAL INTERRUPT OPERATION .................................................................................... 67
6.5 PUSH, POP ROUTINE .................................................................................................................... 67
6.6 EXTERNAL INTERRUPT OPERATION (INT0~INT2)................................................................ 69
6.7 T0 INTERRUPT OPERATION ....................................................................................................... 70
6.8 TC0 INTERRUPT OPERATION..................................................................................................... 71
6.9 TC1 INTERRUPT OPERATION..................................................................................................... 72
6.10 SIO INTERRUPT OPERATION ..................................................................................................... 73
6.11 ADC INTERRUPT OPERATION ................................................................................................... 74
6.12 MULTI-INTERRUPT OPERATION............................................................................................... 75
7
7
7
I/O PORT................................................................................................................................................ 77
7.1 I/O PORT MODE ............................................................................................................................. 77
7.2 I/O PULL UP REGISTER ................................................................................................................ 79
7.3 I/O PORT DATA REGISTER.......................................................................................................... 80
7.4 I/O OPEN-DRAIN REGISTER........................................................................................................ 81
7.5 PORT 4 ADC SHARE PIN............................................................................................................... 82
8
8
8
TIMERS .................................................................................................................................................. 84
8.1 WATCHDOG TIMER...................................................................................................................... 84
8.2 TIMER 0 (T0)................................................................................................................................... 86
8.2.1 OVERVIEW............................................................................................................................. 86
8.2.2 T0M MODE REGISTER ......................................................................................................... 87
8.2.3 T0C COUNTING REGISTER................................................................................................. 88
8.2.4 T0 TIMER OPERATION SEQUENCE................................................................................... 89
8.3 TIMER/COUNTER 0 (TC0) ............................................................................................................ 90
8.3.1 OVERVIEW............................................................................................................................. 90
8.3.2 TC0M MODE REGISTER....................................................................................................... 91
8.3.3 TC0C COUNTING REGISTER .............................................................................................. 92
8.3.4 TC0R AUTO-LOAD REGISTER............................................................................................ 93
8.3.5 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)................................................................ 94
8.3.6 TC0 TIMER OPERATION SEQUENCE................................................................................ 95
8.3.7 TC0 TIMER NOTICE.............................................................................................................. 96
8.4 TIMER/COUNTER 1 (TC1) ............................................................................................................ 97
8.4.1 OVERVIEW............................................................................................................................. 97
8.4.2 TC1M MODE REGISTER....................................................................................................... 98
8.4.3 TC1C COUNTING REGISTER .............................................................................................. 99
8.4.4 TC1R AUTO-LOAD REGISTER.......................................................................................... 100
8.4.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER).............................................................. 101
SONiX TECHNOLOGY CO., LTD Page 5 Version 0.7
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
8.4.6 TC1 TIMER OPERATION SEQUENCE.............................................................................. 102
8.4.7 TC1 TIMER NOTICE............................................................................................................ 103
8.5 PWM0 MODE................................................................................................................................ 104
8.5.1 OVERVIEW........................................................................................................................... 104
8.5.2 TC0IRQ AND PWM DUTY.................................................................................................. 105
8.5.3 PWM PROGRAM EXAMPLE.............................................................................................. 106
8.5.4 PWM0 DUTY CHANGING NOTICE................................................................................... 107
8.6 PWM1 MODE................................................................................................................................ 109
8.6.1 OVERVIEW........................................................................................................................... 109
8.6.2 TC1IRQ AND PWM DUTY.................................................................................................. 110
8.6.3 PWM PROGRAM EXAMPLE.............................................................................................. 111
8.6.4 PWM1 DUTY CHANGING NOTICE................................................................................... 112
9
9
9
SERIAL INPUT/OUTPUT TRANSCEIVER (SIO) ......................................................................... 114
9.1 OVERVIEW................................................................................................................................... 114
9.2 SIO OPERATION .......................................................................................................................... 114
9.3 SIOM MODE REGISTER.............................................................................................................. 116
9.4 SIOB DATA BUFFER ................................................................................................................... 117
9.5 SIOR REGISTER DESCRIPTION ................................................................................................ 118
1
0
1
0
1
0
MAIN SERIAL PORT (MSP)............................................................................................................. 119
10.1 OVERVIEW................................................................................................................................... 119
10.2 MSP STATUS REGISTER ............................................................................................................ 119
10.3 MSP MODE REGISTER 1............................................................................................................. 120
10.4 MSP MODE REGISTER 2............................................................................................................. 121
10.5 MSP MSPBUF REGISTER............................................................................................................ 122
10.6 MSP MSPADR REGISTER........................................................................................................... 122
10.7 SLAVE MODE OPERATION ............................................................................................................... 123
10.7.1 Addressing.............................................................................................................................. 123
10.7.2 Slave Receiving...................................................................................................................... 124
10.7.3 Slave Transmission................................................................................................................. 125
10.7.4 General Call Address.............................................................................................................. 126
10.7.5 Slave Wake up........................................................................................................................ 127
10.8 MASTER MODE ................................................................................................................................ 128
10.8.1 Mater Mode Support............................................................................................................... 128
10.8.2 MSP Rate Generator............................................................................................................... 128
10.8.3 MSP Mater START Condition............................................................................................... 129
10.8.4 MSP Master mode Repeat START Condition ....................................................................... 130
10.8.5 Acknowledge Sequence Timing............................................................................................. 131
10.8.6 STOP Condition Timing......................................................................................................... 132
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
10.8.7 Clock Arbitration.................................................................................................................... 132
10.8.8 Master Mode Transmission.................................................................................................... 133
10.8.9 Master Mode Receiving.......................................................................................................... 134
1
1
1
1
1
1
8 CHANNEL ANALOG TO DIGITAL CONVERTER................................................................... 135
11.1 OVERVIEW................................................................................................................................... 135
11.2 ADM REGISTER........................................................................................................................... 136
11.3 ADR REGISTERS.......................................................................................................................... 137
11.4 ADB REGISTERS.......................................................................................................................... 138
11.5 P4CON REGISTERS ..................................................................................................................... 139
11.6 ADC CONVERTING TIME .......................................................................................................... 139
11.7 ADC ROUTINE EXAMPLE.......................................................................................................... 140
11.8 ADC CIRCUIT............................................................................................................................... 141
1
2
1
2
1
2
DIGITAL TO ANALOG CONVERTER........................................................................................... 142
12.1 OVERVIEW................................................................................................................................... 142
12.2 DAM REGISTER........................................................................................................................... 143
12.3 D/A CONVERTER OPERATION................................................................................................. 143
1
3
1
3
1
3
INSTRUCTION TABLE ..................................................................................................................... 144
1
4
1
4
1
4
ELECTRICAL CHARACTERISTIC................................................................................................ 145
14.1 ABSOLUTE MAXIMUM RATING.............................................................................................. 145
14.2 STANDARD ELECTRICAL CHARACTERISTIC...................................................................... 145
1
5
1
5
1
5
APPLICATION NOTICE ................................................................................................................... 146
15.1 DEVELOPMENT TOOL VERSION ....................................................................................................... 146
15.1.1 ICE (In circuit emulation)....................................................................................................... 146
15.1.2 OTP Writer............................................................................................................................. 147
15.1.3 IDE (Integrated Development Environment)......................................................................... 147
15.2 OTP PROGRAMMING PIN................................................................................................................. 148
15.2.1 The pin assignment of Easy Writer transition board socket:.................................................. 148
15.2.2 The pin assignment of Writer V3.0 and V2.5 transition board socket:.................................. 148
15.2.3 SN8P275X Series Programming Pin Mapping: ..................................................................... 149
1
6
1
6
1
6
PACKAGE INFORMATION ............................................................................................................. 150
16.1 SK-DIP28 PIN................................................................................................................................ 150
16.2 SOP28 PIN...................................................................................................................................... 151
16.3 P-DIP 32 PIN.................................................................................................................................. 152
16.4 SOP 32 PIN..................................................................................................................................... 152
16.5 SSOP 48 PIN................................................................................................................................... 153
SONiX TECHNOLOGY CO., LTD Page 7 Version 0.7
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
16.6 LQFP 48 PIN .................................................................................................................................. 154
1
7
1
7
1
7
MARKING DEFINITION................................................................................................................... 155
17.1 INTRODUCTION.......................................................................................................................... 155
17.2 MARKING INDETIFICATION SYSTEM.................................................................................... 155
17.3 MARKING EXAMPLE ................................................................................................................. 156
17.4 DATECODE SYSTEM.................................................................................................................. 156
SONiX TECHNOLOGY CO., LTD Page 8 Version 0.7
Page 9
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
1
1
1
PRODUCT OVERVIEW
1.1 FEATURES
Memory configuration
♦
OTP ROM size: 4K * 16 bits.
RAM size: 256 * 8 bits (bank 0 and bank 1). Three external interrupts: INT0, INT1, INT2.
8 levels stack buffer.
♦
I/O pin configuration (Total 36 pins)
♦
Bi-directional: P0, P1, P2, P3, P4, P5 TC0: Auto-reload timer/Counter/PWM0/Buzzer output
Programmable open-drain: P1.0, P1.1, P5.2 TC1: Auto-reload timer/Counter/PWM1/Buzzer output
Wakeup: P0, P1 level change trigger
External interrupt: P0
Pull-up resisters: P0, P1, P2, P3, P4, P5
P4 pins shared with ADC inputs.
Programmable open-drain: P1.0, P1.1,P5.2
8-channel 12-bit SAR ADC.
♦
One channel 7-bit R2R DAC.
♦
SIO function.
♦
Powerful instructions
♦
One clocks per instruction cycle (1T)
Most of instructions are one cycle only Green mode: Periodical wakeup by T0 timer
All ROM area lookup table function (MOVC)
Hardware multiplier (MUL)
SN8P2758: SSOP 48 pins, LQFP 48 pins
Memory configuration
♦
OTP ROM size: 4K * 16 bits.
RAM size: 256 * 8 bits (bank 0 and bank 1).
Eight levels stack buffer
I/O pin configuration (Total 36 pins)
♦
Bi-directional: P0, P1, P2, P3, P4, P5 T0: Basic timer
Programmable open-drain: P1.0, P1.1, P5.2 TC0: Auto-reload timer/Counter/PWM0/Buzzer output
Wakeup: P0, P1 level change trigger TC1: Auto-reload timer/Counter/PWM1/Buzzer output
External interrupt: P0
Pull-up resisters: P0, P1, P2, P3, P4, P5
P4 pins shared with ADC inputs.
Build in MSP interface with interrupt function
♦
MSP sleep mode wake up function.
Eight interrupt sources
♦
Six internal interrupts: T0, TC0, TC1, SIO, ADC,MSP.
Three 8-bit Timer/Counter
♦
T0: Basic timer
On chip watchdog timer and clock source is internal
♦
low clock RC type (16KHz @3V, 32KHz @5V).
Dual system clocks
♦
External high clock: RC type up to 10 MHz
External high clock: Crystal type 32KHZ up to 16 MHz
Internal low clock: RC type 16KHz(3V), 32KHz(5V)
Internal high clock: RC type 16MHz.
Operating modes
♦
Normal mode: Both high and low clock active
Slow mode: Low clock only
Sleep mode: Both high and low clock stop
Package (Chip form support)
♦
SN8P2755: PDIP 32 pins, SOP 32 pins
SN8P2754: SK-DIP 28 pins, SOP 28pins
Three 8-bit Timer/Counter
♦
On chip watchdog timer and clock source is internal
♦
low clock RC type (16KHz @3V, 32KHz @5V).
Dual system clocks
♦
SONiX TECHNOLOGY CO., LTD Page 9 Version 0.7
Page 10
) Features Selection Table
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
CHIP ROM RAM Stack
Timer PWM
I/O ADC DAC
T0 TC0 TC1
Buzzer
SIO
Wakeup
Pin no.
Package
SN8P2758 4K*16 256 8 V V V 36 8ch 1ch 2 1 11 SSOP48/LQFP48
SN8P2755 4K*16 256 8 V V V 23 8ch 1ch 2 1 9 DIP32/SOP32
SN8P2754 4K*16 256 8 V V V 18 5ch 1ch 2 1 8 SKDIP28/SOP28
1.2 SYSTEM BLOCK DIAGRAM
system block
system block
Internal
PC
PC
IR
IR
FLAGS
FLAGS
ALU
ALU
ACC
ACC
OTP
OTP
ROM
ROM
SYSTEM REGISTER
SYSTEM REGISTER
H-OSC
H-OSC
TIMING GENERATOR
TIMING GENERATOR
RAM
RAM
Internal
CLK
CLK
Low Volt
Low Volt
Detector
Detector
Watch-Dog
Watch-Dog
Timer
Timer
PWM0
PWM0
PWM1
PWM1
DAC
DAC
ADC
ADC
PWM0/Buzzer0
PWM0/Buzzer0
PWM1/Buzzer1
PWM1/Buzzer1
DAO
DAO
AIN0~AIN7
AIN0~AIN7
PORT 0
PORT 0
INTERRUPT
INTERRUPT
CONTROL
CONTROL
SIO
SIO
TX/RX
TX/RX
PORT 3
PORT 2PORT 1 PORT 4 PORT 5
PORT 2PORT 1 PORT 4 PORT 5
PORT 3
TIMER & COUNTER
TIMER & COUNTER
SONiX TECHNOLOGY CO., LTD Page 10 Version 0.7
Page 11
1.3 PIN ASSIGNMENT
SN8P2754K (SK-DIP28)
SN8P2754A (SOP28)
SN8P2755P (P-DIP32)
SN8P2755S (SOP32)
RST/VPP/P3.3 8 25 AVREFH
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
P1.4 1 U 28 RST/VPP/P3.3
P1.3 2 27 P0.2/INT2
VDD 3 26 P0.1/INT1
P1.2 4 25 P0.0/INT0
SDA/P1.1 5 24 VDD
SCL/P1.0 6 23 XIN/P3.2
VSS 7 22 XOUT/P3.1
P4.4/AIN4 8 21 VSS
P4.3/AIN3 9 20 P5.0/SCK
P4.2/AIN2 10 19 P5.1/SI
P4.1/AIN1 11 18 P5.2/SO
P4.0/AIN0 12 17 P5.3/TC1/PWM1
AVREFH 13 16 P5.4/TC0/PWM0
VDD 14 15 DAO
SN8P2754K
SN8P2754S
VSS 1 U 32 P5.0/SCK
XOUT/P3.1 2 31 P5.1/SI
XIN/P3.2 3 30 P5.2/SO
VDD 4 29 P5.3/BZ1/PWM1
P0.0/INT0 5 28 P5.4/BZ0/PWM0
P0.1/INT1 6 27 DAO
P0.2/INT2 7 26 VDD
P1.5 9 24 P4.0/AIN0
P1.4 10 23 P4.1/AIN1
P1.3 11 22 P4.2/AIN2
P1.2 12 21 P4.3/AIN3
SDA/P1.1 13 20 P4.4/AIN4
SCL/P1.0 14 19 P4.5/AIN5
P2.0 15 18 P4.6/AIN6
VSS 16 17 P4.7/AIN7
SN8P2755P
SN8P2755S
SONiX TECHNOLOGY CO., LTD Page 11 Version 0.7
Page 12
SN8P2758X (SSOP48)
SN8P2758F (LQFP48)
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
P2.5 1 U 48 P2.4
P2.6 2 47 P5.0/SCK
P2.7 3 46 P5.1/SI
P1.7 4 45 P5.2/SO
VSS 5 44 P5.3/BZ1/PWM1
XOUT/P3.1 6 43 P3.0
XIN/P3.2 7 42 P5.4/BZ0/PWM0
VDD 8 41 P5.5
P0.0/INT0 9 40 P5.6
P0.1/INT1 10 39 P5.7
P0.2/INT2 11 38 DAO
RST/VPP/P3.3 12 37 VDD
P1.5 13 36 AVDD
P1.4 14 35 AVREFH
P1.3 15 34 P4.0/AIN0
VDD 16 33 P4.1/AIN1
P1.6 17 32 P4.2/AIN2
P1.2 18 31 P4.3/AIN3
SDA/P1.1 19 30 P4.4/AIN4
SCL/P1.0 20 29 P4.5/AIN5
P2.0 21 28 P4.6/AIN6
P2.1 22 27 P4.7/AIN7
P2.2 23 26 AVREFL
P2.3 24 25 VSS
SN8P2758X
P2.5
P2.6
P2.7
P1.7
VSS
XOUT/P3.1
XIN/P3.2
VDD
P0.0/INT0
P0.1/INT1
P0.2/INT2
RST/VPP/P3.3
P2.4
P5.0/SCK
P5.1/SI
P5.2/SO
P5.3/BZ1/PWM1
P3.0
P5.4/BZ0/PWM0
P5.5
P5.6
P5.7
DAO
VDD
48 47 46 45 44 43 42 41 40
1
2 35
3 34
4 33
5 32
6 SN8P2758F 31
7 30
8 29
9 28
10 27
11 26
12 25
36
O
13 14 15 16 17 18 19 20 21
P1.5
P1.4
P1.3
P1.6
VDD
P1.2
SDA/P1.1
39
22
P2.0
P2.1
SCL/P1.0
38 37
23 24
P2.2
P2.3
AVDD
AVREFH
P4.0/AIN0
P4.1/AIN1
P4.2/AIN2
P4.3/AIN3
P4.4/AIN4
P4.5/AIN5
P4.6/AIN6
P4.7/AIN7
AVREFL
VSS
SONiX TECHNOLOGY CO., LTD Page 12 Version 0.7
Page 13
1.4 PIN DESCRIPTIONS
PIN NAME DESCRIPTION
VDD, VSS P Power supply input pins for digital circuit.
RST/VPP/P3.3 I, P
XIN/P3.2 I/O
XOUT/P3.1 I/O
P0.0/INT0 I/O
P0.1/INT1 I/O
P0.2/INT2 I/O
P1.0/SCL I/O
P1.1/SDA I/O
P1 [7:2] I/O
P2 [7:0] I/O
P3.0 I/O
P4.[7:0]/AIN[7:0] I/O
P5.0/SCK I/O
P5.1/SO I/O
P5.2/SI I/O
P5.3/BZ1/PWM1 I/O
P5.4/BZ0/PWM0 I/O
AVDD P Power supply input pins for A/D circuit
AVREFH I ADC highest reference voltage input
AVREFL I ADC lowest reference voltage input
DAO O 7bit DAC output
RST: System reset input pin. Schmitt trigger structure, low active, normal stay to “high”.
VPP: OTP programming pin.
Port 3.3 input pin.
Schmitt trigger structure as input mode.
No Built-in pull-up resisters.
Oscillator input pin while external oscillator enable (crystal and RC).
Port 3.2 bi-direction pin.
Schmitt trigger structure as input mode.
Built-in pull-up resisters.
XOUT: Oscillator output pin while external crystal enable.
Port 3.1 bi-direction pin.
Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Port 0.0 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Built-in wakeup function.
INT0 trigger pin (Schmitt trigger).
TC0 event counter clock input pin.
Port 0.1 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Built-in wakeup function.
INT1 trigger pin (Schmitt trigger).
TC1 event counter clock input pin.
Port 0.2 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Built-in wakeup function.
INT2 trigger pin (Schmitt trigger).
Port 1.0 bi-direction pin and open-drain pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
MSP serial clock input/output pin.
Programmable open-drain.
Port P1.1 bi-direction pin and open-drain pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
MSP data I/O pin.
Programmable open-drain.
Port 1.2~P1.7 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Port 2 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Port 3.0 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
Port 4 bi-direction pins. No Schmitt trigger structure.
Built-in pull-up resisters.
AIN[7:0]: ADC channel-0~7 input.
Port 5.0 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
SCK: SIO clock pin.
Port 5.1 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
SO: SIO data output pin.
Port 5.2 bi-direction pin and open-drain pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
SI: SIO data input pin.
Port 5.3 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin.
Port 5.4 bi-direction pin. Schmitt trigger structure as input mode.
Built-in pull-up resisters.
TC0 ÷ 2 signal output pin for buzzer or PWM0 output pin.
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page 13 Version 0.7
Page 14
1.5 PIN CIRCUIT DIAGRAMS
Port 1.0, P1.1, P5.2 structure:
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
Pull-Up
Pin
Port 0, 1, 2, 3, 5 structure:
Port 4 structure:
Pin
PnM
PnM
P1OC
Pull-Up
PnM, PnUR
Open-Drain
PnM, PnUR
Pull-Up
Input Bus
Output
Latch
Output Bus
Input Bus
Output
Latch
Output Bus
P4CON
Pin
PnM
GCHS
PnM, PnUR
Output
Latch
Input Bus
Output Bus
Int. ADC
SONiX TECHNOLOGY CO., LTD Page 14 Version 0.7
Page 15
2
2
2
CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
) 4K words ROM
0000H
0001H
.
.
0007H
0008H
0009H User program
.
.
000FH
0010H
0011H
.
.
.
.
.
FFBH
FFCH
FFDH
FFEH
FFFH
General purpose area
General purpose area
ROM
Reset vector
Interrupt vector
Reserved
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
User reset vector
Jump to user start address
User interrupt vector
End of user program
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
2.1.1.1 RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
) Power On Reset (NT0=1, NPD=0).
) Watchdog Reset (NT0=0, NPD=0).
) External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
¾ Example: Defining Reset Vector
…
START:
… ; User program
…
ORG 0 ; 0000H
JMP START ; Jump to user program address.
ORG 10H
; 0010H, The head of user program.
ENDP ; End of program
2.1.1.2 INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
¾ Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
…
…
…
…
ORG 0 ; 0000H
JMP START ; Jump to user program address.
ORG 8 ; Interrupt vector.
PUSH ; Save ACC and PFLAG register to buffers.
POP ; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine
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START: ; The head of user program.
… ; User program
…
JMP START ; End of user program
…
ENDP ; End of program
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
¾ Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
JMP MY_IRQ ; 0008H, Jump to interrupt service routine address.
START: ; 0010H, The head of user program.
… ; User program.
…
…
JMP START ; End of user program.
…
MY_IRQ: ;The head of interrupt service routine.
…
…
…
ENDP ; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.
ORG 8 ; Interrupt vector.
ORG 10H
PUSH ; Save ACC and PFLAG register to buffers.
POP ; Load ACC and PFLAG register from buffers.
RETI ; End of interrupt service routine.
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
2.1.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, X register is pointed to high byte address (bit 16~bit 23), Y register is pointed to
middle byte address (bit 8~bit 15) and Z register is pointed to low byte address (bit 0~bit 7) of ROM. After MOVC
instruction executed, the low-byte data will be stored in ACC and high-byte data stored in R register.
¾ Example: To look up the ROM data located “TABLE1”.
B0MOV X, #TABLE1$H ; To set lookup table1’s high address
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
JMP @F ; Y is not overflow.
INCMS X ; Y is overflow, X=X+1.
NOP
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
Note: The X, Y registers will not increase automatically when Y, Z registers crosses boundary from 0xFF
to 0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register is
overflow, Y register must be added one. If Y register is overflow, X register must be added one. The
following INC_XYZ macro shows a simple method to process X, Y and Z registers automatically.
INCMS Z ; Z+1
JMP @F ; Z is not overflow.
INCMS Y ; Z is overflow, Y=Y+1.
;
; Increment the index address for next address.
¾ Example: INC_XYZ macro.
INC_XYZ MACRO
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Y+1
JMP @F ; Not overflow
INCMS X ; X+1
NOP ; Not overflow
@@:
ENDM
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
¾ Example: Modify above example by “INC_XYZ” macro.
B0MOV X, #TABLE1$H ; To set lookup table1’s high address
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
INC_XYZ
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
The other example of loop-up table is to add X, Y or Z index register by accumulator. Please be careful if
“carry” happen.
¾ Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV X, #TABLE1$H ; To set lookup table1’s high address
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table’s low address.
GETDATA: ;
MOVC ; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
;
B0MOV A, BUF ; Z = Z + BUF.
B0ADD Z, A
B0BTS1 FC ; Check the carry flag.
JMP GETDATA ; FC = 0
INCMS Y ; FC = 1. Y+1.
JMP GETDATA ; Y is not overflow.
INCMS X ; Y is overflow, X=X+1.
NOP
; Increment the index address for next address.
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
2.1.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
¾ Example: Jump table.
ORG 0X0100 ; The jump table is from the head of the ROM boundary
B0ADD PCL, A ; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP A0POINT ; ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
¾ Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A MACRO VAL
IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP ($ | 0XFF)
ORG ($ | 0XFF)
ENDIF
ADD PCL, A
ENDM
Note: “VAL” is the number of the jump table listing number.
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
¾ Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV A, BUF0 ; “BUF0” is from 0 to 4.
@JMP_A 5 ; The number of the jump table listing is five.
JMP A0POINT ; ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
JMP A4POINT ; ACC = 4, jump to A4POINT
If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A” macro will adjust the jump table
routine begin from next ROM boundary (0x0100).
¾ Example: “@JMP_A” operation.
; Before compiling program.
ROM address
B0MOV A, BUF0 ; “BUF0” is from 0 to 4.
@JMP_A 5 ; The number of the jump table listing is five.
0X00FD JMP A0POINT ; ACC = 0, jump to A0POINT
0X00FE JMP A1POINT ; ACC = 1, jump to A1POINT
0X00FF JMP A2POINT ; ACC = 2, jump to A2POINT
0X0100 JMP A3POINT ; ACC = 3, jump to A3POINT
0X0101 JMP A4POINT ; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
B0MOV A, BUF0 ; “BUF0” is from 0 to 4.
@JMP_A 5 ; The number of the jump table listing is five.
0X0100 JMP A0POINT ; ACC = 0, jump to A0POINT
0X0101 JMP A1POINT ; ACC = 1, jump to A1POINT
0X0102 JMP A2POINT ; ACC = 2, jump to A2POINT
0X0103 JMP A3POINT ; ACC = 3, jump to A3POINT
0X0104 JMP A4POINT ; ACC = 4, jump to A4POINT
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
2.1.1.5 CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
¾ Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
MOV A,#END_USER_CODE$L
B0MOV END_ADDR1, A ; Save low end address to end_addr1
MOV A,#END_USER_CODE$M
B0MOV END_ADDR2, A ; Save middle end address to end_addr2
CLR Y ; Set Y to 00H
CLR Z ; Set Z to 00H
@@:
MOVC
B0BSET FC ; Clear C flag
ADD DATA1, A ; Add A to Data1
MOV A, R
ADC DATA2, A ; Add R to Data2
JMP END_CHECK ; Check if the YZ address = the end of code
AAA:
INCMS Z ; Z=Z+1
JMP @B ; If Z != 00H calculate to next address
JMP Y_ADD_1 ; If Z = 00H increase Y
END_CHECK:
MOV A, END_ADDR1
CMPRS A, Z ; Check if Z = low end address
JMP AAA ; If Not jump to checksum calculate
MOV A, END_ADDR2
CMPRS A, Y ; If Yes, check if Y = middle end address
JMP AAA ; If Not jump to checksum calculate
JMP CHECKSUM_END ; If Yes checksum calculated is done.
Y_ADD_1:
INCMS Y ; Increase Y
NOP
JMP @B ; Jump to checksum calculate
CHECKSUM_END:
…
…
END_USER_CODE: ; Label of program end
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8-bit micro-controller build-in 12-bit ADC
2.1.2 CODE OPTION TABLE
Code Option Content Function Description
SN8P275X Series
High_Clk
Watch_Dog
Fcpu
Security
Noise_Filter
Reset_Pin
External Reset
Length
Note:
RC
12M X’tal
4M X’tal Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
IHRC_16M
IHRC_RTC
32K X’tal
Always_On
Enable
Disable Disable Watchdog function.
Fhosc/1
Fhosc/2
Fhosc/4 Instruction cycle is 4 oscillator clocks.
Fhosc/8 Instruction cycle is 8 oscillator clocks.
Fhosc/16 Instruction cycle is 16 oscillator clocks.
Fhosc/32 Instruction cycle is 32 oscillator clocks.
Fhosc/64 Instruction cycle is 64 oscillator clocks.
Fhosc/128 Instruction cycle is 128 oscillator clocks.
Enable Enable ROM code Security function.
Disable Disable ROM code Security function.
Enable Enable Noise Filter.
Disable Disable Noise Filter.
P3.3 Enable P3.3 input only without pull-up resister.
Reset Enable External reset PIN.
No Disable External reset de-bounce time.
128 * ILRC
1. In high noisy environment, enable “Noise Filter” and set Watch_Dog as “Always_On”
Low cost RC for external high clock oscillator and XOUT becomes to
Fcpu frequency output pin.
High speed crystal /resonator (e.g. 12MHz) for external high clock
oscillator.
High speed internal 16MHz RC. XIN/XOUT become to P3.2/P3.1
bi-direction I/O pins.
High speed internal 16MHz RC with 0.5sec RTC. XIN/XOUT become to
P3.2/P3.1 bit-direction I/O pins.
Low frequency, power saving crystal (e.g. 32.768KHz) for external high
clock oscillator.
Watchdog timer is always on enable even in power down and green
mode.
Enable watchdog timer. Watchdog timer stops in power down mode.
Watchdog is running in green mode.
Instruction cycle is oscillator clock.
Notice: In Fosc/1, Noise Filter must be disabled.
Instruction cycle is 2 oscillator clocks.
Notice: In Fosc/1, Noise Filter must be disabled.
Enable External reset de-bounce time.
is strongly recommended.
2. Fcpu code option is only available for High Clock. Fcpu of slow mode is Flosc/4.
3. In external RC mode, the Noise_Filter is enabled by assembler.
4. If watchdog enable, watchdog timer is still counting in green mode.
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2.1.3 DATA MEMORY (RAM)
) 256 X 8-bit RAM
Address
000h
“
“
“
“
“
BANK 0
BANK 1
07Fh
080h
“
“
“
“
“
0FFh
100h
“
“
“
“
“
17Fh
RAM location
General purpose area
System register
End of bank 0 area
General purpose area
End of bank 1 area
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
000h~07Fh of Bank 0 = To store
general purpose data (128 bytes).
080h~0FFh of Bank 0 store system
registers (128 bytes).
100h~17Fh of Bank 1 = To store
general purpose data (128 bytes).
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
2.1.4 SYSTEM REGISTER
2.1.4.1 SYSTEM REGISTER TABLE
0 1 2 3 4 5 6 7 8 9 A B C D E F
L H R Z Y X PFLAG RBANK - - - - - - - -
8
MSPSTAT MSPM1 MSPM2 MSPBUF MSPADR
9
- - - - - - - - - - - - - - P4CON -
A
DAM ADM ADB ADR SIOM SIOR SIOB - P0M - - - - - - PEDGE
B
P1W P1M P2M P3M P4M P5M INTRQ_1 INTEN_1 INTRQ INTEN OSCM -
C
P0 P1 P2 P3 P4 P5 - - T0M T0C TC0M TC0C TC1M TC1C TC1R STKP
D
P0UR P1UR P2UR P3UR P4UR P5UR @HL @YZ - P1OC - - - - - -
E
STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
F
2.1.4.2 SYSTEM REGISTER DESCRIPTION
L, H = Working & @HL addressing register. R = Working register and ROM lookup data buffer.
X = Working and ROM address register. Y, Z = Working, @YZ and ROM addressing register.
PFLAG = ROM page and special flag register. RBANK = RAM Bank Select register.
DAM = DAC’s mode register. ADM = ADC’s mode register.
ADB = ADC’s data buffer. ADR = ADC’s resolution selects register.
SIOM = SIO mode control register. SIOR = SIO’s clock reload buffer.
SIOB = SIO’s data buffer. P1W = Port 1 wakeup register.
PnM = Port n input/output mode register. Pn = Port n data buffer.
INTRQ = Interrupts’ request register. INTEN = Interrupts’ enable register.
OSCM = Oscillator mode register. PCH, PCL = Program counter.
T0M = Timer 0 mode register. TC0M = Timer/Counter 0 mode register.
T0C = Timer 0 counting register. TC0C = Timer/Counter 0 counting register.
TC1M = Timer/Counter 1 mode register. TC0R = Timer/Counter 0 auto-reload data buffer.
TC1C = Timer/Counter 1 counting register. TC1R = Timer/Counter 1 auto-reload data buffer.
STKP = Stack pointer buffer. STK0~STK7 = Stack 0 ~ stack 7 buffer.
@HL = RAM HL indirect addressing index pointer. @YZ = RAM YZ indirect addressing index pointer.
P4CON= Port 4 configuration setting
- - - - - - - - - - -
WDTR
TC0R PCL PCH
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER
Address 080H ~ 09FH
Addr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Register Name
080H LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 R/W L
081H HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBIT0 R/W H
082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 R/W R
083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R/W Z
084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R/W Y
085H XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0 R/W X
086H NT0 NPD C DC Z R/W PFLAG
087H RBNKS0 R/W RBANK
088H
089H
08AH
08BH
08CH
08DH
08EH
08FH
090H CKE D_A P S RED_WRT BF R MSPSTAT
091H WCOL MSPOV MSPENB CKP SLRXCKP MSPWK - MSPC R/W MSPM1
092H GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN R/W MSPM2
093H MSPBUF7 MSPBUF6 MSPBUF5 MSPBUF4 MSPBUF3 MSPBUF2 MSPBUF1 MSPBUF0 R/W MSPBUF
094H MSPADR7 MSPADR6 MSPADR5 MSPADR4 MSPADR3 MSPADR2 MSPADR1 MSPADR0 R/W MSPADR
095H
096H
097H
098H
099H
09AH
09BH
09CH
09DH
09EH
09FH
Address 0A0H ~ 0BFH
Addr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Register Name
0A0H
0A1H
0A2H
0A3H
0A4H
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
0A5H
0A6H
0A7H
0A8H
0A9H
0AAH
0ABH
0ACH
0ADH
0AEH P4CON7 P4CON6 P4CON5 P4CON4 P4CON3 P4CON2 P4CON1 P4CON0 W P4CON
0AFH
0B0H DAENB DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0 R/W DAM
0B1H ADENB ADS EOC GCHS - CHS2 CHS1 CHS0 R/W ADM
0B2H ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 R ADB
0B3H ADCKS2 ADCKS1 ADLEN ADCKS0 ADB3 ADB2 ADB1 ADB0 R/W ADR
0B4H SENB START SRATE1 SRATE0 MLSB SCKMD CPOL CPHA R/W SIOM
0B5H SIOR7 SIOR6 SIOR5 SIOR4 SIOR3 SIOR2 SIOR1 SIOR0 W SIOR
0B6H SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOB0 R/W SIOB
0B7H
0B8H P02M P01M P00M R/W P0M
0B9H
0BAH
0BBH
0BCH
0BDH
0BEH
0BFH P02G1 P02G0 P01G1 P01G0 P00G1 P00G0 R/W PEDGE
Address 0C0H ~ 0DFH
Addr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Register Name
0C0H P17W P16W P15W P14W P13W P12W P11W P10W W P1W
0C1H P17M P16M P15M P14M P13M P12M P11M P10M R/W P1M
0C2H P27M P26M P25M P24M P23M P22M P21M P20M R/W P2M
0C3H - - - - - P32M P31M P30M R/W P3M
0C4H P47M P46M P45M P44M P43M P42M P41M P40M R/W P4M
0C5H P57M P56M P55M P54M P53M P52M P51M P50M R/W P5M
0C6H MSPIRQ R/W INTRQ_1
0C7H MSPIEN R/W INTEN_1
0C8H ADCIRQ TC1IRQ TC0IRQ T0IRQ SIOIRQ P02IRQ P01IRQ P00IRQ R/W INTRQ
0C9H ADCIEN TC1IEN TC0IEN T0IEN SIOIEN P02IEN P01IEN P00IEN R/W INTEN
0CAH CPUM1 CPUM0 CLKMD STPHX R/W OSCM
0CBH
0CCH WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W WDTR
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R
0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W PCL
0CFH PC11 PC10 PC9 PC8 R/W PCH
0D0H P02 P01 P00 R/W P0
0D1H P17 P16 P15 P14 P13 P12 P11 P10 R/W P1
0D2H P27 P26 P25 P24 P23 P22 P21 P20 R/W P2
0D3H P33 P32 P31 P30 R/W P3
0D4H P47 P46 P45 P44 P43 P42 P41 P40 R/W P4
0D5H P57 P56 P55 P54 P53 P52 P51 P50 R/W P5
0D6H
0D7H
0D8H T0ENB T0rate2 T0rate1 T0rate0 TC1X8 TX0X8 T0TB R/W T0M
0D9H T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R/W T0C
0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 TC0CKS ALOAD0 TC0OUT PWM0OUT R/W TC0M
0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 R/W TC0C
0DCH TC1ENB TC1rate2 TC1rate1 TC1rate0 TC1CKS ALOAD1 TC1OUT PWM1OUT R/W TC1M
0DDH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 R/W TC1C
0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R
0DFH GIE STKPB2 STKPB1 STKPB0 R/W STKP
Address 0E0H ~ 0FFH
Addr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Register Name
0E0H - P02R P01R P00R W P0UR
0E1H P17R P16R P15R P14R P13R P12R P11R P10R W P1UR
0E2H P27R P26R P25R P24R P23R P22R P21R P20R W P2UR
0E3H P32R P31R P30R W P3UR
0E4H P47R P46R P45R P44R P43R P42R P41R P40R W P4UR
0E5H P57R P56R P55R P54R P53R P52R P51R P50R W P5UR
0E6H @HL7 @HL6 @HL5 @HL4 @HL3 @HL2 @HL1 @HL0 R/W @HL
0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 R/W @YZ
0E8H
0E9H P52OC P11OC P10OC W P1OC
0EAH
0EBH
0ECH
0EDH
0EEH
0EFH
0F0H S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 R/W STK7L
0F1H S7PC11 S7PC10 S7PC9 S7PC8 R/W STK7H
0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 R/W STK6L
0F3H S6PC11 S6PC10 S6PC9 S6PC8 R/W STK6H
0F4H S5PC7 S5PC6 S5PC5 S5PC4 S5PC3 S5PC2 S5PC1 S5PC0 R/W STK5L
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0F5H S5PC11 S5PC10 S5PC9 S5PC8 R/W STK5H
0F6H S4PC7 S4PC6 S4PC5 S4PC4 S4PC3 S4PC2 S4PC1 S4PC0 R/W STK4L
0F7H S4PC11 S4PC10 S4PC9 S4PC8 R/W STK4H
0F8H S3PC7 S3PC6 S3PC5 S3PC4 S3PC3 S3PC2 S3PC1 S3PC0 R/W STK3L
0F9H S3PC11 S3PC10 S3PC9 S3PC8 R/W STK3H
0FAH S2PC7 S2PC6 S2PC5 S2PC4 S2PC3 S2PC2 S2PC1 S2PC0 R/W STK2L
0FBH S2PC11 S2PC10 S2PC9 S2PC8 R/W STK2H
0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R/W STK1L
0FDH S1PC12 S1PC11 S1PC10 S1PC9 S1PC8 R/W STK1H
0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R/W STK0L
0FFH S0PC11 S0PC10 S0PC9 S0PC8 R/W STK0H
Note:
1. To avoid system error, make sure to put all the “0” and “1” as it indicates in the above table.
2. All of register names had been declared in SN8ASM assembler.
3. One-bit name had been declared in SN8ASM assembler with “F” prefix code.
4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers.
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2.1.4.4 ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
¾ Example: Read and write ACC value.
; Read ACC data and store in BUF data memory
MOV BUF, A
; Write a immediate data into ACC
MOV A, #0FH
; Write ACC data from BUF data memory
MOV A, BUF
The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to
other data memories. “PUSH”, “POP” save and load 0x80~0x87 system registers data into buffers. Users have to save
ACC data by program.
¾ Example: Protect ACC and working registers.
.DATA ACCBUF DS 1 ; Define ACCBUF for store ACC data.
.CODE
INT_SERVICE:
B0XCH A, ACCBUF ; Save ACC to buffer.
PUSH ; Save PFLAG and working registers to buffer.
… .
…
POP ; Load PFLAG and working registers form buffers.
RETI ; Exit interrupt service vector
Note: To save and re-load ACC data, users must use “B0XCH” instruction, or else the PFLAG
B0XCH A, ACCBUF ; Load ACC form buffer.
Register might be modified by ACC operation.
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2.1.4.5 PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.
NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and
watchdog reset. C, DC, Z bits indicate the result status of ALU operation.
086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PFLAG
Read/Write R/W R/W - - - R/W R/W R/W
After reset - - - - - 0 0 0
Bit [7:6] NT0, NPD: Reset status flag.
Bit 2 C: Carry flag
Bit 1 DC: Decimal carry flag
Bit 0 Z: Zero flag
Note: Refer to instruction set table for detailed information of C, DC and Z flags.
NT0 NPD - - - C DC Z
NT0 NPD Reset Status
0 0 Watch-dog time out
0 1 Reserved
1 0 Reset by LVD
1 1 Reset by external Reset Pin
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result
≥ 0.
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison
result < 0.
1 = Addition with carry from low nibble, subtraction without borrow from high nibble.
0 = Addition without carry from low nibble, subtraction with borrow from high nibble.
1 = The result of an arithmetic/logic/branch operation is zero.
0 = The result of an arithmetic/logic/branch operation is not zero.
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2.1.4.6 PROGRAM COUNTER
The program counter (PC) is a 12-bit binary counter separated into the high-byte 4 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 11.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PC
After
reset
) ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
JMP C0STEP ; Else jump to C0STEP.
…
…
C0STEP: NOP
B0MOV A, BUF0 ; Move BUF0 value to ACC.
JMP C1STEP ; Else jump to C1STEP.
…
…
C1STEP: NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
JMP C0STEP ; Else jump to C0STEP.
…
…
C0STEP: NOP
- - - - PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
- - - - 0 0 0 0 0 0 0 0 0 0 0 0
PCH PCL
B0BTS1
B0BTS0
CMPRS
FC ; To skip, if Carry_flag = 1
FZ ; To skip, if Zero flag = 0.
A, #12H ; To skip, if ACC = 12H.
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If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
JMP C0STEP ; Jump to C0STEP if ACC is not zero.
…
…
C0STEP: NOP
INCMS instruction:
JMP C0STEP ; Jump to C0STEP if BUF0 is not zero.
…
…
C0STEP: NOP
If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next
instruction.
DECS instruction:
JMP C0STEP ; Jump to C0STEP if ACC is not zero.
…
…
C0STEP: NOP
DECMS instruction:
JMP C0STEP ; Jump to C0STEP if BUF0 is not zero.
…
…
C0STEP: NOP
INCS
INCMS
DECS
DECMS
BUF0
BUF0
BUF0
BUF0
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) MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate
multi-address jumping function. Program Counter supports “ADD M,A”, ”ADC M,A” and “B0ADD M,A” instructions
for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value
by the three instructions and don’t care PCL overflow problem.
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
¾ Example: If PC = 0323H (PCH = 03H, PCL = 23H)
; PC = 0323H
MOV A, #28H
B0MOV PCL, A ; Jump to address 0328H
…
; PC = 0328H
MOV A, #00H
B0MOV PCL, A ; Jump to address 0300H
…
¾ Example: If PC = 0323H (PCH = 03H, PCL = 23H)
; PC = 0323H
B0ADD PCL, A ; PCL = PCL + ACC, the PCH cannot be changed.
JMP A0POINT ; If ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
…
…
2.1.4.7 H, L REGISTERS
The H and L registers are the 8-bit buffers. There are two major functions of these registers.
z can be used as general working registers
z can be used as RAM data pointers with @HL register
081H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
H
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset X X X X X X X X
080H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
L
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset X X X X X X X X
Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode to
HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBIT0
LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0
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access data as following.
B0MOV H, #00H ; To set RAM bank 0 for H register
B0MOV L, #20H ; To set location 20H for L register
B0MOV A, @HL ; To read a data into ACC
Example: Clear general-purpose data memory area of bank 0 using @HL register.
CLR H ; H = 0, bank 0
B0MOV L, #07FH ; L = 7FH, the last address of the data memory area
CLR_HL_BUF:
CLR @HL ; Clear @HL to be zero
DECMS L ; L – 1, if L = 0, finish the routine
JMP CLR_HL_BUF ; Not zero
CLR @HL
END_CLR: ; End of clear general purpose data memory area of bank 0
…
…
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2.1.4.8 Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
z can be used as general working registers
z can be used as RAM data pointers with @YZ register
z can be used as ROM data pointer with the MOVC instruction for look-up table
084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Y
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset - - - - - - - -
083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Z
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset - - - - - - - -
Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.
B0MOV Y, #00H ; To set RAM bank 0 for Y register
B0MOV Z, #25H ; To set location 25H for Z register
B0MOV A, @YZ ; To read a data into ACC
Example: Uses the Y, Z register as data pointer to clear the RAM data.
B0MOV Y, #0 ; Y = 0, bank 0
B0MOV Z, #07FH ; Z = 7FH, the last address of the data memory area
CLR_YZ_BUF:
CLR @YZ ; Clear @YZ to be zero
DECMS Z ; Z – 1, if Z= 0, finish the routine
JMP CLR_YZ_BUF ; Not zero
CLR @YZ
END_CLR: ; End of clear general purpose data memory area of bank 0
…
YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0
ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0
2.1.4.9
X register is an 8-bit buffer. There are two major functions of the register.
z can be used as general working registers
z can be used as ROM data pointer with the MOVC instruction for look-up table
085H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about X register look-up table application.
X REGISTERS
X
XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0
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2.1.4.10 R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register.
z Can be used as working register
z For store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset - - - - - - - -
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0
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2.2 ADDRESSING MODE
2.2.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.
¾ Example: Move the immediate data 12H to ACC.
MOV A, #12H ; To set an immediate data 12H into ACC.
¾ Example: Move the immediate data 12H to R register.
B0MOV R, #12H ; To set an immediate data 12H into R register.
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.
2.2.2 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.
¾ Example: Move 0x12 RAM location data into ACC.
B0MOV A, 12H ; To get a content of RAM location 0x12 of bank 0 and save in
ACC.
¾ Example: Move ACC data into 0x12 RAM location.
B0MOV 12H, A ; To get a content of ACC and save in RAM location 12H of
bank 0.
2.2.3 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (H/L, Y/Z).
Example: Indirectly addressing mode with @HL register
B0MOV H, #0 ; To clear H register to access RAM bank 0.
B0MOV L, #12H ; To set an immediate data 12H into L register.
B0MOV A, @HL ; Use data pointer @HL reads a data from RAM location
; 012H into ACC.
Example: Indirectly addressing mode with @YZ register
B0MOV Y, #0 ; To clear Y register to access RAM bank 0.
B0MOV Z, #12H ; To set an immediate data 12H into Z register.
B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
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2.3 STACK OPERATION
2.3.1 OVERVIEW
The stack buffer has 8-level. These buffers are designed to push and pop up program counter’s (PC) data when
interrupt service routine and “CALL” instruction are executed. The STKP register is a pointer designed to point active
level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program
counter (PC) data.
RET /
RETI
CALL /
INTERRUPT
PCH
PCL
STACK Level
STKP - 1STKP + 1
STKP = 7
STKP = 6
STKP = 5
STKP
STKP = 4
STKP = 3
STKP = 2
STKP = 1
STKP = 0
STACK Buffer
High Byte
STK7H
STK6H
STK5H
STKP
STK4H
STK3H
STK2H
STK1H
STK0H
STACK Buffer
Low Byte
STK7L
STK6L
STK5L
STK4L
STK3L
STK2L
STK1L
STK0L
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2.3.2 STACK REGISTERS
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 12-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses.
The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push
operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to
the top address of stack buffer and write the last program counter value (PC) into the stack buffer.
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STKP
Read/Write R/W - - - - R/W R/W R/W
After reset 0 - - - - 1 1 1
Bit[2:0] STKPBn: Stack pointer (n = 0 ~ 2)
Bit 7 GIE: Global interrupt control bit.
0 = Disable.
1 = Enable. Please refer to the interrupt chapter.
¾ Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointer in the
beginning of the program.
MOV A, #00000111B
B0MOV STKP, A
0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STKnH
Read/Write - - - - R/W R/W R/W R/W
After reset - - - - 0 0 0 0
0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STKnL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
STKn = STKnH , STKnL (n = 7 ~ 0)
GIE - - - - STKPB2 STKPB1 STKPB0
- - - - SnPC11 SnPC10 SnPC9 SnPC8
SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0
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2.3.3 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
Stack Level
STKPB2 STKPB1 STKPB0 High Byte Low Byte
0
1
2
3
4
5
6
7
8
> 8
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
STKPB2 STKPB1 STKPB0 High Byte Low Byte
8
7
6
5
4
3
2
1
0
STKP Register Stack Buffer
1 1 1 Free Free
1 1 0 STK0H STK0L
1 0 1 STK1H STK1L
1 0 0 STK2H STK2L
0 1 1 STK3H STK3L
0 1 0 STK4H STK4L
0 0 1 STK5H STK5L
0 0 0 STK6H STK6L
1 1 1 STK7H STK7L
1 1 0 - -
STKP Register Stack Buffer
1 1 1 STK7H STK7L
0 0 0 STK6H STK6L
0 0 1 STK5H STK5L
0 1 0 STK4H STK4L
0 1 1 STK3H STK3L
1 0 0 STK2H STK2L
1 0 1 STK1H STK1L
1 1 0 STK0H STK0L
1 1 1 Free Free
Description
Stack Over, error
Description
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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3
3
3
RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
z Power on reset
z Watchdog reset
z Brown out reset
z External reset
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PFLAG
Read/Write R/W R/W - - - R/W R/W R/W
After reset - - - - - 0 0 0
Bit [7:6] NT0, NPD: Reset status flag.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
NT0 NPD - - - C DC Z
NT0 NPD Condition Description
0 0 Watchdog reset Watchdog timer overflow.
0 1 Reserved 1 0 Power on reset and LVD reset. Power voltage is lower than LVD detecting level.
1 1 External reset External reset pin detect low level status.
VDD
Power
External Reset
Watchdog Reset
System Status
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VSS
VDD
VSS
Watchdog Normal Run
Watchdog Stop
System Normal Run
System Stop
LVD Detect Level
Power On
Delay Time
External Reset
Low Detect
External Reset
High Detect
External
Reset Delay
Time
Watchdog
Overflow
Watchdog
Reset Delay
Time
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3.2 POWER ON RESET
The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising
curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.
z Power-up: System detects the power voltage up and waits for power stable.
z External reset: System checks external reset pin status. If external reset pin is not high level, the system keeps
reset status and waits external reset pin released.
z System initialization: All system registers is set as initial conditions and system is ready.
z Oscillator warm up: Oscillator operation is successfully and supply to system clock.
z Program executing: Power on sequence is finished and program executes from ORG 0.
3.3 WATCHDOG RESET
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.
Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer
overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and
returns normal mode. Watchdog reset sequence is as following.
z Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
z System initialization: All system registers is set as initial conditions and system is ready.
z Oscillator warm up: Oscillator operation is successfully and supply to system clock.
z Program executing: Power on sequence is finished and program executes from ORG 0.
Watchdog timer application note is as following.
z Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
z Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
z Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
3.4 BROWN OUT RESET
3.4.1 BROWN OUT DESCRIPTION
The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external
factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well
or executing program error.
VDD
System Work
Well Area
V1
V2
VSS
Brown Out Reset Diagram
The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power
range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset
diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate
the system working area. The above area is the system work well area. The below area is the system work error area
called dead-band. V1 doesn’t touch the below area and not effect the system operation. But the V2 and V3 is under the
below area and may induce the system error occurrence. Let system under dead-band includes some conditions.
DC application:
The power source of DC application is usually using battery. When low battery condition and MCU drive any loading,
the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system
reset voltage. That makes the system under dead-band.
AC application:
In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC
noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating
induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power
situation.
The power on duration and power down duration are longer in AC application. The system power on sequence protects
the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power,
the VDD drops slowly and through the dead-band for a while.
V3
System Work
Error Area
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION
To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system
executing rate and power level. Different system executing rates have different system minimum operating voltage.
The electrical characteristic section shows the system voltage to executing rate relationship.
System Mini.
Vdd (V)
Normal Operating
Area
Operating Voltage.
Dead-Band Area
Reset Area
System Rate (Fcpu)
System Reset
Voltage.
Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is
decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even
higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system
reset voltage.
3.4.3 BROWN OUT RESET IMPROVEMENT
How to improve the brown reset condition? There are some methods to improve brown out reset as following.
z LVD reset
z Watchdog reset
z Reduce the system executing rate
z External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)
Note:
1. The “ Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can
completely improve the brown out reset, DC low battery and AC slow power down conditions.
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips)
and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset
IC”). The structure can improve noise effective and get good EFT characteristic.
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LVD reset:
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
Power
System Status
VDD
VSS
System Normal Run
System Stop
LVD Detect Voltage
Power is below LVD Detect
Voltage and System Reset.
Power On
Delay Time
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD can’t be the protection and need to other reset methods. More detail LVD information
is in the electrical characteristic section.
Watchdog reset:
The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear
at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the
watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t
be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of
watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method
also can improve brown out reset condition and make sure the system to return normal mode.
If the system reset by watchdog and the power is still in dead-band, the system reset sequence won’t be successful
and the system stays in reset status until the power return to normal range.
Reduce the system executing rate:
If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band.
The lower system rate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue
and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue.
This way needs to modify whole program timing to fit the application requirement.
External reset circuit:
The external reset methods also can improve brown out reset and is the complete solution. There are three external
reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External
reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under
power dropping and under dead-band. The external reset information is described in the next section.
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
3.5 EXTERNAL RESET
External reset pin is Schmitt Trigger structure and low level active. The system is running when reset pin is high level
voltage input. The reset pin receives the low voltage and the system is reset. The external reset operation actives in
power on and normal running mode. During system power-up, the external reset pin must be high level input, or the
system keeps in reset status. External reset sequence is as following.
z External reset: System checks external reset pin status. If external reset pin is not high level, the system keeps
reset status and waits external reset pin released.
z System initialization: All system registers is set as initial conditions and system is ready.
z Oscillator warm up: Oscillator operation is successfully and supply to system clock.
z Program executing: Power on sequence is finished and program executes from ORG 0.
The external reset can reset the system during power on duration, and good external reset circuit can protect the
system to avoid working at unusual power condition, e.g. brown out reset in AC power application…
3.6 EXTERNAL RESET CIRCUIT
3.6.1 Simply RC Reset Circuit
VDD
R1
47K ohm
R2
S
T
R
C1
100 ohm
0.1uF
This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into
reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from
the timing difference.
MCU
VSS
VCC
GND
Note: The reset circuit is no any protection against unusual power or brown out reset.
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3.6.2 Diode & RC Reset Circuit
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
VDD
C1
R1
47K ohm
R2
100 ohm
R
VSS
T
S
MCU
VCC
GND
DIODE
0.1uF
This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal.
The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct
higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can
improve slight brown out reset condition.
Note: The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to
limit any current flowing into reset pin from external capacitor C in the event of reset pin
breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).
3.6.3 Zener Diode Reset Circuit
VDD
R1
33K ohm
Vz
R2
10K ohm
The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition
completely. Use zener voltage to be the active level. When VDD voltage level is above “Vz + 0.7V”, the C terminal of
the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of
the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener
specification. Select the right zener voltage to conform the application.
B
R3
40K ohm
E
Q1
R
S
T
C
MCU
VSS
VCC
GND
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3.6.4 Voltage Bias Reset Circuit
R1
47K ohm
R2
10K ohm
B
R3
2K ohm
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
VDD
E
Q1
R
S
T
C
MCU
VSS
VCC
GND
The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely.
The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When
VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high
voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor
outputs low voltage and MCU is in reset mode.
Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the
circuit diagram condition, the MCU’s reset pin level varies with VDD voltage variation, and the differential voltage is
0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the
reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external
reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power
system, the current must be considered to whole system power consumption.
Note: Under unstable power condition as brown out reset, “Zener diode rest circuit” and “Voltage bias
reset circuit” can protects system no any error occurrence as power dropping. When power drops
below the reset detect voltage, the system reset would be triggered, and then system executes
reset sequence. That makes sure the system work well under unstable power situation.
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3.6.5 External Reset IC
VDD
Reset
Capacitor
IC
Bypass
0.1uF
RST
VDD
R
S
T
SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
MCU
VSS
VSS
VCC
GND
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good
effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can
improve all power variation.
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8-bit micro-controller build-in 12-bit ADC
4
4
4
SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is
generated from the external oscillator circuit or on-chip 16MHz high-speed RC oscillator circuit (IHRC 16MHz). The
low-speed clock is generated from on-chip low-speed RC oscillator circuit (ILRC 16KHz @3V, 32KHz @5V).
Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is
divided by 4 to be the instruction cycle (Fcpu).
) Normal Mode (High Clock): Fcpu = Fhosc / N, N = 1 ~ 128 Select N by Fcpu code option.
) Slow Mode (Low Clock): Fcpu = Flosc/4.
SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise
outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable.
4.2 CLOCK BLOCK DIAGRAM
STPHX HOSC
XIN
XOUT
z HOSC: High_Clk code option.
z Fhosc: External high-speed clock / Internal high-speed RC clock.
z Flosc: Internal low-speed RC clock (about 16KHz@3V, 32KHz@5V).
z Fosc: System clock source.
z Fcpu: Instruction cycle.
Fhosc.
CPUM[1:0]
Flosc. Fcpu = Flosc/4
Fcpu = Fhosc/1 ~ Fhosc/128, Noise Filter Disable.
Fcpu = Fhosc/4 ~ Fhosc/128, Noise Filter Enable.
Fcpu Code Option
CLKMD
Fosc
Fcpu
Fosc
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8-bit micro-controller build-in 12-bit ADC
4.3 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OSCM
Read/Write - - - R/W R/W R/W R/W -
After reset - - - 0 0 0 0 -
Bit 1 STPHX: External high-speed oscillator control bit.
0 = External high-speed oscillator free run.
1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running.
Bit 2 CLKMD: System high/Low clock mode control bit.
0 = Normal (dual) mode. System clock is high clock.
1 = Slow mode. System clock is internal low clock.
Bit[4:3] CPUM[1:0]: CPU operating mode control bits.
00 = normal.
01 = sleep (power down) mode.
10 = green mode.
11 = reserved.
¾ Example: Stop high-speed oscillator
B0BSET FSTPHX ; To stop external high-speed oscillator only.
¾ Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal
low-speed oscillator will be stopped.
B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
- - - CPUM1 CPUM0 CLKMD STPHX -
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8-bit micro-controller build-in 12-bit ADC
4.4 SYSTEM HIGH CLOCK
The system high clock is from internal 16MHz oscillator RC type or external oscillator. The high clock type is controlled
by “High_Clk” code option.
High_Clk Code Option Description
IHRC_16M
IHRC_RTC
RC The high clock is external RC type oscillator. XOUT pin is general purpose I/O pin.
32K The high clock is external 32768Hz low speed oscillator.
12M The high clock is external high speed oscillator. The typical frequency is 12MHz.
4M The high clock is external oscillator. The typical frequency is 4MHz.
4.4.1 INTERNAL HIGH RC
The chip is built-in RC type internal high clock (16MHz) controlled by “IHRC_16M” or “IHRC_RTC” code options. In
“IHRC_16M” mode, the system clock is from internal 16MHz RC type oscillator and XIN / XOUT pins are
general-purpose I/O pins. In “IHRC_RTC” mode, the system clock is from internal 16MHz RC type oscillator and XIN /
XOUT pins are connected with external 32768 crystal for real time clock (RTC).
z IHRC: High clock is internal 16MHz oscillator RC type. XIN/XOUT pins are general purpose I/O pins.
z IHRC_RTC: High clock is internal 16MHz oscillator RC type. XIN/XOUT pins are connected with external
32768Hz crystal/ceramic oscillator for RTC clock source.
The RTC period is controlled by OPTION register and RTC timer is T0. Please consult “T0 Timer” chapter to apply
RTC function.
4.4.2 EXTERNAL HIGH CLOCK
External high clock includes three modules (Crystal/Ceramic, RC and external clock signal). The high clock oscillator
module is controlled by High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different.
RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time
length.
4MHz Crystal
The high clock is internal 16MHz oscillator RC type. XIN and XOUT pins are general
purpose I/O pins.
The high clock is internal 16MHz oscillator RC type. XIN and XOUT pins connect
with 32768Hz crystal for RTC clock source.
RC
32768Hz Crystal
4MHz Ceramic
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
4.4.2.1 CRYSTAL/CERAMIC
Crystal/Ceramic devices are driven by XIN, XOUT pins. For high/normal/low frequency, the driving currents are
different. High_Clk code option supports different frequencies. 12M option is for high speed (ex. 12MHz). 4M option is
for normal speed (ex. 4MHz). 32K option is for low speed (ex. 32768Hz).
XIN
CRYSTAL
C
20pF
C
20pF
O
X
T
U
MCU
VDD
VSS
VCC
GND
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of
micro-controller.
4.4.2.2 RC
Selecting RC oscillator is by RC option of High_Clk code option. RC type oscillator’s frequency is up to 10MHz. Using
“R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin.
T
U
O
X
XIN
MCU
C
R
V
VSS
D
D
VCC
GND
Note: Connect the R and C as near as possible to the VDD pin of micro-controller.
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
4.4.2.3 EXTERNAL CLOCK SIGNAL
Selecting external clock signal input to be system clock is by RC option of High_Clk code option. The external clock
signal is input from XIN pin. XOUT pin is general purpose I/O pin.
External Clock Input
XIN
XOUT
MCU
VSS
VDD
VCC
GND
Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller.
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SN8P275X Series
8-bit micro-controller build-in 12-bit ADC
4.5 SYSTEM LOW CLOCK
The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator
uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common
condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relation between the RC
frequency and voltage is as the following figure.
Internal Low RC Frequency
45.00
40.00
35.00
30.00
25.00
20.00
15.00
Freq. (KHz)
10.00
5.00
0.00
2.12.533.13.33.544.555.566.57
7.52
10.64
14.72
16.00
17.24
18.88
22.24
25.96
29.20
32.52
35.40
38.08
40.80
ILRC
VDD (V)
The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD.
) Flosc = Internal low RC oscillator (about 16KHz @3V, 32KHz @5V).
) Slow mode Fcpu = Flosc / 4
There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 32K mode
and watchdog disable. If system is in 32K mode and watchdog disable, only 32K oscillator actives and system is under
low power consumption.
¾ Example: Stop internal low-speed oscillator by power down mode.
B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1
(32K, watchdog disable) bits of OSCM register.
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8-bit micro-controller build-in 12-bit ADC
4.5.1 SYSTEM CLOCK MEASUREMENT
Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is
useful in RC mode.
¾ Example: Fcpu instruction cycle of external oscillator.
B0BSET P0M.0 ; Set P0.0 to be output mode for outputting Fcpu toggle signal.
@@:
B0BSET P0.0 ; Output Fcpu toggle signal in low-speed clock mode.
B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope.
JMP @B
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
frequency.
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8-bit micro-controller build-in 12-bit ADC
5
5
5
SYSTEM OPERATION MODE
5.1 OVERVIEW
The chip is featured with low power consumption by switching around four different modes as following.
z Normal mode (High-speed mode)
z Slow mode (Low-speed mode)
z Power-down mode (Sleep mode)
z Green mode
Power Down Mode
(Sleep Mode)
P0, P1 Wake-up Function Active.
External Reset Circuit Active.
CPUM1, CPUM0 = 01.
CLKMD = 1
Normal Mode
P0, P1 Wake-up Function Active.
External Reset Circuit Active.
Operating mode description
EHOSC: External high clock
ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V)
T0 Timer Time Out.
System Mode Switching Diagram
MODE NORMAL SLOW GREEN
EHOSC Running By STPHX By STPHX Stop
ILRC Running Running Running Stop
CPU instruction Executing Executing Stop Stop
T0 timer *Active *Active *Active Inactive * Active if T0ENB=1
TC0 timer *Active *Active *Active Inactive * Active if TC0ENB=1
TC1 timer *Active *Active *Active Inactive * Active if TC1ENB=1
Watchdog timer
Internal interrupt All active All active T0, TC0 All inactive
External interrupt All active All active All active All inactive
Wakeup source - -
By Watch_Dog
Code option
By Watch_Dog
Code option
CLKMD = 0
CPUM1, CPUM0 = 10.
Green Mode
By Watch_Dog
Code option
P0, P1, T0
Reset
Slow Mode
P0, P1 Wake-up Function Active.
T0 Timer Time Out.
External Reset Circuit
Active.
POWER DOWN
(SLEEP)
By Watch_Dog
Code option
P0, P1, Reset
Refer to code option
REMARK
description
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8-bit micro-controller build-in 12-bit ADC
5.2 SYSTEM MODE SWITCHING
¾ Example: Switch normal/slow mode to power down (sleep) mode.
B0BSET FCPUM0 ; Set CPUM0 = 1.
Note: During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.
¾ Example: Switch normal mode to slow mode.
B0BSET FCLKMD ;To set CLKMD = 1, Change the system into slow mode
B0BSET FSTPHX ;To stop external high-speed oscillator for power saving.
¾ Example: Switch slow mode to normal mode (The external high-speed oscillator is still running)
B0BCLR FCLKMD ;To set CLKMD = 0
¾ Example: Switch slow mode to normal mode (The external high-speed oscillator stops)
If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 20ms for
external clock stable.
B0BCLR FSTPHX ; Turn on the external high-speed oscillator.
B0MOV Z, #54 ; If VDD = 5V, internal RC=32KHz (typical) will delay
@@: DECMS Z ; 0.125ms X 162 = 20.25ms for external clock stable
JMP @B
B0BCLR FCLKMD ; Change the system back to the normal mode
¾ Example: Switch normal/slow mode to green mode.
B0BSET FCPUM1 ; Set CPUM1 = 1.
Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can
wakeup the system backs to the previous operation mode.
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8-bit micro-controller build-in 12-bit ADC
¾ Example: Switch normal/slow mode to Green mode and enable T0 wakeup function.
; Set T0 timer wakeup function.
B0BCLR FT0IEN ; To disable T0 interrupt service
B0BCLR FT0ENB ; To disable T0 timer
MOV A,#20H ;
B0MOV T0M,A ; To set T0 clock = Fcpu / 64
MOV A,#74H
B0MOV T0C,A ; To set T0C initial value = 74H (To set T0 interval = 10 ms)
; Go into green mode
B0BCLR FCPUM0 ;To set CPUMx = 10
B0BSET FCPUM1
Note: During the green mode with T0 wake-up function, the wakeup pins, reset pin and T0 can wakeup
the system back to the last mode. T0 wake-up period is controlled by program and T0ENB must be set.
B0BCLR FT0IEN ; To disable T0 interrupt service
B0BCLR FT0IRQ ; To clear T0 interrupt request
B0BSET FT0ENB ; To enable T0 timer
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5.3 WAKEUP
5.3.1 OVERVIEW
Under power down mode (sleep mode) or green mode, program doesn’t execute. The wakeup trigger can wake the
system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0, P1 level change) and
internal trigger (T0 timer overflow).
z Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change)
z Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger (P0,
P1 level change) and internal trigger (T0 timer overflow).
5.3.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power
down mode, MCU waits for 4096 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit.
After the wakeup time, the system goes into the normal mode.
Note: Wakeup from green mode is no wakeup time because the clock doesn’t stop in green mode.
The value of the wakeup time is as the following.
The Wakeup time = 1/Fosc * 4096 (sec) + high clock start-up time
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
¾ Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system
goes into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 4096 = 1.024 ms (Fosc = 4MHz)
The total wakeup time = 1.024ms + oscillator start-up time
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5.3.3 P1W WAKEUP CONTROL REGISTER
Under power down mode (sleep mode) and green mode, the I/O ports with wakeup function are able to wake the
system up to normal mode. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function always enables, but
the Port 1 is controlled by the P1W register.
0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1W
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
Bit[7:0] P10W~P17W: Port 1 wakeup function control bits.
P17W P16W P15W P14W P13W P12W P11W P10W
0 = Disable P1n wakeup function.
1 = Enable P1n wakeup function.
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6
6
6
6.1 OVERVIEW
This MCU provides nine interrupt sources, including six internal interrupt (T0/TC0/TC1/SIO/ADC/MSP) and three
external interrupt (INT0/INT1/INT2). The external interrupt can wakeup the chip while the system is switched from
power down mode to high-speed normal mode, and interrupt request is latched until return to normal mode. Once
interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt request. On the
contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. All of the interrupt
request signals are stored in INTRQ register.
INTERRUPT
Note: The GIE bit must enable during all interrupt operation.
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6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including three internal interrupts, two external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTEN
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit 0 P00IEN: External P0.0 interrupt (INT0) control bit.
Bit 1 P01IEN: External P0.1 interrupt (INT1) control bit.
Bit 2 P02IEN: External P0.2 interrupt (INT2) control bit.
Bit 3 SIOIEN: SIO interrupt control bit.
Bit 4 T0IEN: T0 timer interrupt control bit.
Bit 5 TC0IEN: TC0 timer interrupt control bit.
Bit 6 TC1IEN: TC1 timer interrupt control bit.
Bit 7 ADCIEN: ADC interrupt control bit.
0C7H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTEN_1
Read/Write - - - - - - - R/W
After Reset - - - - - - - 0
Bit 0 MSPIEN: MSP interrupt control bit..
ADCIEN TC1IEN TC0IEN T0IEN SIOIEN P02IEN P01IEN P00IEN
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
0 = Disable INT1 interrupt function.
1 = Enable INT1 interrupt function.
0 = Disable INT1 interrupt function.
1 = Enable INT1 interrupt function.
0 = Disable SIO interrupt function.
1 = Enable SIO interrupt function.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
0 = Disable TC0 interrupt function.
1 = Enable TC0 interrupt function.
0 = Disable TC1 interrupt function.
1 = Enable TC1 interrupt function.
0 = Disable ADC interrupt function.
1 = Enable ADC interrupt function.
- - - - - - - MSPIEN
0 = Disable
1 = Enable
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6.3 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTRQ
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit 0 P00IRQ: External P0.0 interrupt (INT0) request flag.
Bit 1 P01IRQ: External P0.1 interrupt (INT1) request flag.
Bit 2 P02IRQ: External P0.2 interrupt (INT2) request flag.
Bit 3 SIOIRQ: SIO interrupt request flag.
Bit 4 T0IRQ: T0 timer interrupt request flag.
Bit 5 TC0IRQ: TC0 timer interrupt request flag.
Bit 6 TC1IRQ: TC1 timer interrupt request flag.
Bit 7 ADCIRQ: ADC interrupt request flag.
0C6H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTRQ_1
Read/Write - - - - - - - R/W
After Reset - - - - - - - 0
Bit 0 MSPIRQ: MSP interrupt request bit.
ADCIRQ TC1IRQ TC0IRQ T0IRQ SIOIRQ P02IRQ P01IRQ P00IRQ
0 = None INT0 interrupt request.
1 = INT0 interrupt request.
0 = None INT1 interrupt request.
1 = INT1 interrupt request.
0 = None INT1 interrupt request.
1 = INT1 interrupt request.
0 = None SIO interrupt request.
1 = SIO interrupt request.
0 = None T0 interrupt request.
1 = T0 interrupt request.
0 = None TC0 interrupt request.
1 = TC0 interrupt request.
0 = None TC1 interrupt request.
1 = TC1 interrupt request.
0 = None ADC interrupt request.
1 = ADC interrupt request.
- - - - - - - MSPIRQ
0 = No Request.
1 = Request.
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6.4 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and
the stack add 1 level.
0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STKP
Read/Write R/W - - - - R/W R/W R/W
After reset 0 - - - - 1 1 1
Bit 7 GIE: Global interrupt control bit.
0 = Disable global interrupt.
1 = Enable global interrupt.
Example: Set global interrupt control bit (GIE).
B0BSET FGIE ; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
GIE - - - - STKPB2 STKPB1 STKPB0
6.5 PUSH, POP ROUTINE
When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save
ACC, PFLAG data. The chip includes “PUSH”, “POP” for in/out interrupt service routine. The two instructions save and
load ACC, PFLAG data into buffers and avoid main routine error after interrupt service routine finishing.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is an
unique buffer and only one level.
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine executed.
ORG 0
JMP START
ORG 8
JMP INT_SERVICE
ORG 10H
START:
…
INT_SERVICE:
PUSH ; Save ACC and PFLAG to buffers.
…
…
POP ; Load ACC and PFLAG from buffers.
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RETI ; Exit interrupt service vector
…
ENDP
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6.6 EXTERNAL INTERRUPT OPERATION (INT0~INT2)
Sonix provides 3 sets external interrupt sources in the micro-controller. INT0, INT1 and INT2 are external interrupt
trigger sources and build in edge trigger configuration function. When the external edge trigger occurs, the external
interrupt request flag will be set to “1” when the external interrupt control bit enabled. If the external interrupt control bit
is disabled, the external interrupt request flag won’t active when external edge trigger occurrence. When external
interrupt control bit is enabled and external interrupt edge trigger is occurring, the program counter will jump to the
interrupt vector (ORG 8) and execute interrupt service routine.
The external interrupt builds in wake-up latch function. That means when the system is triggered wake-up from power
down mode, the wake-up source is external interrupt source (P0.0, P0.1 or P0.2), and the trigger edge direction
matches interrupt edge configuration, the trigger edge will be latched, and the system executes interrupt service routine
fist after wake-up.
0BFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PEDGE
Read/Write - - R/W R/W R/W R/W R/W R/W
After reset - - 0 0 0 0 0 0
Bit[5:4] P02G[1:0]: INT2 edge trigger select bits.
00 = reserved,
01 = rising edge,
10 = falling edge,
11 = rising/falling bi-direction.
Bit[3:2] P01G[1:0]: INT1 edge trigger select bits.
00 = reserved,
01 = rising edge,
10 = falling edge,
11 = rising/falling bi-direction.
Bit[1:0] P00G[1:0]: INT0 edge trigger select bits.
00 = reserved,
01 = rising edge,
10 = falling edge,
11 = rising/falling bi-direction.
Example: Setup INT0 interrupt request and bi-direction edge trigger.
MOV A, #98H
B0MOV PEDGE, A ; Set INT0 interrupt trigger as bi-direction edge.
B0BSET FP00IEN ; Enable INT0 interrupt service
B0BCLR FP00IRQ ; Clear INT0 interrupt request flag
B0BSET FGIE ; Enable GIE
Example: INT0 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
- - P02G1 P02G0 P01G1 P01G0 P00G1 P00G0
B0BTS1 FP00IRQ ; Check P00IRQ
JMP EXIT_INT ; P00IRQ = 0, exit interrupt vector
B0BCLR FP00IRQ ; Reset P00IRQ
… ; INT0 interrupt service routine
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6.7 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the
T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the
trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the
operation under multi-interrupt situation.
¾ Example: T0 interrupt request setup.
B0BCLR FT0IEN ; Disable T0 interrupt service
B0BCLR FT0ENB ; Disable T0 timer
MOV A, #20H ;
B0MOV T0M, A ; Set T0 clock = Fcpu / 64
MOV A, #74H ; Set T0C initial value = 74H
B0MOV T0C, A ; Set T0 interval = 10 ms
B0BSET FT0IEN ; Enable T0 interrupt service
B0BCLR FT0IRQ ; Clear T0 interrupt request flag
B0BSET FT0ENB ; Enable T0 timer
B0BSET FGIE ; Enable GIE
Example: T0 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FT0IRQ ; Check T0IRQ
JMP EXIT_INT ; T0IRQ = 0, exit interrupt vector
B0BCLR FT0IRQ ; Reset T0IRQ
MOV A, #74H
B0MOV T0C, A ; Reset T0C.
… ; T0 interrupt service routine
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6.8 TC0 INTERRUPT OPERATION
When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the
TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾ Example: TC0 interrupt request setup.
B0BCLR FTC0IEN ; Disable TC0 interrupt service
B0BCLR FTC0ENB ; Disable TC0 timer
MOV A, #20H ;
B0MOV TC0M, A ; Set TC0 clock = Fcpu / 64
MOV A, #74H ; Set TC0C initial value = 74H
B0MOV TC0C, A ; Set TC0 interval = 10 ms
B0BSET FTC0IEN ; Enable TC0 interrupt service
B0BCLR FTC0IRQ ; Clear TC0 interrupt request flag
B0BSET FTC0ENB ; Enable TC0 timer
B0BSET FGIE ; Enable GIE
¾ Example: TC0 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FTC0IRQ ; Check TC0IRQ
JMP EXIT_INT ; TC0IRQ = 0, exit interrupt vector
B0BCLR FTC0IRQ ; Reset TC0IRQ
MOV A, #74H
B0MOV TC0C, A ; Reset TC0C.
… ; TC0 interrupt service routine
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6.9 TC1 INTERRUPT OPERATION
When the TC1C counter overflows, the TC1IRQ will be set to “1” no matter the TC1IEN is enable or disable. If the
TC1IEN and the trigger event TC1IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC1IEN = 0, the trigger event TC1IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC1IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: TC1 interrupt request setup.
B0BCLR FTC1IEN ; Disable TC1 interrupt service
B0BCLR FTC1ENB ; Disable TC1 timer
MOV A, #20H ;
B0MOV TC1M, A ; Set TC1 clock = Fcpu / 64
MOV A, #74H ; Set TC1C initial value = 74H
B0MOV TC1C, A ; Set TC1 interval = 10 ms
B0BSET FTC1IEN ; Enable TC1 interrupt service
B0BCLR FTC1IRQ ; Clear TC1 interrupt request flag
B0BSET FTC1ENB ; Enable TC1 timer
B0BSET FGIE ; Enable GIE
Example: TC1 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FTC1IRQ ; Check TC1IRQ
JMP EXIT_INT ; TC1IRQ = 0, exit interrupt vector
B0BCLR FTC1IRQ ; Reset TC1IRQ
MOV A, #74H
B0MOV TC1C, A ; Reset TC1C.
… ; TC1 interrupt service routine
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6.10 SIO INTERRUPT OPERATION
When the SIO converting successfully, the SIOIRQ will be set to “1” no matter the SIOIEN is enable or disable. If the
SIOIEN and the trigger event SIOIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
SIOIEN = 0, the trigger event SIOIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the SIOIEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾ Example: SIO interrupt request setup.
B0BSET FSIOIEN ; Enable SIO interrupt service
B0BCLR FSIOIRQ ; Clear SIO interrupt request flag
B0BSET FGIE ; Enable GIE
¾ Example: SIO interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FSIOIRQ ; Check SIOIRQ
JMP EXIT_INT ; SIOIRQ = 0, exit interrupt vector
B0BCLR FSIOIRQ ; Reset SIOIRQ
… ; SIO interrupt service routine
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6.11 ADC INTERRUPT OPERATION
When the ADC converting successfully, the ADCIRQ will be set to “1” no matter the ADCIEN is enable or disable. If the
ADCIEN and the trigger event ADCIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If
the ADCIEN = 0, the trigger event ADCIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector
even when the ADCIEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾ Example: ADC interrupt request setup.
B0BCLR FADCIEN ; Disable ADC interrupt service
MOV A, #10110000B ;
B0MOV ADM, A ; Enable P4.0 ADC input and ADC function.
MOV A, #00000000B ; Set ADC converting rate = Fcpu/16
B0MOV ADR, A
B0BSET FADCIEN ; Enable ADC interrupt service
B0BCLR FADCIRQ ; Clear ADC interrupt request flag
B0BSET FGIE ; Enable GIE
B0BSET FADS ; Start ADC transformation
¾ Example: ADC interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FADCIRQ ; Check ADCIRQ
JMP EXIT_INT ; ADCIRQ = 0, exit interrupt vector
B0BCLR FADCIRQ ; Reset ADCIRQ
… ; ADC interrupt service routine
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6.12 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
Interrupt Name Trigger Event Description
P00IRQ P0.0 trigger controlled by PEDGE
P01IRQ P0.1 trigger controlled by PEDGE
P02IRQ P0.2 trigger controlled by PEDGE
T0IRQ T0C overflow
TC0IRQ TC0C overflow
TC1IRQ TC1C overflow
SIOIRQ SIO transmitting end.
ADCIRQ ADC converting end.
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
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¾ Example: Check the interrupt request under multi-interrupt operation
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
INTP00CHK: ; Check INT0 interrupt request
B0BTS1 FP00IEN ; Check P00IEN
JMP INTP01CHK ; Jump check to next interrupt
B0BTS0 FP00IRQ ; Check P00IRQ
JMP INTP00
INTP01CHK: ; Check INT1 interrupt request
B0BTS1 FP00IEN ; Check P01IEN
JMP INTP02CHK ; Jump check to next interrupt
B0BTS0 FP01IRQ ; Check P01IRQ
JMP INTP01
INTP02CHK: ; Check INT2 interrupt request
B0BTS1 FP00IEN ; Check P02IEN
JMP INTT0CHK ; Jump check to next interrupt
B0BTS0 FP02IRQ ; Check P02IRQ
JMP INTP02
INTT0CHK: ; Check T0 interrupt request
B0BTS1 FT0IEN ; Check T0IEN
JMP INTTC0CHK ; Jump check to next interrupt
B0BTS0 FT0IRQ ; Check T0IRQ
JMP INTT0 ; Jump to T0 interrupt service routine
INTTC0CHK: ; Check TC0 interrupt request
B0BTS1 FTC0IEN ; Check TC0IEN
JMP INTTC1CHK ; Jump check to next interrupt
B0BTS0 FTC0IRQ ; Check TC0IRQ
JMP INTTC0 ; Jump to TC0 interrupt service routine
INTTC1CHK: ; Check T1 interrupt request
B0BTS1 FTC1IEN ; Check TC1IEN
JMP INTSIOHK ; Jump check to next interrupt
B0BTS0 FTC1IRQ ; Check TC1IRQ
JMP INTT1 ; Jump to TC1 interrupt service routine
INTSIOCHK: ; Check SIO interrupt request
B0BTS1 FSIOIEN ; Check SIOIEN
JMP INTADCHK ; Jump check to next interrupt
B0BTS0 FSIOIRQ ; Check SIOIRQ
JMP INTSIO ; Jump to SIO interrupt service routine
INTADCHK: ; Check ADC interrupt request
B0BTS1 FADCIEN ; Check ADCIEN
JMP INT_EXIT ; Jump to exit of IRQ
B0BTS0 FADCIRQ ; Check ADCIRQ
JMP INTADC ; Jump to ADC interrupt service routine
INT_EXIT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
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7
7
7
I/O PORT
7.1 I/O PORT MODE
The port direction is programmed by PnM register. All I/O ports can select input or output direction.
0B8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P0M
Read/Write - - - - - R/W R/W R/W
After reset - - - - - 0 0 0
0C1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1M
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
0C2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P2M
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
0C3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P3M
Read/Write - - - - - R/W R/W R/W
After reset - - - - - 0 0 0
0C4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P4M
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P5M
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit[7:0] PnM[7:0]: Pn mode control bits. (n = 0~5).
0 = Pn is input mode.
1 = Pn is output mode.
Note: Users can program them by bit control instructions (B0BSET, B0BCLR).
Note: If not used ADC function, AVDD must be connect with VDD, otherwise P4 I/O maybe ERROR.
- - - - - P02M P01M P00M
P17M P16M P15M P14M P13M P12M P11M P10M
P27M P26M P25M P24M P23M P22M P21M P20M
- - - - - P32M P31M P30M
P47M P46M P45M P44M P43M P42M P41M P40M
P57M P56M P55M P54M P53M P52M P51M P50M
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¾ Example: I/O mode selecting
CLR P0M ; Set all ports to be input mode.
CLR P4M
CLR P5M
MOV A, #0FFH ; Set all ports to be output mode.
B0MOV P0M, A
B0MOV P4M,A
B0MOV P5M, A
B0BCLR P4M.0 ; Set P4.0 to be input mode.
B0BSET P4M.0 ; Set P4.0 to be output mode.
SN8P275X Series
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7.2 I/O PULL UP REGISTER
0E0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P0UR
Read/Write - - - - - W W W
After reset - - - - - 0 0 0
0E1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1UR
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
0E2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P2UR
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
0E3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P3UR
Read/Write - - - - - W W W
After reset - - - - - 0 0 0
0E4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P4UR
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
0E5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P5UR
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
¾ Example: I/O Pull up Register
MOV A, #0FFH ; Enable Port0, 4, 5 Pull-up register,
B0MOV P0UR, A ;
B0MOV P4UR,A
B0MOV P5UR, A
- - - - - P02R P01R P00R
P17R P16R P15R P14R P13R P12R P11R P10R
P27R P26R P25R P24R P23R P22R P21R P20R
- - - - - P32R P31R P30R
P47R P46R P45R P44R P43R P42R P41R P40R
P57R P56R P55R P54R P53R P52R P51R P50R
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8-bit micro-controller build-in 12-bit ADC
7.3 I/O PORT DATA REGISTER
0D0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P0
Read/Write - - - - - R/W R/W R/W
After reset - - - - - 0 0 0
0D1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
0D2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
0D3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P3
Read/Write - - - - R/W R/W R/W R/W
After reset - - - - 0 0 0 0
0D4H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P4
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P5
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
¾ Example: Read data from input port.
B0MOV A, P0 ; Read data from Port 0
B0MOV A, P4 ; Read data from Port 4
B0MOV A, P5 ; Read data from Port 5
¾ Example: Write data to output port.
MOV A, #0FFH ; Write data FFH to all Port.
B0MOV P0, A
B0MOV P4, A
B0MOV P5, A
¾ Example: Write one bit data to output port.
B0BSET P4.0 ; Set P4.0 and P5.3 to be “1”.
B0BSET P5.3
B0BCLR P4.0 ; Set P4.0 and P5.3 to be “0”.
B0BCLR P5.3
- - - - - P02 P01 P00
P17 P16 P15 P14 P13 P12 P11 P10
P27 P26 P25 P24 P23 P22 P21 P20
- - - - P33 P32 P31 P30
P47 P46 P45 P44 P43 P42 P41 P40
P57 P56 P55 P54 P53 P52 P51 P50
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8-bit micro-controller build-in 12-bit ADC
7.4 I/O OPEN-DRAIN REGISTER
P1.0/P1.1/P5.2 is built-in open-drain function. P1.0/P1.1/P5.2 must be set as output mode when enable open-drain
function. Open-drain external circuit is as following.
MCU1
MCU2
U
VCC
Pull-up Resistor
Open-drain pin Open-drain pin
U
The pull-up resistor is necessary. Open-drain output high is driven by pull-up resistor. Output low is sunken by MCU’s
pin.
0E9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1OC
Read/Write - - - - - W W W
After reset - - - - - 0 0 0
Bit 2 P52OC: P5.2 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Bit 1 P11OC: P1.1 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Bit 0 P10OC: P1.0 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
¾ Example: Enable P1.0 to open-drain mode and output high.
B0BSET P1.0 ; Set P1.0 buffer high.
B0BSET P10M ; Enable P1.0 output mode.
MOV A, #01H ; Enable P1.0 open-drain function.
B0MOV P1OC, A
Note: P1OC is write only register. Setting P10OC must be used “MOV” instructions.
¾ Example: Disable P1.0 to open-drain mode and output low.
MOV A, #0 ; Disable P1.0 open-drain function.
B0MOV P1OC, A
Note: After disable open-drain function, I/O mode returns to last I/O mode.
- - - - -
P52OC P11OC P10OC
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8-bit micro-controller build-in 12-bit ADC
7.5 PORT 4 ADC SHARE PIN
The Port 4 is shared with ADC input function and no Schmitt trigger structure. Only one pin of port 4 can be configured
as ADC input in the same time by ADM register. The other pins of port 4 are digital I/O pins. Connect an analog signal
to COMS digital input pin, especially the analog signal level is about 1/2 VDD will cause extra current leakage. In the
power down mode, the above leakage current will be a big problem. Unfortunately, if users connect more than one
analog input signal to port 4 will encounter above current leakage situation. P4CON is Port4 Configuration register.
Write “1” into P4CON.n will configure related port 4 pin as pure analog input pin to avoid current leakage.
0AEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P4CON
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit[4:0] P4CON[7:0]: P4.n configuration control bits.
0 = P4.n can be an analog input (ADC input) or digital I/O pins.
1 = P4.n is pure analog input, can’t be a digital I/O pin.
Note: When Port 4.n is general I/O port not ADC channel, P4CON.n must set to “0” or the Port 4.n digital
I/O signal would be isolated.
Port 4 ADC analog input is controlled by GCHS and CHSn bits of ADM register. If GCHS = 0, P4.n is general purpose
bi-direction I/O port. If GCHS = 1, P4.n pointed by CHSn is ADC analog signal input pin. Users should set P4 ADC
input pin as input mode without pull-up.
0B1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADM
Read/Write R/W R/W R/W R/W - R/W R/W R/W
After reset 0 0 0 0 - 0 0 0
Bit 4 GCHS: Global channel select bit.
0 = Disable AIN channel.
1 = Enable AIN channel.
Bit[2:0] CHS[2:0]: ADC input channels select bit.
000 = AIN0, 001 = AIN1, … 110 = AIN6, 111 = AIN7.
Note: For P4.n general purpose I/O function, users should make sure of P4.n’s ADC channel is disabled.
P4CON7 P4CON6 P4CON5 P4CON4 P4CON3 P4CON2 P4CON1 P4CON0
ADENB ADS EOC GCHS - CHS2 CHS1 CHS0
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¾ Example: Set P4.1 to be general purpose input mode. P4CON.1 must be set as “0”.
; Check GCHS and CHS[2:0] status.
B0BCLR FGCHS
; Clear P4CON.
B0BCLR P4CON.1 ; Enable P4.1 digital function.
; Enable P4.1 input mode.
B0BCLR P4M.1 ; Set P4.1 as input mode.
¾ Example: Set P4.1 to be general purpose output. P4CON.1 must be set as “0”.
; Check GCHS and CHS[2:0] status.
B0BCLR FGCHS
; Clear P4CON.
B0BCLR P4CON.1 ; Enable P4.1 digital function.
; Set P4.1 output buffer to avoid glitch.
B0BSET P4.1 ; Set P4.1 buffer as “1”.
; or
B0BCLR P4.1 ; Set P4.1 buffer as “0”.
; Enable P4.1 output mode.
B0BSET P4M.1 ; Set P4.1 as input mode.
;If CHS[2:0] point to P4.1 (CHS[2:0] = 001B), set GCHS=0
;If CHS[2:0] don’t point to P4.1 (CHS[2:0] ≠ 001B), don’t
care GCHS status.
;If CHS[2:0] point to P4.1 (CHS[2:0] = 001B), set GCHS=0.
;If CHS[2:0] don’t point to P4.1 (CHS[2:0] ≠ 001B), don’t
care GCHS status.
SN8P275X Series
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8
8
8
TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator (16KHz @3V, 32KHz @5V).
Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).
VDD Internal Low RC Freq. Watchdog Overflow Time
3V 16KHz 512ms
5V 32KHz 256ms
Note:
1. If watchdog is “Always_On” mode, it keeps running event under power down mode or green
mode.
2. For S8KD ICE simulation, clear watchdog timer using “@RST_WDT” macro is necessary. Or
the S8KD watchdog would be error.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDTR
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
¾ Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
…
…
CALL SUB1
CALL SUB2
…
…
JMP MAIN
WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0
MOV A, #5AH ; Clear the watchdog timer.
B0MOV WDTR, A
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¾ Example: Clear watchdog timer by @RST_WDT macro.
Main:
@RST_WDT ; Clear the watchdog timer.
…
CALL SUB1
CALL SUB2
…
…
JMP MAIN
Watchdog timer application note is as following.
z Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
z Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
z Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top of the
main routine of the program.
Main:
… ; Check I/O.
… ; Check RAM
Err: JMP $ ; I/O or RAM error. Program jump here and don’t
; clear watchdog. Wait watchdog timer overflow to reset IC.
Correct: ; I/O and RAM are correct. Clear watchdog timer and
; execute program.
B0BSET FWDRST ; Only one clearing watchdog timer of whole program.
…
CALL SUB1
CALL SUB2
…
…
…
JMP MAIN
…
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8.2 TIMER 0 (T0)
8.2.1 OVERVIEW
The T0 is an 8-bit binary up timer and event counter. If T0 timer occurs an overflow (from FFH to 00H), it will continue
counting and issue a time-out signal to trigger T0 interrupt to request interrupt service.
The main purposes of the T0 timer is as following.
) 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
) RTC timer: Generates interrupts at real time intervals based on the selected clock source. RTC function is only
available in T0TB=1.
) Green mode wakeup function: T0 can be green mode wake-up time as T0ENB = 1. System will be wake-up by
T0 time out.
T0 Rate
(Fcpu/2~Fcpu/256)
T0ENB
Internal Data Bus
Fcpu
RTC
Load
T0C 8-Bit Binary Up Counting Counter
CPUM0,1
T0ENB
T0TB
¾ Note: In RTC mode, the T0 interval time is fixed at 0.5 sec and isn’t controlled by T0C.
T0 Time Out
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8.2.2 T0M MODE REGISTER
0D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T0M
Read/Write R/W R/W R/W R/W R/W R/W - R/W
After reset 0 0 0 0 0 0 - 0
Bit 0 T0TB: RTC clock source control bit.
Bit 2 TC0X8: TC0 internal clock source control bit.
Bit 3 TC1X8: TC1 internal clock source control bit.
Bit [6:4] T0RATE[2:0]: T0 internal clock select bits.
Bit 7 T0ENB: T0 counter control bit.
¾ Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec.
T0ENB T0rate2 T0rate1 T0rate0 TC1X8 TC0X8 - T0TB
0 = Disable RTC (T0 clock source from Fcpu).
1 = Enable RTC, T0 will be 0.5 sec RTC (Low clock must be 32768 cyrstal).
0 = TC0 internal clock source is Fcpu. TC0RATE is from Fcpu/2~Fcpu/256.
1 = TC0 internal clock source is Fosc. TC0RATE is from Fosc/1~Fosc/128.
0 = TC1 internal clock source is Fcpu. TC1RATE is from Fcpu/2~Fcpu/256.
1 = TC1 internal clock source is Fosc. TC1RATE is from Fosc/1~Fosc/128.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
0 = Disable T0 timer.
1 = Enable T0 timer.
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8.2.3 T0C COUNTING REGISTER
T0C is an 8-bit counter register for T0 interval time control.
0D9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T0C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
The equation of T0C initial value is as following.
¾ Example: To set 10ms interval time for T0 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select
T0RATE=010 (Fcpu/64).
The basic timer table interval time of T0.
T0RATE T0CLOCK
000 Fcpu/256 65.536 ms 256 us 2000 ms 7812.5 us
001 Fcpu/128 32.768 ms 128 us 1000 ms 3906.25 us
010 Fcpu/64 16.384 ms 64 us 500 ms 1953.12 us
011 Fcpu/32 8.192 ms 32 us 250 ms 976.56 us
100 Fcpu/16 4.096 ms 16 us 125 ms 488.28 us
101 Fcpu/8 2.048 ms 8 us 62.5 ms 244.14 us
110 Fcpu/4 1.024 ms 4 us 31.25 ms 122.07 us
111 Fcpu/2 0.512 ms 2 us 15.625 ms 61.035 us
¾ Note: T0C is not available in RTC mode. The T0 interval time is fixed at 0.5 sec.
T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0
T0C initial value = 256 - (T0 interrupt interval time * input clock)
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10
= 100
= 64H
High speed mode (Fcpu = 4MHz / 4) Low speed mode (Fcpu = 32768Hz / 1)
Max overflow interval One step = max/256 Max overflow interval One step = max/256
-2
* 4 * 106 / 4 / 64)
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8.2.4 T0 TIMER OPERATION SEQUENCE
T0 timer operation sequence of setup T0 timer is as following.
) Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag.
B0BCLR FT0ENB ; T0 timer.
B0BCLR FT0IEN ; T0 interrupt function is disabled.
B0BCLR FT0IRQ ; T0 interrupt request flag is cleared.
) Set T0 timer rate.
MOV A, #0xxx0000b ;The T0 rate control bits exist in bit4~bit6 of T0M. The
; value is from x000xxxxb~x111xxxxb.
B0MOV T0M,A ; T0 timer is disabled.
) Set T0 clock source from Fcpu or RTC.
B0BCLR FT0TB ; Select T0 Fcpu clock source.
or
B0BSET FT0TB ; Select T0 RTC clock source.
) Set T0 interrupt interval time.
) Set T0 timer function mode.
) Enable T0 timer.
MOV A,#7FH
B0MOV T0C,A ; Set T0C value.
B0BSET FT0IEN ; Enable T0 interrupt function.
B0BSET FT0ENB ; Enable T0 timer.
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8.3 TIMER/COUNTER 0 (TC0)
8.3.1 OVERVIEW
The TC0 is an 8-bit binary up counting timer. TC0 has two clock sources including internal clock and external clock for
counting a precision time. The internal clock source is from Fcpu. The external clock is INT0 from P0.0 pin (Falling
edge trigger). Using TC0M register selects TC0C’s clock source from internal or external. If TC0 timer occurs an
overflow, it will continue counting and issue a time-out signal to trigger TC0 interrupt to request interrupt service. TC0
overflow time is 0xFF to 0X00 normally. Under PWM mode, TC0 overflow is still 256 counts.
The main purposes of the TC0 timer is as following.
) 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
) External event counter: Counts system “events” based on falling edge detection of external clock signals at the
INT0 input pin.
) Buzzer output
) PWM output
Internal P5.4 I/O Circuit
ALOAD0
Auto. Reload
Buzzer
TC0 / 2
TC0OUT
P5.4
INT0
(Schmitter Trigger)
Fcpu
TC0 Rate
(Fcpu/2~Fcpu/256)
TC0CKS TC0ENB
CPUM0,1
TC0R Reload
Data Buffer
Load
TC0C
8-Bit Binary Up
Counting Counter
Compare
R
PWM
S
PWM0OUT
TC0 Time Out
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8.3.2 TC0M MODE REGISTER
0DAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC0M
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit 0 PWM0OUT: PWM output control bit.
Bit 1 TC0OUT: TC0 time out toggle signal output control bit. Only valid when PWM0OUT = 0.
0 = Disable, P5.4 is I/O function.
1 = Enable, P5.4 is output TC0OUT signal.
Bit 2 ALOAD0: Auto-reload control bit. Only valid when PWM0OUT = 0.
Bit 3 TC0CKS: TC0 clock source select bit.
Bit [6:4] TC0RATE[2:0]: TC0 internal clock select bits.
Bit 7 TC0ENB: TC0 counter control bit.
Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0
interrupt request will be raised. (P0.0IRQ will be always 0).
TC0ENB TC0rate2 TC0rate1 TC0rate0 TC0CKS ALOAD0 TC0OUT PWM0OUT
0 = Disable PWM output.
1 = Enable PWM output. PWM duty controlled by TC0OUT, ALOAD0 bits.
0 = Disable TC0 auto-reload function.
1 = Enable TC0 auto-reload function.
0 = Internal clock (Fcpu).
1 = External clock from P0.0/INT0 pin.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
0 = Disable TC0 timer.
1 = Enable TC0 timer.
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8.3.3 TC0C COUNTING REGISTER
TC0C is an 8-bit counter register for TC0 interval time control.
0DBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC0C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
The equation of TC0C initial value is as following.
¾ Example: To set 10ms interval time for TC0 interrupt. TC0 clock source is Fcpu (TC0KS=0). High clock is
external 4MHz. Fcpu=Fosc/4. Select TC0RATE=010 (Fcpu/64).
The basic timer table interval time of TC0.
TC0RATE TC0CLOCK
000 Fcpu/256 65.536 ms 256 us 8000 ms 31250 us
001 Fcpu/128 32.768 ms 128 us 4000 ms 15625 us
010 Fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us
011 Fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us
100 Fcpu/16 4.096 ms 16 us 500 ms 1953.125 us
101 Fcpu/8 2.048 ms 8 us 250 ms 976.563 us
110 Fcpu/4 1.024 ms 4 us 125 ms 488.281 us
111 Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us
Note: TC0C can’t be set as 0xFF when TC0 timer operating in interrupt, buzzer output modes. TC0C
available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode.
TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0
TC0C initial value = 256 - (TC0 interrupt interval time * input clock)
TC0C initial value = 256 - (TC0 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10
= 100
= 64H
High speed mode (Fcpu = 4MHz / 4) Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval One step = max/256 Max overflow interval One step = max/256
-2
* 4 * 106 / 4 / 64)
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8.3.4 TC0R AUTO-LOAD REGISTER
TC0 timer is with auto-load function controlled by ALOAD0 bit of TC0M. When TC0C overflow occurring, TC0R value
will load to TC0C by system. It is easy to generate an accurate time, and users don’t reset TC0C during interrupt
service routine.
0CDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC0R
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
The equation of TC0R initial value is as following.
N is TC0 overflow boundary number. TC0 timer overflow time has five types (TC0 timer, TC0 event counter, TC0 Fcpu
clock source, PWM mode and no PWM mode). These parameters decide TC0 overflow time and valid value as follow
table.
¾ Example: To set 10ms interval time for TC0 interrupt. TC0 clock source is Fcpu (TC0KS=0) and no PWM
output (PWM0=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC0RATE=010 (Fcpu/64).
Note: TC0R can’t be set as 0xFF when TC0 timer operating in interrupt, buzzer output modes. TC0R
available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode.
TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0
TC0R initial value = N - (TC0 interrupt interval time * input clock)
TC0CKS PWM0 ALOAD0 TC0OUT N
0 x x 256 0x00~0xFF 00000000b~11111111b
1 0 0 256 0x00~0xFF 00000000b~11111111b
0
1 - - - 256 0x00~0xFF 00000000b~11111111b
1 0 1 64 0x00~0x3F xx000000b~xx111111b
1 1 0 32 0x00~0x1F xxx00000b~xxx11111b
1 1 1 16 0x00~0x0F xxxx0000b~xxxx1111b
TC0R valid
value
TC0R value
binary type
TC0R initial value = N - (TC0 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
-2
= 256 - (10
* 4 * 106 / 4 / 64)
= 100
= 64H
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8.3.5 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)
Buzzer output (TC0OUT) is from TC0 timer/counter frequency output function. By setting the TC0 clock frequency, the
clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0OUT frequency is
divided by 2 from TC0 interval time. TC0OUT frequency is 1/2 TC0 frequency. The TC0 clock has many combinations
and easily to make difference frequency. The TC0OUT frequency waveform is as following.
1 2 3 4
TC1 Overflow Clock
1 2 3 4
TC1OUT (Buzzer) Output Clock
¾ Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The
TC0OUT frequency is 0.5KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 1KHz. The
TC0 clock source is from external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110.
TC0C = TC0R = 131.
MOV A,#01100000B
B0MOV TC0M,A ; Set the TC0 rate to Fcpu/4
MOV A,#131 ; Set the auto-reload reference value
B0MOV TC0C,A
B0MOV TC0R,A
B0BSET FTC0OUT ; Enable TC0 output to P5.4 and disable P5.4 I/O function
B0BSET FALOAD0 ; Enable TC0 auto-reload function
B0BSET FTC0ENB ; Enable TC0 timer
Note: Buzzer output is enabled, and “PWM0OUT” must be “0”.
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8.3.6 TC0 TIMER OPERATION SEQUENCE
TC0 timer operation includes timer interrupt, event counter, TC0OUT and PWM. The sequence of setup TC0 timer is
as following.
) Stop TC0 timer counting, disable TC0 interrupt function and clear TC0 interrupt request flag.
B0BCLR FTC0ENB ; TC0 timer, TC0OUT and PWM stop.
B0BCLR FTC0IEN ; TC0 interrupt function is disabled.
B0BCLR FTC0IRQ ; TC0 interrupt request flag is cleared.
) Set TC0 timer rate. (Besides event counter mode.)
MOV A, #0xxx0000b ;The TC0 rate control bits exist in bit4~bit6 of TC0M. The
; value is from x000xxxxb~x111xxxxb.
B0MOV TC0M,A ; TC0 timer is disabled.
) Set TC0 timer clock source.
; Select TC0 internal / external clock source.
B0BCLR FTC0CKS ; Select TC0 internal clock source.
or
B0BSET FTC0CKS ; Select TC0 external clock source.
) Set TC0 timer auto-load mode.
B0BCLR FALOAD0 ; Enable TC0 auto reload function.
or
B0BSET FALOAD0 ; Disable TC0 auto reload function.
) Set TC0 interrupt interval time, TC0OUT (Buzzer) frequency or PWM duty cycle.
; Set TC0 interrupt interval time, TC0OUT (Buzzer) frequency or PWM duty.
; In PWM mode, set PWM cycle.
or
or
or
MOV A,#7FH ; TC0C and TC0R value is decided by TC0 mode.
B0MOV TC0C,A ; Set TC0C value.
B0MOV TC0R,A ; Set TC0R value under auto reload mode or PWM mode.
B0BCLR FALOAD0 ; ALOAD0, TC0OUT = 00, PWM cycle boundary is 0~255.
B0BCLR FTC0OUT
B0BCLR FALOAD0 ; ALOAD0, TC0OUT = 01, PWM cycle boundary is 0~63.
B0BSET FTC0OUT
B0BSET FALOAD0 ; ALOAD0, TC0OUT = 10, PWM cycle boundary is 0~31.
B0BCLR FTC0OUT
B0BSET FALOAD0 ; ALOAD0, TC0OUT = 11, PWM cycle boundary is 0~15.
B0BSET FTC0OUT
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) Set TC0 timer function mode.
or
or
) Enable TC0 timer.
B0BSET FTC0IEN ; Enable TC0 interrupt function.
B0BSET FTC0OUT ; Enable TC0OUT (Buzzer) function.
B0BSET FPWM0OUT ; Enable PWM function.
B0BSET FTC0ENB ; Enable TC0 timer.
8.3.7 TC0 TIMER NOTICE
When TC0C value changes from “0xFF” to not “0xFF”, TC0IRQ is set “1” whether TC0 is operating or not. If TC0IRQ =
0 and TC0C is changed by program, TC0IRQ might be set as TC0C is from “0xFF” to not “0xFF”. The condition makes
unexpected TC0 interrupt occurring.
¾ Example: TC0C = 0xFF and TC0IRQ = 0. TC0IRQ will set as “1” when TC0C is cleared by program (TC0C =
0).
MOV A, #0 ; Clear TC0C.
B0MOV TC0C, A ; TC0IRQ changed from “0” to “1”.
B0BSET FTC0IEN ; Enable TC0 interrupt function and system jumps to interrupt
; vector (ORG 8) at next cycle.
If TC0C changing in system operating duration is necessary, to disable TC0 interrupt function (TC0IEN = 0) before
changing TC0C value. The solution can avoid unexpected TC0 interrupt occurring and example is as following.
¾ Example: TC0C = 0xFF and TC0IRQ = 0. Clearing TC0C must be after TC0 interrupt disable.
B0BCLR FTC0IEN ; Disable TC0 interrupt function.
MOV A, #0 ; Clear TC0C.
B0MOV TC0C, A ; TC0IRQ changed from “0” to “1”.
B0BCLR FTC0IRQ ; Clear TC0IRQ flag.
B0BSET FTC0IEN ; Enable TC0 interrupt function.
…
…
Note: Disable TC0 interrupt function first, and load new TC0C value into TC0C buffer. This way can avoid
unexpected TC0 interrupt occurring.
Note: TC0C and TC0R can’t be set as 0xFF when TC0 timer operating in interrupt, buzzer output modes.
TC0C and TC0R available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode.
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8.4 TIMER/COUNTER 1 (TC1)
8.4.1 OVERVIEW
The TC1 is an 8-bit binary up counting timer. TC1 has two clock sources including internal clock and external clock for
counting a precision time. The internal clock source is from Fcpu. The external clock is INT1 from P0.1 pin (Falling
edge trigger). Using TC1M register selects TC1C’s clock source from internal or external. If TC1 timer occurs an
overflow, it will continue counting and issue a time-out signal to trigger TC1 interrupt to request interrupt service. TC1
overflow time is 0xFF to 0X00 normally. Under PWM mode, TC1 overflow is still 256 counts.
The main purposes of the TC1 timer is as following.
) 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
) External event counter: Counts system “events” based on falling edge detection of external clock signals at the
INT1 input pin.
) Buzzer output
) PWM output
Internal P5.3 I/O Circuit
ALOAD1
Auto. Reload
Buzzer
TC1 / 2
TC1OUT
P5.3
INT1
(Schmitter Trigger)
Fcpu
TC1 Rate
(Fcpu/2~Fcpu/256)
TC1CKS TC1ENB
CPUM0,1
TC1R Reload
Data Buffer
Load
TC1C
8-Bit Binary Up
Counting Counter
Compare
R
PWM
S
PWM1OUT
TC1 Time Out
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8.4.2 TC1M MODE REGISTER
0DCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC1M
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit 0 PWM1OUT: PWM output control bit.
Bit 1 TC1OUT: TC1 time out toggle signal output control bit. Only valid when PWM1OUT = 0.
0 = Disable, P5.3 is I/O function.
1 = Enable, P5.3 is output TC1OUT signal.
Bit 2 ALOAD1: Auto-reload control bit. Only valid when PWM1OUT = 0.
Bit 3 TC1CKS: TC1 clock source select bit.
Bit [6:4] TC1RATE[2:0]: TC1 internal clock select bits.
Bit 7 TC1ENB: TC1 counter control bit.
Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1
interrupt request will be raised. (P0.1IRQ will be always 0).
TC1ENB TC1rate2 TC1rate1 TC1rate0 TC1CKS ALOAD1 TC1OUT PWM1OUT
0 = Disable PWM output.
1 = Enable PWM output. PWM duty controlled by TC1OUT, ALOAD1 bits.
0 = Disable TC1 auto-reload function.
1 = Enable TC1 auto-reload function.
0 = Internal clock (Fcpu).
1 = External clock from P0.1/INT1 pin.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
0 = Disable TC1 timer.
1 = Enable TC1 timer.
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8.4.3 TC1C COUNTING REGISTER
TC1C is an 8-bit counter register for TC1 interval time control.
0DDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC1C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
The equation of TC1C initial value is as following.
¾ Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0). High clock is
external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).
The basic timer table interval time of TC1.
TC1RATE TC1CLOCK
000 Fcpu/256 65.536 ms 256 us 8000 ms 31250 us
001 Fcpu/128 32.768 ms 128 us 4000 ms 15625 us
010 Fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us
011 Fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us
100 Fcpu/16 4.096 ms 16 us 500 ms 1953.125 us
101 Fcpu/8 2.048 ms 8 us 250 ms 976.563 us
110 Fcpu/4 1.024 ms 4 us 125 ms 488.281 us
111 Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us
Note: TC1C and TC1R can’t be set as 0xFF when TC1 timer operating in interrupt, buzzer output modes.
TC1C and TC1R available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode.
TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0
TC1C initial value = 256 - (TC1 interrupt interval time * input clock)
TC1C initial value = 256 - (TC1 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10
= 100
= 64H
High speed mode (Fcpu = 4MHz / 4) Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval One step = max/256 Max overflow interval One step = max/256
-2
* 4 * 106 / 4 / 64)
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8.4.4 TC1R AUTO-LOAD REGISTER
TC1 timer is with auto-load function controlled by ALOAD1 bit of TC1M. When TC1C overflow occurring, TC1R value
will load to TC1C by system. It is easy to generate an accurate time, and users don’t reset TC1C during interrupt
service routine.
0DEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC1R
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
The equation of TC1R initial value is as following.
N is TC1 overflow boundary number. TC1 timer overflow time has five types (TC1 timer, TC1 event counter, TC1 Fcpu
clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time and valid value as follow
table.
¾ Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM
output (PWM1=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).
Note: TC1R can’t be set as 0xFF when TC1 timer operating in interrupt, buzzer output modes. TC1R
available range is 0x00~0xFE. The problem doesn’t exist in pure PWM mode.
TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0
TC1R initial value = N - (TC1 interrupt interval time * input clock)
TC1CKS PWM1 ALOAD1 TC1OUT N
0 x x 256 0x00~0xFF 00000000b~11111111b
1 0 0 256 0x00~0xFF 00000000b~11111111b
0
1 - - - 256 0x00~0xFF 00000000b~11111111b
1 0 1 64 0x00~0x3F xx000000b~xx111111b
1 1 0 32 0x00~0x1F xxx00000b~xxx11111b
1 1 1 16 0x00~0x0F xxxx0000b~xxxx1111b
TC1R valid
value
TC1R value
binary type
TC1R initial value = N - (TC1 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
-2
= 256 - (10
* 4 * 106 / 4 / 64)
= 100
= 64H
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