Page 1
S
S
O
O
N
Nii
X
X 88--
B
Biitt
M
Miiccrroo--
C
Coonnttrroolllleerr
SN8P26L38
USER’S MANUAL
Version 1.5
SN8P26L38
8-Bit Micro-Controller
SN8P26L38
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD Page 1 Version 1.5
Page 2
SN8P26L38
Version
Date
Description
VER 0.1
Dec. 2007
First Issue.
VER 0.2
Jan. 2008
Modify system register table.
VER 0.3
Feb. 2008
Modify internal low RC frequency to 10KHz.
VER 0.4
Otc. 2008
Add SN8P26L38F LQFP package type.
VER 1.0
Aug. 2009
Modify comparator pin assignment description.
VER 1.1
Jun. 2010
1. Modify UART baud rate description.
2. Modify IR register name.
3. Modify SYSTEM REGISTER TABLE.
VER 1.2
Feb. 2013
Modify LQFP package type marking definition.
VER 1.3
Apr. 2013
Add RAM limited:
The 1E6H, 1E7H of RAM address doesn’t support directly addressing mode to
access RAM but support indirectly addressing mode @HL/@YZ.
VER 1.4
Aug. 2013
Modify “SIO chapter” SCK frequency formula and description.
VER 1.5
Jan. 2019
Delete SSOP48 package.
8-Bit Micro-Controller
AMENDMENT HISTORY
SONiX TECHNOLOGY CO., LTD Page 2 Version 1.5
Page 3
SN8P26L38
8-Bit Micro-Controller
Table of Content
AMENDMENT HISTORY ............................................................................................................................ 2
1 PRODUCT OVERVIEW .............................................................................................................................. 8
1.1 FEATURES .............................................................................................................................................. 8
1.2 SYSTEM BLOCK DIAGRAM ................................................................................................................ 9
1.3 PIN ASSIGNMENT ............................................................................................................................... 10
1.4 PIN DESCRIPTIONS ............................................................................................................................. 11
1.5 PIN CIRCUIT DIAGRAMS ................................................................................................................... 12
2 CENTRAL PROCESSOR UNIT (CPU) ................................................................................................... 14
2.1 PROGRAM MEMORY (ROM) ............................................................................................................. 14
2.1.1 RESET VECTOR(0000H) ................................................................................................................ 15
2.1.2 INTERRUPT VECTOR(0008H) ...................................................................................................... 16
2.1.3 LOOK-UP TABLE DESCRIPTION ................................................................................................. 18
2.1.4 JUMP TABLE DESCRIPTION ........................................................................................................ 20
2.1.5 CHECKSUM CALCULATION ........................................................................................................ 22
2.2 DATA MEMORY (RAM) ...................................................................................................................... 23
2.2.1 SYSTEM REGISTER ........................................................................................................................ 24
2.2.1.1 SYSTEM REGISTER TABLE ................................................................................................ 24
2.2.1.2 SYSTEM REGISTER DESCRIPTION ................................................................................... 24
2.2.1.3 BIT DEFINITION of SYSTEM REGISTER ........................................................................... 25
2.2.2 ACCUMULATOR ............................................................................................................................ 27
2.2.3 PROGRAM FLAG ........................................................................................................................... 28
2.2.4 PROGRAM COUNTER ................................................................................................................... 29
2.2.5 H, L REGISTERS ............................................................................................................................. 32
2.2.6 Y, Z REGISTERS.............................................................................................................................. 33
2.2.7 R REGISTERS.................................................................................................................................. 34
2.3 ADDRESSING MODE........................................................................................................................... 35
2.3.1 IMMEDIATE ADDRESSING MODE .............................................................................................. 35
2.3.2 DIRECTLY ADDRESSING MODE ................................................................................................. 35
2.3.3 INDIRECTLY ADDRESSING MODE ............................................................................................. 35
2.4 STACK OPERATION ............................................................................................................................ 36
2.4.1 OVERVIEW ..................................................................................................................................... 36
2.4.2 STACK REGISTERS ........................................................................................................................ 37
2.4.3 STACK OPERATION EXAMPLE .................................................................................................... 38
2.5 CODE OPTION TABLE ........................................................................................................................ 39
2.5.1 RESET_PIN CODE OPTION .......................................................................................................... 39
2.5.2 SECURITY CODE OPTION ............................................................................................................ 39
SONiX TECHNOLOGY CO., LTD Page 3 Version 1.5
Page 4
SN8P26L38
8-Bit Micro-Controller
3 RESET .......................................................................................................................................................... 40
3.1 OVERVIEW ........................................................................................................................................... 40
3.2 POWER ON RESET ............................................................................................................................... 41
3.3 WATCHDOG RESET ............................................................................................................................ 41
3.4 BROWN OUT RESET ........................................................................................................................... 42
3.4.1 THE SYSTEM OPERATING VOLTAGE ......................................................................................... 43
3.4.2 LOW VOLTAGE DETECTOR (LVD) .............................................................................................. 43
3.4.3 BROWN OUT RESET IMPROVEMENT ......................................................................................... 45
3.5 EXTERNAL RESET .............................................................................................................................. 46
3.6 EXTERNAL RESET CIRCUIT ............................................................................................................. 46
3.6.1 Simply RC Reset Circuit .................................................................................................................. 46
3.6.2 Diode & RC Reset Circuit ............................................................................................................... 47
3.6.3 Zener Diode Reset Circuit ............................................................................................................... 47
3.6.4 Voltage Bias Reset Circuit ............................................................................................................... 48
3.6.5 External Reset IC ............................................................................................................................. 49
4 SYSTEM CLOCK ....................................................................................................................................... 50
4.1 OVERVIEW ........................................................................................................................................... 50
4.2 CLOCK BLOCK DIAGRAM ................................................................................................................. 50
4.3 FCPU (INSTRUCTION CYCLE) ............................................................................................................ 50
4.4 OSCM REGISTER ................................................................................................................................. 51
4.5 SYSTEM HIGH CLOCK ....................................................................................................................... 51
4.6 INTERNAL HIGH RC ........................................................................................................................... 52
4.7 EXTERNAL HIGH CLOCK .................................................................................................................. 52
4.7.1 CRYSTAL/CERAMIC....................................................................................................................... 53
4.7.2 RC .................................................................................................................................................... 53
4.7.3 EXTERNAL CLOCK SIGNAL ......................................................................................................... 54
4.8 SYSTEM LOW CLOCK ........................................................................................................................ 55
4.8.1 SYSTEM CLOCK MEASUREMENT ............................................................................................... 55
5 SYSTEM OPERATION MODE ................................................................................................................ 56
5.1 OVERVIEW ........................................................................................................................................... 56
5.2 NORMAL MODE................................................................................................................................... 57
5.3 SLOW MODE......................................................................................................................................... 57
5.4 POWER DOWN MDOE ......................................................................................................................... 57
5.5 GREEN MODE....................................................................................................................................... 58
5.6 OPERATING MODE CONTROL MACRO .......................................................................................... 58
5.7 WAKEUP ............................................................................................................................................... 60
5.7.1 OVERVIEW ..................................................................................................................................... 60
5.7.2 WAKEUP TIME ............................................................................................................................... 60
SONiX TECHNOLOGY CO., LTD Page 4 Version 1.5
Page 5
SN8P26L38
8-Bit Micro-Controller
5.7.3 P1W WAKEUP CONTROL REGISTER .......................................................................................... 61
6 INTERRUPT ................................................................................................................................................ 62
6.1 OVERVIEW ........................................................................................................................................... 62
6.2 INTEN INTERRUPT ENABLE REGISTER ......................................................................................... 63
6.3 INTRQ INTERRUPT REQUEST REGISTER ....................................................................................... 64
6.4 GIE GLOBAL INTERRUPT OPERATION .......................................................................................... 65
6.5 PUSH, POP ROUTINE ........................................................................................................................... 66
6.6 EXTERNAL INTERRUPT OPERATION (INT0) ................................................................................. 67
6.7 INT1 (P0.1) INTERRUPT OPERATION ............................................................................................... 68
6.8 T0 INTERRUPT OPERATION .............................................................................................................. 69
6.9 T1 INTERRUPT OPERATION .............................................................................................................. 71
6.10 TC1 INTERRUPT OPERATION ......................................................................................................... 72
6.11 COMPARATOR INTERRUPT OPERATION (CMP0, CMP1) .......................................................... 73
6.12 SIO INTERRUPT OPERATION .......................................................................................................... 74
6.13 UART INTERRUPT OPERATION ..................................................................................................... 75
6.14 MULTI-INTERRUPT OPERATION ................................................................................................... 76
7 I/O PORT ..................................................................................................................................................... 77
7.1 OVERVIEW ........................................................................................................................................... 77
7.2 I/O PORT MODE ................................................................................................................................... 78
7.3 I/O PULL UP REGISTER ...................................................................................................................... 79
7.4 I/O OPEN-DRAIN REGISTER .............................................................................................................. 80
7.5 I/O PORT DATA REGISTER ................................................................................................................ 82
8 TIMERS ....................................................................................................................................................... 83
8.1 WATCHDOG TIMER ............................................................................................................................ 83
8.2 TIMER 0 (T0) ......................................................................................................................................... 85
8.2.1 OVERVIEW ..................................................................................................................................... 85
8.2.2 T0M MODE REGISTER .................................................................................................................. 86
8.2.3 T0C COUNTING REGISTER .......................................................................................................... 87
8.2.4 T0 TIMER OPERATION SEQUENCE ............................................................................................ 88
8.3 TIMER 1 (T1) ......................................................................................................................................... 89
8.3.1 OVERVIEW ..................................................................................................................................... 89
8.3.2 T1M MODE REGISTER .................................................................................................................. 89
8.3.3 T1CH, T1CL COUNTING REGISTER ............................................................................................ 90
8.3.4 T1 TIMER OPERATION SEQUENCE ............................................................................................ 92
8.4 TIMER/COUNTER 0 (TC1) ................................................................................................................... 93
8.4.1 OVERVIEW ..................................................................................................................................... 93
8.4.2 TC1M MODE REGISTER ............................................................................................................... 94
8.4.3 TC1C COUNTING REGISTER ....................................................................................................... 95
SONiX TECHNOLOGY CO., LTD Page 5 Version 1.5
Page 6
SN8P26L38
8-Bit Micro-Controller
8.4.4 TC1R AUTO-LOAD REGISTER ..................................................................................................... 96
8.4.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER) ......................................................................... 97
8.4.6 TC1 TIMER OPERATION SEQUENCE ......................................................................................... 98
8.5 PWM1 MODE ........................................................................................................................................ 99
8.5.1 OVERVIEW ..................................................................................................................................... 99
8.5.2 TC1IRQ AND PWM DUTY ........................................................................................................... 100
8.5.3 PWM PROGRAM EXAMPLE ....................................................................................................... 101
8.5.4 PWM1 DUTY CHANGING NOTICE ............................................................................................ 102
9 ANALOG COMPARATOR ..................................................................................................................... 104
9.1 OVERVIEW ......................................................................................................................................... 104
9.2 CMP0M REGISTER ............................................................................................................................ 106
9.3 CMP1M REGISTER ............................................................................................................................ 107
9.4 ANALOG COMPARATOR APPLICATION ...................................................................................... 108
10 IR OUTPUT ............................................................................................................................................. 110
10.1 OVERVIEW ....................................................................................................................................... 110
10.2 IR CONTROL REGISTER ................................................................................................................. 111
10.2.1 IRM MODE REGISTER .............................................................................................................. 111
10.2.2 IRC COUNTING REGISTER ...................................................................................................... 111
10.2.3 IRR AUTO-LOAD REGISTER..................................................................................................... 112
10.2.4 IRD IR DUTY CONTROL REGISTER ........................................................................................ 113
10.2.5 IR OUTPUT OPERATION SEQUENCE ..................................................................................... 114
11 SERIAL INPUT/OUTPUT TRANSCEIVER (SIO) ............................................................................ 115
11.1 OVERVIEW ....................................................................................................................................... 115
11.2 SIO OPERATION............................................................................................................................... 115
11.3 SIOM MODE REGISTER .................................................................................................................. 117
11.4 SIOB DATA BUFFER ....................................................................................................................... 118
11.5 SIOR REGISTER DESCRIPTION ..................................................................................................... 119
12 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) ..................................... 120
12.1 OVERVIEW ....................................................................................................................................... 120
12.2 UART OPERATION .......................................................................................................................... 120
12.3 UART RECEIVER CONTROL REGISTER ...................................................................................... 123
12.4 UART TRANSMITTER CONTROL REGISTER ............................................................................. 123
12.5 UART BAUD RATE CONTROL REGISTER ................................................................................... 124
12.6 UART DATA BUFFER ...................................................................................................................... 125
13 INSTRUCTION TABLE ........................................................................................................................ 126
14 ELECTRICAL CHARACTERISTIC ................................................................................................... 127
SONiX TECHNOLOGY CO., LTD Page 6 Version 1.5
Page 7
SN8P26L38
8-Bit Micro-Controller
14.1 ABSOLUTE MAXIMUM RATING .................................................................................................. 127
14.2 ELECTRICAL CHARACTERISTIC ................................................................................................. 127
15 DEVELOPMENT TOOL ....................................................................................................................... 128
15.1 SN8P26L38 EV-KIT ............................................................................................................................ 128
15.2 ICE AND EV-KIT APPLICATION NOTIC ........................................................................................ 129
16 OTP PROGRAMMING PIN .................................................................................................................. 130
16.1 THE PIN ASSIGNMENT OF EASY WRITER TRANSITION BOARD SOCKET: ................................................. 130
16.2 PROGRAMMING PIN MAPPING: ............................................................................................................. 131
17 MARKING DEFINITION ...................................................................................................................... 132
17.1 INTRODUCTION .............................................................................................................................. 132
17.2 MARKING INDETIFICATION SYSTEM ........................................................................................ 132
17.3 MARKING EXAMPLE ...................................................................................................................... 133
17.4 DATECODE SYSTEM ...................................................................................................................... 133
18 PACKAGE INFORMATION ................................................................................................................ 134
18.1 P-DIP 48 PIN ...................................................................................................................................... 134
18.2 LQFP 48 PIN ....................................................................................................................................... 135
SONiX TECHNOLOGY CO., LTD Page 7 Version 1.5
Page 8
SN8P26L38
Memory configuration
Two 8-bit Timer/Counter
OTP ROM size: 8K * 16 bits.
T0: Basic timer.
RAM size: 880 * 8 bits.
TC1: Auto-reload timer/counter.
8 levels stack buffer
One RTC timer (T0).
One channels PWM output.
I/O pin configuration
One channels buzzer output.
Bi-directional: P0, P1, P2, P3, P4, P5
One channel IR output (duty/cycle programmable
Programmable open-drain: P1.0, P1.1, P5.0~P5.2,
PWM, TC0).
P3.2, P3.3.
On chip watchdog timer and clock source is internal
Wakeup:P0, P1 level change trigger.
low clock RC type (about 10KHz @3V).
P1 wake-up function controlled by P1W.
Pull-up resisters: P0, P1, P2, P3, P4, P5
One channel SIO interface.
External interrupt input: P0.0, P0.1
One channel UART interface.
External Interrupt trigger edge:
P0.0 controlled by PEDGE register
Four system clocks
External high clock: RC type up to 8 MHz
3-Level LVD.
External high clock: Crystal type up to 8 MHz
Reset system and power monitor.
Internal high clock: RC type 8MHz.
Internal low clock: RC type 10KHz(3V).
2-ch analog comparators with internal selectable
reference voltage 0.9V/1.0V/1.1V/1.2V and
Four operating modes
external reference input.
Normal mode: Both high and low clock active
Slow mode: Low clock only
8 interrupt sources
Sleep mode: Both high and low clock stop
6 internal interrupts: T0, TC1, CM0, CM1, SIO,
Green mode: Periodical wakeup by timer
UART
2 external interrupts: INT0 INT1
Package (Chip form support)
P-DIP 48 pins
Powerful instructions
LQFP 48 pins
One clock per instruction cycle (1T)
All ROM area JMP instruction.
All ROM area CALL address instruction.
All ROM area lookup table function (MOVC)
1 PRODUCT OVERVIEW
1.1 FEATURES
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 8 Version 1.5
Page 9
INTERRUPT
CONTROL
EXTERNAL
HIGH OSC.
ACC
INTERNAL
LOW RC
TIMING GENERATOR
RAM
SYSTEM REGISTERS
LVD
(Low Voltage Detector)
WATCHDOG TIMER
TIMER & COUNTER
P0 P3P1
PWM 1
BUZZER 1
ALU
PC
FLAGS
IR
OTP
ROM
PWM1
BZ1
P2
INTERNAL HIGH
RC 8MHz
Comparator 0
Comparator 1
CM0P
CM0N
CM0O
CM1P
CM1N
CM1O
IR OUT IROUT
UART
SIO
P4 P5
UTX, URX
SI, SO, SCK
1.2 SYSTEM BLOCK DIAGRAM
SN8P26L38
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 9 Version 1.5
Page 10
VSS
1 U 48
VDD
P0.0/INT0
2 47
P5.7
P0.1/INT1
3 46
P5.6
P0.2/RST/VPP
4 45
P5.5
P0.3/XIN
5 44
P5.4/IROUT
P0.4/XOUT
6 43
P5.3/PWM1/BZ1
P0.5
7 42
P5.2/SO
P0.6
8 41
P5.1/SI
P0.7
9 40
P5.0/SCK
P1.0
10 39
P3.3/UTX
P1.1
11 38
P3.2/URX
P1.2
12 37
P3.1
P1.3
13 36
P3.0
P1.4
14 35
P4.7
P1.5
15 34
P4.6
P1.6
16 33
P4.5
P1.7
17 32
P4.4
P2.0
18 31
P4.3
P2.1
19 30
P4.2
P2.2/CM0N
20 29
P4.1
P2.3/CM0P
21 28
P4.0
P2.4/CM0O
22 27
VDD
P2.5/CM1N
23 26
VSS
P2.6/CM1P
24 25
P2.7/CM1O
P0.4/XOUT
P0.3/XIN
P0.2/RST/VPP
P0.1/INT1
P0.0/INT0
VSS
VDD
P5.7
P5.6
P5.5
P5.4/IROUT
P5.3/BZ1/PWM1
48
47
46
45
44
43
42
41
40
39
38
37
P0.5
1 O
36
P5.2/SO
P0.6
2
35
P5.1/SI
P0.7
3
34
P5.0/SCK
P1.0
4
33
P3.3/UTX
P1.1
5
32
P3.2/URX
P1.2
6
31
P3.1
P1.3
7
30
P3.0
P1.4
8
29
P4.7
P1.5
9
28
P4.6
P1.6
10
27
P4.5
P1.7
11
26
P4.4
P2.0
12
25
P4.3
13
14
15
16
17
18
19
20
21
22
23
24
P2.1
P2.2/CM0N
P2.3/CM0P
P2.4/CM0O
P2.5/CM1N
P2.6/CM1P
P2.7/CM1O
VSS
VDD
P4.0
P4.1
P4.2
1.3 PIN ASSIGNMENT
SN8P26L38P (P-DIP 48 pins)
SN8P26L38
8-Bit Micro-Controller
SN8P26L38F (LQFP 48 pins)
SONiX TECHNOLOGY CO., LTD Page 10 Version 1.5
Page 11
PIN NAME
TYPE
DESCRIPTION
VDD, VSS
P
Power supply input pins for digital and analog circuit.
P0.2/RST/
VPP
I, P
RST: System external reset input pin. Schmitt trigger structure, active “low”, normal stay
to “high”. Build-in wake-up function.
VPP: OTP power input pin in programming mode.
P0.2: Input only pin with Schmitt trigger structure and no pull-up resistor.
XIN/P0.3
I/O
XIN: Oscillator input pin while external oscillator enable (crystal and RC).
P0.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Build-in wake-up function.
XOUT/P0.4
I/O
XOUT: Oscillator output pin while external crystal enable.
P0.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Build-in wake-up function.
P0.0/INT0
I/O
P0.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Build-in wake-up function.
INT0: External interrupt 0 input pin.
P0.1/INT1
I/O
P0.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Build-in wake-up function.
INT1: External interrupt 0 input pin.
TC1 event counter input pin.
P0[7:5]
I/O
P0[7:5]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Build-in wake-up function.
P1[1:0]
I/O
P1[1:0]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Build-in wake-up function. Open-drain structure controlled by P1OC register.
P1[7:0]
I/O
P1[7:2]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Build-in wake-up function.
P2[1:0]
I/O
P2[1:0]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
P2.2/CM0N
I/O
P2.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
CM0N: The negative input pin of comparator.
P2.3/CM0P
I/O
P2.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
CM0P: The positive input pin of comparator.
BTO: Band-gap trimming mode output pin.
P2.4/CM0O
I/O
P2.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
CM0O: The output pin of comparator.
P2.5/CM1N
I/O
P2.5: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
CM1N: The negative input pin of comparator.
P2.6/CM1P
I/O
P2.6: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
CM1P: The positive input pin of comparator.
P2.7/CM1O
I/O
P2.7: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
CM1O: The output pin of comparator.
P3[1:0]
I/O
P3[1:0]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Open-drain structure controlled by P1OC register.
P3.2/URX
I/O
P3.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Open-drain structure controlled by P1OC register.
URX: UART data receive pin.
P3.3/UTX
I/O
P3.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Open-drain structure controlled by P1OC register.
UTX: UART data transmit pin.
P4[7:0]
I/O
P4[7:0]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
P5.0/SCK
I/O
P5.0: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Open-drain structure controlled by P1OC register.
SCK: SIO clock pin.
P5.1/SI
I/O
P5.1: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Open-drain structure controlled by P1OC register.
SI: SIO data input pin.
P5.2/SO
I/O
P5.2: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
1.4 PIN DESCRIPTIONS
SN8P26L38
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 11 Version 1.5
Page 12
Open-drain structure controlled by P1OC register.
SO: SIO data output pin.
P5.3/BZ1/PWM1
I/O
P5.3: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
BZ1: Programmable buzzer output pin from TC1/2 signal.
PWM1: Programmable PWM output pin from TC1.
P5.4/IROUT
I/O
P5.4: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
IROUT: IR signal output pin.
P5[7:5]
I/O
P5[7:5]: Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
P1OC
Open-Drain I/O Bus
Pin
OTP Program Mode
Input Bus
OTP Vpp Input
Reset Pin Code Option
Reset Trigger
1.5 PIN CIRCUIT DIAGRAMS
General purpose I/O pin:
SN8P26L38
8-Bit Micro-Controller
General purpose I/O pin with open-drain structure:
Input only pin shared with reset pin:
SONiX TECHNOLOGY CO., LTD Page 12 Version 1.5
Page 13
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
CMnEN
Comparator
Negative Input
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
CMnEN
Comparator
Positive Input
CMnREF
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
CMnEN
Comparator
Output
CMnOEN
Pull-Up
Resistor
Output
Latch
Pin
PnUR
PnM
Input Bus
Output Bus
Oscillator
Code Option
Oscillator
General purpose I/O pin shared with Comparator:
Comparator Negative Pin:
SN8P26L38
8-Bit Micro-Controller
Comparator Positive Pin:
Comparator Output Pin:
General purpose I/O pin shared with external oscillator:
SONiX TECHNOLOGY CO., LTD Page 13 Version 1.5
Page 14
SN8P26L38
ROM
0000H
Reset vector
User reset vector
Jump to user start address
0001H
General purpose area
. .
0007H
0008H
Interrupt vector
User interrupt vector
0009H
General purpose area
User program
. . 000FH
0010H
0011H . . . . . 1FFCH
End of user program
1FFDH
Reserved
1FFEH
1FFFH
8-Bit Micro-Controller
2 CENTRAL PROCESSOR UNIT (CPU)
2.1 PROGRAM MEMORY (ROM)
8K words ROM
The ROM includes Reset vector, Interrupt vector, General purpose area and Reserved area. The Reset vector is
program beginning address. The Interrupt vector is the head of interrupt service routine when any interrupt occurring.
The General purpose area is main program area including main loop, sub-routines and data table.
SONiX TECHNOLOGY CO., LTD Page 14 Version 1.5
Page 15
SN8P26L38
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
10H
START:
; 0010H, The head of user program.
…
; User program
…
ENDP
; End of program
8-Bit Micro-Controller
2.1.1 RESET VECTOR(0000H)
A one-word vector address area is used to execute system reset.
Power On Reset (NT0=1, NPD=0).
Watchdog Reset (NT0=0, NPD=0).
External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
Example: Defining Reset Vector
SONiX TECHNOLOGY CO., LTD Page 15 Version 1.5
Page 16
SN8P26L38
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
PUSH
; Save ACC and PFLAG register to buffers.
… …
POP
; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine
…
START:
; The head of user program.
…
; User program
…
JMP
START
; End of user program
…
ENDP
; End of program
8-Bit Micro-Controller
2.1.2 INTERRUPT VECTOR(0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
SONiX TECHNOLOGY CO., LTD Page 16 Version 1.5
Page 17
SN8P26L38
.CODE
ORG
0
; 0000H
JMP
START
; Jump to user program address.
…
ORG
8
; Interrupt vector.
JMP
MY_IRQ
; 0008H, Jump to interrupt service routine address.
ORG
10H
START:
; 0010H, The head of user program.
…
; User program.
…
…
JMP
START
; End of user program.
…
MY_IRQ:
;The head of interrupt service routine.
PUSH
; Save ACC and PFLAG register to buffers.
…
…
POP
; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine.
…
ENDP
; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.
8-Bit Micro-Controller
Example: Defining Interrupt Vector. The interrupt service routine is following user program.
SONiX TECHNOLOGY CO., LTD Page 17 Version 1.5
Page 18
SN8P26L38
B0MOV
Y, #TABLE1$M
; To set lookup table1’s middle address
B0MOV
Z, #TABLE1$L
; To set lookup table1’s low address.
MOVC
; To lookup data, R = 00H, ACC = 35H
; Increment the index address for next address.
INCMS
Z
; Z+1
JMP
@F
; Z is not overflow.
INCMS
Y
; Z overflow (FFH 00), Y=Y+1
NOP
;
;
@@:
MOVC
; To lookup data, R = 51H, ACC = 05H.
… ; TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid look-up table errors. If Z register is
overflow, Y register must be added one. The following INC_YZ macro shows a simple method to process
Y and Z registers automatically.
INC_YZ
MACRO
INCMS
Z
; Z+1
JMP
@F
; Not overflow
INCMS
Y
; Y+1
NOP
; Not overflow
@@:
ENDM
8-Bit Micro-Controller
2.1.3 LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
Example: To look up the ROM data located “TABLE1”.
Example: INC_YZ macro.
SONiX TECHNOLOGY CO., LTD Page 18 Version 1.5
Page 19
SN8P26L38
B0MOV
Y, #TABLE1$M
; To set lookup table1’s middle address
B0MOV
Z, #TABLE1$L
; To set lookup table1’s low address.
MOVC
; To lookup data, R = 00H, ACC = 35H
INC_YZ
; Increment the index address for next address.
;
@@:
MOVC
; To lookup data, R = 51H, ACC = 05H.
… ; TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
B0MOV
Y, #TABLE1$M
; To set lookup table’s middle address.
B0MOV
Z, #TABLE1$L
; To set lookup table’s low address.
B0MOV
A, BUF
; Z = Z + BUF.
B0ADD
Z, A
B0BTS1
FC
; Check the carry flag.
JMP
GETDATA
; FC = 0
INCMS
Y
; FC = 1. Y+1.
NOP
GETDATA:
;
MOVC
; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
TABLE1:
DW
0035H
; To define a word (16 bits) data.
DW
5105H
DW
2012H
…
8-Bit Micro-Controller
Example: Modify above example by “INC_YZ” macro.
The other example of look-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
Example: Increase Y and Z register by B0ADD/ADD instruction.
SONiX TECHNOLOGY CO., LTD Page 19 Version 1.5
Page 20
SN8P26L38
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
ORG
0X0100
; The jump table is from the head of the ROM boundary
B0ADD
PCL, A
; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP
A0POINT
; ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
@JMP_A
MACRO
VAL
IF
(($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP
($ | 0XFF)
ORG
($ | 0XFF)
ENDIF
ADD
PCL, A
ENDM
Note: “VAL” is the number of the jump table listing number.
8-Bit Micro-Controller
2.1.4 JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Example: Jump table.
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
Example: If “jump table” crosses over ROM boundary will cause errors.
SONiX TECHNOLOGY CO., LTD Page 20 Version 1.5
Page 21
SN8P26L38
B0MOV
A, BUF0
; “BUF0” is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
JMP
A0POINT
; ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
JMP
A4POINT
; ACC = 4, jump to A4POINT
; Before compiling program.
ROM address
B0MOV
A, BUF0
; “BUF0” is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
0X00FD
JMP
A0POINT
; ACC = 0, jump to A0POINT
0X00FE
JMP
A1POINT
; ACC = 1, jump to A1POINT
0X00FF
JMP
A2POINT
; ACC = 2, jump to A2POINT
0X0100
JMP
A3POINT
; ACC = 3, jump to A3POINT
0X0101
JMP
A4POINT
; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
B0MOV
A, BUF0
; “BUF0” is from 0 to 4.
@JMP_A
5
; The number of the jump table listing is five.
0X0100
JMP
A0POINT
; ACC = 0, jump to A0POINT
0X0101
JMP
A1POINT
; ACC = 1, jump to A1POINT
0X0102
JMP
A2POINT
; ACC = 2, jump to A2POINT
0X0103
JMP
A3POINT
; ACC = 3, jump to A3POINT
0X0104
JMP
A4POINT
; ACC = 4, jump to A4POINT
8-Bit Micro-Controller
Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A” macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
Example: “@JMP_A” operation.
SONiX TECHNOLOGY CO., LTD Page 21 Version 1.5
Page 22
SN8P26L38
MOV
A,#END_USER_CODE$L
B0MOV
END_ADDR1, A
; Save low end address to end_addr1
MOV
A,#END_USER_CODE$M
B0MOV
END_ADDR2, A
; Save middle end address to end_addr2
CLR
Y
; Set Y to 00H
CLR
Z
; Set Z to 00H
@@:
MOVC
B0BSET
FC
; Clear C flag
ADD
DATA1, A
; Add A to Data1
MOV
A, R
ADC
DATA2, A
; Add R to Data2
JMP
END_CHECK
; Check if the YZ address = the end of code
AAA:
INCMS
Z
; Z=Z+1
JMP
@B
; If Z != 00H calculate to next address
JMP
Y_ADD_1
; If Z = 00H increase Y
END_CHECK:
MOV
A, END_ADDR1
CMPRS
A, Z
; Check if Z = low end address
JMP
AAA
; If Not jump to checksum calculate
MOV
A, END_ADDR2
CMPRS
A, Y
; If Yes, check if Y = middle end address
JMP
AAA
; If Not jump to checksum calculate
JMP
CHECKSUM_END
; If Yes checksum calculated is done.
Y_ADD_1:
INCMS
Y
; Increase Y
NOP
JMP
@B
; Jump to checksum calculate
CHECKSUM_END:
… …
END_USER_CODE:
; Label of program end
8-Bit Micro-Controller
2.1.5 CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
SONiX TECHNOLOGY CO., LTD Page 22 Version 1.5
Page 23
BANK
Address
RAM Location
Bank 0
000H
General purpose area
RAM Bank 0 ...
...
07FH
080H
System Register
80h~FFh of Bank 0 store
system registers (128
bytes). ...
0FFH
End of Bank 0
Bank 1
100H
General purpose area
RAM Bank 1 …
…
1FFH
End of Bank 1
Bank 2
200H
General purpose area
RAM Bank 2 …
…
2FFH
End of Bank 2
Bank 3
300H
General purpose area
RAM Bank 3 …
…
3EFH
End of Bank 3
; Bank 1 (RBANK = 1)
B0MOV
A, WK00
; Use Bank 0 type instruction to access Bank 0 RAM.
MOV
WK01,A
Note: For multi-bank RAM program, it is not easy to control RAM Bank selection. Users have to take care
the RBANK condition very carefully, especially for interrupt service routine. The system won’t save the
RBANK and switch RAM bank to Bank 0, so these controls must be through program. It is a good to use
Bank 0 type instruction to process the situations.
The 1E6H, 1E7H of RAM address doesn’t support directly addressing mode to access RAM but support
indirectly addressing mode @HL/@YZ.
2.2 DATA MEMORY (RAM)
880 X 8-bit RAM
SN8P26L38
8-Bit Micro-Controller
The 880-byte general purpose RAM is separated into Bank 0~Bank 3. Accessing the two banks’ RAM is controlled by
“RBANK” register. When RBANK = 0, the program controls Bank 0 RAM directly. When RBANK = 1, the program
controls Bank 1 RAM directly. Under one bank condition and need to access the other bank RAM, setup the RBANK
register is necessary. Sonix provides “Bank 0” type instructions (e.g. b0mov, b0add, b0bts1, b0bset…) to control Bank
0 RAM in non-zero RAM bank condition directly.
Example: Access Bank 0 RAM in Bank 1 condition. Move Bank 0 RAM (WK00) value to Bank 1 RAM
(WK01).
SONiX TECHNOLOGY CO., LTD Page 23 Version 1.5
Page 24
0 1 2 3 4 5 6 7 8 9 A B C D E F
8
L H R Z Y - PFLAG
RBANK - - - - - - - -
9
- - - - - - - - - - - - CMP0M
CMP1M - -
A
T1M
T1CL
T1CH
-
URTX
URRX
URBRC
URTXD
1
URTXD
2
URRXD
1
URRXD
2
- - - - -
B
- - - - SIOM
SIOR
SIOB
-
P0M - - - -
-
-
PEDGE
C
P1W
P1M
P2M
P3M
P4M
P5M - -
INTRQ
INTEN
OSCM
-
WDTR
IRR
PCL
PCH D P0
P1
P2
P3
P4
P5 - -
T0M
T0C
IRM
IRC
TC1M
TC1C
TC1R
STKP
E
P0UR
P1UR
P2UR
P3UR
P4UR
P5UR
@HL
@YZ
IRD
P1OC - - - - - -
F
STK7L
STK7H
STK6L
STK6H
STK5L
STK5H
STK4L
STK4H
STK3L
STK3H
STK2L
STK2H
STK1L
STK1H
STK0L
STK0H
PFLAG =
ROM page and special flag register.
R =
Working register and ROM look-up data buffer.
H, L =
Working, @HL and ROM addressing register.
Y, Z =
Working, @YZ and ROM addressing register.
P1W =
Port 1 wakeup register.
RBANK =
Ram bank selection register.
CMPnM =
Comparator control register.
@HL =
RAM HL indirect addressing index pointer.
PEDGE =
P0.0 edge direction register.
@YZ =
RAM YZ indirect addressing index pointer.
PnM =
Port n input/output mode register.
Pn =
Port n data buffer.
P1OC =
Open-drain control register.
PnUR =
Port n pull-up resister control register.
INTRQ =
Interrupt request register.
INTEN =
Interrupt enable register.
OSCM =
Oscillator mode register.
PCH, PCL =
Program counter.
T0M =
T0 mode register.
T0C =
T0 counting register.
TC1M =
TC1 mode control register.
TC1C =
TC1 counter register.
TC1R =
TC1 auto-reload buffer.
T1M =
T1 mode register.
T1CH,L =
T1 16-bit counter register.
IRM =
IR output control register.
IRC =
IR cycle control register.
IRR =
IR auto-reload register.
IRD =
IR duty control register.
WDTR =
Watchdog timer clear register.
URTX =
UART transmit control register.
URRX =
UART receive control register.
URTXD1,2 =
UART transmit data buffers.
URRXD1,2 =
UART receive data buffers.
URBRC =
UART baud rate control register.
SIOM =
SIO mode control register.
SIOR =
SIO clock rate control register.
SIOB =
SIO data buffer.
STKP =
Stack pointer buffer.
STK0~STK7 =
Stack 0 ~ stack 7 buffer.
2.2.1 SYSTEM REGISTER
2.2.1.1SYSTEM REGISTER TABLE
2.2.1.2SYSTEM REGISTER DESCRIPTION
SN8P26L38
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 24 Version 1.5
Page 25
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
R/W
Remarks
080H
LBIT7
LBIT6
LBIT5
LBIT4
LBIT3
LBIT2
LBIT1
LBIT0
R/W L 081H
HBIT7
HBIT6
HBIT5
HBIT4
HBIT3
HBIT2
HBIT1
HBIT0
R/W
H
082H
RBIT7
RBIT6
RBIT5
RBIT4
RBIT3
RBIT2
RBIT1
RBIT0
R/W R 083H
ZBIT7
ZBIT6
ZBIT5
ZBIT4
ZBIT3
ZBIT2
ZBIT1
ZBIT0
R/W Z 084H
YBIT7
YBIT6
YBIT5
YBIT4
YBIT3
YBIT2
YBIT1
YBIT0
R/W Y 086H
NT0
NPD
LVD28
LVD24 - C
DC
Z
R/W
PFLAG
087H - - - -
-
RBANKS2
RBANKS1
RBANKS0
R/W
RBANK
09CH
CM0EN
CM0IEN
CM0IRQ
CM0OEN
CM0REF
CM0OUT
CMS1
CMS0
R/W
CMP0M
09DH
CM1EN
CM1IEN
CM1IRQ
CM1OEN
CM1REF
CM1OUT
- - R/W
CMP1M
0A0H
T1ENB
T1rate2
T1rate1
T1rate0
R/W
T1M
0A1H
T1CL7
T1CL6
T1CL5
T1CL4
T1CL3
T1CL2
T1CL1
T1CL0
R/W
T1CL
0A2H
T1CH7
T1CH6
T1CH5
T1CH4
T1CH3
T1CH2
T1CH1
T1CH0
R/W
T1CH
0A4H UTXEN
UTXPEN
UTXPS
UTXM
R/W
URTX
0A5H
URXEN
URXS1
URXS0
URXPEN
URXPS
URXPC
URXM
R/W
URRX
0A6H
UDIV4
UDIV3
UDIV2
UDIV1
UDIV0
UPCS2
UPCS1
UPCS0
R/W
URBRC
0A7H
UTXD17
UTXD16
UTXD15
UTXD14
UTXD13
UTXD12
UTXD11
UTXD10
R/W
URTXD1
0A8H
UTXD27
UTXD26
UTXD25
UTXD24
UTXD23
UTXD22
UTXD21
UTXD20
R/W
URTXD2
0A9H
URXD17
URXD16
URXD15
URXD14
URXD13
URXD12
URXD11
URXD10
R/W
URRXD1
0AAH
URXD27
URXD26
URXD25
URXD24
URXD23
URXD22
URXD21
URXD20
R/W
URRXD2
0B4H
SENB
START
SRATE1
SRATE0
MLSB
SCLKMD
CPOL
CPHA
R/W
SIOM
0B5H
SIOR7
SIOR6
SIOR5
SIOR4
SIOR3
SIOR2
SIOR1
SIOR0
W
SIOR
0B6H
SIOB7
SIOB6
SIOB5
SIOB4
SIOB3
SIOB2
SIOB1
SIOB0
R/W
SIOB
0B8H
P07M
P06M
P05M
P04M
P03M
-
P01M
P00M
R/W
P0M
0BFH - - - P00G1
P00G0 - - - R/W
PEDGE
0C0H
P17W
P16W
P15W
P14W
P13W
P12W
P11W
P10W
W
P1W wakeup register
0C1H
P17M
P16M
P15M
P14M
P13M
P12M
P11M
P10M
R/W
P1M I/O direction
0C2H
P27M
P26M
P25M
P24M
P23M
P22M
P21M
P20M
R/W
P2M I/O direction
0C3H - - - -
P33M
P32M
P31M
P30M
R/W
P3M I/O direction
0C4H
P47M
P46M
P45M
P44M
P43M
P42M
P41M
P40M
R/W
P4M I/O direction
0C5H
P57M
P56M
P55M
P54M
P53M
P52M
P51M
P50M
R/W
P5M I/O direction
0C8H
SIOIRQ
TC1IRQ
T1IRQ
T0IRQ
RXIRQ
TXIRQ
P01IRQ
P00IRQ
R/W
INTRQ
0C9H
SIOIEN
TC1IEN
T1IEN
T0IEN
RXIEN
TXIEN
P01IEN
P00IEN
R/W
INTEN
0CAH - - - CPUM1
CPUM0
CLKMD
STPHX
-
R/W
OSCM
0CCH
WDTR7
WDTR6
WDTR5
WDTR4
WDTR3
WDTR2
WDTR1
WDTR0
W
WDTR
0CDH
IRR7
IRR6
IRR5
IRR4
IRR3
IRR2
IRR1
IRR0
W
IRR
0CEH
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
R/W
PCL
0CFH - - - PC12
PC11
PC10
PC9
PC8
R/W
PCH
0D0H
P07
P06
P05
P04
P03
P02
P01
P00
R/W
P0 data buffer
0D1H
P17
P16
P15
P14
P13
P12
P11
P10
R/W
P1 data buffer
0D2H
P27
P26
P25
P24
P23
P22
P21
P20
R/W
P2 data buffer
0D3H - - - -
P33
P32
P31
P30
R/W
P3 data buffer
0D4H
P47
P46
P45
P44
P43
P42
P41
P40
R/W
P4 data buffer
0D5H
P57
P56
P55
P54
P53
P52
P51
P50
R/W
P5 data buffer
0D8H
T0ENB
T0rate2
T0rate1
T0rate0 - - - T0TB
R/W
T0M
0D9H
T0C7
T0C6
T0C5
T0C4
T0C3
T0C2
T0C1
T0C0
R/W
T0C
0DAH - - - - - -
IREN
CREN
R/W
IRM
0DBH
IRC7
IRC6
IRC5
IRC4
IRC3
IRC2
IRC1
IRC0
R/W
IRC
0DCH
TC1ENB
TC1rate2
TC1rate1
TC1rate0
TC1CKS
ALOAD1
TC1OUT
PWM1OUT
R/W
TC1M
0DDH
TC1C7
TC1C6
TC1C5
TC1C4
TC1C3
TC1C2
TC1C1
TC1C0
R/W
TC1C
0DEH
TC1R7
TC1R6
TC1R5
TC1R4
TC1R3
TC1R2
TC1R1
TC1R0
W
TC1R
0DFH
GIE - - - -
STKPB2
STKPB1
STKPB0
R/W
STKP stack pointer
0E0H
P07R
P06R
P05R
P04R
P03R
-
P01R
P00R
W
P0 pull-up register
0E1H
P17R
P16R
P15R
P14R
P13R
P12R
P11R
P10R
W
P1 pull-up register
0E2H
P27R
P26R
P25R
P24R
P23R
P22R
P21R
P20R
W
P2 pull-up register
0E3H - - - -
P33R
P32R
P31R
P30R
W
P3 pull-up register
0E4H
P47R
P46R
P45R
P44R
P43R
P42R
P41R
P40R
W
P4 pull-up register
0E5H
P57R
P56R
P55R
P54R
P53R
P52R
P51R
P50R
W
P5 pull-up register
0E6H
@HL7
@ HL 6
@ HL5
@ HL4
@ HL3
@ HL2
@ HL1
@ HL0
R/W
@HL index pointer
0E7H
@YZ7
@YZ6
@YZ5
@YZ4
@YZ3
@YZ2
@YZ1
@YZ0
R/W
@YZ index pointer
0E8H
IRD7
IRD6
IRD5
IRD4
IRD3
IRD2
IRD1
IRD0
W
IRD
0E9H
P52OC
P51OC
P50OC
P33OC
P32OC
-
P11OC
P10OC
W
P1OC
0F0H
S7PC7
S7PC6
S7PC5
S7PC4
S7PC3
S7PC2
S7PC1
S7PC0
R/W
STK7L
0F1H 1 1 1 S7PC12
S7PC11
S7PC10
S7PC9
S7PC8
R/W
STK7H
0F2H
S6PC7
S6PC6
S6PC5
S6PC4
S6PC3
S6PC2
S6PC1
S6PC0
R/W
STK6L
0F3H 1 1 1 S6PC12
S6PC11
S6PC10
S6PC9
S6PC8
R/W
STK6H
0F4H
S5PC7
S5PC6
S5PC5
S5PC4
S5PC3
S5PC2
S5PC1
S5PC0
R/W
STK5L
2.2.1.3BIT DEFINITION of SYSTEM REGISTER
SN8P26L38
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 25 Version 1.5
Page 26
SN8P26L38
0F5H 1 1 1 S5PC12
S5PC11
S5PC10
S5PC9
S5PC8
R/W
STK5H
0F6H
S4PC7
S4PC6
S4PC5
S4PC4
S4PC3
S4PC2
S4PC1
S4PC0
R/W
STK4L
0F7H 1 1 1 S4PC12
S4PC11
S4PC10
S4PC9
S4PC8
R/W
STK4H
0F8H
S3PC7
S3PC6
S3PC5
S3PC4
S3PC3
S3PC2
S3PC1
S3PC0
R/W
STK3L
0F9H 1 1 1 S3PC12
S3PC11
S3PC10
S3PC9
S3PC8
R/W
STK3H
0FAH
S2PC7
S2PC6
S2PC5
S2PC4
S2PC3
S2PC2
S2PC1
S2PC0
R/W
STK2L
0FBH 1 1 1 S2PC12
S2PC11
S2PC10
S2PC9
S2PC8
R/W
STK2H
0FCH
S1PC7
S1PC6
S1PC5
S1PC4
S1PC3
S1PC2
S1PC1
S1PC0
R/W
STK1L
0FDH 1 1 1 S1PC12
S1PC11
S1PC10
S1PC9
S1PC8
R/W
STK1H
0FEH
S0PC7
S0PC6
S0PC5
S0PC4
S0PC3
S0PC2
S0PC1
S0PC0
R/W
STK0L
0FFH 1 1 1 S0PC12
S0PC11
S0PC10
S0PC9
S0PC8
R/W
STK0H
Note:
1. To avoid system error, please be sure to put all the “0” and “1” as it indicates in the above table.
2. All of register names had been declared in SN8ASM assembler.
3. One-bit name had been declared in SN8ASM assembler with “F” prefix code.
4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers.
5. For detail description, please refer to the “System Register Quick Reference Table”.
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 26 Version 1.5
Page 27
SN8P26L38
; Read ACC data and store in BUF data memory.
MOV
BUF, A
; Write a immediate data into ACC.
MOV
A, #0FH
; Write ACC data from BUF data memory.
MOV
A, BUF
; or
B0MOV
A, BUF
INT_SERVICE:
PUSH
; Save ACC and PFLAG to buffers.
… .
…
POP
; Load ACC and PFLAG from buffers.
RETI
; Exit interrupt service vector
8-Bit Micro-Controller
2.2.2 ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
Example: Read and write ACC value.
The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to
other data memories. “PUSH”, “POP” save and load ACC, PFLAG data into buffers.
Example: Protect ACC and working registers.
SONiX TECHNOLOGY CO., LTD Page 27 Version 1.5
Page 28
SN8P26L38
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFLAG
NT0
NPD
LVD28
LVD24
- C DC
Z
Read/Write
R/W
R/W R R - R/W
R/W
R/W
After reset
- - 0 0 - 0 0
0
NT0
NPD
Reset Status
0
0
Watch-dog time out
0
1
Reserved
1
0
Reset by LVD
1
1
Reset by external Reset Pin
Note: Refer to instruction set table for detailed information of C, DC and Z flags.
8-Bit Micro-Controller
2.2.3 PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.
NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and
watchdog reset. C, DC, Z bits indicate the result status of ALU operation. LVD24, LVD28 bits indicate LVD detecting
power voltage status.
Bit [7:6] NT0, NPD: Reset status flag.
Bit 5 LVD30: LVD 2.8V operating flag and only support LVD code option is LVD_H.
0 = Inactive (VDD > 2.8V).
1 = Active (VDD ≦ 2.8V).
Bit 4 LVD24: LVD 2.4V operating flag and only support LVD code option is LVD_M.
0 = Inactive (VDD > 2.4V).
1 = Active (VDD ≦ 2.4V).
Bit 2 C: Carry flag
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result
≥ 0.
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison
result < 0.
Bit 1 DC: Decimal carry flag
1 = Addition with carry from low nibble, subtraction without borrow from high nibble.
0 = Addition without carry from low nibble, subtraction with borrow from high nibble.
Bit 0 Z: Zero flag
1 = The result of an arithmetic/logic/branch operation is zero.
0 = The result of an arithmetic/logic/branch operation is not zero.
SONiX TECHNOLOGY CO., LTD Page 28 Version 1.5
Page 29
SN8P26L38
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC
- - -
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
After
reset
- - - 0 0 0 0 0 0 0 0 0 0 0 0
0
PCH
PCL
B0BTS1
FC
; To skip, if Carry_flag = 1
JMP
C0STEP
; Else jump to C0STEP.
…
…
C0STEP:
NOP
B0MOV
A, BUF0
; Move BUF0 value to ACC.
B0BTS0
FZ
; To skip, if Zero flag = 0.
JMP
C1STEP
; Else jump to C1STEP.
…
… C1STEP:
NOP
CMPRS
A, #12H
; To skip, if ACC = 12H.
JMP
C0STEP
; Else jump to C0STEP.
…
… C0STEP:
NOP
8-Bit Micro-Controller
2.2.4 PROGRAM COUNTER
The program counter (PC) is a 13-bit binary counter separated into the high-byte 5 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 12.
ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
SONiX TECHNOLOGY CO., LTD Page 29 Version 1.5
Page 30
SN8P26L38
INCS
BUF0
JMP
C0STEP
; Jump to C0STEP if ACC is not zero.
…
…
C0STEP:
NOP
INCMS
BUF0
JMP
C0STEP
; Jump to C0STEP if BUF0 is not zero.
…
… C0STEP:
NOP
DECS
BUF0
JMP
C0STEP
; Jump to C0STEP if ACC is not zero.
…
… C0STEP:
NOP
DECMS
BUF0
JMP
C0STEP
; Jump to C0STEP if BUF0 is not zero.
… … C0STEP:
NOP
8-Bit Micro-Controller
If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
INCMS instruction:
If the destination decreased by 1, which results underflow of 0x01 to 0x00, the PC will add 2 steps to skip next
instruction.
DECS instruction:
DECMS instruction:
SONiX TECHNOLOGY CO., LTD Page 30 Version 1.5
Page 31
SN8P26L38
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
; PC = 0323H
MOV
A, #28H
B0MOV
PCL, A
; Jump to address 0328H
…
; PC = 0328H
MOV
A, #00H
B0MOV
PCL, A
; Jump to address 0300H
…
; PC = 0323H
B0ADD
PCL, A
; PCL = PCL + ACC, the PCH cannot be changed.
JMP
A0POINT
; If ACC = 0, jump to A0POINT
JMP
A1POINT
; ACC = 1, jump to A1POINT
JMP
A2POINT
; ACC = 2, jump to A2POINT
JMP
A3POINT
; ACC = 3, jump to A3POINT
… …
8-Bit Micro-Controller
MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate
multi-address jumping function. Program Counter supports “ADD M,A”, ”ADC M,A” and “B0ADD M,A” instructions
for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value
by the three instructions and don’t care PCL overflow problem.
Example: If PC = 0323H (PCH = 03H, PCL = 23H)
Example: If PC = 0323H (PCH = 03H, PCL = 23H)
SONiX TECHNOLOGY CO., LTD Page 31 Version 1.5
Page 32
SN8P26L38
081H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H
HBIT7
HBIT6
HBIT5
HBIT4
HBIT3
HBIT2
HBIT1
HBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
X X X X X X X
X
080H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
L
LBIT7
LBIT6
LBIT5
LBIT4
LBIT3
LBIT2
LBIT1
LBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
X X X X X X X
X
B0MOV
H, #00H
; To set RAM bank 0 for H register
B0MOV
L, #20H
; To set location 20H for L register
B0MOV
A, @HL
; To read a data into ACC
CLR
H
; H = 0, bank 0
B0MOV
L, #07FH
; L = 7FH, the last address of the data memory area
CLR_HL_BUF:
CLR
@HL
; Clear @HL to be zero
DECMS
L
; L – 1, if L = 0, finish the routine
JMP
CLR_HL_BUF
; Not zero
CLR
@HL
END_CLR:
; End of clear general purpose data memory area of bank 0
… …
8-Bit Micro-Controller
2.2.5 H, L REGISTERS
The H and L registers are the 8-bit buffers. There are two major functions of these registers.
can be used as general working registers
can be used as RAM data pointers with @HL register
Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode
to access data as following.
Example: Clear general-purpose data memory area of bank 0 using @HL register.
SONiX TECHNOLOGY CO., LTD Page 32 Version 1.5
Page 33
SN8P26L38
084H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Y
YBIT7
YBIT6
YBIT5
YBIT4
YBIT3
YBIT2
YBIT1
YBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
- - - - - - -
- 083H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Z
ZBIT7
ZBIT6
ZBIT5
ZBIT4
ZBIT3
ZBIT2
ZBIT1
ZBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
- - - - - - -
-
B0MOV
Y, #00H
; To set RAM bank 0 for Y register
B0MOV
Z, #25H
; To set location 25H for Z register
B0MOV
A, @YZ
; To read a data into ACC
B0MOV
Y, #0
; Y = 0, bank 0
B0MOV
Z, #07FH
; Z = 7FH, the last address of the data memory area
CLR_YZ_BUF:
CLR
@YZ
; Clear @YZ to be zero
DECMS
Z
; Z – 1, if Z= 0, finish the routine
JMP
CLR_YZ_BUF
; Not zero
CLR
@YZ
END_CLR:
; End of clear general purpose data memory area of bank 0
…
8-Bit Micro-Controller
2.2.6 Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
can be used as general working registers
can be used as RAM data pointers with @YZ register
can be used as ROM data pointer with the MOVC instruction for look-up table
Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.
Example: Uses the Y, Z register as data pointer to clear the RAM data.
SONiX TECHNOLOGY CO., LTD Page 33 Version 1.5
Page 34
SN8P26L38
082H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
RBIT7
RBIT6
RBIT5
RBIT4
RBIT3
RBIT2
RBIT1
RBIT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
- - - - - - -
-
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
8-Bit Micro-Controller
2.2.7 R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register.
Can be used as working register
For store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
SONiX TECHNOLOGY CO., LTD Page 34 Version 1.5
Page 35
SN8P26L38
MOV
A, #12H
; To set an immediate data 12H into ACC.
B0MOV
R, #12H
; To set an immediate data 12H into R register.
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.
B0MOV
A, 12H
; To get a content of RAM location 0x12 of bank 0 and save in
ACC.
B0MOV
12H, A
; To get a content of ACC and save in RAM location 12H of
bank 0.
B0MOV
Y, #0
; To clear Y register to access RAM bank 0.
B0MOV
Z, #12H
; To set an immediate data 12H into Z register.
B0MOV
A, @YZ
; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
8-Bit Micro-Controller
2.3 ADDRESSING MODE
2.3.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.
Example: Move the immediate data 12H to ACC.
Example: Move the immediate data 12H to R register.
2.3.2 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.
Example: Move 0x12 RAM location data into ACC.
Example: Move ACC data into 0x12 RAM location.
2.3.3 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (Y/Z).
Example: Indirectly addressing mode with @YZ register.
SONiX TECHNOLOGY CO., LTD Page 35 Version 1.5
Page 36
SN8P26L38
RET /
RETI
CALL /
INTERRUPT
STKP = 7
STKP = 6
STKP = 5
STKP = 4
STACK Level
STK7H
STK6H
STK5H
STK4H
STACK Buffer
High Byte
PCH
STKP
STK7L
STK6L
STK5L
STK4L
STACK Buffer
Low Byte
PCL
STKP
STKP - 1STKP + 1
STKP = 3
STKP = 2
STKP = 1
STKP = 0
STK3L
STK2L
STK1L
STK0L
STK3H
STK2H
STK1H
STK0H
8-Bit Micro-Controller
2.4 STACK OPERATION
2.4.1 OVERVIEW
The stack buffer has 8-level. These buffers are designed to push and pop up program counter’s (PC) data when
interrupt service routine and “CALL” instruction are executed. The STKP register is a pointer designed to point active
level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program
counter (PC) data.
SONiX TECHNOLOGY CO., LTD Page 36 Version 1.5
Page 37
SN8P26L38
0DFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STKP
GIE - - - -
STKPB2
STKPB1
STKPB0
Read/Write
R/W - - - -
R/W
R/W
R/W
After reset
0 - - - - 1 1
1
MOV
A, #00000111B
B0MOV
STKP, A
0F0H~0FFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STKnH
- - -
SnPC12
SnPC11
SnPC10
SnPC9
SnPC8
Read/Write
- - -
R/W
R/W
R/W
R/W
R/W
After reset
- - - 0 0 0 0
0
0F0H~0FFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STKnL
SnPC7
SnPC6
SnPC5
SnPC4
SnPC3
SnPC2
SnPC1
SnPC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
8-Bit Micro-Controller
2.4.2 STACK REGISTERS
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 13-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses.
The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push
operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to
the top address of stack buffer and write the last program counter value (PC) into the stack buffer.
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
Bit[2:0] STKPBn: Stack pointer (n = 0 ~ 2)
Bit 7 GIE: Global interrupt control bit.
0 = Disable.
1 = Enable. Please refer to the interrupt chapter.
Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the
beginning of the program.
STKn = STKnH , STKnL (n = 7 ~ 0)
SONiX TECHNOLOGY CO., LTD Page 37 Version 1.5
Page 38
SN8P26L38
Stack Level
STKP Register
Stack Buffer
Description
STKPB2
STKPB1
STKPB0
High Byte
Low Byte
0
1 1 1
Free
Free
-
1
1 1 0
STK0H
STK0L
-
2
1 0 1
STK1H
STK1L
-
3
1 0 0
STK2H
STK2L
-
4
0 1 1
STK3H
STK3L
-
5
0 1 0
STK4H
STK4L
-
6
0 0 1
STK5H
STK5L
-
7
0 0 0
STK6H
STK6L
-
8
1 1 1
STK7H
STK7L
-
> 8
1 1 0 - -
Stack Over, error
Stack Level
STKP Register
Stack Buffer
Description
STKPB2
STKPB1
STKPB0
High Byte
Low Byte
8
1 1 1
STK7H
STK7L
-
7
0 0 0
STK6H
STK6L
-
6
0 0 1
STK5H
STK5L
-
5
0 1 0
STK4H
STK4L
-
4
0 1 1
STK3H
STK3L
-
3
1 0 0
STK2H
STK2L
-
2
1 0 1
STK1H
STK1L
-
1
1 1 0
STK0H
STK0L
-
0
1 1 1
Free
Free
-
8-Bit Micro-Controller
2.4.3 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
SONiX TECHNOLOGY CO., LTD Page 38 Version 1.5
Page 39
SN8P26L38
Code Option
Content
Function Description
Fcpu
Fhosc/1
Instruction cycle is oscillator clock.
Fhosc/2
Instruction cycle is 2 oscillator clocks.
Fhosc/4
Instruction cycle is 4 oscillator clocks.
Fhosc/8
Instruction cycle is 8 oscillator clocks.
High_Clk
IHRC_8M
High speed internal 8MHz RC. XIN/XOUT become to P0.3/P0.4
bi-direction I/O pins.
IHRC_RTC
High speed internal 8MHz RC with 0.5sec RTC. XIN/XOUT become to
P0.3/P0.4 bit-direction I/O pins.
RC
Low cost RC for external high clock oscillator and XOUT becomes to P0.4
bit-direction I/O pin.
32K X’tal
Low frequency, power saving crystal (e.g. 32.768KHz) for external high
clock oscillator.
8M X’tal
High speed crystal /resonator (e.g. 8MHz) for external high clock
oscillator.
4M X’tal
Standard crystal /resonator (e.g. 4M) for external high clock oscillator.
Watch_Dog
Always_On
Watchdog timer is always on enable even in power down and green
mode.
Enable
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
Disable
Disable Watchdog function.
Reset_Pin
Reset
Enable External reset pin.
P02
Enable P0.2 input only without pull-up resister.
LVD
LVD_L
LVD will reset chip if VDD is below 1.8V
LVD_M
LVD will reset chip if VDD is below 1.8V
Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator.
LVD_H
LVD will reset chip if VDD is below 2.4V
Enable LVD28 bit of PFLAG register for 2.8V low voltage indicator.
Security
Enable
Enable ROM code Security function.
Disable
Disable ROM code Security function.
8-Bit Micro-Controller
2.5 CODE OPTION TABLE
The code option is the system hardware configurations including oscillator type, watchdog timer operation, LVD option,
reset pin option and OTP ROM security control. The code option items are as following table:
2.5.1 RESET_PIN CODE OPTION
The reset pin is shared with general input only pin controlled by code option.
Reset: The reset pin external reset function. When falling edge trigger occurring, the system will be reset.
P02: Set reset pin to general purpose input only pin (P0.2). The external reset function is disable and the pin is
input pin.
2.5.2 SECURITY CODE OPTION
Security code option is OTP ROM protection. When enable security code option, the ROM code is secured and not
dumped complete ROM contents.
SONiX TECHNOLOGY CO., LTD Page 39 Version 1.5
Page 40
SN8P26L38
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFLAG
NT0
NPD
LVD28
LVD24
- C DC
Z
Read/Write
R/W
R/W R R - R/W
R/W
R/W
After reset
- - 0 0 - 0 0
0
NT0
NPD
Condition
Description
0
0
Watchdog reset
Watchdog timer overflow.
0
1
Reserved
- 1 0
Power on reset and LVD reset.
Power voltage is lower than LVD detecting level.
1
1
External reset
External reset pin detect low level status.
VDD
VSS
VDD
VSS
Watchdog Normal Run
Watchdog Stop
System Normal Run
System Stop
LVD Detect Level
External Reset
Low Detect
External Reset
High Detect
Watchdog
Overflow
Watchdog
Reset Delay
Time
External
Reset Delay
Time
Power On
Delay Time
Power
External Reset
Watchdog Reset
System Status
8-Bit Micro-Controller
3 RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
Power on reset
Watchdog reset
Brown out reset
External reset (only supports external reset pin enable situation)
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
Bit [7:6] NT0, NPD: Reset status flag.
Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
SONiX TECHNOLOGY CO., LTD Page 40 Version 1.5
Page 41
SN8P26L38
Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.
8-Bit Micro-Controller
3.2 POWER ON RESET
The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising
curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.
Power-up: System detects the power voltage up and waits for power stable.
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
3.3 WATCHDOG RESET
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.
Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer
overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and
returns normal mode. Watchdog reset sequence is as following.
Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
Watchdog timer application note is as following.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
SONiX TECHNOLOGY CO., LTD Page 41 Version 1.5
Page 42
SN8P26L38
VDD
VSS
V1
V2
V3
System Work
Well Area
System Work
Error Area
8-Bit Micro-Controller
3.4 BROWN OUT RESET
The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external
factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well
or executing program error.
Brown Out Reset Diagram
The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power
range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset
diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate
the system working area. The above area is the system work well area. The below area is the system work error area
called dead-band. V1 doesn’t touch the below area and not effect the system operation. But the V2 and V3 is under the
below area and may induce the system error occurrence. Let system under dead-band includes some conditions.
DC application:
The power source of DC application is usually using battery. When low battery condition and MCU drive any loading,
the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system
reset voltage. That makes the system under dead-band.
AC application:
In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC
noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating
induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power
situation.
The power on duration and power down duration are longer in AC application. The system power on sequence protects
the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power,
the VDD drops slowly and through the dead-band for a while.
SONiX TECHNOLOGY CO., LTD Page 42 Version 1.5
Page 43
SN8P26L38
Vdd (V)
System Rate (Fcpu)
System Mini.
Operating Voltage.
System Reset
Voltage.
Dead-Band Area
Normal Operating
Area
Reset Area
VDD
VSS
System Normal Run
System Stop
LVD Detect Voltage
Power On
Delay Time
Power
System Status
Power is below LVD Detect
Voltage and System Reset.
8-Bit Micro-Controller
3.4.1 THE SYSTEM OPERATING VOLTAGE
To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system
executing rate and power level. Different system executing rates have different system minimum operating voltage.
The electrical characteristic section shows the system voltage to executing rate relationship.
Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is
decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even
higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system
reset voltage.
3.4.2 LOW VOLTAGE DETECTOR (LVD)
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD can’t be the protection and need to other reset methods. More detail LVD information
is in the electrical characteristic section.
The LVD is three levels design (1.8V/2.4V/2.8V) and controlled by LVD code option. The 1.8V LVD is always enable for
power on reset and Brown Out reset. The 2.4V LVD includes LVD reset function and flag function to indicate VDD
status function. The 2.8V includes flag function to indicate VDD status. LVD flag function can be an easy low battery
detector. LVD24, LVD28 flags indicate VDD voltage level. For low battery detect application, only checking LVD24,
LVD28 status to be battery status. This is a cheap and easy solution.
SONiX TECHNOLOGY CO., LTD Page 43 Version 1.5
Page 44
SN8P26L38
086H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFLAG
NT0
NPD
LVD28
LVD24
- C DC
Z
Read/Write
R/W
R/W R R - R/W
R/W
R/W
After reset
- - 0 0 - 0 0
0
LVD
LVD Code Option
LVD_L
LVD_M
LVD_H
1.8V Reset
Available
Available
Available
2.4V Flag - Available
-
2.4V Reset - -
Available
2.8V Flag - -
Available
Note:
1. After any LVD reset, LVD24, LVD28 flags are cleared.
2. The voltage level of LVD 2.4V or 2.8V is for design reference only. Don’t use the LVD indicator as
precision VDD measurement.
Bit 5 LVD28: LVD 2.8V operating flag and only support LVD code option is LVD_H.
0 = Inactive (VDD > 2.8V).
1 = Active (VDD <= 2.8V).
Bit 4 LVD24: LVD 2.4V operating flag and only support LVD code option is LVD_M.
0 = Inactive (VDD > 2.4V).
1 = Active (VDD <= 2.4V).
LVD_L
If VDD < 1.8V, system will be reset.
Disable LVD24 and LVD28 bit of PFLAG register
LVD_M
If VDD < 1.8V, system will be reset.
Enable LVD24 bit of PFLAG register. If VDD > 2.4V, LVD24 is “0”. If VDD ≦ 2.4V, LVD24 flag is “1”
Disable LVD28 bit of PFLAG register
LVD2_H
If VDD < 2.4V, system will be reset.
Enable LVD24 bit of PFLAG register. If VDD > 2.4V, LVD24 is “0”. If VDD ≦ 2.4V, LVD24 flag is “1”
8-Bit Micro-Controller
Enable LVD28 bit of PFLAG register. If VDD > 2.8V, LVD28 is “0”. If VDD ≦ 2.8V, LVD28 flag is “1”
SONiX TECHNOLOGY CO., LTD Page 44 Version 1.5
Page 45
SN8P26L38
Note:
1. The “ Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can completely
improve the brown out reset, DC low battery and AC slow power down conditions.
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and
use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset IC”). The
structure can improve noise effective and get good EFT characteristic.
8-Bit Micro-Controller
3.4.3 BROWN OUT RESET IMPROVEMENT
How to improve the brown reset condition? There are some methods to improve brown out reset as following.
LVD reset
Watchdog reset
Reduce the system executing rate
External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)
Watchdog reset:
The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear
at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the
watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t
be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of
watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method
also can improve brown out reset condition and make sure the system to return normal mode.
If the system reset by watchdog and the power is still in dead-band, the system reset sequence won’t be successful
and the system stays in reset status until the power return to normal range. Watchdog timer application note is as
following.
Reduce the system executing rate:
If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band.
The lower system rate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue
and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue.
This way needs to modify whole program timing to fit the application requirement.
External reset circuit:
The external reset methods also can improve brown out reset and is the complete solution. There are three external
reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External
reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under
power dropping and under dead-band. The external reset information is described in the next section.
SONiX TECHNOLOGY CO., LTD Page 45 Version 1.5
Page 46
SN8P26L38
MCU
VDD
VSS
VCC
GND
R
S
T
R1
47K ohm
C1
0.1uF
R2
100 ohm
Note: The reset circuit is no any protection against unusual power or brown out reset.
8-Bit Micro-Controller
3.5 EXTERNAL RESET
External reset function is controlled by “Reset_Pin” code option. Set the code option as “Reset” option to enable
external reset function. External reset pin is Schmitt Trigger structure and low level active. The system is running when
reset pin is high level voltage input. The reset pin receives the low voltage and the system is reset. The external reset
operation actives in power on and normal running mode. During system power-up, the external reset pin must be high
level input, or the system keeps in reset status. External reset sequence is as following.
External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
System initialization: All system registers is set as initial conditions and system is ready.
Oscillator warm up: Oscillator operation is successfully and supply to system clock.
Program executing: Power on sequence is finished and program executes from ORG 0.
The external reset can reset the system during power on duration, and good external reset circuit can protect the
system to avoid working at unusual power condition, e.g. brown out reset in AC power application…
3.6 EXTERNAL RESET CIRCUIT
3.6.1 Simply RC Reset Circuit
This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into
reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from
the timing difference.
SONiX TECHNOLOGY CO., LTD Page 46 Version 1.5
Page 47
MCU
VDD
VSS
VCC
GND
R
S
T
R1
47K ohm
C1
0.1uF
DIODE
R2
100 ohm
Note: The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to
limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due
to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).
MCU
VDD
VSS
VCC
GND
R
S
T
R1
33K ohm
R3
40K ohm
R2
10K ohm
Vz
Q1
E
C
B
3.6.2 Diode & RC Reset Circuit
SN8P26L38
8-Bit Micro-Controller
This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal.
The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct
higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can
improve slight brown out reset condition.
3.6.3 Zener Diode Reset Circuit
The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition
completely. Use zener voltage to be the active level. When VDD voltage level is above “Vz + 0.7V”, the C terminal of
the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of
the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener
specification. Select the right zener voltage to conform the application.
SONiX TECHNOLOGY CO., LTD Page 47 Version 1.5
Page 48
MCU
VDD
VSS
VCC
GND
R
S
T
R1
47K ohm
R3
2K ohm
R2
10K ohm
Q1
E
C
B
Note: Under unstable power condition as brown out reset, “Zener diode rest circuit” and “Voltage bias
reset circuit” can protects system no any error occurrence as power dropping. When power drops below
the reset detect voltage, the system reset would be triggered, and then system executes reset sequence.
That makes sure the system work well under unstable power situation.
3.6.4 Voltage Bias Reset Circuit
SN8P26L38
8-Bit Micro-Controller
The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely.
The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When
VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high
voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor
outputs low voltage and MCU is in reset mode.
Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the
circuit diagram condition, the MCU’s reset pin level varies with VDD voltage variation, and the differential voltage is
0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the
reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external
reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power
system, the current must be considered to whole system power consumption.
SONiX TECHNOLOGY CO., LTD Page 48 Version 1.5
Page 49
MCU
VDD
VSS
VCC
GND
R
S
T
Reset
IC
VDD
VSS
RST
Bypass
Capacitor
0.1uF
3.6.5 External Reset IC
SN8P26L38
8-Bit Micro-Controller
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good
effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can
improve all power variation.
SONiX TECHNOLOGY CO., LTD Page 49 Version 1.5
Page 50
SN8P26L38
Fhosc. Fcpu = Fhosc/1 ~ Fhosc/8
Flosc. Fcpu = Flosc/4
CPUM[1:0]
XIN
XOUT
STPHX HOSC
Fcpu Code Option
Fosc
Fosc
CLKMD
Fcpu
8-Bit Micro-Controller
4 SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is
generated from the external oscillator circuit or on-chip 8MHz high-speed RC oscillator circuit (IHRC 8MHz). The
low-speed clock is generated from on-chip low-speed RC oscillator circuit (ILRC 10KHz @3V).
Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is
divided by 4 to be the instruction cycle (Fcpu).
Normal Mode (High Clock): Fcpu = Fhosc / N, N = 1 ~ 8, Select N by Fcpu code option.
Slow Mode (Low Clock): Fcpu = Flosc/4.
4.2 CLOCK BLOCK DIAGRAM
HOSC: High_Clk code option.
Fhosc: External high-speed clock / Internal high-speed RC clock.
Flosc: Internal low-speed RC clock (about 10KHz@3V).
Fosc: System clock source.
Fcpu: Instruction cycle.
4.3 Fcpu (INSTRUCTION CYCLE)
Fcpu is instruction cycle which is divided from the system high clock source and decides the system operating rate.
Fcpu rate is selected by code option from Fhosc/1~Fhosc/8 If the system high clock source is from external 16MHz
crystal, and the Fcpu code option is Fhosc/4, the Fcpu frequency is 16MHz/4 = 4MHz. The code option doesn’t support
slow mode because the Fcpu of slow mode is fixed Flosc/4 condition.
In high noisy environment, below “Fhosc/4” of Fcpu code option is the strongly recommendation to reduce
high frequency noise effect.
SONiX TECHNOLOGY CO., LTD Page 50 Version 1.5
Page 51
SN8P26L38
0CAH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCM
0 0 0
CPUM1
CPUM0
CLKMD
STPHX
0
Read/Write
- - -
R/W
R/W
R/W
R/W
-
After reset
- - - 0 0 0 0
-
8-Bit Micro-Controller
4.4 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
Bit 1 STPHX: External high-speed oscillator control bit.
0 = External high-speed oscillator free run.
1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running.
Bit 2 CLKMD: System high/Low clock mode control bit.
0 = Normal (dual) mode. System clock is high clock.
1 = Slow mode. System clock is internal low clock.
Bit[4:3] CPUM[1:0]: CPU operating mode control bits.
00 = normal.
01 = sleep (power down) mode.
10 = green mode.
11 = reserved.
“STPHX” bit controls internal high speed RC type oscillator and external oscillator operations. When “STPHX=0”, the
external oscillator or internal high speed RC type oscillator active. When “STPHX=1”, the external oscillator or internal
high speed RC type oscillator are disabled. The STPHX function is depend on different high clock options to do
different controls.
High_CLK = IHRC_8M: “STPHX=1” disables internal high speed RC type oscillator.
High_CLK = IHRC_RTC: “STPHX=1” disables internal high speed RC type oscillator and external 32768Hz
crystal.
High_CLK = RC, 4M, 8M, 32K: “STPHX=1” disables external oscillator.
4.5 SYSTEM HIGH CLOCK
The system high clock is from internal 8MHz oscillator RC type or external oscillator. The high clock type is controlled
by “High_Clk” code option.
IHRC_8M: The system clock source is from internal high speed 8MHz RC type oscillator. In the mode, XIN and
XOUT pins are bi-direction GPIO mode, and not to connect any external oscillator.
IHRC_RTC: The system clock source is from internal high speed 8MHz RC type oscillator, and includes external
low speed 32768Hz crystal for RTC function. The XIN and XOUT pins are defined to drive external 32768Hz
crystal and not GPIO mode.
RC: The system clock source is from external low cost RC type oscillator. The RC oscillator circuit only connects
to XIN pin, and the XOUT pin is bi-direction GPIO mode.
32K X’tal: The system clock source is from external low speed 32768Hz crystal. The option only supports
32768Hz crystal.
8M X’tal: The system clock source is from external high speed crystal/resonator. The oscillator bandwidth is
8MHz~16MHz.
4M X’tal: The system clock source is from external high speed crystal/resonator. The oscillator bandwidth is
1MHz~10MHz.
SONiX TECHNOLOGY CO., LTD Page 51 Version 1.5
Page 52
SN8P26L38
RC
4MHz Ceramic
4MHz Crystal
32768Hz Crystal
8-Bit Micro-Controller
4.6 INTERNAL HIGH RC
The chip is built-in RC type internal high clock (8MHz) controlled by “IHRC_8M” or “IHRC_RTC” code options. In
“IHRC_8M” mode, the system clock is from internal 8MHz RC type oscillator and XIN / XOUT pins are general-purpose
I/O pins. In “IHRC_RTC” mode, the system clock is from internal 8MHz RC type oscillator and XIN / XOUT pins are
connected with external 32768 crystal for real time clock (RTC).
IHRC: High clock is internal 8MHz oscillator RC type. XIN/XOUT pins are general purpose I/O pins.
IHRC_RTC: High clock is internal 8MHz oscillator RC type. XIN/XOUT pins are connected with external 32768Hz
crystal/ceramic oscillator for RTC clock source.
The RTC period is 0.5 sec and RTC timer is T0. Please consult “T0 Timer” chapter to apply RTC function.
4.7 EXTERNAL HIGH CLOCK
External high clock includes three modules (Crystal/Ceramic, RC and external clock signal). The high clock oscillator
module is controlled by High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different.
RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time
length.
SONiX TECHNOLOGY CO., LTD Page 52 Version 1.5
Page 53
SN8P26L38
MCU
VCC
GND
C
20pF
XIN
X
O
U
T
VDD
VSS
C
20pF
CRYSTAL
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of
micro-controller.
R
MCU
VCC
GND
XIN
X
O
U
T
V
D
D
VSS
C
Note: Connect the R and C as near as possible to the VDD pin of micro-controller.
8-Bit Micro-Controller
4.7.1 CRYSTAL/CERAMIC
Crystal/Ceramic devices are driven by XIN, XOUT pins. For high/normal/low frequency, the driving currents are
different. High_Clk code option supports different frequencies. 8M option is for high speed (ex. 8MHz). 4M option is for
normal speed (ex. 4MHz). 32K option is for low speed (ex. 32768Hz).
4.7.2 RC
Selecting RC oscillator is by RC option of High_Clk code option. RC type oscillator’s frequency is up to 10MHz. Using
“R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin.
SONiX TECHNOLOGY CO., LTD Page 53 Version 1.5
Page 54
SN8P26L38
MCU
VCC
GND
VSS
VDD
XIN
XOUT
External Clock Input
Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller.
8-Bit Micro-Controller
4.7.3 EXTERNAL CLOCK SIGNAL
Selecting external clock signal input to be system clock is by RC option of High_Clk code option. The external clock
signal is input from XIN pin. XOUT pin is general purpose I/O pin.
SONiX TECHNOLOGY CO., LTD Page 54 Version 1.5
Page 55
SN8P26L38
B0BSET
FCPUM0
; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1
bits of OSCM register.
B0BSET
P0M.0
; Set P0.0 to be output mode for outputting Fcpu toggle signal.
@@:
B0BSET
P0.0
; Output Fcpu toggle signal in low-speed clock mode.
B0BCLR
P0.0
; Measure the Fcpu frequency by oscilloscope.
JMP
@B
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
frequency.
8-Bit Micro-Controller
4.8 SYSTEM LOW CLOCK
The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator
uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common
condition, the frequency of the RC oscillator is about 10KHz at 3V. The relation between the RC frequency and voltage
is as the following figure.
The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD.
Flosc = Internal low RC oscillator (about 10KHz @3V).
Slow mode Fcpu = Flosc / 4
There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 455K
mode and watchdog disable. If system is in 455K mode and watchdog disable, only 455K oscillator actives and system
is under low power consumption.
Example: Stop internal low-speed oscillator by power down mode.
4.8.1 SYSTEM CLOCK MEASUREMENT
Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is
useful in RC mode.
Example: Fcpu instruction cycle of external oscillator.
SONiX TECHNOLOGY CO., LTD Page 55 Version 1.5
Page 56
SN8P26L38
Power Down Mode
(Sleep Mode)
Slow Mode
Green Mode
Normal Mode
CLKMD = 1
CLKMD = 0
P0, P1 Wake-up Function Active.
External Reset Circuit Active.
CPUM1, CPUM0 = 01.
CPUM1, CPUM0 = 10.
P0, P1 Wake-up Function Active.
T0 Timer Time Out.
External Reset Circuit
Active.
P0, P1 Wake-up Function Active.
T0 Timer Time Out.
External Reset Circuit Active.
Operating mode description
MODE
NORMAL
SLOW
GREEN
POWER DOWN
(SLEEP)
REMARK
EHOSC
Running
By STPHX
By STPHX
Stop
IHRC
Running
By STPHX
By STPHX
Stop
ILRC
Running
Running
Running
Stop
EHOSC with RTC
Running
By STPHX
Running
Stop
IHRC with RTC
Running
By STPHX
Stop
Stop
ILRC with RTC
Running
Running
Stop
Stop
CPU instruction
Executing
Executing
Stop
Stop
T0 timer
*Active
*Active
*Active
Inactive
* Active if T0ENB=1
TC1 timer
*Active
*Active
Inactive
Inactive
* Active if TC1ENB=1
Watchdog timer
By Watch_Dog
Code option
By Watch_Dog
Code option
By Watch_Dog
Code option
By Watch_Dog
Code option
Refer to code option
description
Internal interrupt
All active
All active
T0
All inactive
External interrupt
All active
All active
All active
All inactive
Wakeup source
-
-
P0, P1, T0
Reset
P0, P1, Reset
8-Bit Micro-Controller
5 SYSTEM OPERATION MODE
5.1 OVERVIEW
The chip is featured with low power consumption by switching around four different modes as following.
High-speed mode
Low-speed mode
Power-down mode (Sleep mode)
Green mode
EHOSC: External high clock
IHRC: Internal high clock (8M RC oscillator)
ILRC: Internal low clock (10K RC oscillator at 3V)
System Mode Switching Diagram
SONiX TECHNOLOGY CO., LTD Page 56 Version 1.5
Page 57
SN8P26L38
Note: If the system is in normal mode, to set STPHX=1 to disable the high clock oscillator. The system is
under no system clock condition. This condition makes the system stay as power down mode, and can
be wake-up by P0, P1 level change trigger.
8-Bit Micro-Controller
5.2 NORMAL MODE
The Normal Mode is system high clock operating mode. The system clock source is from high speed oscillator. The
program is executed. After power on and any reset trigger released, the system inserts into normal mode to execute
program. When the system is wake-up from power down mode, the system also inserts into normal mode. In normal
mode, the high speed oscillator actives, and the power consumption is largest of all operating modes.
The program is executed, and full functions are controllable.
The system rate is high speed.
The high speed oscillator and internal low speed RC type oscillator active.
Normal mode can be switched to other operating modes through OSCM register.
Power down mode is wake-up to normal mode.
Slow mode is switched to normal mode.
Green mode from normal mode is wake-up to normal mode.
5.3 SLOW MODE
The slow mode is system low clock operating mode. The system clock source is from internal low speed RC type
oscillator (10Hz @3V). The slow mode is controlled by CLKMD bit of OSCM register. When CLKMD=0, the system is in
normal mode. When CLKMD=1, the system inserts into slow mode. The high speed oscillator won’t be disabled
automatically after switching to slow mode, and must be disabled by SPTHX bit to reduce power consumption. In slow
mode, the system rate is fixed Flosc/4 (Flosc is internal low speed RC type oscillator frequency).
The program is executed, and full functions are controllable.
The system rate is low speed (Flosc/4).
The internal low speed RC type oscillator actives, and the high speed oscillator is controlled by STPHX=1. In slow
mode, to stop high speed oscillator is strongly recommendation.
Slow mode can be switched to other operating modes through OSCM register.
Power down mode from slow mode is wake-up to normal mode.
Normal mode is switched to slow mode.
Green mode from slow mode is wake-up to slow mode.
5.4 POWER DOWN MDOE
The power down mode is the system ideal status. No program execution and oscillator operation. Whole chip is under
low power consumption status under 1uA. The power down mode is waked up by P0, P1 hardware level change trigger.
P1 wake-up function is controlled by P1W register. Any operating modes into power down mode, the system is waked
up to normal mode. Inserting power down mode is controlled by CPUM0 bit of OSCM register. When CPUM0=1, the
system inserts into power down mode. After system wake-up from power down mode, the CPUM0 bit is disabled (zero
status) automatically.
The program stops executing, and full functions are disabled.
All oscillators including external high speed oscillator, internal high speed oscillator and internal low speed
oscillator stop.
The power consumption is under 1uA.
The system inserts into normal mode after wake-up from power down mode.
The power down mode wake-up source is P0 and P1 level change trigger.
SONiX TECHNOLOGY CO., LTD Page 57 Version 1.5
Page 58
SN8P26L38
Note: Sonix provides “GreenMode” macro to control green mode operation. It is necessary to use
“@GreenMode” macro to control system inserting green mode.
The macro includes three instructions. Please take care the macro length as using BRANCH type
instructions, e.g. bts0, bts1, b0bts0, b0bts1, ins, incms, decs, decms, cmprs, jmp, or the routine would
be error.
Macro
Length
Description
SleepMode
1-word
The system insets into Sleep Mode (Power Down Mode).
GreenMode
3-word
The system inserts into Green Mode.
SlowMode
2-word
The system inserts into Slow Mode and stops high speed oscillator.
Slow2Normal
5-word
The system returns to Normal Mode from Slow Mode. The macro
includes operating mode switch, enable high speed oscillator, high
speed oscillator warm-up delay time.
SleepMode
; Declare “SleepMode” macro directly.
SlowMode
; Declare “SlowMode” macro directly.
Slow2Normal
; Declare “Slow2Normal” macro directly.
GreenMode
; Declare “GreenMode” macro directly.
8-Bit Micro-Controller
5.5 GREEN MODE
The green mode is another system ideal status not like power down mode. In power down mode, all functions and
hardware devices are disabled. But in green mode, the system clock source keeps running, so the power consumption
of green mode is larger than power down mode. In green mode, the program isn’t executed, but the timer with wake-up
function actives as enabled, and the timer clock source is the non-stop system clock. The green mode has 2 wake-up
sources. One is the P0, P1 level change trigger wake-up. The other one is internal timer with wake-up function
occurring overflow. That’s mean users can setup one fix period to timer, and the system is waked up until the time out.
Inserting green mode is controlled by CPUM1 bit of OSCM register. When CPUM1=1, the system inserts into green
mode. After system wake-up from green mode, the CPUM1 bit is disabled (zero status) automatically.
The program stops executing, and full functions are disabled.
Only the timer with wake-up function actives.
The oscillator to be the system clock source keeps running, and the other oscillators operation is depend on
system operation mode configuration.
If inserting green mode from normal mode, the system insets to normal mode after wake-up.
If inserting green mode from slow mode, the system insets to slow mode after wake-up.
The green mode wake-up source are P0, P1 level change trigger and unique time overflow.
5.6 OPERATING MODE CONTROL MACRO
Sonix provides operating mode control macros to switch system operating mode easily.
Example: Switch normal/slow mode to power down (sleep) mode.
Example: Switch normal mode to slow mode.
Example: Switch slow mode to normal mode (The external high-speed oscillator stops).
Example: Switch normal/slow mode to green mode.
SONiX TECHNOLOGY CO., LTD Page 58 Version 1.5
Page 59
SN8P26L38
; Set T0 timer wakeup function.
B0BCLR
FT0IEN
; To disable T0 interrupt service
B0BCLR
FT0ENB
; To disable T0 timer
MOV
A,#20H
; B0MOV
T0M,A
; To set T0 clock = Fcpu / 64
MOV
A,#74H
B0MOV
T0C,A
; To set T0C initial value = 74H (To set T0 interval = 10 ms)
B0BCLR
FT0IEN
; To disable T0 interrupt service
B0BCLR
FT0IRQ
; To clear T0 interrupt request
B0BSET
FT0ENB
; To enable T0 timer
; Go into green mode
GreenMode
; Declare “GreenMode” macro directly.
CLR
T0C
; Clear T0 counter.
B0BSET
FT0ENB
; To enable T0 timer
; Go into green mode
GreenMode
; Declare “GreenMode” macro directly.
8-Bit Micro-Controller
Example: Switch normal/slow mode to green mode and enable T0 wake-up function.
Example: Switch normal/slow mode to green mode and enable T0 wake-up function with RTC.
SONiX TECHNOLOGY CO., LTD Page 59 Version 1.5
Page 60
SN8P26L38
Note: Wakeup from green mode is no wakeup time because the clock doesn’t stop in green mode.
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
8-Bit Micro-Controller
5.7 WAKEUP
5.7.1 OVERVIEW
Under power down mode (sleep mode) or green mode, program doesn’t execute. The wakeup trigger can wake the
system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0, P1 level change) and
internal trigger (T0 timer overflow).
Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change)
Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger (P0,
P1 level change) and internal trigger (T0 timer overflow).
5.7.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power
down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit.
After the wakeup time, the system goes into the normal mode.
The value of the wakeup time is as the following.
The Wakeup time = 1/Fosc * 2048 (sec) + high clock start-up time
Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system
goes into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz)
The total wakeup time = 0.512 ms + oscillator start-up time
SONiX TECHNOLOGY CO., LTD Page 60 Version 1.5
Page 61
SN8P26L38
0C0H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1W
P17W
P16W
P15W
P14W
P13W
P12W
P11W
P10W
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
8-Bit Micro-Controller
5.7.3 P1W WAKEUP CONTROL REGISTER
Under power down mode (sleep mode) and green mode, the I/O ports with wakeup function are able to wake the
system up to normal mode. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function always enables, but
the Port 1 is controlled by the P1W register.
Bit[7:0] P10W~P17W: Port 1 wakeup function control bits.
0 = Disable P1n wakeup function.
1 = Enable P1n wakeup function.
SONiX TECHNOLOGY CO., LTD Page 61 Version 1.5
Page 62
SN8P26L38
INTEN Interrupt Enable Register
Interrupt
Enable
Gating
INTRQ
8-Bit
&
CMnM
2-Bit
Latchs
P00IRQ
P01IRQ
T0IRQ
Interrupt Vector Address (0008H)
Global Interrupt Request Signal
INT0 Trigger
T1 Time Out
TC1 Time Out
SIO Transmitter End
T1IRQ
INT1 Trigger
T0 Time Out
Comparator 0 Trigger
Comparator 1 Trigger
UART Transmit End
TC1IRQ
SIOIRQ
CM0IRQ
CM1IRQ
TXIRQ
UART Receive End
RXIRQ
Note: The GIE bit must enable during all interrupt operation.
8-Bit Micro-Controller
6 INTERRUPT
6.1 OVERVIEW
This MCU provides 10 interrupt sources, including 8 internal interrupt (T0/T1/TC1/CM0/CM1/SIO/URRX/URTX) and 2
external interrupt (INT0/INT1). The external interrupt can wakeup the chip while the system is switched from power
down mode to high-speed normal mode, and interrupt request is latched until return to normal mode. Once interrupt
service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt request. On the contrast,
when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. Most of the interrupt
request signals are stored in INTRQ register, but comparator interrupt request flags are stored in CMnM registers.
SONiX TECHNOLOGY CO., LTD Page 62 Version 1.5
Page 63
SN8P26L38
0C9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTEN
SIOIEN
TC1IEN
T1IEN
T0IEN
RXIEN
TXIEN
P01IEN
P00IEN
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
8-Bit Micro-Controller
6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including three internal interrupts, two external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
Bit 0 P00IEN: External P0.0 interrupt (INT0) control bit.
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
Bit 1 P01IEN: External P0.1 interrupt (INT1) control bit.
0 = Disable INT1 interrupt function.
1 = Enable INT1 interrupt function.
Bit 2 TXIEN: UART transmit interrupt control bit.
0 = Disable UART transmit interrupt function.
1 = Enable UART transmit interrupt function.
Bit 3 RXIEN: UART receive interrupt control bit.
0 = Disable UART receive interrupt function.
1 = Enable UART receive interrupt function.
Bit 4 T0IEN: T0 timer interrupt control bit.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
Bit 5 T1IEN: T1 timer interrupt control bit.
0 = Disable T1 interrupt function.
1 = Enable T1 interrupt function.
Bit 6 TC1IEN: TC1 timer interrupt control bit.
0 = Disable TC1 interrupt function.
1 = Enable TC1 interrupt function.
Bit 7 SIOIEN: SIO interrupt control bit.
0 = Disable SIO interrupt function.
1 = Enable SIO interrupt function.
CM0IEN (CM0M’s bit 6): Comparator 0 interrupt control bit.
0 = Disable comparator 0 interrupt function.
1 = Enable comparator 0 interrupt function.
CM1IEN (CM1M’s bit 6): Comparator 1 interrupt control bit.
0 = Disable comparator 1 interrupt function.
1 = Enable comparator 1 interrupt function.
SONiX TECHNOLOGY CO., LTD Page 63 Version 1.5
Page 64
SN8P26L38
0C8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTRQ
SIOIRQ
TC1IRQ
T1IRQ
T0IRQ
RXIRQ
TXIRQ
P01IRQ
P00IRQ
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
8-Bit Micro-Controller
6.3 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
Bit 0 P00IRQ: External P0.0 interrupt (INT0) request flag.
0 = None INT0 interrupt request.
1 = INT0 interrupt request.
Bit 1 P01IRQ: External P0.1 interrupt (INT1) request flag.
0 = None INT1 interrupt request.
1 = INT1 interrupt request.
Bit 2 TXIRQ: UART transmit interrupt request flag.
0 = None UART transmit interrupt request.
1 = UART transmit interrupt request.
Bit 3 RXIRQ: UART receive interrupt request flag.
0 = None UART receive interrupt request.
1 = UART receive interrupt request.
Bit 4 T0IRQ: T0 timer interrupt request flag.
0 = None T0 interrupt request.
1 = T0 interrupt request.
Bit 5 T1IRQ: T1 timer interrupt request flag.
0 = None T1 interrupt request.
1 = T1 interrupt request.
Bit 6 TC1IRQ: TC1 timer interrupt request flag.
0 = None TC1 interrupt request.
1 = TC1 interrupt request.
Bit 7 SIOIRQ: SIO interrupt request flag.
0 = None SIO interrupt request.
1 = SIO interrupt request.
CM0IRQ (CM0M’s bit 5): Comparator 0 interrupt request flag.
0 = None comparator 0 interrupt request.
1 = Comparator 0 interrupt request.
CM1IRQ (CM1M’s bit 5): Comparator 1 interrupt request flag.
0 = None comparator 1 interrupt request.
1 = Comparator 1 interrupt request.
SONiX TECHNOLOGY CO., LTD Page 64 Version 1.5
Page 65
SN8P26L38
0DFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STKP
GIE - - - -
STKPB2
STKPB1
STKPB0
Read/Write
R/W - - - -
R/W
R/W
R/W
After reset
0 - - - - 1 1
1
B0BSET
FGIE
; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
8-Bit Micro-Controller
6.4 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and
the stack add 1 level.
Bit 7 GIE: Global interrupt control bit.
0 = Disable global interrupt.
1 = Enable global interrupt.
Example: Set global interrupt control bit (GIE).
SONiX TECHNOLOGY CO., LTD Page 65 Version 1.5
Page 66
SN8P26L38
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is
an unique buffer and only one level.
ORG
0
JMP
START
ORG
8
JMP
INT_SERVICE
ORG
10H
START:
…
INT_SERVICE:
PUSH
; Save ACC and PFLAG to buffers.
… …
POP
; Load ACC and PFLAG from buffers.
RETI
; Exit interrupt service vector
…
ENDP
8-Bit Micro-Controller
6.5 PUSH, POP ROUTINE
When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save
ACC, PFLAG data. The chip includes “PUSH”, “POP” for in/out interrupt service routine. The two instructions save and
load ACC, PFLAG data into buffers and avoid main routine error after interrupt service routine finishing.
Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine
executed.
SONiX TECHNOLOGY CO., LTD Page 66 Version 1.5
Page 67
SN8P26L38
0BFH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PEDGE
- - -
P00G1
P00G0
- - -
Read/Write
- - -
R/W
R/W - -
-
After reset
- - - 0 0 - -
-
MOV
A, #98H
B0MOV
PEDGE, A
; Set INT0 interrupt trigger as bi-direction edge.
B0BSET
FP00IEN
; Enable INT0 interrupt service
B0BCLR
FP00IRQ
; Clear INT0 interrupt request flag
B0BSET
FGIE
; Enable GIE
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FP00IRQ
; Check P00IRQ
JMP
EXIT_INT
; P00IRQ = 0, exit interrupt vector
B0BCLR
FP00IRQ
; Reset P00IRQ
… ; INT0 interrupt service routine
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.6 EXTERNAL INTERRUPT OPERATION (INT0)
Sonix provides 1 external interrupt sources in the micro-controller. INT0 is external interrupt trigger source and builds in
edge trigger configuration function. When the external edge trigger occurs, the external interrupt request flag will be set
to “1” no matter the external interrupt control bit enabled or disable. When external interrupt control bit is enabled and
external interrupt edge trigger is occurring, the program counter will jump to the interrupt vector (ORG 8) and execute
interrupt service routine.
The external interrupt builds in wake-up latch function. That means when the system is triggered wake-up from power
down mode, the wake-up source is external interrupt source (P0.0), and the trigger edge direction matches interrupt
edge configuration, the trigger edge will be latched, and the system executes interrupt service routine fist after
wake-up.
Bit[4:3] P00G[1:0]: INT0 edge trigger select bits.
00 = reserved,
01 = rising edge,
10 = falling edge,
11 = rising/falling bi-direction.
Example: Setup INT0 interrupt request and bi-direction edge trigger.
Example: INT0 interrupt service routine.
SONiX TECHNOLOGY CO., LTD Page 67 Version 1.5
Page 68
SN8P26L38
Note: The interrupt trigger direction of P0.1 is falling edge.
B0BSET
FP01IEN
; Enable INT1 interrupt service
B0BCLR
FP01IRQ
; Clear INT1 interrupt request flag
B0BSET
FGIE
; Enable GIE
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FP01IRQ
; Check P01IRQ
JMP
EXIT_INT
; P01IRQ = 0, exit interrupt vector
B0BCLR
FP01IRQ
; Reset P01IRQ
… ; INT1 interrupt service routine
… EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.7 INT1 (P0.1) INTERRUPT OPERATION
When the INT1 trigger occurs, the P01IRQ will be set to “1” no matter the P01IEN is enable or disable. If the P01IEN =
1 and the trigger event P01IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG
8). If the P01IEN = 0 and the trigger event P01IRQ is still set to be “1”. Moreover, the system won’t execute interrupt
vector even when the P01IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt
situation.
Example: INT1 interrupt request setup.
Example: INT1 interrupt service routine.
SONiX TECHNOLOGY CO., LTD Page 68 Version 1.5
Page 69
SN8P26L38
B0BCLR
FT0IEN
; Disable T0 interrupt service
B0BCLR
FT0ENB
; Disable T0 timer
MOV
A, #20H
;
B0MOV
T0M, A
; Set T0 clock = Fcpu / 64
MOV
A, #74H
; Set T0C initial value = 74H
B0MOV
T0C, A
; Set T0 interval = 10 ms
B0BSET
FT0IEN
; Enable T0 interrupt service
B0BCLR
FT0IRQ
; Clear T0 interrupt request flag
B0BSET
FT0ENB
; Enable T0 timer
B0BSET
FGIE
; Enable GIE
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FT0IRQ
; Check T0IRQ
JMP
EXIT_INT
; T0IRQ = 0, exit interrupt vector
B0BCLR
FT0IRQ
; Reset T0IRQ
MOV
A, #74H
B0MOV
T0C, A
; Reset T0C.
… ; T0 interrupt service routine
… EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.8 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the
T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the
trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the
operation under multi-interrupt situation.
Example: T0 interrupt request setup.
Example: T0 interrupt service routine as no RTC function.
SONiX TECHNOLOGY CO., LTD Page 69 Version 1.5
Page 70
Note:
1. In RTC mode, clear T0IRQ must be after 1/2 RTC clock source (32768Hz), or the RTC interval time is
error. The delay is about 16us and use T0 interrupt service routine executing time to be the 16us
delay time.
2. In RTC mode, don’t reset T0C in interrupt service routine.
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
> 16us
B0BTS1
FT0IRQ
; Check T0IRQ
JMP
EXIT_INT
; T0IRQ = 0, exit interrupt vector
… ; T0 interrupt service routine
… ; The time must be longer than 16us.
B0BCLR
FT0IRQ
; Reset T0IRQ
… EXIT_INT:
…
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
Example: T0 interrupt service routine with RTC function.
SN8P26L38
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 70 Version 1.5
Page 71
SN8P26L38
B0BCLR
FT1IEN
; Disable T1 interrupt service
B0BCLR
FT1ENB
; Disable T1 timer
MOV
A, #20H
; B0MOV
T1M, A
; Set T1 clock = Fcpu / 64 and falling edge trigger.
CLR
T1C
B0BSET
FT1IEN
; Enable T1 interrupt service
B0BCLR
FT1IRQ
; Clear T1 interrupt request flag
B0BSET
FT1ENB
; Enable T1 timer
B0BSET
FGIE
; Enable GIE
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
PUSH
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FT1IRQ
; Check T1IRQ
JMP
EXIT_INT
; T1IRQ = 0, exit interrupt vector
B0BCLR
FT1IRQ
; Reset T1IRQ
B0MOV
A, T1C
B0MOV
T1CBUF, A
; Save pulse width.
CLR
T1C
… ; T1 interrupt service routine
… EXIT_INT:
POP
; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.9 T1 INTERRUPT OPERATION
When the T1C (T1CH, T1CL) counter occurs overflow, the T1IRQ will be set to “1” however the T1IEN is enable or
disable. If the T1IEN = 1, the trigger event will make the T1IRQ to be “1” and the system enter interrupt vector. If the
T1IEN = 0, the trigger event will make the T1IRQ to be “1” but the system will not enter interrupt vector. Users need to
care for the operation under multi-interrupt situation.
Example: T1 interrupt request setup.
Example: T1 interrupt service routine.
SONiX TECHNOLOGY CO., LTD Page 71 Version 1.5
Page 72
SN8P26L38
B0BCLR
FTC1IEN
; Disable TC1 interrupt service
B0BCLR
FTC1ENB
; Disable TC1 timer
MOV
A, #20H
;
B0MOV
TC1M, A
; Set TC1 clock = Fcpu / 64
MOV
A, #74H
; Set TC1C initial value = 74H
B0MOV
TC1C, A
; Set TC1 interval = 10 ms
B0BSET
FTC1IEN
; Enable TC1 interrupt service
B0BCLR
FTC1IRQ
; Clear TC1 interrupt request flag
B0BSET
FTC1ENB
; Enable TC1 timer
B0BSET
FGIE
; Enable GIE
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FTC1IRQ
; Check TC1IRQ
JMP
EXIT_INT
; TC1IRQ = 0, exit interrupt vector
B0BCLR
FTC1IRQ
; Reset TC1IRQ
MOV
A, #74H
B0MOV
TC1C, A
; Reset TC1C.
… ; TC1 interrupt service routine
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.10 TC1 INTERRUPT OPERATION
When the TC1C counter overflows, the TC1IRQ will be set to “1” no matter the TC1IEN is enable or disable. If the
TC1IEN and the trigger event TC1IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC1IEN = 0, the trigger event TC1IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC1IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: TC1 interrupt request setup.
Example: TC1 interrupt service routine.
SONiX TECHNOLOGY CO., LTD Page 72 Version 1.5
Page 73
SN8P26L38
09CH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMP0M
CM0EN
CM0IEN
CM0IRQ
CM0OEN
CM0REF
CM0OUT
CMS1
CMS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
After Reset
0 0 0 0 0 0 0
0
09DH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CMP1M
CM1EN
CM1IEN
CM1IRQ
CM1OEN
CM1REF
CM1OUT
-
-
Read/Write
R/W
R/W
R/W
R/W
R/W R -
-
After Reset
0 0 0 0 0 0 -
-
B0BSET
FCM0IEN
; Enable comparator 0 interrupt service
B0BCLR
FCM0IRQ
; Clear comparator 0 interrupt request flag
B0BSET
FCM0EN
; Enable comparator 0.
B0BSET
FGIE
; Enable GIE
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FCM0IRQ
; Check CM0IRQ
JMP
EXIT_INT
; CM0IRQ = 0, exit interrupt vector
B0BCLR
FCM0IRQ
; Reset CM0IRQ
… ; Comparator 0 interrupt service routine
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.11 COMPARATOR INTERRUPT OPERATION (CMP0, CMP1)
Sonix provides 2 sets comparator with interrupt function in the micro-controller. The comparator interrupt trigger edge
direction is the rising edge of comparator output . When the comparator output status transition occurs, the comparator
interrupt request flag will be set to “1” no matter the comparator interrupt control bit status. The comparator interrupt
flag doesn’t active only when comparator control bit is disabled. When comparator interrupt control bit is enabled and
comparator interrupt edge trigger is occurring, the program counter will jump to the interrupt vector (ORG 8) and
execute interrupt service routine.
Bit 6 CM0IEN: Comparator 0 interrupt function control bit.
0 = Disable.
1 = Enable.
Bit 5 CM0IRQ: Comparator 0 interrupt request bit.
0 = Non comparator interrupt request.
1 = Announce comparator interrupt request.
Bit 6 CM1IEN: Comparator 1 interrupt function control bit.
0 = Disable.
1 = Enable.
Bit 5 CM1IRQ: Comparator 1 interrupt request bit.
0 = Non comparator interrupt request.
1 = Announce comparator interrupt request.
Example: Setup comparator 0 interrupt request.
Example: Comparator 0 interrupt service routine.
SONiX TECHNOLOGY CO., LTD Page 73 Version 1.5
Page 74
SN8P26L38
B0BSET
FSIOIEN
; Enable SIO interrupt service
B0BCLR
FSIOIRQ
; Clear SIO interrupt request flag
B0BSET
FGIE
; Enable GIE
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FSIOIRQ
; Check SIOIRQ
JMP
EXIT_INT
; SIOIRQ = 0, exit interrupt vector
B0BCLR
FSIOIRQ
; Reset SIOIRQ
… ; SIO interrupt service routine
… EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.12 SIO INTERRUPT OPERATION
When the SIO converting successfully, the SIOIRQ will be set to “1” no matter the SIOIEN is enable or disable. If the
SIOIEN and the trigger event SIOIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
SIOIEN = 0, the trigger event SIOIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the SIOIEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
Example: SIO interrupt request setup.
Example: SIO interrupt service routine.
SONiX TECHNOLOGY CO., LTD Page 74 Version 1.5
Page 75
SN8P26L38
B0BSET
FRXIEN
; Enable UART receive interrupt service
B0BCLR
FRXIRQ
; Clear UART receive interrupt request flag
B0BSET
FTXIEN
; Enable UART transmit interrupt service
B0BCLR
FTXIRQ
; Clear UART transmit interrupt request flag
B0BSET
FGIE
; Enable GIE
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
B0BTS1
FRXIRQ
; Check RXIRQ
JMP
EXIT_INT
; RXIRQ = 0, exit interrupt vector
B0BCLR
FRXIRQ
; Reset RXIRQ
… ; UART receive interrupt service routine
… EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.13 UART INTERRUPT OPERATION
When the UART transmitter successfully, the RXIRQ/TXIRQ will be set to “1” no matter the RXIEN/TXIEN is enable or
disable. If the RXIEN/TXIEN and the trigger event RXIRQ/TXIRQ is set to be “1”. As the result, the system will
execute the interrupt vector. If the RXIEN/TXIEN = 0, the trigger event RXIRQ/TXIRQ is still set to be “1”. Moreover,
the system won’t execute interrupt vector even when the RXIEN/TXIEN is set to be “1”. Users need to be cautious with
the operation under multi-interrupt situation.
Example: UART receive and transmit interrupt request setup.
Example: UART receive interrupt service routine.
SONiX TECHNOLOGY CO., LTD Page 75 Version 1.5
Page 76
SN8P26L38
Interrupt Name
Trigger Event Description
P00IRQ
P0.0 trigger controlled by PEDGE
P01IRQ
P0.1 falling edge trigger.
T0IRQ
T0C overflow
T1IRQ
T1C overflow
TC1IRQ
TC1C overflow
SIOIRQ
SIO transmitter successfully.
CM0IRQ
Comparator 0 output level transition.
CM1IRQ
Comparator 1 output level transition.
RXIRQ/TXIRQ
UART transmitter successfully.
ORG
8
; Interrupt vector
JMP
INT_SERVICE
INT_SERVICE:
…
; Push routine to save ACC and PFLAG to buffers.
INTP00CHK:
; Check INT0 interrupt request
B0BTS1
FP00IEN
; Check P00IEN
JMP
INTT0CHK
; Jump check to next interrupt
B0BTS0
FP00IRQ
; Check P00IRQ
JMP
INTP00
INTT0CHK:
; Check T0 interrupt request
B0BTS1
FT0IEN
; Check T0IEN
JMP
INTTC1CHK
; Jump check to next interrupt
B0BTS0
FT0IRQ
; Check T0IRQ
JMP
INTT0
; Jump to T0 interrupt service routine
INTTC1CHK:
; Check TC1 interrupt request
B0BTS1
FTC1IEN
; Check TC1IEN
JMP
INTSIOHK
; Jump check to next interrupt
B0BTS0
FTC1IRQ
; Check TC1IRQ
JMP
INTTC1
; Jump to TC1 interrupt service routine
INTSIOHK:
; Check SIO interrupt request
B0BTS1
FSIOIEN
; Check SIOIEN
JMP
…
; Jump check to next interrupt
B0BTS0
FSIOIRQ
; Check SIOIRQ
JMP
INTSIO
; Jump to SIO interrupt service routine
…
…
INT_EXIT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI
; Exit interrupt vector
8-Bit Micro-Controller
6.14 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
Example: Check the interrupt request under multi-interrupt operation
SONiX TECHNOLOGY CO., LTD Page 76 Version 1.5
Page 77
SN8P26L38
I/O Pin
Shared Pin
Shared Pin Control Condition
Name
Type
Name
Type
P0.0
I/O
INT0
DC
P00IEN=1
P0.1
IO
INT1
DC
P01IEN=1
P0.2
I
RST
DC
Reset_Pin code option = Reset
VPP
HV
OTP Programming
P0.3
I/O
XIN
AC
High_CLK code option = IHRC_RTC, RC, 32K, 4M, 8M
P0.4
I/O
XOUT
AC
High_CLK code option = IHRC_RTC, 32K, 4M, 8M
P2.2
I/O
CM0N
AC
CM0EN=1
P2.3
I/O
CM0P
AC
CM0EN=1, CM0REF=0
P2.4
I/O
CM0O
AC
CM0EN=1, CM0OEN=1
P2.5
I/O
CM1N
AC
CM1EN=1
P2.6
I/O
CM1P
AC
CM1EN=1, CM1REF=0
P2.7
I/O
CM1O
AC
CM1EN=1, CM1OEN=1
P3.2
I/O
URX
DC
URXEN=1.
P3.3
I/O
UTX
DC
UTXEN=1.
P5.0
I/O
SCK
DC
SENB=1.
P5.1
I/O
SI
DC
SENB=1.
P5.2
I/O
SO
DC
SENB=1.
P5.3
I/O
BZ1/PWM1
DC
TC1ENB=1, TC1OUT=1 or PWM1OUT=1
P5.4
I/O
IROUT
DC
IREN=1
8-Bit Micro-Controller
7 I/O PORT
7.1 OVERVIEW
The micro-controller builds in 44 pin I/O. Most of the I/O pins are mixed with analog pins and special function pins. The
I/O shared pin list is as following.
* DC: Digital Characteristic. AC: Analog Characteristic. HV: High Voltage Characteristic.
SONiX TECHNOLOGY CO., LTD Page 77 Version 1.5
Page 78
SN8P26L38
0B8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0M
P07M
P06M
P05M
P04M
P03M
-
P01M
P00M
Read/Write
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
After reset
0 0 0 0 0 - 0
0 0C1H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1M
P17M
P16M
P15M
P14M
P13M
P12M
P11M
P10M
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0C2H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P2M
P27M
P26M
P25M
P24M
P23M
P22M
P21M
P20M
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0C3H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3M
- - - - P33M
P32M
P31M
P30M
Read/Write
- - - - R/W
R/W
R/W
R/W
After reset
- - - - 0 0 0
0 0C4H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P4M
P47M
P46M
P45M
P44M
P43M
P42M
P41M
P40M
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0C5H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P5M
P57M
P56M
P55M
P54M
P53M
P52M
P51M
P50M
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
Note:
1. Users can program them by bit control instructions (B0BSET, B0BCLR).
2. P0.2 is input only pin, and the P0M.2 keeps “1”.
CLR
P0M
; Set all ports to be input mode.
CLR
P1M
CLR
P5M
MOV
A, #0FFH
; Set all ports to be output mode.
B0MOV
P0M, A
B0MOV
P1M, A
B0MOV
P5M, A
B0BCLR
P1M.2
; Set P1.2 to be input mode.
B0BSET
P1M.2
; Set P1.2 to be output mode.
7.2 I/O PORT MODE
The port direction is programmed by PnM register. All I/O ports can select input or output direction.
8-Bit Micro-Controller
Bit[7:0] PnM[7:0]: Pn mode control bits. (n = 0~5).
0 = Pn is input mode.
1 = Pn is output mode.
Example: I/O mode selecting
SONiX TECHNOLOGY CO., LTD Page 78 Version 1.5
Page 79
0E0H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0UR
P07R
P06R
P05R
P04R
P03R
-
P01R
P00R
Read/Write
W W W W W - W
W
After reset
0 0 0 0 0 - 0
0 0E1H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1UR
P17R
P16R
P15R
P14R
P13R
P12R
P11R
P10R
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0 0E2H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P2UR
P27R
P26R
P25R
P24R
P23R
P22R
P21R
P20R
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0 0E3H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3UR
- - - - P33R
P32R
P31R
P30R
Read/Write
- - - - W W W
W
After reset
- - - - 0 0 0
0 0E4H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P4UR
P47R
P46R
P45R
P44R
P43R
P42R
P41R
P40R
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0 0E5H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P5UR
P57R
P56R
P55R
P54R
P53R
P52R
P51R
P50R
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 keeps “1”.
MOV
A, #0FFH
; Enable Port0, 1, 5 Pull-up register,
B0MOV
P0UR, A
; B0MOV
P1UR, A
B0MOV
P5UR, A
7.3 I/O PULL UP REGISTER
SN8P26L38
8-Bit Micro-Controller
Example: I/O Pull up Register
SONiX TECHNOLOGY CO., LTD Page 79 Version 1.5
Page 80
SN8P26L38
U
MCU2
U
VCC
Open-drain pin Open-drain pin
MCU1
Pull-up Resistor
0E9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1OC
P52OC
P51OC
P50OC
P33OC
P32OC
-
P11OC
P10OC
Read/Write
W W W W W - W
W
After reset
0 0 0 0 0 - 0
0
8-Bit Micro-Controller
7.4 I/O OPEN-DRAIN REGISTER
P1.0/P1.1/P3.2/P3.3/P5.0/P5.1/P5.2 built in open-drain function. P1.0/P1.1/P3.2/P3.3/P5.0/P5.1/P5.2 must be set as
output mode when enable open-drain function. Open-drain external circuit is as following.
The pull-up resistor is necessary. Open-drain output high is driven by pull-up resistor. Output low is sunken by MCU’s
pin.
Bit 0 P10OC: P1.0 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Bit 1 P11OC: P1.1 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Bit 3 P32OC: P3.2 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Bit 4 P33OC: P3.3 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Bit 5 P50OC: P5.0 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Bit 6 P51OC: P5.1 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
Bit 7 P52OC: P5.2 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
SONiX TECHNOLOGY CO., LTD Page 80 Version 1.5
Page 81
SN8P26L38
B0BSET
P1.0
; Set P1.0 buffer high.
B0BSET
P10M
; Enable P1.0 output mode.
MOV
A, #01H
; Enable P1.0 open-drain function.
B0MOV
P1OC, A
Note: P1OC is write only register. Setting P10OC must be used “MOV” instructions.
MOV
A, #0
; Disable P1.0 open-drain function.
B0MOV
P1OC, A
Note: After disable P1 open-drain function, P1 mode returns to last I/O mode.
Example: Enable P1.0 to open-drain mode and output high.
Example: Disable P1.0 to open-drain mode and output low.
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 81 Version 1.5
Page 82
0D0H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P0
P07
P06
P05
P04
P03
P02
P01
P00
Read/Write
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0D1H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P1
P17
P16
P15
P14
P13
P12
P11
P10
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0D2H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P2
P27
P26
P25
P24
P23
P22
P21
P20
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0D3H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P3
- - - - P33
P32
P31
P30
Read/Write
- - - - R/W
R/W
R/W
R/W
After reset
- - - - 0 0 0
0 0D4H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P4
P47
P46
P45
P44
P43
P42
P41
P40
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0D5H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
P5
P57
P56
P55
P54
P53
P52
P51
P50
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
Note: The P02 keeps “1” when external reset enable by code option.
B0MOV
A, P0
; Read data from Port 0
B0MOV
A, P1
; Read data from Port 1
B0MOV
A, P5
; Read data from Port 5
MOV
A, #0FFH
; Write data FFH to all Port.
B0MOV
P0, A
B0MOV
P1, A
B0MOV
P5, A
B0BSET
P1.3
; Set P1.3 and P5.4 to be “1”.
B0BSET
P5.4
B0BCLR
P1.3
; Set P1.3 and P5.4 to be “0”.
B0BCLR
P5.4
7.5 I/O PORT DATA REGISTER
SN8P26L38
8-Bit Micro-Controller
Example: Read data from input port.
Example: Write data to output port.
Example: Write one bit data to output port.
SONiX TECHNOLOGY CO., LTD Page 82 Version 1.5
Page 83
SN8P26L38
VDD
Internal Low RC Freq.
Watchdog Overflow Time
3V
10KHz
819.2ms
0CCH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTR
WDTR7
WDTR6
WDTR5
WDTR4
WDTR3
WDTR2
WDTR1
WDTR0
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
Main:
MOV
A, #5AH
; Clear the watchdog timer.
B0MOV
WDTR, A
… …
CALL
SUB1
CALL
SUB2
…
…
JMP
MAIN
8-Bit Micro-Controller
8 TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator (10KHz @3V).
Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).
The watchdog timer has three operating options controlled “WatchDog” code option.
Disable: Disable watchdog timer function.
Enable: Enable watchdog timer function. Watchdog timer actives in normal mode and slow mode. In power down
mode and green mode, the watchdog timer stops.
Always_On: Enable watchdog timer function. The watchdog timer actives and not stop in power down mode and
green mode.
In high noisy environment, the “Always_On” option of watchdog operations is the strongly recommendation
to make the system reset under error situations and re-start again.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
SONiX TECHNOLOGY CO., LTD Page 83 Version 1.5
Page 84
SN8P26L38
Main:
@RST_WDT
; Clear the watchdog timer.
…
…
CALL
SUB1
CALL
SUB2
… …
JMP
MAIN
Main:
… ; Check I/O.
…
; Check RAM
Err:
JMP $
; I/O or RAM error. Program jump here and don’t
; clear watchdog. Wait watchdog timer overflow to reset IC.
Correct:
; I/O and RAM are correct. Clear watchdog timer and
; execute program.
MOV
A, #5AH
; Clear the watchdog timer.
B0MOV
WDTR, A
…
CALL
SUB1
CALL
SUB2
… … …
JMP
MAIN
8-Bit Micro-Controller
Example: Clear watchdog timer by @RST_WDT macro.
Watchdog timer application note is as following.
Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
SONiX TECHNOLOGY CO., LTD Page 84 Version 1.5
Page 85
SN8P26L38
Fcpu
T0 Rate
(Fcpu/2~Fcpu/256)
T0ENB
CPUM0,1
T0C 8-Bit Binary Up Counting Counter
T0 Time Out
Load
Internal Data Bus
T0ENB
RTC
T0TB
Note:1. In RTC mode, clear T0IRQ must be after 1/2 RTC clock source (32768Hz), or the RTC interval time
is error. The delay is about 16us and use T0 interrupt service routine executing time to be the
16us delay time.
2. In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts.
8-Bit Micro-Controller
8.2 TIMER 0 (T0)
8.2.1 OVERVIEW
The T0 is an 8-bit binary up timer and event counter. If T0 timer occurs an overflow (from FFH to 00H), it will continue
counting and issue a time-out signal to trigger T0 interrupt to request interrupt service.
The main purposes of the T0 timer is as following.
8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
RTC timer: Generates interrupts at real time intervals based on the selected clock source. RTC function is only
available in High_Clk code option = "IHRC_RTC".
Green mode wakeup function: T0 can be green mode wake-up time as T0ENB = 1. System will be wake-up by
T0 time out.
SONiX TECHNOLOGY CO., LTD Page 85 Version 1.5
Page 86
0D8H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0M
T0ENB
T0rate2
T0rate1
T0rate0
- - -
T0TB
Read/Write
R/W
R/W
R/W
R/W - - - R/W
After reset
0 0 0 0 - - -
0
Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec.
8.2.2 T0M MODE REGISTER
Bit 0 T0TB: RTC clock source control bit.
0 = Disable RTC (T0 clock source from Fcpu).
1 = Enable RTC.
Bit [6:4] T0RATE[2:0]: T0 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7 T0ENB: T0 counter control bit.
0 = Disable T0 timer.
1 = Enable T0 timer.
SN8P26L38
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 86 Version 1.5
Page 87
SN8P26L38
0D9H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0C
T0C7
T0C6
T0C5
T0C4
T0C3
T0C2
T0C1
T0C0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
The basic timer table interval time of T0.
T0RATE
T0CLOCK
High speed mode (Fcpu = 4MHz / 4)
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval
One step = max/256
Max overflow interval
One step = max/256
000
Fcpu/256
65.536 ms
256 us
8000 ms
31250 us
001
Fcpu/128
32.768 ms
128 us
4000 ms
15625 us
010
Fcpu/64
16.384 ms
64 us
2000 ms
7812.5 us
011
Fcpu/32
8.192 ms
32 us
1000 ms
3906.25 us
100
Fcpu/16
4.096 ms
16 us
500 ms
1953.125 us
101
Fcpu/8
2.048 ms
8 us
250 ms
976.563 us
110
Fcpu/4
1.024 ms
4 us
125 ms
488.281 us
111
Fcpu/2
0.512 ms
2 us
62.5 ms
244.141 us
Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in
RTC mode.
8-Bit Micro-Controller
8.2.3 T0C COUNTING REGISTER
T0C is an 8-bit counter register for T0 interval time control.
The equation of T0C initial value is as following.
T0C initial value = 256 - (T0 interrupt interval time * input clock)
Example: To set 10ms interval time for T0 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select
T0RATE=010 (Fcpu/64).
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10-2 * 4 * 106 / 4 / 64)
= 100
= 64H
SONiX TECHNOLOGY CO., LTD Page 87 Version 1.5
Page 88
SN8P26L38
B0BCLR
FT0ENB
; T0 timer.
B0BCLR
FT0IEN
; T0 interrupt function is disabled.
B0BCLR
FT0IRQ
; T0 interrupt request flag is cleared.
MOV
A, #0xxx0000b
;The T0 rate control bits exist in bit4~bit6 of T0M. The
; value is from x000xxxxb~x111xxxxb.
B0MOV
T0M,A
; T0 timer is disabled.
B0BCLR
FT0TB
; Select T0 Fcpu clock source.
or
B0BSET
FT0TB
; Select T0 RTC clock source.
MOV
A,#7FH
B0MOV
T0C,A
; Set T0C value.
B0BSET
FT0IEN
; Enable T0 interrupt function.
B0BSET
FT0ENB
; Enable T0 timer.
8.2.4 T0 TIMER OPERATION SEQUENCE
T0 timer operation sequence of setup T0 timer is as following.
Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag.
Set T0 timer rate.
Set T0 clock source from Fcpu or RTC.
Set T0 interrupt interval time.
8-Bit Micro-Controller
Set T0 timer function mode.
Enable T0 timer.
SONiX TECHNOLOGY CO., LTD Page 88 Version 1.5
Page 89
SN8P26L38
Fcpu
T1 Rate
(Fcpu/2~Fcpu/256)
T1ENB
CPUM0,1
T1C
16-Bit Binary Up Counting Counter
T1 Time Out
T1CH T1CL
Read/Write T1CH Register
0A0H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1M
T1ENB
T1RATE2
T1RATE1
T1RATE0
- - -
-
Read/Write
R/W
R/W
R/W
R/W - - - -
After reset
0 0 0 0 - - -
-
8-Bit Micro-Controller
8.3 TIMER 1 (T1)
8.3.1 OVERVIEW
The T1 is an 16-bit binary up timer. If T1 timer occurs an overflow (from FFFFH to 0000H), it will continue counting and
issue a time-out signal to trigger T1 interrupt to request interrupt service.
The main purposes of the T1 timer is as following.
16-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
8.3.2 T1M MODE REGISTER
Bit 7 T1ENB: T1 counter control bit.
0 = Disable T1 timer.
1 = Enable T1 timer.
Bit [6:4] T1RATE[2:0]: T1 timer internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
SONiX TECHNOLOGY CO., LTD Page 89 Version 1.5
Page 90
SN8P26L38
0A1H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1CL
T1CL7
T1CL6
T1CL5
T1CL4
T1CL3
T1CL2
T1CL1
T1CL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0 0A2H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1CH
T1CH7
T1CH6
T1CH5
T1CH4
T1CH3
T1CH2
T1CH1
T1CH0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
The basic timer table interval time of T1.
T1RATE
T1CLOCK
High speed mode (Fcpu = 4MHz / 4)
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval
One step = max/256
Max overflow interval
One step = max/256
000
Fcpu/256
16.777 s
256 us
2048 s
31250 us
001
Fcpu/128
8.388 s
128 us
1024 s
15625 us
010
Fcpu/64
4.194 s
64 us
512 s
7812.5 us
011
Fcpu/32
2.097 s
32 us
256 s
3906.25 us
100
Fcpu/16
1.048 s
16 us
128 s
1953.125 us
101
Fcpu/8
524.288 ms
8 us
64 s
976.563 us
110
Fcpu/4
262.144 ms
4 us
31 s
488.281 us
111
Fcpu/2
131.072 ms
2 us
16 s
244.141 us
8-Bit Micro-Controller
8.3.3 T1CH, T1CL COUNTING REGISTER
T1C is an 16-bit counter register for T1 interval time control. T1CH is high byte of T1C. T1CL is low byte of T1C.
The equation of T1C [T1CH, T1CL] initial value is as following.
T1C initial value = 65536 - (T1 interrupt interval time * input clock)
Example: To set 10ms interval time for T1 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select
T1RATE=010 (Fcpu/64).
T1C initial value = 65536 - (T1 interrupt interval time * input clock)
= 65536 - (10ms * 4MHz / 4 / 64)
= 65536 - (10-2 * 4 * 106 / 4 / 64)
= 65380
= FF64H ;T1CH=0xFF, T1CL=0x64
SONiX TECHNOLOGY CO., LTD Page 90 Version 1.5
Page 91
SN8P26L38
B0MOV
A, T1CH
; Read T1CH first and T1C low byte data exported to T1CL.
…
B0MOV
A, T1CL
; Read T1CL data from buffer.
…
Note: Read T1CH first when reading T1C 16-bit buffer.
…
B0MOV
T1CL, A
; Write T1CL data into T1CL buffer first.
…
B0MOV
T1CH, A
; Write T1CH data and T1CH, T1CL are imported to T1C
; 16-bit buffer.
Note: Write T1CL first when writing T1C 16-bit buffer.
MOV
A, #0
B0MOV
T1CL, A
; Write “0” into T1CL to clear T1CL.
…
B0MOV
T1CH, A
; Write T1CH data and T1CH, T1CL are imported to T1C
; 16-bit buffer.
Note: Don’t clear T1CL by “CLR” instruction.
8-Bit Micro-Controller
The T1 16-bit counter buffer is T1CH and T1CL combination. System provides a routine to process the 16-bit data
buffer under 8-bit situation to make high/low bytes of 16-bit data processed at the same time. T1CH register is the key
to control the T1 16-bit counter buffer processed through T1CH, T1CL buffers. Export T1C 16-bit buffer data to T1CH,
T1CL registers is by reading T1CH register. Import T1C 16-bit buffer data from T1CH, T1CL registers is by writing
T1CH register after setting T1CL register data.
Example: Reading T1C 16-bit buffer data is controlled by reading T1CH register. Read T1CH register data
and low byte data of T1C 16-bit buffer exporting to T1CL register at the same time.
Example: Writing and setting T1C 16-bit buffer data is controlled by writing data into T1CH register. When
writing T1CH register data, T1CH, T1CL data are imported into T1C 16-bit buffer at the same time. Setting
T1CL register data first is necessary, or the T1C low byte data would be error.
Example: Write T1CL is by write T1CH. Only executing “CLR T1CL” and no do any T1CH writing operation
can’t clear T1CL buffer. Clear T1CL must be using “MOV” instruction as following.
SONiX TECHNOLOGY CO., LTD Page 91 Version 1.5
Page 92
SN8P26L38
B0BCLR
FT1ENB
; T1 timer.
B0BCLR
FT1IEN
; T1 interrupt function is disabled.
B0BCLR
FT1IRQ
; T1 interrupt request flag is cleared.
MOV
A, #0xxx0000b
;The T1 rate control bits exist in bit4~bit6 of T1M. The
; value is from x000xxxxb~x111xxxxb.
B0MOV
T1M,A
; T1 timer is disabled.
MOV
A,#7FH
B0MOV
T1CL,A
; Set T1CL value.
MOV
A,#7FH
B0MOV
T1CH,A
; Set T1CH value.
B0BSET
FT1IEN
; Enable T1 interrupt function.
B0BSET
FT1ENB
; Enable T1 timer.
8.3.4 T1 TIMER OPERATION SEQUENCE
T1 timer operation sequence of setup T1 timer is as following.
Stop T1 timer counting, disable T1 interrupt function and clear T1 interrupt request flag.
Set T1 timer rate.
Set T1 interrupt interval time.
8-Bit Micro-Controller
Set T1 timer function mode.
Enable T1 timer.
SONiX TECHNOLOGY CO., LTD Page 92 Version 1.5
Page 93
SN8P26L38
Fcpu
TC1 Rate
(Fcpu/2~Fcpu/256)
INT1
(Schmitter Trigger)
TC1CKS TC1ENB
CPUM0,1
TC1C
8-Bit Binary Up
Counting Counter
TC1R Reload
Data Buffer
Up Counting
Reload Value
TC1 Time Out
Compare
ALOAD1
R
S
TC1 Time Out
Auto. Reload
TC1 / 2
Buzzer
Internal P5.3 I/O Circuit
P5.3
PWM
PWM1OUT
TC1OUT
ALOAD1, TC1OUT
Load
8-Bit Micro-Controller
8.4 TIMER/COUNTER 0 (TC1)
8.4.1 OVERVIEW
The TC1 is an 8-bit binary up counting timer with double buffers. TC1 has two clock sources including internal clock
and external clock for counting a precision time. The internal clock source is from Fcpu. The external clock is INT1 from
P0.1 pin (Falling edge trigger). Using TC1M register selects TC1C’s clock source from internal or external. If TC1 timer
occurs an overflow, it will continue counting and issue a time-out signal to trigger TC1 interrupt to request interrupt
service. TC1 overflow time is 0xFF to 0X00 normally. Under PWM mode, TC1 overflow is decided by PWM cycle
controlled by ALOAD1 and TC1OUT bits.
The main purposes of the TC1 timer is as following.
8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
External event counter: Counts system “events” based on falling edge detection of external clock signals at the
INT1 input pin.
Buzzer output
PWM output
SONiX TECHNOLOGY CO., LTD Page 93 Version 1.5
Page 94
SN8P26L38
0DCH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1M
TC1ENB
TC1rate2
TC1rate1
TC1rate0
TC1CKS
ALOAD1
TC1OUT
PWM1OUT
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1
interrupt request will be raised. (P0.1IRQ will be always 0).
8.4.2 TC1M MODE REGISTER
Bit 0 PWM1OUT: PWM output control bit.
0 = Disable PWM output.
1 = Enable PWM output. PWM duty controlled by TC1OUT, ALOAD1 bits.
Bit 1 TC1OUT: TC1 time out toggle signal output control bit. Only valid when PWM1OUT = 0.
0 = Disable, P5.3 is I/O function.
1 = Enable, P5.3 is output TC1OUT signal.
Bit 2 ALOAD1: Auto-reload control bit. Only valid when PWM1OUT = 0.
0 = Disable TC1 auto-reload function.
1 = Enable TC1 auto-reload function.
Bit 3 TC1CKS: TC1 clock source select bit.
0 = Internal clock (Fcpu or Fosc).
1 = External clock from P0.1/INT1 pin.
Bit [6:4] TC1RATE[2:0]: TC1 internal clock select bits.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
Bit 7 TC1ENB: TC1 counter control bit.
0 = Disable TC1 timer.
1 = Enable TC1 timer.
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 94 Version 1.5
Page 95
SN8P26L38
0DDH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1C
TC1C7
TC1C6
TC1C5
TC1C4
TC1C3
TC1C2
TC1C1
TC1C0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
After reset
0 0 0 0 0 0 0
0
TC1CKS
PWM1
ALOAD1
TC1OUT
N
TC1C valid
value
TC1C value
binary type
Remark
0
0 x x
256
0x00~0xFF
00000000b~11111111b
Overflow per 256 count
1 0 0
256
0x00~0xFF
00000000b~11111111b
Overflow per 256 count
1 0 1
64
0x00~0x3F
xx000000b~xx111111b
Overflow per 64 count
1 1 0
32
0x00~0x1F
xxx00000b~xxx11111b
Overflow per 32 count
1 1 1
16
0x00~0x0F
xxxx0000b~xxxx1111b
Overflow per 16 count
1 - - - 256
0x00~0xFF
00000000b~11111111b
Overflow per 256 count
The basic timer table interval time of TC1.
TC1RATE
TC1CLOCK
High speed mode (Fcpu = 4MHz / 4)
Low speed mode (Fcpu = 32768Hz / 4)
Max overflow interval
One step = max/256
Max overflow interval
One step = max/256
000
Fcpu/256
65.536 ms
256 us
8000 ms
31250 us
001
Fcpu/128
32.768 ms
128 us
4000 ms
15625 us
010
Fcpu/64
16.384 ms
64 us
2000 ms
7812.5 us
011
Fcpu/32
8.192 ms
32 us
1000 ms
3906.25 us
100
Fcpu/16
4.096 ms
16 us
500 ms
1953.125 us
101
Fcpu/8
2.048 ms
8 us
250 ms
976.563 us
110
Fcpu/4
1.024 ms
4 us
125 ms
488.281 us
111
Fcpu/2
0.512 ms
2 us
62.5 ms
244.141 us
8-Bit Micro-Controller
8.4.3 TC1C COUNTING REGISTER
TC1C is an 8-bit counter register for TC1 interval time control.
The equation of TC1C initial value is as following.
TC1C initial value = N - (TC1 interrupt interval time * input clock)
N is TC1 overflow boundary number. TC1 timer overflow time has six types (TC1 timer, TC1 event counter, TC1 Fcpu
clock source, TC1 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time
and valid value as follow table.
Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM
output (PWM1=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).
TC1C initial value = N - (TC1 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10-2 * 4 * 106 / 4 / 64)
= 100
= 64H
SONiX TECHNOLOGY CO., LTD Page 95 Version 1.5
Page 96
SN8P26L38
Note: Under PWM mode, auto-load is enabled automatically. The ALOAD1 bit is selecting overflow
boundary.
0DEH
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TC1R
TC1R7
TC1R6
TC1R5
TC1R4
TC1R3
TC1R2
TC1R1
TC1R0
Read/Write
W W W W W W W
W
After reset
0 0 0 0 0 0 0
0
TC1CKS
PWM1
ALOAD1
TC1OUT
N
TC1R valid
value
TC1R value
binary type
0
0 x x
256
0x00~0xFF
00000000b~11111111b
1 0 0
256
0x00~0xFF
00000000b~11111111b
1 0 1
64
0x00~0x3F
xx000000b~xx111111b
1 1 0
32
0x00~0x1F
xxx00000b~xxx11111b
1 1 1
16
0x00~0x0F
xxxx0000b~xxxx1111b
1 - - - 256
0x00~0xFF
00000000b~11111111b
8-Bit Micro-Controller
8.4.4 TC1R AUTO-LOAD REGISTER
TC1 timer is with auto-load function controlled by ALOAD1 bit of TC1M. When TC1C overflow occurring, TC1R value
will load to TC1C by system. It is easy to generate an accurate time, and users don’t reset TC1C during interrupt
service routine.
TC1 is double buffer design. If new TC1R value is set by program, the new value is stored in 1st buffer. Until TC1
overflow occurs, the new value moves to real TC1R buffer. This way can avoid TC1 interval time error and glitch in
PWM and Buzzer output.
The equation of TC1R initial value is as following.
TC1R initial value = N - (TC1 interrupt interval time * input clock)
N is TC1 overflow boundary number. TC1 timer overflow time has six types (TC1 timer, TC1 event counter, TC1 Fcpu
clock source, TC1 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time
and valid value as follow table.
Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM
output (PWM1=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).
TC1R initial value = N - (TC1 interrupt interval time * input clock)
= 256 - (10ms * 4MHz / 4 / 64)
= 256 - (10-2 * 4 * 106 / 4 / 64)
= 100
= 64H
SONiX TECHNOLOGY CO., LTD Page 96 Version 1.5
Page 97
SN8P26L38
1 2 3 4
1 2 3 4
TC1 Overflow Clock
TC1OUT (Buzzer) Output Clock
MOV
A,#01100000B
B0MOV
TC1M,A
; Set the TC1 rate to Fcpu/4
MOV
A,#131
; Set the auto-reload reference value
B0MOV
TC1C,A
B0MOV
TC1R,A
B0BSET
FTC1OUT
; Enable TC1 output to P5.3 and disable P5.3 I/O function
B0BSET
FALOAD1
; Enable TC1 auto-reload function
B0BSET
FTC1ENB
; Enable TC1 timer
Note: Buzzer output is enable, and “PWM1OUT” must be “0”.
8-Bit Micro-Controller
8.4.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)
Buzzer output (TC1OUT) is from TC1 timer/counter frequency output function. By setting the TC1 clock frequency, the
clock signal is output to P5.3 and the P5.3 general purpose I/O function is auto-disable. The TC1OUT frequency is
divided by 2 from TC1 interval time. TC1OUT frequency is 1/2 TC1 frequency. The TC1 clock has many combinations
and easily to make difference frequency. The TC1OUT frequency waveform is as following.
Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. Fcpu
= Fosc/4 = 1MIPS. The TC1OUT frequency is 1KHz. Because the TC1OUT signal is divided by 2, set the
TC1 clock to 2KHz. The TC1 clock source is from external oscillator clock. TC1 rate is Fcpu/4. The
TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 131.
SONiX TECHNOLOGY CO., LTD Page 97 Version 1.5
Page 98
SN8P26L38
B0BCLR
FTC1ENB
; TC1 timer, TC1OUT and PWM stop.
B0BCLR
FTC1IEN
; TC1 interrupt function is disabled.
B0BCLR
FTC1IRQ
; TC1 interrupt request flag is cleared.
MOV
A, #0xxx0000b
;The TC1 rate control bits exist in bit4~bit6 of TC1M. The
; value is from x000xxxxb~x111xxxxb.
B0MOV
TC1M,A
; TC1 interrupt function is disabled.
; Select TC1 internal / external clock source.
B0BCLR
FTC1CKS
; Select TC1 internal clock source.
or
B0BSET
FTC1CKS
; Select TC1 external clock source.
B0BCLR
FALOAD1
; Enable TC1 auto reload function.
or
B0BSET
FALOAD1
; Disable TC1 auto reload function.
; Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty.
MOV
A,#7FH
; TC1C and TC1R value is decided by TC1 mode.
B0MOV
TC1C,A
; Set TC1C value.
B0MOV
TC1R,A
; Set TC1R value under auto reload mode or PWM mode.
; In PWM mode, set PWM cycle.
B0BCLR
FALOAD1
; ALOAD1, TC1OUT = 00, PWM cycle boundary is
B0BCLR
FTC1OUT
; 0~255.
or
B0BCLR
FALOAD1
; ALOAD1, TC1OUT = 01, PWM cycle boundary is
B0BSET
FTC1OUT
; 0~63.
or
B0BSET
FALOAD1
; ALOAD1, TC1OUT = 10, PWM cycle boundary is
B0BCLR
FTC1OUT
; 0~31.
or
B0BSET
FALOAD1
; ALOAD1, TC1OUT = 11, PWM cycle boundary is
B0BSET
FTC1OUT
; 0~15.
B0BSET
FTC1IEN
; Enable TC1 interrupt function.
or
B0BSET
FTC1OUT
; Enable TC1OUT (Buzzer) function.
or
B0BSET
FPWM1OUT
; Enable PWM function.
B0BSET
FTC1ENB
; Enable TC1 timer.
8-Bit Micro-Controller
8.4.6 TC1 TIMER OPERATION SEQUENCE
TC1 timer operation includes timer interrupt, event counter, TC1OUT and PWM. The sequence of setup TC1 timer is
as following.
Stop TC1 timer counting, disable TC1 interrupt function and clear TC1 interrupt request flag.
Set TC1 timer rate. (Besides event counter mode.)
Set TC1 timer clock source.
Set TC1 timer auto-load mode.
Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty cycle.
Set TC1 timer function mode.
Enable TC1 timer.
SONiX TECHNOLOGY CO., LTD Page 98 Version 1.5
Page 99
SN8P26L38
ALOAD1
TC1OUT
PWM duty range
TC1C valid value
TC1R valid bits value
MAX. PWM
Frequency
(Fcpu = 4MHz)
Remark
0 0 0/256~255/256
0x00~0xFF
0x00~0xFF
7.8125K
Overflow per 256 count
0 1 0/64~63/64
0x00~0x3F
0x00~0x3F
31.25K
Overflow per 64 count
1 0 0/32~31/32
0x00~0x1F
0x00~0x1F
62.5K
Overflow per 32 count
1 1 0/16~15/16
0x00~0x0F
0x00~0x0F
125K
Overflow per 16 count
TC1 Clock
TC1R=00H
TC1R=01H
TC1R=80H
TC1R=FFH
0 1 128 254 255
…… ……
0 1 128 254 255
…… ……
Low
Low
Low
High
High
Low
High
8-Bit Micro-Controller
8.5 PWM1 MODE
8.5.1 OVERVIEW
PWM function is generated by TC1 timer counter and output the PWM signal to PWM1OUT pin (P5.3). The 8-bit
counter counts modulus 256, 64, 32, 16 controlled by ALOAD1, TC1OUT bits. The value of the 8-bit counter (TC1C) is
compared to the contents of the reference register (TC1R). When the reference register value (TC1R) is equal to the
counter value (TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The
low-to-high ratio (duty) of the PWM1 output is TC1R/256, 64, 32, 16.
The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256.
SONiX TECHNOLOGY CO., LTD Page 99 Version 1.5
Page 100
SN8P26L38
TC1C Value
PWM1 Output
(Duty Range 0~255)
PWM1 Output
(Duty Range 0~63)
PWM1 Output
(Duty Range 0~31)
PWM1 Output
(Duty Range 0~15)
TC1 Overflow,
TC1IRQ = 1
0xFF
0x00
8-Bit Micro-Controller
8.5.2 TC1IRQ AND PWM DUTY
In PWM mode, the frequency of TC1IRQ is depended on PWM duty range. From following diagram, the TC1IRQ
frequency is related with PWM duty.
SONiX TECHNOLOGY CO., LTD Page 100 Version 1.5
Loading...