SONIX SN8P2624, SN8P26L00 Series, SN8P26L34, SN8P26L32, SN8P26L321 User Manual

SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 1 Version 0.3

SN8P2624

USER’S MANUAL

Preliminary Specification Version 0.3

SN8P2624

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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.

SN8P2624

8-Bit Micro-Controller

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AMENDENT HISTORY

Version Date Description

VER 0.1 Jan. 2005 First issue

Apr. 2005 Remove SN8P26242 part number. VER 0.2 Nov.2005 1. ADD Brown-Out reset circuit.

2. Working Voltage vs. Frequency graphs.

VER 0.3 Nov 2005 1. Modify Topr value.

Dec 2005 2. Modify Brown-Out Reset description

3. Remove power consumption(Pc)

4. Remove Noise Filter Enable Working Voltage

5. Remove High clock32K mode

6. Add Fcpu limitation by noise filter.

7. Modify ELECTRICAL CHARACTERISTIC.

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Table of Content

AMENDENT HISTORY................................................................................................................................ 2

1

PRODUCT OVERVIEW......................................................................................................................... 7

1.1 FEATURES........................................................................................................................................ 7

1.2 SYSTEM BLOCK DIAGRAM.......................................................................................................... 8

1.3 PIN ASSIGNMENT........................................................................................................................... 9

1.4 PIN DESCRIPTIONS....................................................................................................................... 10

1.5 PIN CIRCUIT DIAGRAMS............................................................................................................. 11

2

CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 12

2.1 MEMORY MAP............................................................................................................................... 12

2.1.1 PROGRAM MEMORY (ROM) ................................................................................................. 12

2.1.1.1 RESET VECTOR (0000H) .................................................................................................. 13

2.1.1.2 INTERRUPT VECTOR (0008H)......................................................................................... 14

2.1.1.3 LOOK-UP TABLE DESCRIPTION.................................................................................... 16

2.1.1.4 JUMP TABLE DESCRIPTION........................................................................................... 18

2.1.1.5 CHECKSUM CALCULATION........................................................................................... 20

2.1.2 CODE OPTION TABLE........................................................................................................... 21

2.1.3 DATA MEMORY (RAM)........................................................................................................... 22

2.1.4 SYSTEM REGISTER.................................................................................................................23

2.1.4.1 SYSTEM REGISTER TABLE ............................................................................................ 23

2.1.4.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 23

2.1.4.3 BIT DEFINITION of SYSTEM REGISTER....................................................................... 24

2.1.4.4 ACCUMULATOR ............................................................................................................... 25

2.1.4.5 PROGRAM FLAG............................................................................................................... 26

2.1.4.6 PROGRAM COUNTER....................................................................................................... 27

2.1.4.7 H, L REGISTERS................................................................................................................. 30

2.1.4.8 Y, Z REGISTERS................................................................................................................. 31

2.1.4.9 R REGISTERS..................................................................................................................... 32

2.2 ADDRESSING MODE .................................................................................................................... 33

2.2.1 IMMEDIATE ADDRESSING MODE....................................................................................... 33

2.2.2 DIRECTLY ADDRESSING MODE.......................................................................................... 33

2.2.3 INDIRECTLY ADDRESSING MODE...................................................................................... 33

2.3 STACK OPERATION...................................................................................................................... 34

2.3.1 OVERVIEW .............................................................................................................................. 34

2.3.2 STACK REGISTERS.................................................................................................................35

2.3.3 STACK OPERATION EXAMPLE............................................................................................. 36

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3

RESET..................................................................................................................................................... 37

3.1 OVERVIEW..................................................................................................................................... 37

3.2 POWER ON RESET......................................................................................................................... 38

3.3 WATCHDOG RESET...................................................................................................................... 38

3.4 BROWN OUT RESET ..................................................................................................................... 39

3.4.1 BROWN OUT DESCRIPTION................................................................................................. 39

3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION........................................................ 40

3.4.3 BROWN OUT RESET IMPROVEMENT.................................................................................. 40

3.5 EXTERNAL RESET........................................................................................................................ 42

3.6 EXTERNAL RESET CIRCUIT ....................................................................................................... 42

3.6.1 Simply RC Reset Circuit........................................................................................................... 42

3.6.2 Diode & RC Reset Circuit........................................................................................................43

3.6.3 Zener Diode Reset Circuit........................................................................................................ 43

3.6.4 Voltage Bias Reset Circuit........................................................................................................ 44

3.6.5 External Reset IC...................................................................................................................... 45

4

SYSTEM CLOCK.................................................................................................................................. 46

4.1 OVERVIEW..................................................................................................................................... 46

4.2 CLOCK BLOCK DIAGRAM .......................................................................................................... 46

4.3 OSCM REGISTER........................................................................................................................... 47

4.4 SYSTEM HIGH CLOCK ................................................................................................................. 48

4.4.1 EXTERNAL HIGH CLOCK...................................................................................................... 48

4.4.1.1 CRYSTAL/CERAMIC......................................................................................................... 49

4.4.1.2 RC......................................................................................................................................... 49

4.4.1.3 EXTERNAL CLOCK SIGNAL........................................................................................... 50

4.5 SYSTEM

LOW CLOCK.................................................................................................................. 51

4.5.1 SYSTEM CLOCK MEASUREMENT........................................................................................ 52

5

SYSTEM OPERATION MODE...........................................................................................................53

5.1 OVERVIEW..................................................................................................................................... 53

5.2 SYSTEM

MODE SWITCHING....................................................................................................... 54

5.3 WAKEUP......................................................................................................................................... 56

5.3.1 OVERVIEW .............................................................................................................................. 56

5.3.2 WAKEUP TIME........................................................................................................................ 56

5.3.3 P1W WAKEUP CONTROL REGISTER................................................................................... 57

6

INTERRUPT........................................................................................................................................... 58

6.1 OVERVIEW..................................................................................................................................... 58

6.2 INTEN INTERRUPT ENABLE REGISTER................................................................................... 59

6.3 INTRQ INTERRUPT REQUEST REGISTER ................................................................................ 60

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6.4 GIE GLOBAL INTERRUPT OPERATION .................................................................................... 60

6.5 PUSH, POP ROUTINE .................................................................................................................... 61

6.6 INT0 (P0.0) INTERRUPT OPERATION......................................................................................... 62

6.7 INT1 (P0.1) INTERRUPT OPERATION......................................................................................... 63

6.8 T0 INTERRUPT OPERATION ....................................................................................................... 64

6.9 TC1 INTERRUPT OPERATION..................................................................................................... 65

6.10 MULTI-INTERRUPT OPERATION............................................................................................... 66

7

I/O PORT................................................................................................................................................ 67

7.1 I/O PORT MODE ............................................................................................................................. 67

7.2 I/O PULL UP REGISTER ................................................................................................................ 68

7.3 I/O OPEN-DRAIN REGISTER........................................................................................................ 69

7.4 I/O PORT DATA REGISTER.......................................................................................................... 70

8

TIMERS .................................................................................................................................................. 71

8.1 WATCHDOG TIMER...................................................................................................................... 71

8.2 TIMER 0 (T0)................................................................................................................................... 73

8.2.1 OVERVIEW .............................................................................................................................. 73

8.2.2 T0M MODE REGISTER........................................................................................................... 73

8.2.3 T0C COUNTING REGISTER................................................................................................... 74

8.2.4 T0 TIMER OPERATION SEQUENCE..................................................................................... 75

8.3 TIMER/COUNTER 0 (TC1) ............................................................................................................ 76

8.3.1 OVERVIEW .............................................................................................................................. 76

8.3.2 TC1M MODE REGISTER........................................................................................................ 77

8.3.3 TC1C COUNTING REGISTER................................................................................................ 78

8.3.4 TC1R AUTO-LOAD REGISTER .............................................................................................. 79

8.3.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER).................................................................. 80

8.3.6 TC1 TIMER OPERATION SEQUENCE .................................................................................. 81

8.4 PWM1

MODE.................................................................................................................................. 82

8.4.1 OVERVIEW .............................................................................................................................. 82

8.4.2 TCxIRQ and PWM Duty........................................................................................................... 83

8.4.3 PWM Duty with TCxR Changing.............................................................................................. 84

8.4.4 PWM PROGRAM EXAMPLE .................................................................................................. 85

9

INSTRUCTION TABLE ....................................................................................................................... 86

1

0

ELECTRICAL CHARACTERISTIC.............................................................................................. 87

10.1 ABSOLUTE

MAXIMUM RATING................................................................................................ 87

10.2 ELECTRICAL CHARACTERISTIC............................................................................................... 87

10.3 CHARACTERISTIC GRAPHS ....................................................................................................... 88

1

OTP PROGRAMMING PIN.............................................................................................................89

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11.1.1 EASY WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT.................................... 89

11.1.2 WRITER V2.5 AND V3.0 TRANSITION BOARD SOCKET PIN ASSIGNMENT .................... 89

11.1.3 PROGRAMMING PIN MAPPING........................................................................................... 90

1

2

PACKAGE INFORMATION ........................................................................................................... 91

12.1 SK-DIP 28 PIN ................................................................................................................................. 91

12.2 SOP 28 PIN....................................................................................................................................... 92

12.3 SSOP 28 PIN..................................................................................................................................... 93

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8-Bit Micro-Controller

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1

PRODUCT OVERVIEW

1.1 FEATURES

) Features Selection Table

Timer

PWM

CHIP ROM RAM Stack

T0 TC1

I/O

Green

Mode

Buzzer

Wakeup

Pin No.

Package

SN8P1604A

4K*16 128 8

V 22

-

V 10

SK-DIP28/SOP28

SN8P2604 4K*16 128 8 V V 24 V V 11 SK-DIP28/SOP28/SSOP28

SN8P26042 4K*16 128 8 V V 16 V V 11 P-DIP20/SOP20/SSOP20

SN8P2624 2K*16 64 8 V V 24 V V 11 SK-DIP28/SOP28/SSOP28

♦

Memory configuration

♦

Two 8-bit Timer/Counter

OTP ROM size: 2K * 16 bits. T0: Basic timer RAM size: 64 * 8 bits. TC1: Auto-reload timer/Counter/PWM1/Buzzer output Eight levels stack buffer

♦

On chip watchdog timer and clock source is internal

♦

I/O pin configuration

low clock RC type (16KHz @3V, 32KHz @5V).

Bi-directional: P0, P1, P2, P5 Input only pin: P0.2

♦

Dual system clocks

Programmable open-drain: P1.0, P1.1

External high clock: RC type up to 10 MHz Wakeup: P0, P1 level change trigger External high clock: Crystal type up to 16 MHz Pull-up resisters: P0, P1, P2, P5 Internal low clock: RC type 16KHz(3V), 32KHz(5V) External Interrupt trigger edge: P0.0 controlled by PEDGE register

♦

Operating modes

P0.1 is falling edge trigger only Normal mode: Both high and low clock active Slow mode: Low clock only ♦

Four interrupt sources

Sleep mode: Both high and low clock stop Two internal interrupts: T0, TC1. Green mode: Periodical wakeup by T0 timer Two external interrupts: INT0, INT1.

♦

Package (Chip form support)

SK-DIP 28 pins ♦

Powerful instructions

SOP 28 pins

One clocks per instruction cycle (1T)

SSOP 28 pins Most of instructions are one cycle only. All ROM area JMP instruction. All ROM area CALL address instruction. All ROM area lookup table function (MOVC)

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1.2 SYSTEM BLOCK DIAGRAM

INTERRUPT

CONTROL

EXTERNAL HIGH OSC.

ACC

INTERNAL

LOW RC

TIMING GENERATOR

RAM

SYSTEM REGISTERS

LVD

(Low Voltage Detector)

WATCHDOG TIMER

TIMER & COUNTER

P0 P5P1

PWM 1

BUZZER 1

ALU

PC

FLAGS

IR

OTP

ROM

PWM1

BUZZER1

P2

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1.3 PIN ASSIGNMENT

SN8P2624K (SK-DIP 28 pins) SN8P2624S (SOP 28 pins) SN8P2624X (SSOP 28 pins)

P0.1/INT1 1 U 28 RST/VPP/P0.2

VDD 2 27 XIN P5.4 3 26 XOUT/Fcpu

VSS 4 25 P2.7

P0.0/INT0 5 24 P2.6

P5.0 6 23 P2.5 P5.1 7 22 P2.4 P5.2 8 21 P2.3

P5.3/BZ1/PWM1 9 20 P2.2

P1.0 10 19 P2.1 P1.1 11 18 P2.0 P1.2 12 17 P1.7 P1.3 13 16 P1.6 P1.4 14 15 P1.5

SN8P2624K SN8P2624S SN8P2624X

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8-Bit Micro-Controller

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1.4 PIN DESCRIPTIONS

PIN NAME TYPE DESCRIPTION

VDD, VSS P Power supply input pins for digital circuit.

P0.2/RST/VPP I, P

P0.2: Input only pin (Schmitt trigger) if disable external reset function.

P0.2 without build-in pull-up resister.

Built-in wakeup function. RST: System reset input pin. Schmitt trigger structure, low active, normal stay to “high”. VPP: OTP programming pin.

XIN I Oscillator input pin while external oscillator enable (crystal and RC).

XOUT/Fcpu I/O

XOUT: Oscillator output pin while external crystal enable. Fcpu: Signal output pin while external RC mode enable.

P0.0/INT0 I/O

Port 0.0 bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Built-in wakeup function. INT0 trigger pin (Schmitt trigger).

P0.1/INT1 I/O

Port 0.1 bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. Built-in wakeup function. INT1 trigger pin (Schmitt trigger). TC1 event counter clock input pin.

P1.0~P1.1 I/O

Port 1.0, P1.1 bi-direction pin and open-drain pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.

P1.2~P1.7 I/O

Port 1.2~P1.7 bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.

P2.0~P2.7 I/O

Bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.

P5.0~P5.2, P5.4 I/O

Port 5 bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters.

P5.3/BZ1/PWM1 I/O

Port 5.3 bi-direction pin. Schmitt trigger structure as input mode. Built-in pull-up resisters. TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin.

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1.5 PIN CIRCUIT DIAGRAMS

Port 0, 1, 2, 5 structure:

Pull-Up

Output

Latch

PnM, PnUR

Input Bus

PnM

Output Bus

Port 1.0, P1.1 structure:

Pull-Up

Output

Latch

PnM, PnUR

Input Bus

PnM

Output Bus

P1OC

Open-Drain

Port 0.2 structure:

Ext. Reset

Code Option

Int. Bus

Int. Rst

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2

CENTRAL PROCESSOR UNIT (CPU)

2.1 MEMORY MAP

2.1.1 PROGRAM MEMORY (ROM)

) 2K words ROM

ROM

0000H

Reset vector

User reset vector

0001H Jump to user start address

. .

0007H

General purpose area

0008H

Interrupt vector

User interrupt vector

0009H User program

.

. 000FH 0010H 0011H

.

03FCH

General purpose area

End of user program 03FDH 03FEH

03FFH

Reserved

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2.1.1.1 RESET VECTOR (0000H)

A one-word vector address area is used to execute system reset.

) Power On Reset (NT0=1, NPD=0). ) Watchdog Reset (NT0=0, NPD=0). ) External Reset (NT0=1, NPD=1).

After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.

¾ Example: Defining Reset Vector

ORG 0 ; 0000H JMP START ; Jump to user program address.

…

ORG 10H

START:

; 0010H, The head of user program. … ; User program …

ENDP ; End of program

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2.1.1.2 INTERRUPT VECTOR (0008H)

A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory.

 Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a

unique buffer and only one level.

¾ Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.

.CODE

ORG 0 ; 0000H

JMP START ; Jump to user program address. …

ORG 8 ; Interrupt vector.

PUSH ; Save ACC and PFLAG register to buffers.

… …

POP ; Load ACC and PFLAG register from buffers.

RETI

; End of interrupt service routine

…

START: ; The head of user program. … ; User program … JMP START ; End of user program …

ENDP ; End of program

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¾ Example: Defining Interrupt Vector. The interrupt service routine is following user program.

.CODE ORG 0 ; 0000H JMP START ; Jump to user program address. …

ORG 8 ; Interrupt vector. JMP MY_IRQ ; 0008H, Jump to interrupt service routine address.

ORG 10H START: ; 0010H, The head of user program. … ; User program. … … JMP START ; End of user program. …

MY_IRQ: ;The head of interrupt service routine.

PUSH ; Save ACC and PFLAG register to buffers.

… …

POP ; Load ACC and PFLAG register from buffers.

RETI ; End of interrupt service routine.

…

ENDP ; End of program.

 Note: It is easy to understand the rules of SONIX program from demo programs given above. These

points are as following:

1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.

2. The address 0008H is interrupt vector.

3. User’s program is a loop routine for main purpose application.

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2.1.1.3 LOOK-UP TABLE DESCRIPTION

In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and high-byte data stored in R register.

¾ Example: To look up the ROM data located “TABLE1”.

B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address B0MOV Z, #TABLE1$L ; To set lookup table1’s low address. MOVC ; To lookup data, R = 00H, ACC = 35H

; Increment the index address for next address. INCMS Z ; Z+1 JMP @F ; Z is not overflow. INCMS Y ; Z overflow (FFH Æ 00), Æ Y=Y+1

NOP ;

;

@@: MOVC ; To lookup data, R = 51H, ACC = 05H. … ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H DW 2012H …

 Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to

0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflows, Y register must be added one. The following INC_YZ macro shows a simple method to process Y and Z registers automatically.

¾ Example: INC_YZ macro.

INC_YZ MACRO INCMS Z ; Z+1 JMP @F ; Not overflow

INCMS Y ; Y+1 NOP ; Not overflow @@: ENDM

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¾ Example: Modify above example by “INC_YZ” macro.

B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address B0MOV Z, #TABLE1$L ; To set lookup table1’s low address. MOVC ; To lookup data, R = 00H, ACC = 35H

INC_YZ

; Increment the index address for next address.

;

@@: MOVC ; To lookup data, R = 51H, ACC = 05H. … ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H DW 2012H …

The other example of loop-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen. ¾ Example: Increase Y and Z register by B0ADD/ADD instruction.

B0MOV Y, #TABLE1$M ; To set lookup table’s middle address. B0MOV Z, #TABLE1$L ; To set lookup table’s low address.

B0MOV A, BUF ; Z = Z + BUF. B0ADD Z, A

B0BTS1 FC ; Check the carry flag. JMP GETDATA ; FC = 0 INCMS Y ; FC = 1. Y+1. NOP

GETDATA: ; MOVC ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 …

TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H DW 2012H …

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2.1.1.4 JUMP TABLE DESCRIPTION

The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter (PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the value of the accumulator (A).

 Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is

carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and not change.

¾ Example: Jump table.

ORG 0X0100 ; The jump table is from the head of the ROM boundary B0ADD PCL, A ; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.

JMP A0POINT ; ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT

SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size.

¾ Example: If “jump table” crosses over ROM boundary will cause errors.

@JMP_A MACRO VAL IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) JMP ($ | 0XFF) ORG ($ | 0XFF) ENDIF ADD PCL, A ENDM

 Note: “VAL” is the number of the jump table listing number.

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¾ Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.

B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A 5 ; The number of the jump table listing is five. JMP A0POINT ; ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT JMP A4POINT ; ACC = 4, jump to A4POINT

If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A” macro will adjust the jump table routine begin from next RAM boundary (0x0100).

¾ Example: “@JMP_A” operation.

; Before compiling program.

ROM address B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A 5 ; The number of the jump table listing is five. 0X00FD JMP A0POINT ; ACC = 0, jump to A0POINT 0X00FE JMP A1POINT ; ACC = 1, jump to A1POINT 0X00FF JMP A2POINT ; ACC = 2, jump to A2POINT 0X0100 JMP A3POINT ; ACC = 3, jump to A3POINT 0X0101 JMP A4POINT ; ACC = 4, jump to A4POINT

; After compiling program.

ROM address B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A 5 ; The number of the jump table listing is five. 0X0100 JMP A0POINT ; ACC = 0, jump to A0POINT 0X0101 JMP A1POINT ; ACC = 1, jump to A1POINT 0X0102 JMP A2POINT ; ACC = 2, jump to A2POINT 0X0103 JMP A3POINT ; ACC = 3, jump to A3POINT 0X0104 JMP A4POINT ; ACC = 4, jump to A4POINT

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2.1.1.5 CHECKSUM CALCULATION

The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the Checksum value.

¾ Example: The demo program shows how to calculated Checksum from 00H to the end of user’s cod e.

MOV A,#END_USER_CODE$L B0MOV END_ADDR1, A ; Save low end address to end_addr1 MOV A,#END_USER_CODE$M B0MOV END_ADDR2, A ; Save middle end address to end_addr2 CLR Y ; Set Y to 00H CLR Z ; Set Z to 00H @@: MOVC B0BSET FC ; Clear C flag ADD DATA1, A ; Add A to Data1 MOV A, R ADC DATA2, A ; Add R to Data2 JMP END_CHECK ; Check if the YZ address = the end of code AAA: INCMS Z ; Z=Z+1 JMP @B ; If Z != 00H calculate to next address JMP Y_ADD_1 ; If Z = 00H increase Y END_CHECK: MOV A, END_ADDR1 CMPRS A, Z ; Check if Z = low end address JMP AAA ; If Not jump to checksum calculate MOV A, END_ADDR2 CMPRS A, Y ; If Yes, check if Y = middle end address JMP AAA ; If Not jump to checksum calculate JMP CHECKSUM_END ; If Yes checksum calculated is done.

Y_ADD_1: INCMS Y ; Increase Y NOP JMP @B ; Jump to checksum calculate CHECKSUM_END: … … END_USER_CODE: ; Label of program end

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2.1.2 CODE OPTION TABLE

Code Option Content Function Description

RC

Low cost RC for external high clock oscillator and XOUT becomes to P0.2 bit-direction I/O pin.

12M X’tal

High speed crystal /resonator (e.g. 12MHz) for external high clock oscillator.

High_Clk

4M X’tal Standard crystal /resonator (e.g. 4M) for external high clock oscillator.

Always_On

Watchdog timer is always on enable even in power down and green mode.

Enable

Enable watchdog timer. Watchdog timer stops in power down mode and green mode.

Watch_Dog

Disable Disable Watchdog function.

Fhosc/1

Instruction cycle is oscillator clock. Notice: In Fosc/1, Noise Filter must be disabled.

Fhosc/2

Instruction cycle is 2 oscillator clocks. Notice: In Fosc/2, Noise Filter must be disabled.

Fhosc/4 Instruction cycle is 4 oscillator clocks.

Fcpu

Fhosc/8 Instruction cycle is 8 oscillator clocks.

Reset Enable External reset pin.

Reset_Pin

P02 Enable P0.2 input only without pull-up resister.

Enable Enable ROM code Security function.

Security

Disable Disable ROM code Security function.

Enable Enable Noise Filter and the Fcpu is Fosc/4~Fosc/8.

Noise_Filter

Disable Disable Noise Filter and the Fcpu is Fosc/1~Fosc/8.

 Note:

1. In high noisy environment, enable “Noise Filter” and set Watch_Dog as “Always_On”

is strongly recommended. Enable “Noise_Filter” will limit the Fcpu = Fosc/4 ~ Fosc/128.

2. If users define watchdog as “Always_On”, assembler will Enable “Watch_Dog”

automatically.

3. Fcpu code option is only available for High Clock. Fcpu of slow mode is Fosc/4 (the

Fosc is internal low clock).

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2.1.3 DATA MEMORY (RAM)

) 64 X 8-bit RAM

Address

RAM location

000h

“ “ “ “ “

03Fh

General purpose area

080h

“

080h~0FFh of Bank 0 store system

registers (128 bytes). “ “ “ “

System register

BANK 0

0FFh

End of bank 0 area

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2.1.4 SYSTEM REGISTER

2.1.4.1 SYSTEM REGISTER TABLE

0 1 2 3 4 5 6 7 8 9 A B C D E F

8

L H R Z Y - PFLAG - - - - - - - - -

9

- - - - - - - - - - - - - - - -

A

- - - - - - - - - - - - - - - -

B

- - - - - - - - P0M - - - - -

- PEDGE

C

P1W P1M P2M - - P5M - - INTRQ INTEN OSCM - WDTR - PCL PCH

D

P0 P1 P2 - - P5 - - T0M T0C - - TC1M TC1C TC1R STKP

E

P0UR P1UR P2UR - - P5UR @HL @YZ - P1OC - - - - - -

F

STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H

2.1.4.2 SYSTEM REGISTER DESCRIPTION

PFLAG = ROM page and special flag register. R = Working register and ROM look-up data buffer.

H, L = Working, @HL and ROM addressing register. Y, Z = Working, @YZ and ROM addressing register.

P1W = Port 1 wakeup register. PEDGE = P0.0 edge direction register.

PnM = Port n input/output mode register. Pn = Port n data buffer.

P1OC = Port 1 open-drain control register. PnUR = Port n pull-up resister control register.

INTRQ = Interrupt request register. INTEN = Interrupt enable register.

OSCM = Oscillator mode register. PCH, PCL = Program counter.

T0M = T0 mode register. T0C = TC1 counting register.

TC1M = TC1 mode register. TC1C = TC1 counting register.

TC1R = TC1 auto-reload data buffer. WDTR = Watchdog timer clear register.

STKP = Stack pointer buffer. STK0~STK7 = Stack 0 ~ stack 7 buffer.

@YZ = RAM YZ indirect addressing index pointer. @HL = RAM HL indirect addressing index pointer.

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2.1.4.3 BIT DEFINITION of SYSTEM REGISTER

Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Remarks

080H LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 R/W L 081H HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBIT0 R/W H 082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 R/W R 083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R/W Z 084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R/W Y

086H NT0 NPD C DC Z R/W PFLAG 0B8H P01M P00M R/W P0M 0BFH P00G1 P00G0 R/W PEDGE 0C0H P17W P16W P15W P14W P13W P12W P11W P10W W P1W 0C1H P17M P16M P15M P14M P13M P12M P11M P10M R/W P1M 0C2H P27M P26M P25M P24M P23M P22M P21M P20M R/W P2M 0C5H P54M P53M P52M P51M P50M R/W P5M 0C8H TC1IRQ T0IRQ P01IRQ P00IRQ R/W INTRQ 0C9H TC1IEN T0IEN P01IEN P00IEN R/W INTEN 0CAH CPUM1 CPUM0 CLKMD STPHX R/W OSCM 0CCH WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W WDTR 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W PCL 0CFH PC10 PC9 PC8 R/W PCH 0D0H P02 P01 P00 R/W P0 0D1H P17 P16 P15 P14 P13 P12 P11 P10 R/W P1 0D2H P27 P26 P25 P24 P23 P22 P21 P20 R/W P2 0D5H P54 P53 P52 P51 P50 R/W P5 0D8H T0ENB T0rate2 T0rate1 T0rate0 R/W T0M 0D9H T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R/W T0C 0DCH TC1ENB TC1rate2 TC1rate1 TC1rate0 TC1CKS ALOAD1 TC1OUT PWM1OUT R/W TC1M 0DDH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 R/W TC1C 0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R 0DFH GIE STKPB2 STKPB1 STKPB0 R/W STKP 0E0H P01R P00R W P0UR 0E1H P17R P16R P15R P14R P13R P12R P11R P10R W P1UR 0E2H P27R P26R P25R P24R P23R P22R P21R P20R W P2UR 0E5H P54R P53R P52R P51R P50R W P5UR 0E6H @HL7 @ HL 6 @ HL5 @ HL4 @ HL3 @ HL2 @ HL1 @ HL0 R/W @ HL 0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 R/W @YZ 0E9H P11OC P10OC W P1OC 0F0H S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 R/W STK7L 0F1H S7PC10 S7PC9 S7PC8 R/W STK7H 0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 R/W STK6L 0F3H S6PC10 S6PC9 S6PC8 R/W STK6H 0F4H S5PC7 S5PC6 S5PC5 S5PC4 S5PC3 S5PC2 S5PC1 S5PC0 R/W STK5L 0F5H S5PC10 S5PC9 S5PC8 R/W STK5H 0F6H S4PC7 S4PC6 S4PC5 S4PC4 S4PC3 S4PC2 S4PC1 S4PC0 R/W STK4L 0F7H S4PC10 S4PC9 S4PC8 R/W STK4H 0F8H S3PC7 S3PC6 S3PC5 S3PC4 S3PC3 S3PC2 S3PC1 S3PC0 R/W STK3L 0F9H S3PC10 S3PC9 S3PC8 R/W STK3H 0FAH S2PC7 S2PC6 S2PC5 S2PC4 S2PC3 S2PC2 S2PC1 S2PC0 R/W STK2L 0FBH S2PC10 S2PC9 S2PC8 R/W STK2H 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R/W STK1L 0FDH S1PC10 S1PC9 S1PC8 R/W STK1H 0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R/W STK0L 0FFH S0PC10 S0PC9 S0PC8 R/W STK0H

 Note:

1. To avoid system error, make sure to put all the “0” and “1” as it indicates in the above table.

2. All of register names had been declared in SN8ASM assembler.

3. One-bit name had been declared in SN8ASM assembler with “F” prefix code.

4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers..

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2.1.4.4 ACCUMULATOR

The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register. ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing mode.

¾ Example: Read and write ACC value.

; Read ACC data and store in BUF data memory.

MOV BUF, A

; Write a immediate data into ACC.

MOV A, #0FH ; Write ACC data from BUF data memory.

MOV A, BUF ; or B0MOV A, BUF

The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to other data memories. “PUSH”, “POP” save and load ACC, PFLAG data into buffers.

¾ Example: Protect ACC and working registers.

INT_SERVICE:

PUSH ; Save ACC and PFLAG to buffers.

… . …

POP ; Load ACC and PFLAG from buffers.

RETI ; Exit interrupt service vector

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2.1.4.5 PROGRAM FLAG

The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status. NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and watchdog reset. C, DC, Z bits indicate the result status of ALU operation.

086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PFLAG

NT0 NPD - - - C DC Z

Read/Write R/W R/W - - - R/W R/W R/W

After reset - - - - - 0 0 0

Bit [7:6] NT0, NPD: Reset status flag.

NT0 NPD Reset Status

0 0 Watch-dog time out 0 1 Reserved 1 0 Reset by LVD 1 1 Reset by external Reset Pin

Bit 2 C: Carry flag

1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result

≥ 0.

0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison

result < 0.

Bit 1 DC: Decimal carry flag

1 = Addition with carry from low nibble, subtraction without borrow from high nibble. 0 = Addition without carry from low nibble, subtraction with borrow from high nibble.

Bit 0 Z: Zero flag

1 = The result of an arithmetic/logic/branch operation is zero. 0 = The result of an arithmetic/logic/branch operation is not zero.

 Note: Refer to instruction set table for detailed information of C, DC and Z flags.

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2.1.4.6 PROGRAM COUNTER

The program counter (PC) is a 11-bit binary counter separated into the high-byte 3 and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program execution.

Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 10.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PC

- - - - - PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

After reset

- - - - - 0 0 0 0 0 0 0 0 0 0 0

PCH PCL

) ONE ADDRESS SKIPPING

There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.

If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.

B0BTS1

FC ; To skip, if Carry_flag = 1 JMP C0STEP ; Else jump to C0STEP. … … C0STEP: NOP

B0MOV A, BUF0 ; Move BUF0 value to ACC.

B0BTS0

FZ ; To skip, if Zero flag = 0. JMP C1STEP ; Else jump to C1STEP. … … C1STEP: NOP

If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.

CMPRS

A, #12H ; To skip, if ACC = 12H. JMP C0STEP ; Else jump to C0STEP. … … C0STEP: NOP

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If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next instruction.

INCS instruction:

INCS

BUF0 JMP C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: NOP

INCMS instruction:

INCMS

BUF0 JMP C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: NOP

If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next instruction.

DECS instruction:

DECS

BUF0 JMP C0STEP ; Jump to C0STEP if ACC is not zero. … … C0STEP: NOP

DECMS instruction:

DECMS

BUF0 JMP C0STEP ; Jump to C0STEP if BUF0 is not zero. … … C0STEP: NOP

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) MULTI-ADDRESS JUMPING

Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate multi-address jumping function. Program Counter supports “ADD M,A”, ”ADC M,A” and “B0ADD M,A” instructions for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value by the three instructions and don’t care PCL overflow problem.

 Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is

carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and not change.

¾ Example: If PC = 0323H (PCH = 03H, PCL = 23H)

; PC = 0323H MOV A, #28H B0MOV PCL, A ; Jump to address 0328H …

; PC = 0328H MOV A, #00H B0MOV PCL, A ; Jump to address 0300H …

¾ Example: If PC = 0323H (PCH = 03H, PCL = 23H)

; PC = 0323H B0ADD PCL, A ; PCL = PCL + ACC, the PCH cannot be changed. JMP A0POINT ; If ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT … …

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2.1.4.7 H, L REGISTERS

The H and L registers are the 8-bit buffers. There are two major functions of these registers.

z can be used as general working registers z can be used as RAM data pointers with @HL register

081H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

H

HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBIT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset X X X X X X X X

080H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

L

LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset X X X X X X X X

¾ Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode

to access data as following.

B0MOV H, #00H ; To set RAM bank 0 for H register B0MOV L, #20H ; To set location 20H for L register B0MOV A, @HL ; To read a data into ACC

¾ Example: Clear general-purpose data memory area of bank 0 using @HL register.

CLR H ; H = 0, bank 0 B0MOV L, #07FH ; L = 7FH, the last address of the data memory area CLR_HL_BUF: CLR @HL ; Clear @HL to be zero DECMS L ; L – 1, if L = 0, finish the routine JMP CLR_HL_BUF ; Not zero

CLR @HL END_CLR: ; End of clear general purpose data memory area of bank 0 … …

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2.1.4.8 Y, Z REGISTERS

The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.

z can be used as general working registers z can be used as RAM data pointers with @YZ register z can be used as ROM data pointer with the MOVC instruction for look-up table

084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Y

YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset - - - - - - - -

083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Z

ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset - - - - - - - -

¾ Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.

B0MOV Y, #00H ; To set RAM bank 0 for Y register B0MOV Z, #25H ; To set location 25H for Z register B0MOV A, @YZ ; To read a data into ACC

¾ Example: Uses the Y, Z register as data pointer to clear the RAM data.

B0MOV Y, #0 ; Y = 0, bank 0 B0MOV Z, #07FH ; Z = 7FH, the last address of the data memory area

CLR_YZ_BUF: CLR @YZ ; Clear @YZ to be zero

DECMS Z ; Z – 1, if Z= 0, finish the routine JMP CLR_YZ_BUF ; Not zero

CLR @YZ END_CLR: ; End of clear general purpose data memory area of bank 0 …

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2.1.4.9 R REGISTERS

R register is an 8-bit buffer. There are two major functions of the register.

z Can be used as working register z For store high-byte data of look-up table

(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the low-byte data will be stored in ACC).

082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

R

RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset - - - - - - - -

 Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.

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2.2 ADDRESSING MODE

2.2.1 IMMEDIATE ADDRESSING MODE

The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.

¾ Example: Move the immediate data 12H to ACC.

MOV A, #12H ; To set an immediate data 12H into ACC.

¾ Example: Move the immediate data 12H to R register.

B0MOV R, #12H ; To set an immediate data 12H into R register.

 Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.

2.2.2 DIRECTLY ADDRESSING MODE

The directly addressing mode moves the content of RAM location in or out of ACC.

¾ Example: Move 0x12 RAM location data into ACC.

B0MOV A, 12H ; To get a content of RAM location 0x12 of bank 0 and save in

ACC.

¾ Example: Move ACC data into 0x12 RAM location.

B0MOV 12H, A ; To get a content of ACC and save in RAM location 12H of

bank 0.

2.2.3 INDIRECTLY ADDRESSING MODE

The indirectly addressing mode is to access the memory by the data pointer registers (H/L, Y/Z). ¾ Example: Indirectly addressing mode with @HL register

B0MOV H, #0 ; To clear H register to access RAM bank 0. B0MOV L, #12H ; To set an immediate data 12H into L register. B0MOV A, @HL ; Use data pointer @HL reads a data from RAM location ; 012H into ACC.

¾ Example: Indirectly addressing mode with @YZ register

B0MOV Y, #0 ; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.

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2.3 STACK OPERATION

2.3.1 OVERVIEW

The stack buffer has 8-level. These buffers are designed to push and pop up program counter’s (PC) data when interrupt service routine and “CALL” instruction are executed. The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program counter (PC) data.

RET /

RETI

CALL /

INTERRUPT

STKP = 7

STKP = 6

STKP = 5

STKP = 4

STACK Level

STK7H

STK6H

STK5H

STK4H

STACK Buffer

High Byte

PCH

STKP

STK7L

STK6L

STK5L

STK4L

STACK Buffer

Low Byte

PCL

STKP

STKP - 1STKP + 1

STKP = 3

STKP = 2

STKP = 1

STKP = 0

STK3L

STK2L

STK1L

STK0L

STK3H

STK2H

STK1H

STK0H

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2.3.2 STACK REGISTERS

The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 11-bit data memory (STKnH and STKnL) set aside for temporary storage of stack addresses.

The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to the top address of stack buffer and write the last program counter value (PC) into the stack buffer.

The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0.

0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKP

GIE - - - - STKPB2 STKPB1 STKPB0

Read/Write R/W - - - - R/W R/W R/W

After reset 0 - - - - 1 1 1

Bit[2:0] STKPBn: Stack pointer (n = 0 ~ 2) Bit 7 GIE: Global interrupt control bit.

0 = Disable. 1 = Enable. Please refer to the interrupt chapter.

¾ Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointer in the

beginning of the program.

MOV A, #00000111B B0MOV STKP, A

0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKnH

- - - - - SnPC10 SnPC9 SnPC8

Read/Write - - - - - R/W R/W R/W

After reset - - - - - 0 0 0

0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKnL

SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

STKn = STKnH , STKnL (n = 7 ~ 0)

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2.3.3 STACK OPERATION EXAMPLE

The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC) to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as the following table.

STKP Register Stack Buffer

Stack Level

STKPB2 STKPB1 STKPB0 High Byte Low Byte

Description

0

1 1 1 Free Free

-

1

1 1 0 STK0H STK0L

-

2

1 0 1 STK1H STK1L

-

3

1 0 0 STK2H STK2L

-

4

0 1 1 STK3H STK3L

-

5

0 1 0 STK4H STK4L

-

6

0 0 1 STK5H STK5L

-

7

0 0 0 STK6H STK6L

-

8

1 1 1 STK7H STK7L

-

> 8

1 1 0 - -

Stack Over, error

There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as the following table.

STKP Register Stack Buffer

Stack Level

STKPB2 STKPB1 STKPB0 High Byte Low Byte

Description

8

1 1 1 STK7H STK7L

-

7

0 0 0 STK6H STK6L

-

6

0 0 1 STK5H STK5L

-

5

0 1 0 STK4H STK4L

-

4

0 1 1 STK3H STK3L

-

3

1 0 0 STK2H STK2L

-

2

1 0 1 STK1H STK1L

-

1

1 1 0 STK0H STK0L

-

0

1 1 1 Free Free

-

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3

RESET

3.1 OVERVIEW

The system would be reset in three conditions as following.

z Power on reset z Watchdog reset z Brown out reset z External reset (only supports external reset pin enable situation)

When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared. After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.

086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PFLAG

NT0 NPD - - - C DC Z

Read/Write R/W R/W - - - R/W R/W R/W

After reset - - - - - 0 0 0

Bit [7:6] NT0, NPD: Reset status flag.

NT0 NPD Condition Description

0 0 Watchdog reset Watchdog timer overflow. 0 1 Reserved 1 0 Power on reset and LVD reset. Power voltage is lower than LVD detecting level. 1 1 External reset External reset pin detect low level status.

Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client terminal application, users have to take care the power on reset time for the master terminal requirement. The reset timing diagram is as following.

VDD

VSS

VDD

VSS

Watchdog Normal Run

Watchdog Stop

System Normal Run

System Stop

LVD Detect Level

External Reset Low Detect

External Reset High Detect

Watchdog Overflow

Watchdog Reset Delay Time

External Reset Delay Time

Power On Delay Time

Power

External Reset

Watchdog Reset

System Status

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3.2 POWER ON RESET

The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.

z Power-up: System detects the power voltage up and waits for power stable. z External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is

not high level, the system keeps reset status and waits external reset pin released.

z System initialization: All system registers is set as initial conditions and system is ready. z Oscillator warm up: Oscillator operation is successfully and supply to system clock. z Program executing: Power on sequence is finished and program executes from ORG 0.

3.3 WATCHDOG RESET

Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program. Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and returns normal mode. Watchdog reset sequence is as following.

z Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the

system is reset.

z System initialization: All system registers is set as initial conditions and system is ready. z Oscillator warm up: Oscillator operation is successfully and supply to system clock. z Program executing: Power on sequence is finished and program executes from ORG 0.

Watchdog timer application note is as following.

z Before clearing watchdog timer, check I/O status and check RAM contents can improve system error. z Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail. z Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the

watchdog timer function.

 Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.

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3.4 BROWN OUT RESET

3.4.1 BROWN OUT DESCRIPTION

The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well or executing program error.

VDD

VSS

V1

V2

V3

System Work

Well Area

System Work

Error Area

Brown Out Reset Diagram

The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate the system working area. The above area is the system work well area. The below area is the system work error area called dead-band. V1 doesn’t touch the below area and not effect the system operation. But the V2 and V3 is under the below area and may induce the system error occurrence. Let system under dead-band includes some conditions.

DC application:

The power source of DC application is usually using battery. When low battery condition and MCU drive any loading, the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system reset voltage. That makes the system under dead-band.

AC application:

In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power situation. The power on duration and power down duration are longer in AC application. The system power on sequence protects the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while.

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3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION

To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. Different system executing rates have different system minimum operating voltage. The electrical characteristic section shows the system voltage to executing rate relationship.

Vdd (V)

System Rate (Fcpu)

System Mini.

Operating Voltage.

System Reset

Voltage.

Dead-Band Area

Normal Operating

Area

Reset Area

Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system reset voltage.

3.4.3 BROWN OUT RESET IMPROVEMENT

How to improve the brown reset condition? There are some methods to improve brown out reset as following.

z LVD reset z Watchdog reset z Reduce the system executing rate z External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)

 Note:

1. The “ Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can completely improve the brown out reset, DC low battery and AC slow power down conditions.

2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips) and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset IC”). The structure can improve noise effective and get good EFT characteristic.

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LVD reset:

VDD

VSS

System Normal Run

System Stop

LVD Detect Voltage

Power On Delay Time

Power

System Status

Power is below LVD Detect Voltage and System Reset.

The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to improve brown out reset is depend on application requirement and environment. If the power variation is very deep, violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and make system work error, the LVD can’t be the protection and need to other reset methods. More detail LVD information is in the electrical characteristic section.

Watchdog reset:

The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method also can improve brown out reset condition and make sure the system to return normal mode. If the system reset by watchdog and the power is still in dead-band, the system reset sequence won’t be successful and the system stays in reset status until the power return to normal range.

Reduce the system executing rate:

If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band. The lower system rate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue. This way needs to modify whole program timing to fit the application requirement.

External reset circuit: The external reset methods also can improve brown out reset and is the complete solution. There are three external reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead-band. The external reset information is described in the next section.

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3.5 EXTERNAL RESET

External reset function is controlled by “Reset_Pin” code option. Set the code option as “Reset” option to enable external reset function. External reset pin is Schmitt Trigger structure and low level active. The system is running when reset pin is high level voltage input. The reset pin receives the low voltage and the system is reset. The external reset operation actives in power on and normal running mode. During system power-up, the external reset pin must be high level input, or the system keeps in reset status. External reset sequence is as following.

z External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is

not high level, the system keeps reset status and waits external reset pin released.

z System initialization: All system registers is set as initial conditions and system is ready. z Oscillator warm up: Oscillator operation is successfully and supply to system clock. z Program executing: Power on sequence is finished and program executes from ORG 0.

The external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in AC power application…

3.6 EXTERNAL RESET CIRCUIT

3.6.1 Simply RC Reset Circuit

MCU

VDD

VSS

VCC

GND

R

S

T

R1

47K ohm

C1

0.1uF

R2

100 ohm

This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference.

 Note: The reset circuit is no any protection against unusual power or brown out reset.

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3.6.2 Diode & RC Reset Circuit

MCU

VDD

VSS

VCC

GND

R

S

T

R1 47K ohm

C1

0.1uF

DIODE

R2

100 ohm

This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal. The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can improve slight brown out reset condition.

 Note: The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to

limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).

3.6.3 Zener Diode Reset Circuit

MCU

VDD

VSS

VCC

GND

R

S

T

R1

33K ohm

R3

40K ohm

R2

10K ohm

Vz

Q1

E

C

B

The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely. Use zener voltage to be the active level. When VDD voltage level is above “Vz + 0.7V”, the C terminal of

the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener specification. Select the right zener voltage to conform the application.

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3.6.4 Voltage Bias Reset Circuit

MCU

VDD

VSS

VCC

GND

R

S

T

R1

47K ohm

R3

2K ohm

R2

10K ohm

Q1

E

C

B

The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely. The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the circuit diagram condition, the MCU’s reset pin level varies with VDD voltage variation, and the differential voltage is

0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power system, the current must be considered to whole system power consumption.

 Note: Under unstable power condition as brown out reset, “Zener diode rest circuit” and “Voltage bias

reset circuit” can protects system no any error occurrence as power dropping. When power drops below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation.

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3.6.5 External Reset IC

MCU

VDD

VSS

VCC

GND

R

S

T

Reset

IC

VDD

VSS

RST

Bypass

Capacitor

0.1uF

The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation.

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4

SYSTEM CLOCK

4.1 OVERVIEW

The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is generated from the external oscillator circuit. The low-speed clock is generated from on-chip low-speed RC oscillator circuit (ILRC 16KHz @3V, 32KHz @5V).

Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is divided by 4 to be the instruction cycle (Fcpu).

) Normal Mode (High Clock): Fcpu = Fhosc / N, N = 1 ~ 8, Select N by Fcpu code option. ) Slow Mode (Low Clock): Fcpu = Flosc/4.

SONIX provides a “Noise Filter” controlled by code option. In high noisy situation, the noise filter can isolate noise outside and protect system works well. The minimum Fcpu of high clock is limited at Fhosc/4 when noise filter enable.

4.2 CLOCK BLOCK DIAGRAM

Fhosc.

Fcpu = Fhosc/1 ~ Fhosc/8, Noise Filter Disable. Fcpu = Fhosc/4 ~ Fhosc/8, Noise Filter Enable.

Flosc. Fcpu = Flosc/4

CPUM[1:0]

XIN

XOUT

STPHX HOSC

Fcpu Code Option

Fosc

CLKMD

Fcpu

z HOSC: High_Clk code option. z Fhosc: External high-speed clock. z Flosc: Internal low-speed RC clock (about 16KHz@3V, 32KHz@5V). z Fosc: System clock source. z Fcpu: Instruction cycle.

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4.3 OSCM REGISTER

The OSCM register is an oscillator control register. It controls oscillator status, system mode.

0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCM

0 0 0 CPUM1 CPUM0 CLKMD STPHX 0

Read/Write - - - R/W R/W R/W R/W -

After reset - - - 0 0 0 0 -

Bit 1 STPHX: External high-speed oscillator control bit.

0 = External high-speed oscillator free run. 1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running.

Bit 2 CLKMD: System high/Low clock mode control bit.

0 = Normal (dual) mode. System clock is high clock. 1 = Slow mode. System clock is internal low clock.

Bit[4:3] CPUM[1:0]: CPU operating mode control bits.

00 = normal. 01 = sleep (power down) mode. 10 = green mode. 11 = reserved.

¾ Example: Stop high-speed oscillator

B0BSET FSTPHX ; To stop external high-speed oscillator only.

¾ Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal

low-speed oscillator will be stopped.

B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode).

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4.4 SYSTEM HIGH CLOCK

The system high clock is from external oscillator. The high clock type is controlled by “High_Clk” code option.

High_Clk Code Option Description

RC The high clock is external RC type oscillator. XOUT pin is general purpose I/O pin.

12M The high clock is external high speed oscillator. The typical frequency is 12MHz.

4M The high clock is external oscillator. The typical frequency is 4MHz.

4.4.1 EXTERNAL HIGH CLOCK

External high clock includes three modules (Crystal/Ceramic, RC and external clock signal). The high clock oscillator module is controlled by High_Clk code option. The start up time of crystal/ceramic and RC type oscillator is different. RC type oscillator’s start-up time is very short, but the crystal’s is longer. The oscillator start-up time decides reset time length.

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4.4.1.1 CRYSTAL/CERAMIC

Crystal/Ceramic devices are driven by XIN, XOUT pins. For high/normal/low frequency, the driving currents are different. High_Clk code option supports different frequencies. 12M option is for high speed (ex. 12MHz). 4M option is for normal speed (ex. 4MHz).

MCU

VCC

GND

C

20pF

XIN

X

O

U

T

VDD

VSS

C

20pF

CRYSTAL

 Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of

micro-controller.

4.4.1.2 RC

Selecting RC oscillator is by RC option of High_Clk code option. RC type oscillator’s frequency is up to 10MHz. Using “R” value is to change frequency. 50P~100P is good value for “C”. XOUT pin is general purpose I/O pin.

R

MCU

VCC

GND

XIN

X

O

U

T

V

D

VSS

C

 Note: Connect the R and C as near as possible to the VDD pin of micro-controller.

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4.4.1.3 EXTERNAL CLOCK SIGNAL

Selecting external clock signal input to be system clock is by RC option of High_Clk code option. The external clock signal is input from XIN pin. XOUT pin is general purpose I/O pin.

MCU

VCC

GND

VSS

VDD

XIN

XOUT

External Clock Input

 Note: The GND of external oscillator circuit must be as near as possible to VSS pin of micro-controller.

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4.5 SYSTEM LOW CLOCK

The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relation between the RC frequency and voltage is as the following figure.

Internal Low RC Frequency

7.52

10.64

14.72

16.00

17.24

18.88

22.24

25.96

29.20

32.52

35.40

38.08

40.80

0.00

5.00

10.00

15.00

20.00

25.00

30.00

35.00

40.00

45.00

2.12.533.13.33.544.555.566.57

VDD (V)

Freq. (KHz)

ILRC

The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD.

) Flosc = Internal low RC oscillator (about 16KHz @3V, 32KHz @5V).

) Slow mode Fcpu = Flosc / 4

There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 32K mode and watchdog disable. If system is in 32K mode and watchdog disable, only 32K oscillator actives and system is under low power consumption.

¾ Example: Stop internal low-speed oscillator by power down mode.

B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode).

 Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1

(32K, watchdog disable) bits of OSCM register.

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4.5.1 SYSTEM CLOCK MEASUREMENT

Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is useful in RC mode.

¾ Example: Fcpu instruction cycle of external oscillator.

B0BSET P0M.0 ; Set P0.0 to be output mode for outputting Fcpu toggle signal.

@@: B0BSET P0.0 ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope. JMP @B

 Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC

frequency.

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5

SYSTEM OPERATION MODE

5.1 OVERVIEW

The chip is featured with low power consumption by switching around four different modes as following.

z Normal mode (High-speed mode) z Slow mode (Low-speed mode) z Power-down mode (Sleep mode) z Green mode

Power Down Mode

(Sleep Mode)

Slow Mode

Green Mode

Normal Mode

CLKMD = 1

CLKMD = 0

P0, P1 Wake-up Function Active.

External Reset Circuit Active.

CPUM1, CPUM0 = 01.

CPUM1, CPUM0 = 10.

P0, P1 Wake-up Function Active. T0 Timer Time Out.

External Reset Circuit Active.

P0, P1 Wake-up Function Active.

T0 Timer Time Out.

External Reset Circuit Active.

System Mode Switching Diagram

Operating mode description

MODE NORMAL SLOW GREEN

POWER DOWN

(SLEEP)

REMARK

EHOSC Running By STPHX By STPHX Stop

ILRC Running Running Running Stop

CPU instruction Executing Executing Stop Stop

T0 timer *Active *Active *Active Inactive * Active if T0ENB=1

TC1 timer *Active *Active *Active Inactive * Active if TC1ENB=1

Watchdog timer

By Watch_Dog

Code option

By Watch_Dog

Code option

By Watch_Dog

Code option

By Watch_Dog

Code option

Refer to code option

description

Internal interrupt All active All active T0, TC1 All inactive

External interrupt All active All active All active All inactive

Wakeup source - -

P0, P1, T0

Reset

P0, P1, Reset

EHOSC: External high clock ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V)

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5.2 SYSTEM MODE SWITCHING

¾ Example: Switch normal/slow mode to power down (sleep) mode.

B0BSET FCPUM0 ; Set CPUM0 = 1.

 Note: During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.

¾ Example: Switch normal mode to slow mode.

B0BSET FCLKMD ;To set CLKMD = 1, Change the system into slow mode B0BSET FSTPHX ;To stop external high-speed oscillator for power saving.

¾ Example: Switch slow mode to normal mode (The external high-speed oscillator is still running)

B0BCLR FCLKMD ;To set CLKMD = 0

¾ Example: Switch slow mode to normal mode (The external high-speed oscillator stops)

If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 20ms for external clock stable.

B0BCLR FSTPHX ; Turn on the external high-speed oscillator.

B0MOV Z, #54 ; If VDD = 5V, internal RC=32KHz (typical) will delay @@: DECMS Z ; 0.125ms X 162 = 20.25ms for external clock stable JMP @B

B0BCLR FCLKMD ; Change the system back to the normal mode

¾ Example: Switch normal/slow mode to green mode.

B0BSET FCPUM1 ; Set CPUM1 = 1.

 Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can

wakeup the system backs to the previous operation mode.

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¾ Example: Switch normal/slow mode to Green mode and enable T0 wakeup function.

; Set T0 timer wakeup function. B0BCLR FT0IEN ; To disable T0 interrupt service B0BCLR FT0ENB ; To disable T0 timer MOV A,#20H ; B0MOV T0M,A ; To set T0 clock = Fcpu / 64 MOV A,#74H B0MOV T0C,A ; To set T0C initial value = 74H (To set T0 interval = 10 ms)

B0BCLR FT0IEN ; To disable T0 interrupt service B0BCLR FT0IRQ ; To clear T0 interrupt request B0BSET FT0ENB ; To enable T0 timer

; Go into green mode B0BCLR FCPUM0 ;To set CPUMx = 10 B0BSET FCPUM1

 Note: During the green mode with T0 wake-up function, the wakeup pins, reset pin and T0 can wakeup

the system back to the last mode. T0 wake-up period is controlled by program and T0ENB must be set.

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5.3 WAKEUP

5.3.1 OVERVIEW

Under power down mode (sleep mode) or green mode, program doesn’t execute. The wakeup trigger can wake the system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0, P1 level change) and internal trigger (T0 timer overflow).

z Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change) z Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger (P0,

P1 level change) and internal trigger (T0 timer overflow).

5.3.2 WAKEUP TIME

When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode.

 Note: Wakeup from green mode is no wakeup time because the clock doesn’t stop in green mode.

The value of the wakeup time is as the following.

The Wakeup time = 1/Fosc * 2048 (sec) + high clock start-up time

 Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.

¾ Example: In power down mode (sleep mode), the system is waked up. After the wakeup time, the system

goes into normal mode. The wakeup time is as the following.

The wakeup time = 1/Fosc * 2048 = 0.512 ms (Fosc = 4MHz)

The total wakeup time = 0.512 ms + oscillator start-up time

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5.3.3 P1W WAKEUP CONTROL REGISTER

Under power down mode (sleep mode) and green mode, the I/O ports with wakeup function are able to wake the system up to normal mode. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function always enables, but the Port 1 is controlled by the P1W register.

0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P1W

P17W P16W P15W P14W P13W P12W P11W P10W

Read/Write W W W W W W W W

After reset 0 0 0 0 0 0 0 0

Bit[7:0] P10W~P17W: Port 1 wakeup function control bits.

0 = Disable P1n wakeup function. 1 = Enable P1n wakeup function.

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6

INTERRUPT

6.1 OVERVIEW

This MCU provides three interrupt sources, including two internal interrupt (T0/TC1) and two external interrupt (INT0, INT1). The external interrupt can wakeup the chip while the system is switched from power down mode to high-speed normal mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. All of the interrupt request signals are stored in INTRQ register.

INTEN Interrupt Enable Register

Interrupt

Enable

Gating

INTRQ

4-Bit

Latchs

P00IRQ

P01IRQ

T0IRQ

TC1IRQ

Interrupt Vector Address (0008H)

Global Interrupt Request Signal

INT0 Trigger

INT1 Trigger

T0 Time Out

TC1 Time Out

 Note: The GIE bit must enable during all interrupt operation.

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6.2 INTEN INTERRUPT ENABLE REGISTER

INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed.

0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTEN

- TC1IEN - T0IEN - - P01IEN P00IEN

Read/Write - R/W - R/W - - R/W R/W

After reset - 0 - 0 - - 0 0

Bit 0 P00IEN: External P0.0 interrupt (INT0) control bit.

0 = Disable INT0 interrupt function. 1 = Enable INT0 interrupt function.

Bit 1 P01IEN: External P0.1 interrupt (INT1) control bit.

0 = Disable INT1 interrupt function. 1 = Enable INT1 interrupt function.

Bit 4 T0IEN: T0 timer interrupt control bit.

0 = Disable T0 interrupt function. 1 = Enable T0 interrupt function.

Bit 6 TC1IEN: TC1 timer interrupt control bit.

0 = Disable TC1 interrupt function. 1 = Enable TC1 interrupt function.

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6.3 INTRQ INTERRUPT REQUEST REGISTER

INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request.

0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTRQ

- TC1IRQ - T0IRQ - - P01IRQ P00IRQ

Read/Write - R/W - R/W - - R/W R/W

After reset - 0 - 0 - - 0 0

Bit 0 P00IRQ: External P0.0 interrupt (INT0) request flag.

0 = None INT0 interrupt request. 1 = INT0 interrupt request.

Bit 1 P01IRQ: External P0.1 interrupt (INT1) request flag.

0 = None INT1 interrupt request. 1 = INT1 interrupt request.

Bit 4 T0IRQ: T0 timer interrupt request flag.

0 = None T0 interrupt request. 1 = T0 interrupt request.

Bit 6 TC1IRQ: TC1 timer interrupt request flag.

0 = None TC1 interrupt request. 1 = TC1 interrupt request.

6.4 GIE GLOBAL INTERRUPT OPERATION

GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and the stack add 1 level.

0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKP

GIE - - - - STKPB2 STKPB1 STKPB0

Read/Write R/W - - - - R/W R/W R/W

After reset 0 - - - - 1 1 1

Bit 7 GIE: Global interrupt control bit.

0 = Disable global interrupt. 1 = Enable global interrupt.

¾ Example: Set global interrupt control bit (GIE).

B0BSET FGIE ; Enable GIE

 Note: The GIE bit must enable during all interrupt operation.

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6.5 PUSH, POP ROUTINE

When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save ACC, PFLAG data. The chip includes “PUSH”, “POP” for in/out interrupt service routine. The two instruction save and load ACC, PFLAG data into buffers and avoid main routine error after interrupt service routine finishing.

 Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is

an unique buffer and only one level.

¾ Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine

executed.

ORG 0 JMP START

ORG 8 JMP INT_SERVICE

ORG 10H START: …

INT_SERVICE:

PUSH ; Save ACC and PFLAG to buffers.

… …

POP ; Load ACC and PFLAG from buffers.

RETI ; Exit interrupt service vector … ENDP

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6.6 INT0 (P0.0) INTERRUPT OPERATION

When the INT0 trigger occurs, the P00IRQ will be set to “1” no matter the P00IEN is enable or disable. If the P00IEN = 1 and the trigger event P00IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG

8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the P00IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.

 Note: The interrupt trigger direction of P0.0 is control by PEDGE register.

0BFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PEDGE

- - - P00G1 P00G0 - - -

Read/Write - - - R/W R/W - - -

After reset - - - 1 0 - - -

Bit[4:3] P00G[1:0]: P0.0 interrupt trigger edge control bits.

00 = reserved. 01 = rising edge. 10 = falling edge. 11 = rising/falling bi-direction (Level change trigger).

¾ Example: Setup INT0 interrupt request and bi-direction edge trigger.

MOV A, #18H B0MOV PEDGE, A ; Set INT0 interrupt trigger as bi-direction edge.

B0BSET FP00IEN ; Enable INT0 interrupt service B0BCLR FP00IRQ ; Clear INT0 interrupt request flag B0BSET FGIE ; Enable GIE

¾ Example: INT0 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

… ; Push routine to save ACC and PFLAG to buffers.

B0BTS1 FP00IRQ ; Check P00IRQ JMP EXIT_INT ; P00IRQ = 0, exit interrupt vector

B0BCLR FP00IRQ ; Reset P00IRQ … ; INT0 interrupt service routine

… EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers.

RETI ; Exit interrupt vector

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6.7 INT1 (P0.1) INTERRUPT OPERATION

When the INT1 trigger occurs, the P01IRQ will be set to “1” no matter the P01IEN is enable or disable. If the P01IEN = 1 and the trigger event P01IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG

8). If the P01IEN = 0 and the trigger event P01IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the P01IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.

 Note: The interrupt trigger direction of P0.1 is falling edge.

¾ Example: INT1 interrupt request setup.

B0BSET FP01IEN ; Enable INT1 interrupt service B0BCLR FP01IRQ ; Clear INT1 interrupt request flag B0BSET FGIE ; Enable GIE

¾ Example: INT1 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

… ; Push routine to save ACC and PFLAG to buffers.

B0BTS1 FP01IRQ ; Check P01IRQ JMP EXIT_INT ; P01IRQ = 0, exit interrupt vector

B0BCLR FP01IRQ ; Reset P01IRQ … ; INT1 interrupt service routine

… EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers.

RETI ; Exit interrupt vector

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6.8 T0 INTERRUPT OPERATION

When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.

¾ Example: T0 interrupt request setup.

B0BCLR FT0IEN ; Disable T0 interrupt service B0BCLR FT0ENB ; Disable T0 timer MOV A, #20H ; B0MOV T0M, A ; Set T0 clock = Fcpu / 64 MOV A, #74H ; Set T0C initial value = 74H B0MOV T0C, A ; Set T0 interval = 10 ms

B0BSET FT0IEN ; Enable T0 interrupt service B0BCLR FT0IRQ ; Clear T0 interrupt request flag B0BSET FT0ENB ; Enable T0 timer

B0BSET FGIE ; Enable GIE

¾ Example: T0 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

… ; Push routine to save ACC and PFLAG to buffers.

B0BTS1 FT0IRQ ; Check T0IRQ JMP EXIT_INT ; T0IRQ = 0, exit interrupt vector

B0BCLR FT0IRQ ; Reset T0IRQ MOV A, #74H B0MOV T0C, A ; Reset T0C. … ; T0 interrupt service routine

… EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers.

RETI ; Exit interrupt vector

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6.9 TC1 INTERRUPT OPERATION

When the TC1C counter overflows, the TC1IRQ will be set to “1” no matter the TC1IEN is enable or disable. If the TC1IEN and the trigger event TC1IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the TC1IEN = 0, the trigger event TC1IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even when the TC1IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.

¾ Example: TC1 interrupt request setup.

B0BCLR FTC1IEN ; Disable TC1 interrupt service B0BCLR FTC1ENB ; Disable TC1 timer MOV A, #20H ; B0MOV TC1M, A ; Set TC1 clock = Fcpu / 64 MOV A, #74H ; Set TC1C initial value = 74H B0MOV TC1C, A ; Set TC1 interval = 10 ms

B0BSET FTC1IEN ; Enable TC1 interrupt service B0BCLR FTC1IRQ ; Clear TC1 interrupt request flag B0BSET FTC1ENB ; Enable TC1 timer

B0BSET FGIE ; Enable GIE

¾ Example: TC1 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

… ; Push routine to save ACC and PFLAG to buffers.

B0BTS1 FTC1IRQ ; Check TC1IRQ JMP EXIT_INT ; TC1IRQ = 0, exit interrupt vector

B0BCLR FTC1IRQ ; Reset TC1IRQ MOV A, #74H B0MOV TC1C, A ; Reset TC1C. … ; TC1 interrupt service routine

… EXIT_INT: … ; Pop routine to load ACC and PFLAG from buffers.

RETI ; Exit interrupt vector

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6.10 MULTI-INTERRUPT OPERATION

Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be logic “1”. The IRQ and its trigger event relationship is as the below table.

Interrupt Name Trigger Event Description

P00IRQ P0.0 trigger controlled by PEDGE. P01IRQ P0.1 falling edge trigger.

T0IRQ T0C overflow.

TC1IRQ TC1C overflow.

For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests. Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and interrupt request flag in interrupt routine.

¾ Example: Check the interrupt request under multi-interrupt operation

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

… ; Push routine to save ACC and PFLAG to buffers.

INTP00CHK: ; Check INT0 interrupt request B0BTS1 FP00IEN ; Check P00IEN

JMP INTP01CHK ; Jump check to next interrupt B0BTS0 FP00IRQ ; Check P00IRQ JMP INTP00 ; Jump to INT0 interrupt service routine

INTP01CHK: ; Check INT0 interrupt request B0BTS1 FP01IEN ; Check P01IEN

JMP INTT0CHK ; Jump check to next interrupt B0BTS0 FP01IRQ ; Check P01IRQ JMP INTP01 ; Jump to INT1 interrupt service routine

INTT0CHK: ; Check T0 interrupt request B0BTS1 FT0IEN ; Check T0IEN

JMP INTTC1CHK ; Jump check to next interrupt B0BTS0 FT0IRQ ; Check T0IRQ JMP INTT0 ; Jump to T0 interrupt service routine

INTTC1CHK: ; Check TC1 interrupt request B0BTS1 FTC1IEN ; Check TC1IEN

JMP INT_EXIT ; Jump to exit of IRQ B0BTS0 FTC1IRQ ; Check TC1IRQ JMP INTTC1 ; Jump to TC1 interrupt service routine INT_EXIT:

… ; Pop routine to load ACC and PFLAG from buffers.

RETI ; Exit interrupt vector

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7

I/O PORT

7.1 I/O PORT MODE

The port direction is programmed by PnM register. All I/O ports can select input or output direction.

0B8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P0M

- - - - - - P01M P00M

Read/Write - - - - - - R/W R/W

After reset - - - - - - 0 0

0C1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P1M

P17M P16M P15M P14M P13M P12M P12M P10M

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

0C2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P2M

P27M P26M P25M P24M P23M P22M P22M P20M

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P5M

- - - P54M P53M P52M P51M P50M

Read/Write - - - R/W R/W R/W R/W R/W

After reset - - - 0 0 0 0 0

Bit[7:0] PnM[7:0]: Pn mode control bits. (n = 0~5). 0 = Pn is input mode.

1 = Pn is output mode.

 Note:

1. Users can program them by bit control instructions (B0BSET, B0BCLR).

2. P0.2 is input only pin, and the P0M.2 keeps “1”.

¾ Example: I/O mode selecting

CLR P0M ; Set all ports to be input mode. CLR P2M CLR P1M CLR P5M

MOV A, #0FFH ; Set all ports to be output mode. B0MOV P0M, A B0MOV P1M, A B0MOV P2M, A B0MOV P5M, A

B0BCLR P1M.2 ; Set P1.2 to be input mode.

B0BSET P1M.2 ; Set P1.2 to be output mode.

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7.2 I/O PULL UP REGISTER

0E0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P0UR

- - - - - - P01R P00R

Read/Write - - - - - - W W

After reset - - - - - - 0 0

0E1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P1UR

P17R P16R P15R P14R P13R P12R P11R P10R

Read/Write W W W W W W W W

After reset 0 0 0 0 0 0 0 0

0E2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P2UR

P27R P26R P25R P24R P23R P22R P21R P20R

Read/Write W W W W W W W W

After reset 0 0 0 0 0 0 0 0

0E5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P5UR

- - - P54R P53R P52R P51R P50R

Read/Write - - - W W W W W

After reset - - - 0 0 0 0 0

 Note: P0.2 is input only pin and without pull-up resister. The P0UR.2 keeps “1”.

¾ Example: I/O Pull up Register

MOV A, #0FFH ; Enable Port0, 1, 2, 5 Pull-up register, B0MOV P0UR, A ; B0MOV P1UR, A B0MOV P2UR, A B0MOV P5UR, A

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7.3 I/O OPEN-DRAIN REGISTER

P1.0, P1.1 are built-in open-drain function. P1.0, P1.1 must be set as output mode when enable open-drain function. Open-drain external circuit is as following.

U

MCU2

U

VCC

Open-drain pin Open-drain pin

MCU1

Pull-up Resistor

The pull-up resistor is necessary. Open-drain output high is driven by pull-up resistor. Output low is sunken by MCU’s pin.

0E9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P1OC

- - - - - -

P11OC P10OC

Read/Write - - - - - - W W

After reset - - - - - - 0 0

Bit 0 P10OC: P10 open-drain control bit

0 = Disable open-drain mode 1 = Enable open-drain mode

Bit 1 P11OC: P11 open-drain control bit

0 = Disable open-drain mode 1 = Enable open-drain mode

¾ Example: Enable P1.0 to open-drain mode and output high.

B0BSET P1.0 ; Set P1.0 buffer high.

B0BSET P10M ; Enable P1.0 output mode. MOV A, #01H ; Enable P1.0 open-drain function. B0MOV P1OC, A

 Note: P1OC is write only register. Setting P10OC must be used “MOV” instructions.

¾ Example: Disable P1.0 to open-drain mode and output low.

MOV A, #0 ; Disable P1.0 open-drain function. B0MOV P1OC, A

 Note: After disable P1.0 open-drain function, P1.0 mode returns to last I/O mode.

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7.4 I/O PORT DATA REGISTER

0D0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P0

- - - - - P02 P01 P00

Read/Write - - - - - R R/W R/W

After reset - - - - - 0 0 0

0D1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P1

P17 P16 P15 P14 P13 P12 P11 P10

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

0D2H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P2

P27 P26 P25 P24 P23 P22 P21 P20

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P5

- - - P54 P53 P52 P51 P50

Read/Write - - - R/W R/W R/W R/W R/W

After reset - - - 0 0 0 0 0

 Note: The P02 keeps “1” when external reset enable by code option.

¾ Example: Read data from input port.

B0MOV A, P0 ; Read data from Port 0 B0MOV A, P1 ; Read data from Port 1 B0MOV A, P2 ; Read data from Port 2 B0MOV A, P5 ; Read data from Port 5

¾ Example: Write data to output port. MOV A, #0FFH ; Write data FFH to all Port. B0MOV P0, A B0MOV P1, A B0MOV P2, A B0MOV P5, A

¾ Example: Write one bit data to output port. B0BSET P1.3 ; Set P1.3 and P5.5 to be “1”. B0BSET P5.5

B0BCLR P1.3 ; Set P1.3 and P5.5 to be “0”. B0BCLR P5.5

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8

TIMERS

8.1 WATCHDOG TIMER

The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by code option and the clock source is internal low-speed oscillator (16KHz @3V, 32KHz @5V).

Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).

VDD Internal Low RC Freq. Watchdog Overflow Time

3V 16KHz 512ms 5V 32KHz 256ms

 Note: If watchdog is “Always_On” mode, it keeps running event under power down mode or green

mode.

Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.

0CCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

WDTR

WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0

Read/Write W W W W W W W W

After reset 0 0 0 0 0 0 0 0

¾ Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top

of the main routine of the program.

Main:

MOV A,#5AH ; Clear the watchdog timer. B0MOV WDTR,A

… CALL SUB1 CALL SUB2 … … … JMP MAIN

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Watchdog timer application note is as following.

z Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.

z Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail. z Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the

watchdog timer function.

¾ Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top

of the main routine of the program.

Main: … ; Check I/O. … ; Check RAM Err: JMP $ ; I/O or RAM error. Program jump here and don’t ; clear watchdog. Wait watchdog timer overflow to reset IC.

Correct: ; I/O and RAM are correct. Clear watchdog timer and ; execute program. B0BSET FWDRST ; Only one clearing watchdog timer of whole program. … CALL SUB1 CALL SUB2 … … … JMP MAIN

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8.2 TIMER 0 (T0)

8.2.1 OVERVIEW

The T0 is an 8-bit binary up timer and event counter. If T0 timer occurs an overflow (from FFH to 00H), it will continue counting and issue a time-out signal to trigger T0 interrupt to request interrupt service.

The main purposes of the T0 timer is as following. ) 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected

clock frequency.

) Green mode wakeup function: T0 can be green mode wake-up time as T0ENB = 1. System will be wake-up by

T0 time out.

Fcpu

T0 Rate

(Fcpu/2~Fcpu/256)

T0ENB

CPUM0,1

T0C 8-Bit Binary Up Counting Counter T0 Time Out

Load

Internal Data Bus

8.2.2 T0M MODE REGISTER

0D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T0M

T0ENB T0rate2 T0rate1 T0rate0 - - - -

Read/Write R/W R/W R/W R/W - - - -

After reset 0 0 0 0 - - - -

Bit [6:4] T0RATE[2:0]: T0 internal clock select bits.

000 = fcpu/256. 001 = fcpu/128. … 110 = fcpu/4. 111 = fcpu/2.

Bit 7 T0ENB: T0 counter control bit.

0 = Disable T0 timer. 1 = Enable T0 timer.

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8.2.3 T0C COUNTING REGISTER

T0C is an 8-bit counter register for T0 interval time control.

0D9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T0C

T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

The equation of T0C initial value is as following.

T0C initial value = 256 - (T0 interrupt interval time * input clock)

¾ Example: To set 10ms interval time for T0 interrupt. High clock is external 4MHz. Fcpu=Fosc/4. Select

T0RATE=010 (Fcpu/64).

T0C initial value = 256 - (T0 interrupt interval time * input clock)

= 256 - (10ms * 4MHz / 4 / 64) = 256 - (10

-2

* 4 * 106 / 4 / 64) = 100 = 64H

The basic timer table interval time of T0.

High speed mode (Fcpu = 4MHz / 4) Low speed mode (Fcpu = 32768Hz / 4)

T0RATE T0CLOCK

Max overflow interval One step = max/256 Max overflow interval One step = max/256

000 Fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 Fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 Fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 Fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 Fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 Fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 Fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us

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8.2.4 T0 TIMER OPERATION SEQUENCE

T0 timer operation sequence of setup T0 timer is as following.

) Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag.

B0BCLR FT0ENB ; T0 timer. B0BCLR FT0IEN ; T0 interrupt function is disabled. B0BCLR FT0IRQ ; T0 interrupt request flag is cleared.

) Set T0 timer rate.

MOV A, #0xxx0000b ;The T0 rate control bits exist in bit4~bit6 of T0M. The ; value is from x000xxxxb~x111xxxxb. B0MOV T0M,A ; T0 timer is disabled.

) Set T0 interrupt interval time.

MOV A,#7FH B0MOV T0C,A ; Set T0C value.

) Set T0 timer function mode.

B0BSET FT0IEN ; Enable T0 interrupt function.

) Enable T0 timer.

B0BSET FT0ENB ; Enable T0 timer.

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8.3 TIMER/COUNTER 0 (TC1)

8.3.1 OVERVIEW

The TC1 is an 8-bit binary up counting timer with double buffers. TC1 has two clock sources including internal clock and external clock for counting a precision time. The internal clock source is from Fcpu. The external clock is INT1 from P0.1 pin (Falling edge trigger). Using TC1M register selects TC1C’s clock source from internal or external. If TC1 timer occurs an overflow, it will continue counting and issue a time-out signal to trigger TC1 interrupt to request interrupt service. TC1 overflow time is 0xFF to 0X00 normally. Under PWM mode, TC1 overflow is decided by PWM cycle controlled by ALOAD1 and TC1OUT bits.

The main purposes of the TC1 timer is as following. ) 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected

clock frequency.

) External event counter: Counts system “events” based on falling edge detection of external clock signals at the

INT1 input pin.

) Buzzer output ) PWM output

Fcpu

TC1 Rate

(Fcpu/2~Fcpu/256)

INT1

(Schmitter Trigger)

TC1CKS TC1ENB

CPUM0,1

TC1C

8-Bit Binary Up

Counting Counter

TC1R Reload

Data Buffer

Up Counting

Reload Value

TC1 Time Out

Compare

ALOAD1

R

S

TC1 Time Out

Auto. Reload

TC1 / 2

Buzzer

Internal P5.3 I/O Circuit

P5.3

PWM

PWM1OUT

TC1OUT

ALOAD1, TC1OUT

Load

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8.3.2 TC1M MODE REGISTER

0DCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC1M

TC1ENB TC1rate2 TC1rate1 TC1rate0 TC1CKS ALOAD1 TC1OUT PWM1OUT

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

Bit 0 PWM1OUT: PWM output control bit.

0 = Disable PWM output. 1 = Enable PWM output. PWM duty controlled by TC1OUT, ALOAD1 bits.

Bit 1 TC1OUT: TC1 time out toggle signal output control bit. Only valid when PWM1OUT = 0. 0 = Disable, P5.3 is I/O function. 1 = Enable, P5.3 is output TC1OUT signal.

Bit 2 ALOAD1: Auto-reload control bit. Only valid when PWM1OUT = 0.

0 = Disable TC1 auto-reload function. 1 = Enable TC1 auto-reload function.

Bit 3 TC1CKS: TC1 clock source select bit.

0 = Internal clock (Fcpu or Fosc). 1 = External clock from P0.1/INT1 pin.

Bit [6:4] TC1RATE[2:0]: TC1 internal clock select bits.

000 = fcpu/256. 001 = fcpu/128. … 110 = fcpu/4. 111 = fcpu/2.

Bit 7 TC1ENB: TC1 counter control bit.

0 = Disable TC1 timer. 1 = Enable TC1 timer.

 Note: When TC1CKS=1, TC1 became an external event counter and TC1RATE is useless. No more P0.1

interrupt request will be raised. (P0.1IRQ will be always 0).

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8.3.3 TC1C COUNTING REGISTER

TC1C is an 8-bit counter register for TC1 interval time control.

0DDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC1C

TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

The equation of TC1C initial value is as following.

TC1C initial value = N - (TC1 interrupt interval time * input clock)

N is TC1 overflow boundary number. TC1 timer overflow time has six types (TC1 timer, TC1 event counter, TC1 Fcpu clock source, TC1 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time and valid value as follow table.

TC1CKS PWM1 ALOAD1 TC1OUT

N

TC1C valid

value

TC1C value

binary type

Remark

0 x x 256 0x00~0xFF 00000000b~11111111b Overflow per 256 count 1 0 0 256 0x00~0xFF 00000000b~11111111b Overflow per 256 count 1 0 1 64 0x00~0x3F xx000000b~xx111111b Overflow per 64 count 1 1 0 32 0x00~0x1F xxx00000b~xxx11111b Overflow per 32 count

0

1 1 1 16 0x00~0x0F xxxx0000b~xxxx1111b Overflow per 16 count

1 - - - 256 0x00~0xFF 00000000b~11111111b Overflow per 256 count

¾ Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM

output (PWM1=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).

TC1C initial value = N - (TC1 interrupt interval time * input clock)

= 256 - (10ms * 4MHz / 4 / 64) = 256 - (10

-2

* 4 * 106 / 4 / 64) = 100 = 64H

The basic timer table interval time of TC1.

High speed mode (Fcpu = 4MHz / 4) Low speed mode (Fcpu = 32768Hz / 4)

TC1RATE TC1CLOCK

Max overflow interval One step = max/256 Max overflow interval One step = max/256

000 Fcpu/256 65.536 ms 256 us 8000 ms 31250 us 001 Fcpu/128 32.768 ms 128 us 4000 ms 15625 us 010 Fcpu/64 16.384 ms 64 us 2000 ms 7812.5 us 011 Fcpu/32 8.192 ms 32 us 1000 ms 3906.25 us 100 Fcpu/16 4.096 ms 16 us 500 ms 1953.125 us 101 Fcpu/8 2.048 ms 8 us 250 ms 976.563 us 110 Fcpu/4 1.024 ms 4 us 125 ms 488.281 us 111 Fcpu/2 0.512 ms 2 us 62.5 ms 244.141 us

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8.3.4 TC1R AUTO-LOAD REGISTER

TC1 timer is with auto-load function controlled by ALOAD1 bit of TC1M. When TC1C overflow occurring, TC1R value will load to TC1C by system. It is easy to generate an accurate time, and users don’t reset TC1C during interrupt service routine.

TC1 is double buffer design. If new TC1R value is set by program, the new value is stored in 1

st

buffer. Until TC1 overflow occurs, the new value moves to real TC1R buffer. This way can avoid TC1 interval time error and glitch in PWM and Buzzer output.

 Note: Under PWM mode, auto-load is enabled automatically. The ALOAD1 bit is selecting overflow

boundary.

0DEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC1R

TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0

Read/Write W W W W W W W W

After reset 0 0 0 0 0 0 0 0

The equation of TC1R initial value is as following.

TC1R initial value = N - (TC1 interrupt interval time * input clock)

N is TC1 overflow boundary number. TC1 timer overflow time has six types (TC1 timer, TC1 event counter, TC1 Fcpu clock source, TC1 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC1 overflow time and valid value as follow table.

TC1CKS PWM1 ALOAD1 TC1OUT

N

TC1R valid

value

TC1R value

binary type

0 x x 256 0x00~0xFF 00000000b~11111111b 1 0 0 256 0x00~0xFF 00000000b~11111111b 1 0 1 64 0x00~0x3F xx000000b~xx111111b 1 1 0 32 0x00~0x1F xxx00000b~xxx11111b

0

1 1 1 16 0x00~0x0F xxxx0000b~xxxx1111b

1 - - - 256 0x00~0xFF 00000000b~11111111b

¾ Example: To set 10ms interval time for TC1 interrupt. TC1 clock source is Fcpu (TC1KS=0) and no PWM

output (PWM1=0). High clock is external 4MHz. Fcpu=Fosc/4. Select TC1RATE=010 (Fcpu/64).

TC1R initial value = N - (TC1 interrupt interval time * input clock)

= 256 - (10ms * 4MHz / 4 / 64) = 256 - (10

-2

* 4 * 106 / 4 / 64) = 100 = 64H

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8.3.5 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)

Buzzer output (TC1OUT) is from TC1 timer/counter frequency output function. By setting the TC1 clock frequency, the clock signal is output to P5.3 and the P5.3 general purpose I/O function is auto-disable. The TC1OUT frequency is divided by 2 from TC1 interval time. TC1OUT frequency is 1/2 TC1 frequency. The TC1 clock has many combinations and easily to make difference frequency. The TC1OUT frequency waveform is as following.

1 2 3 4

TC0 Overflow Clock

TC0OUT (Buzzer) Output Clock

¾ Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. The

TC1OUT frequency is 0.5KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 1KHz. The TC1 clock source is from external oscillator clock. T0C rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 131.

MOV A,#01100000B B0MOV TC1M,A ; Set the TC1 rate to Fcpu/4

MOV A,#131 ; Set the auto-reload reference value B0MOV TC1C,A B0MOV TC1R,A

B0BSET FTC1OUT ; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer

 Note: Buzzer output is enable, and “PWM1OUT” must be “0”.

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8.3.6 TC1 TIMER OPERATION SEQUENCE

TC1 timer operation includes timer interrupt, event counter, TC1OUT and PWM. The sequence of setup TC1 timer is as following.

) Stop TC1 timer counting, disable TC1 interrupt function and clear TC1 interrupt request flag.

B0BCLR FTC1ENB ; TC1 timer, TC1OUT and PWM stop. B0BCLR FTC1IEN ; TC1 interrupt function is disabled. B0BCLR FTC1IRQ ; TC1 interrupt request flag is cleared.

) Set TC1 timer rate. (Besides event counter mode.)

MOV A, #0xxx0000b ;The TC1 rate control bits exist in bit4~bit6 of TC1M. The ; value is from x000xxxxb~x111xxxxb. B0MOV TC1M,A ; TC1 interrupt function is disabled.

) Set TC1 timer clock source.

; Select TC1 internal / external clock source.

B0BCLR FTC1CKS ; Select TC1 internal clock source.

or

B0BSET FTC1CKS ; Select TC1 external clock source.

) Set TC1 timer auto-load mode.

B0BCLR FALOAD1 ; Enable TC1 auto reload function.

or

B0BSET FALOAD1 ; Disable TC1 auto reload function. ) Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty cycle.

; Set TC1 interrupt interval time, TC1OUT (Buzzer) frequency or PWM duty.

MOV A,#7FH ; TC1C and TC1R value is decided by TC1 mode. B0MOV TC1C,A ; Set TC1C value. B0MOV TC1R,A ; Set TC1R value under auto reload mode or PWM mode.

; In PWM mode, set PWM cycle.

B0BCLR FALOAD1 ; ALOAD1, TC1OUT = 00, PWM cycle boundary is B0BCLR FTC1OUT ; 0~255.

or

B0BCLR FALOAD1 ; ALOAD1, TC1OUT = 01, PWM cycle boundary is B0BSET FTC1OUT ; 0~63.

or

B0BSET FALOAD1 ; ALOAD1, TC1OUT = 10, PWM cycle boundary is B0BCLR FTC1OUT ; 0~31.

or

B0BSET FALOAD1 ; ALOAD1, TC1OUT = 11, PWM cycle boundary is B0BSET FTC1OUT ; 0~15.

) Set TC1 timer function mode.

B0BSET FTC1IEN ; Enable TC1 interrupt function.

or

B0BSET FTC1OUT ; Enable TC1OUT (Buzzer) function.

or

B0BSET FPWM1OUT ; Enable PWM function.

) Enable TC1 timer.

B0BSET FTC1ENB ; Enable TC1 timer.

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8.4 PWM1 MODE

8.4.1 OVERVIEW

PWM function is generated by TC1 timer counter and output the PWM signal to PWM1OUT pin (P5.3). The 8-bit counter counts modulus 256, 64, 32, 16 controlled by ALOAD1, TC1OUT bits. The value of the 8-bit counter (TC1C) is compared to the contents of the reference register (TC1R). When the reference register value (TC1R) is equal to the counter value (TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The low-to-high ratio (duty) of the PWM1 output is TC1R/256, 64, 32, 16.

PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to change the PWM’s duty cycle is to modify the TC1R.

 Note: TC1 is double buffer design. Modifying TC1R to change PWM duty by program, there is no glitch

and error duty signal in PWM output waveform. Users can change TC1R any time, and the new reload value is loaded to TC1R buffer at TC1 overflow.

ALOAD1 TC1OUT PWM duty range TC1C valid value TC1R valid bits value

MAX. PWM

Frequency

(Fcpu = 4MHz)

Remark

0 0 0/256~255/256 0x00~0xFF 0x00~0xFF 7.8125K Overflow per 256 count 0 1 0/64~63/64 0x00~0x3F 0x00~0x3F 31.25K Overflow per 64 count 1 0 0/32~31/32 0x00~0x1F 0x00~0x1F 62.5K Overflow per 32 count 1 1 0/16~15/16 0x00~0x0F 0x00~0x0F 125K Overflow per 16 count

The Output duty of PWM is with different TC1R. Duty range is from 0/256~255/256.

TC1 Clock

TC1R=00H

TC1R=01H

TC1R=80H

TC1R=FFH

0 1 128 254 255

…… ……

0 1 128 254 255

…… ……

Low

High

Low

High

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8.4.2 TCxIRQ and PWM Duty

In PWM mode, the frequency of TC1IRQ is depended on PWM duty range. From following diagram, the TC1IRQ frequency is related with PWM duty.

TC1 Overflow,

TC1IRQ = 1

PWM1 Output

(Duty Range 0~15)

0xFF

TC1C Value

0x00

PWM1 Output

(Duty Range 0~31)

0xFF

TC1C Value

0x00

PWM1 Output

(Duty Range 0~63)

0xFF

TC1C Value

0x00

0xFF

TC1C Value

0x00

PWM1 Output

(Duty Range 0~255)

TC1 Overflow,

TC1IRQ = 1

TC1 Overflow,

TC1IRQ = 1

TC1 Overflow,

TC1IRQ = 1

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8.4.3 PWM Duty with TCxR Changing

In PWM mode, the system will compare TC1C and TC1R all the time. When TC1C<TC1R, the PWM will output logic “High”, when TC1C≧ TC1R, the PWM will output logic “Low”. If TC1C is changed in certain period, the PWM duty will change in next PWM period. If TC1R is fixed all the time, the PWM waveform is also the same.

TC1C overflow and TC1IRQ set

TC1C = TC1R

0xFF

TC1C Value

0x00

PWM1 Output

1 2 3 4 5 6 7

Period

Above diagram is shown the waveform with fixed TC1R. In every TC1C overflow PWM output “High, when TC1C≧ TC1R PWM output ”Low”. If TC1R is changing in the program processing, the PWM waveform will became as following

diagram.

1

1st PWM

2

Update PWM Duty

3

2nd PWM

4

Update PWM Duty

0xFF

TC1C Value

0x00

PWM1 Output

Period

5

3th PWM

TC1C overflow and TC1IRQ set

Old TC1R Old TC1RNew TC1R New TC1R

Update New TC1R! Old TC1R < TC1C < New TC1R

Update New TC1R! New TC1R < TC1C < Old TC1R

TC1C > = TC1R PWM High > Low

TC1C < TC1R PWM Low > High

In period 2 and period 4, new Duty (TC1R) is set. TC1 is double buffer design. The PWM still keeps the same duty in period 2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation.

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8.4.4 PWM PROGRAM EXAMPLE

¾ Example: Setup PWM1 output from TC1 to PWM1OUT (P5.3). The external high-speed oscillator clock is

4MHz. Fcpu = Fosc/4. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock source is from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 30.

MOV A,#01100000B B0MOV TC1M,A ; Set the TC1 rate to Fcpu/4

MOV A,#30 ; Set the PWM duty to 30/256 B0MOV TC1C,A B0MOV TC1R,A

B0BCLR FTC1OUT ; Set duty range as 0/256~255/256. B0BCLR FALOAD1 B0BSET FPWM1OUT ; Enable PWM1 output to P5.3 and disable P5.3 I/O function B0BSET FTC1ENB ; Enable TC1 timer

 Note: The TC1R is write-only register. Don’t process them using INCMS, DECMS instructions.

¾ Example: Modify TC1R registers’ value.

MOV A, #30H ; Input a number using B0MOV instruction. B0MOV TC1R, A

INCMS BUF0 ; Get the new TC1R value from the BUF0 buffer defined by NOP ; programming. B0MOV A, BUF0 B0MOV TC1R, A

 Note: The PWM can work with interrupt request.

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9

INSTRUCTION TABLE

Field Mnemonic Description C DC Z Cycle

MOV A,M

A

← M

- -

√

1

M MOV M,A

M

← A

- - - 1

O B0MOV A,M

A

← M (bank 0)

- -

√

1

V B0MOV M,A

M (bank 0)

← A

- - - 1

E MOV A,I

A

← I

- - - 1

B0MOV M,I

M

← I, “M” only supports 0x80~0x87 registers (e.g. PFLAG,R,Y,Z…)

- - - 1

XCH A,M

A

←→M

- - - 1+N

B0XCH A,M

A

←→M (bank 0)

- - - 1+N

MOVC

R, A

← ROM [Y,Z]

- - - 2

ADC A,M

A

← A + M + C, if occur carry, then C=1, else C=0

√ √ √

1

A ADC M,A

M

← A + M + C, if occur carry, then C=1, else C=0

√ √ √

1+N

R ADD A,M

A

← A + M, if occur carry, then C=1, else C=0

√ √ √

1

I ADD M,A

M

← A + M, if occur carry, then C=1, else C=0

√ √ √

1+N

T B0ADD M,A

M (bank 0)

← M (bank 0) + A, if occur carry, then C=1, else C=0

√ √ √

1+N

H ADD A,I

A

← A + I, if occur carry, then C=1, else C=0

√ √ √

1

M SBC A,M

A

← A - M - /C, if occur borrow, then C=0, else C=1

√ √ √

1

E SBC M,A

M

← A - M - /C, if occur borrow, then C=0, else C=1

√ √ √

1+N

T SUB A,M

A

← A - M, if occur borrow, then C=0, else C=1

√ √ √

1

I SUB M,A

M

← A - M, if occur borrow, then C=0, else C=1

√ √ √

1+N

C SUB A,I

A

← A - I, if occur borrow, then C=0, else C=1

√ √ √

1

AND A,M

A

← A and M

- -

√

1

L AND M,A

M

← A and M

- -

√

1+N

O AND A,I

A

← A and I

- -

√

1

G OR A,M

A

← A or M

- -

√

1

I OR M,A

M

← A or M

- -

√

1+N

C OR A,I

A

← A or I

- -

√

1

XOR A,M

A

← A xor M

- -

√

1

XOR M,A

M

← A xor M

- -

√

1+N

XOR A,I

A

← A xor I

- -

√

1

SWAP M

A (b3~b0, b7~b4)

←M(b7~b4, b3~b0)

- - - 1

P SWAPM M

M(b3~b0, b7~b4)

← M(b7~b4, b3~b0)

- - - 1+N

R RRC M

A

← RRC M

√

-- 1

O RRCM M

M

← RRC M

√

-- 1+N

C RLC M

A

← RLC M

√

-- 1

E RLCM M

M

← RLC M

√

-- 1+N

S CLR M

M

← 0

- - - 1

S BCLR M.b

M.b

← 0

- - - 1+N

BSET M.b

M.b

← 1

- - - 1+N

B0BCLR M.b

M(bank 0).b

← 0

- - - 1+N

B0BSET M.b

M(bank 0).b

← 1

- - - 1+N

CMPRS A,I

ZF,C

← A - I, If A = I, then skip next instruction

√

-

√

1 + S

B CMPRS A,M

ZF,C

← A – M, If A = M, then skip next instruction

√

-

√

1 + S

R INCS M

A

← M + 1, If A = 0, then skip next instruction

- - - 1+ S

A INCMS M

M

← M + 1, If M = 0, then skip next instruction

- - - 1+N+S

N DECS M

A

← M - 1, If A = 0, then skip next instruction

- - - 1+ S

C DECMS M

M

← M - 1, If M = 0, then skip next instruction

- - - 1+N+S

H BTS0 M.b If M.b = 0, then skip next instruction - - - 1 + S

BTS1 M.b If M.b = 1, then skip next instruction - - - 1 + S B0BTS0 M.b If M(bank 0).b = 0, then skip next instruction - - - 1 + S B0BTS1 M.b If M(bank 0).b = 1, then skip next instruction - - - 1 + S JMP d

PC15/14

← RomPages1/0, PC13~PC0 ← d

- - - 2

CALL d

Stack

← PC15~PC0, PC15/14 ← RomPages1/0, PC13~PC0 ← d

- - - 2

M RET

PC

← Stack

- - - 2

I RETI

PC

← Stack, and to enable global interrupt

- - - 2 S PUSH To push ACC and PFLAG (except NT0, NPD bit) into buffers. - - - 1 C

POP To pop ACC and PFLAG (except NT0, NPD bit) from buffers.

√ √ √

1

NOP No operation - - - 1

Note: 1. “M” is system register or RAM. If “M” is system registers then “N” = 0, otherwise “N” = 1.

2. If branch condition is true then “S = 1”, otherwise “S = 0”.

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1

0

ELECTRICAL CHARACTERISTIC

10.1 ABSOLUTE MAXIMUM RATING

Supply voltage (Vdd)…………………………………………………………………………………………………………………….……………… - 0.3V ~ 6.0V Input in voltage (Vin)…………………………………………………………………………………………………………………….… Vss – 0.2V ~ Vdd + 0.2V Operating ambient temperature (Topr) SN8P2624K, SN8P2624S, SN8P2624X ………………………………………………………………………………………………….. 0

°C ~ + 70°C

SN8P2624KD, SN8P2624SD, SN8P2624XD ……………………………………………………………………………………………. –40

°C ~ + 85°C

Storage ambient temperature (Tstor) ………………………………………………………………….………………………………………… –30

°C ~ + 125°C

10.2 ELECTRICAL CHARACTERISTIC

(All of voltages refer to Vss, Vdd = 5.0V, fosc = 4MHz, ambient temperature is 25°C unless otherwise note.)

PARAMETER SYM. DESCRIPTION MIN. TYP. MAX. UNIT

Operating voltage Vdd Normal mode, Vpp = Vdd 2.4 5.0 5.5 V

RAM Data Retention voltage Vdr - 1.5* - V

Vdd rise rate Vpor Vdd rise rate to ensure power-on reset 0.05 - - V/ms

ViL1 All input ports Vss - 0.3Vdd V

Input Low Voltage

ViL2 Reset pin Vss - 0.2Vdd V ViH1 All input ports 0.7Vdd - Vdd V

Input High Voltage

ViH2 Reset pin 0.9Vdd - Vdd V

Reset pin leakage current Ilekg Vin = Vdd - - 2 uA

Vin = Vss , Vdd = 3V 100 200 300

I/O port pull-up resistor Rup

Vin = Vss , Vdd = 5V 50 100 150

K

Ω

I/O port input leakage current Ilekg Pull-up resistor disable, Vin = Vdd - - 2 uA

I/O output source current IoH Vop = Vdd – 0.5V - 12* -

sink current IoL Vop = Vss + 0.5V - 15* -

mA

INTn trigger pulse width Tint0 INT0 interrupt request pulse width 2/fcpu - - cycle

Vdd= 5V, 4Mhz - 2.5 5 mA

Idd1

normal Mode (No loading, Fcpu = Fosc/4)

Vdd= 3V, 4Mhz - 1 2 mA

Vdd= 5V, 32Khz - 20 40 uA

Idd2

Slow Mode (Internal low RC, stop high clock)

Vdd= 3V, 16Khz - 5 10 uA

Vdd= 5V - 1 2 uA

Idd3 Sleep Mode

Vdd= 3V - 0.7 1.5 uA Vdd= 5V, 4Mhz - 0.6 1.2 mA

Vdd= 3V, 4Mhz - 0.25 0.5 mA Vdd=5V, ILRC 32Khz - 15 30 uA

Supply Current

Idd4

Green Mode (No loading, Fcpu = Fosc/4 Watchdog Disable)

Vdd=3V, ILRC 16Khz - 3 6 uA

LVD detect level V

LVD

Low voltage detect level 1.6 2.0 2.2 V

*These parameters are for design reference, not tested.

SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 88 Version 0.3

Working area

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

1M 2M 4M 8M 12M 16M

Fcpu

VDD

10.3 CHARACTERISTIC GRAPHS

The Graphs in this section are for design guidance, not tested or guaranteed. In some graphs, the data presented are outside specified operating range. This is for information only and devices are guaranteed to operate properly only within the specified range.

SN8P2624

Working Voltage vs. Frequency

(Noise Filter Disable、25℃)

SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 89 Version 0.3

1

OTP PROGRAMMING PIN

11.1.1 EASY WRITER TRANSITION BOARD SOCKET PIN ASSIGNMENT

Easy Writer JP1/JP2 Easy Writer JP3 (Mapping to 48-pin text tool)

VSS 2 1 VDD DIP1 1 48 DIP48

CE 4 3 CLK/PGCLK DIP2 2 47 DIP47

OE/ShiftDat 6 5 PGM/OTPCLK DIP3 3 46 DIP46

D0 8 7 D1 DIP4 4 45 DIP45 D2 10 9 D3 DIP5 5 44 DIP44 D4 12 11 D5 DIP6 6 43 DIP43

D6 14 13 D7 DIP7 7 42 DIP42 VPP 16 15 VDD DIP8 8 41 DIP41 RST 18 17 HLS DIP9 9 40 DIP40

ALSB/PDB 20 19 - DIP10 10 39 DIP39

DIP11 11 38 DIP38

JP1 for MP transition board

DIP12 12 37 DIP38

JP2 for Writer V3.0 transition board

DIP13 13 36 DIP36

DIP14 14 35 DIP35 DIP15 15 34 DIP34 DIP16 16 33 DIP33 DIP17 17 32 DIP32 DIP18 18 31 DIP31 DIP19 19 30 DIP30 DIP20 20 29 DIP29 DIP21 21 28 DIP28 DIP22 22 27 DIP27 DIP23 23 26 DIP26 DIP24 24 25 DIP25

JP3 for MP transition board

11.1.2 WRITER V2.5 AND V3.0 TRANSITION BOARD SOCKET PIN ASSIGNMENT

GND 2 1 VDD

GND 1 2 VDD CE 4 3 CLK

CE 3 4 CLK OE 6 5 PGM

OE 5 6 PGM D0 8 7 D1

D0 7 8 D1 D2 10 9 D3 D2 9 10 D3 D4 12 11 D5 D4 11 12 D5 D6 14 13 D7

D6 13 14 D7 VPP 16 15 VDD VPP 15 16 VDD RST 18 17 HLS RST 17 18 HLS 20 19

Writer V2.5 JP1 Pin Assignment Writer V3.0 JP1 Pin Assignment

 Note: For supporting the body programming, SONIX writer V2.5 must update V3.0 firmware and modify

circuit. Please contact SONIX agent about SONIX Writer V2.5 upgrade.

SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 90 Version 0.3

11.1.3 PROGRAMMING PIN MAPPING

Programming Information of SN8P2600A Series

Chip Name SN8P2624

Writer V2.5

Connector

EZ Writer / Writer

V3.0

Connector

OTP IC / JP3 Pin Assigment

Number Name Number Name Number Pin Number Pin

2 VDD 1 VDD 2 VDD 1 GND 2 GND 4 VSS 4 CLK 3 CLK 6 P5.0 3 CE 4 CE - - 6 PGM 5 PGM 10 P1.0 5 OE 6 OE 7 P5.1 8 D1 7 D1 - - 7 D0 8 D0 - -

10 D3 9 D3 - -

9 D2 10 D2 - - 12 D5 11 D5 - - 11 D4 12 D4 - - 14 D7 13 D7 - - 13 D6 14 D6 - - 16 VDD 15 VDD - - 15 VPP 16 VPP 28 RST 18 HLS 17 HLS - - 17 RST 18 RST - -

- - 19 - - -

- - 20 ALSB/PDB 11 P1.1

SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 91 Version 0.3

1

2

PACKAGE INFORMATION

12.1 SK-DIP 28 PIN

MIN NOR MAX MIN NOR MAX

SYMBOLS

(inch) (mm)

A - - 0.210 - - 5.334 A1 0.015 - - 0.381 - A2 0.114 0.130 0.135 2.896 3.302 3.429

D 1.390 1.390 1.400 35.306 35.306 35.560

E 0.310 7.874 E1 0.283 0.288 0.293 7.188 7.315 7.442

L 0.115 0.130 0.150 2.921 3.302 3.810

ｅ

B

0.330 0.350 0.370 8.382 8.890 9.398

θ° 0° 7° 15° 0° 7° 15°

SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 92 Version 0.3

12.2 SOP 28 PIN

MIN NOR MAX MIN NOR MAX

SYMBOLS

(inch) (mm)

A 0.093 0.099 0.104 2.362 2.502 2.642 A1 0.004 0.008 0.012 0.102 0.203 0.305

D 0.697 0.705 0.713 17.704 17.907 18.110

E 0.291 0.295 0.299 7.391 7.493 7.595

H 0.394 0.407 0.419 10.008 10.325 10.643

L 0.016 0.033 0.050 0.406 0.838 1.270

θ° 0° 4° 8° 0° 4° 8°

SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 93 Version 0.3

12.3 SSOP 28 PIN

MIN NOR MAX MIN NOR MAX

SYMBOLS

(inch) (mm)

A

- - 0.08

- - 2.13

A1

0.00 - 0.01

0.05 - 0.25

A2

0.06 0.07 0.07

1.63 1.75 1.88

b

0.01 - 0.01

0.22 - 0.38

C

0.00 - 0.01

0.09 - 0.20

D

0.39 0.40 0.41

9.90 10.20 10.50

E

0.29 0.31 0.32

7.40 7.80 8.20

E1

0.20 0.21 0.22

5.00 5.30 5.60

[e] 0.0259BSC 0.65BSC

L

0.02 0.04 0.04

0.63 0.90 1.03

R

0.00 - -

0.09 - -

θ°

0° 4° 8°

SN8P2624

8-Bit Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 94 Version 0.3

SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.

Main Office:

Address: 9F, NO. 8, Hsien Cheng 5th St, Chupei City, Hsinchu, Taiwan R.O.C. Tel: 886-3-551 0520 Fax: 886-3-551 0523

Taipei Office:

Address: 15F-2, NO. 171, Song Ted Road, Taipei, Taiwan R.O.C. Tel: 886-2-2759 1980 Fax: 886-2-2759 8180

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Address: Flat 3 9/F Energy Plaza 92 Granville Road, Tsimshatsui East Kowloon. Tel: 852-2723 8086 Fax: 852-2723 9179

Technical Support by Email:

Sn8fae@sonix.com.tw

SONIX SN8P2624, SN8P26L00 Series, SN8P26L34, SN8P26L32, SN8P26L321 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual