Page 1
SN8P2200 Series
SN8P2200 Series
USER’S MANUAL
USB 1.1 Low-Speed 8-Bit Micro-Controller
SN8P2204
SN8P2203
SN8P2202
SN8P22021
SN8P2201
S
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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
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SONiX TECHNOLOGY CO., LTD Page 1 Version 1.7
Page 2
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
AMENDMENT HISTORY
Version Date Description
VER 0.1 Aug. 2005 1. First issue.
2. ADD BROWN-OUT circuit.
1. Modify Topr value.
2. Modify Brown-Out Reset description.
VER 0.2 Dec. 2005
VER 0.3 Feb. 2006
VER1.0 Nov. 2006
VER1.1 Jan.2007
3. Modify M2IDE 1.08
4. Remove power consumption(Pc)
5. Modify ELECTRICAL CHARACTERISTIC.
1. Modify operating voltage 3.0V~5.5V.
2. Modify UPID register bit definition of register table.
3. Modify UBDE bit definition, 0:disable, 1: enable.
4. Update IDE display picture of development tools section.
5. Modify OTP program pin number of section 14.
1. Modify ELECTRICAL CHARACTERISTIC.
2. Modify USB register naming
3. Modify code option IHRC description
4. Modify P0UR register
1. Modify PS2 Host to device diagram
VER1.3 Nov. 2007
VER1.3k Nov.2007
VER1.4 Dec.2007
VER1.5 Feb.2008
VER1.6 Mar. 2008
VER1.7 May. 2008
1.Modify 9.5.3 UE1R to UE3R’s bit description
Modify chapter 13. The minimum working voltage of USB mode = 3.6 volts and the
VREG voltage will between 3.2 ~ 3.5 volts.
1. Modify chapter 13. Typing error.
2. Add new 2201 QFN package
Modify chapter 13. The minimum working voltage of USB mode = 3.3 volts and the
VREG voltage will between 3.1 ~ 3.5 volts.
1. Modify the 9.5.10 the USTATUS register bit 6’s description.
2. Add chapter 16 marking definition
Add SN8P22021
SONiX TECHNOLOGY CO., LTD Page 2 Version 1.7
Page 3
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
Table of Content
AMENDMENT HISTORY............................................................................................................................ 2
1 PRODUCT OVERVIEW.............................................................................................................................. 8
1.1 FEATURES.............................................................................................................................................. 8
1.2 SYSTEM BLOCK DIAGRAM ................................................................................................................ 9
1.3 PIN ASSIGNMENT ............................................................................................................................... 10
1.4 PIN DESCRIPTIONS............................................................................................................................. 13
1.5 PIN CIRCUIT DIAGRAMS................................................................................................................... 14
2 CENTRAL PROCESSOR UNIT (CPU) ................................................................................................... 15
2.1 MEMORY MAP..................................................................................................................................... 15
2.1.1 PROGRAM MEMORY (ROM) ........................................................................................................ 15
2.1.1.1 RESET VECTOR (0000H) ...................................................................................................... 16
2.1.1.2 INTERRUPT VECTOR (0008H)............................................................................................. 17
2.1.1.3 LOOK-UP TABLE DESCRIPTION........................................................................................ 19
2.1.1.4 JUMP TABLE DESCRIPTION............................................................................................... 21
2.1.1.5 CHECKSUM CALCULATION .............................................................................................. 23
2.1.2 CODE OPTION TABLE.................................................................................................................. 24
2.1.3 DATA MEMORY (RAM).................................................................................................................. 25
2.1.4 SYSTEM REGISTER........................................................................................................................ 26
2.1.4.1 SYSTEM REGISTER TABLE ................................................................................................ 26
2.1.4.2 SYSTEM REGISTER DESCRIPTION ................................................................................... 26
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER........................................................................... 27
2.1.4.4 ACCUMULATOR ................................................................................................................... 29
2.1.4.5 PROGRAM FLAG................................................................................................................... 30
2.1.4.6 PROGRAM COUNTER .......................................................................................................... 31
2.1.4.7 Y, Z REGISTERS .................................................................................................................... 34
2.1.4.8 R REGISTERS......................................................................................................................... 35
2.2 ADDRESSING MODE .......................................................................................................................... 36
2.2.1 IMMEDIATE ADDRESSING MODE.............................................................................................. 36
2.2.2 DIRECTLY ADDRESSING MODE................................................................................................. 36
2.2.3 INDIRECTLY ADDRESSING MODE............................................................................................. 36
2.3 STACK OPERATION............................................................................................................................ 37
2.3.1 OVERVIEW ..................................................................................................................................... 37
2.3.2 STACK REGISTERS........................................................................................................................ 38
2.3.3 STACK OPERATION EXAMPLE.................................................................................................... 39
3 RESET.......................................................................................................................................................... 40
SONiX TECHNOLOGY CO., LTD Page 3 Version 1.7
Page 4
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
3.1 OVERVIEW........................................................................................................................................... 40
3.2 POWER ON RESET............................................................................................................................... 42
3.3 WATCHDOG RESET............................................................................................................................ 42
3.4 BROWN OUT RESET ........................................................................................................................... 43
3.4.1 BROWN OUT DESCRIPTION........................................................................................................ 43
3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION............................................................... 44
3.4.3 BROWN OUT RESET IMPROVEMENT......................................................................................... 45
3.5 EXTERNAL RESET .............................................................................................................................. 46
3.6 EXTERNAL RESET CIRCUIT ............................................................................................................. 46
3.6.1 Simply RC Reset Circuit.................................................................................................................. 46
3.6.2 Diode & RC Reset Circuit............................................................................................................... 47
3.6.3 Zener Diode Reset Circuit............................................................................................................... 47
3.6.4 Voltage Bias Reset Circuit............................................................................................................... 48
3.6.5 External Reset IC............................................................................................................................. 48
4 SYSTEM CLOCK....................................................................................................................................... 49
4.1 OVERVIEW........................................................................................................................................... 49
4.2 CLOCK BLOCK DIAGRAM................................................................................................................. 49
4.3 OSCM REGISTER................................................................................................................................. 50
4.4 SYSTEM HIGH CLOCK ....................................................................................................................... 51
4.4.1 INTERNAL HIGH RC...................................................................................................................... 51
4.4.2 EXTERNAL HIGH CLOCK............................................................................................................. 51
4.4.2.1 CRYSTAL/CERAMIC............................................................................................................. 51
4.5 SYSTEM LOW CLOCK ........................................................................................................................ 52
4.5.1 SYSTEM CLOCK MEASUREMENT............................................................................................... 53
5 SYSTEM OPERATION MODE................................................................................................................ 54
5.1 OVERVIEW........................................................................................................................................... 54
5.2 SYSTEM MODE SWITCHING EXAMPLE......................................................................................... 55
5.3 WAKEUP ............................................................................................................................................... 57
5.3.1 OVERVIEW ..................................................................................................................................... 57
5.3.2 WAKEUP TIME............................................................................................................................... 57
6 INTERRUPT................................................................................................................................................ 58
6.1 OVERVIEW........................................................................................................................................... 58
6.2 INTEN INTERRUPT ENABLE REGISTER......................................................................................... 59
6.3 INTRQ INTERRUPT REQUEST REGISTER....................................................................................... 60
6.4 GIE GLOBAL INTERRUPT OPERATION .......................................................................................... 60
6.5 PUSH, POP ROUTINE........................................................................................................................... 61
6.6 INT0 (P0.0) INTERRUPT OPERATION............................................................................................... 62
6.7 T0 INTERRUPT OPERATION.............................................................................................................. 64
SONiX TECHNOLOGY CO., LTD Page 4 Version 1.7
Page 5
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
6.8 TC0 INTERRUPT OPERATION........................................................................................................... 65
6.9 USB INTERRUPT OPERATION .......................................................................................................... 66
6.10 T1 INTERRUPT OPERATION............................................................................................................ 67
6.11 T2 INTERRUPT OPERATION............................................................................................................ 68
6.12 MULTI-INTERRUPT OPERATION................................................................................................... 69
7 I/O PORT..................................................................................................................................................... 70
7.1 I/O PORT MODE ................................................................................................................................... 70
7.2 I/O PULL UP REGISTER ...................................................................................................................... 71
7.3 I/O OPEN-DRAIN REGISTER.............................................................................................................. 72
7.4 I/O PORT DATA REGISTER ................................................................................................................ 73
8 TIMERS ....................................................................................................................................................... 74
8.1 WATCHDOG TIMER............................................................................................................................ 74
8.2 TIMER 0 (T0)......................................................................................................................................... 76
8.2.1 OVERVIEW ..................................................................................................................................... 76
8.2.2 T0M MODE REGISTER.................................................................................................................. 77
8.2.3 T0C COUNTING REGISTER.......................................................................................................... 78
8.2.4 T0 TIMER OPERATION SEQUENCE............................................................................................ 79
8.3 TIMER/COUNTER 0 (TC0)................................................................................................................... 80
8.3.1 OVERVIEW ..................................................................................................................................... 80
8.3.2 TC0M MODE REGISTER............................................................................................................... 81
8.3.3 TC0C COUNTING REGISTER....................................................................................................... 82
8.3.4 TC0R AUTO-LOAD REGISTER ..................................................................................................... 83
8.3.5 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)......................................................................... 84
8.3.6 TC0 TIMER OPERATION SEQUENCE ......................................................................................... 85
8.4 PWM0 MODE........................................................................................................................................ 86
8.4.1 OVERVIEW ..................................................................................................................................... 86
8.4.2 TCxIRQ and PWM Duty.................................................................................................................. 87
8.4.3 PWM Duty with TCxR Changing..................................................................................................... 88
8.4.4 PWM PROGRAM EXAMPLE ......................................................................................................... 89
8.5 T1, T2 8-BIT TIMER CAPTURE........................................................................................................... 90
8.5.1 OVERVIEW ..................................................................................................................................... 90
8.5.2 TnM MODE REGISTER.................................................................................................................. 91
8.5.3 Tn COUNTING REGISTER ............................................................................................................ 91
8.5.4 Tn TIMER CAPTURE OPERATION............................................................................................... 92
8.5.5 Tn INPUT PERIOD MEASUREMENT ........................................................................................... 93
8.5.6 Tn INPUT PULSE WIDTH MEASUREMENT................................................................................ 95
9 UNIVERSAL SERIAL BUS (USB) ........................................................................................................... 97
9.1 OVERVIEW........................................................................................................................................... 97
SONiX TECHNOLOGY CO., LTD Page 5 Version 1.7
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
9.2 USB MACHINE..................................................................................................................................... 97
9.3 USB INTERRUPT.................................................................................................................................. 98
9.4 USB ENUMERATION .......................................................................................................................... 99
9.5 USB REGISTERS .................................................................................................................................. 99
9.5.1 USB DEVICE ADDRESS REGISTER ............................................................................................. 99
9.5.2 USB ENDPOINT 0 ENABLE REGISTER ..................................................................................... 100
9.5.3 USB ENDPOINT 1 ENABLE REGISTER ..................................................................................... 101
Example: Check the Endpoint 1’s IN request......................................................................................... 101
Example: Check the Endpoint 1’s OUT request..................................................................................... 102
9.5.4 USB ENDPOINT 2 ENABLE REGISTER ..................................................................................... 102
9.5.5 USB ENDPOINT 3 ENABLE REGISTER ..................................................................................... 103
9.5.6 USB DATA POINTER 0 REGISTER............................................................................................. 103
9.5.7 USB DATA REGISTER.................................................................................................................. 105
9.5.8 USB DATA POINTER 1 REGISTER............................................................................................. 105
9.5.9 USB DATA REGISTER.................................................................................................................. 105
9.5.10 USB STATUS REGISTER............................................................................................................ 105
9.5.11 UPID REGISTER ........................................................................................................................ 106
10 PS/2 INTERFACE................................................................................................................................... 107
10.1 OVERVIEW....................................................................................................................................... 107
10.2 PS/2 OPERATION ............................................................................................................................. 107
10.3 PS2_1 DESCRIPITON....................................................................................................................... 108
10.4 PS2_2 DESCRIPITON....................................................................................................................... 109
11 INSTRUCTION TABLE ........................................................................................................................ 110
12 DEVELOPMENT TOOL....................................................................................................................... 111
12.1 ICE (IN CIRCUIT EMULATION)............................................................................................................. 111
12.2 SN8P2200 EV-KIT .............................................................................................................................. 113
12.3 ICE AND EV-KIT APPLICATION NOTIC........................................................................................ 115
12.4 IDE (INTEGRATED DEVELOPMENT ENVIRONMENT)............................................................................. 116
13 ELECTRICAL CHARACTERISTIC................................................................................................... 117
13.1 ABSOLUTE MAXIMUM RATING.................................................................................................. 117
13.2 ELECTRICAL CHARACTERISTIC................................................................................................. 117
14 OTP PROGRAMMING PIN.................................................................................................................. 118
14.1 THE PIN ASSIGNMENT OF EASY WRITER TRANSITION BOARD SOCKET.......................... 118
14.2 PROGRAMMING PIN MAPPING.................................................................................................... 119
15 PACKAGE INFORMATION ................................................................................................................ 120
15.1 SK-DIP 28 PIN ................................................................................................................................... 120
SONiX TECHNOLOGY CO., LTD Page 6 Version 1.7
Page 7
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
15.2 SK-DIP 24 PIN ................................................................................................................................... 121
15.3 P-DIP 18 PIN ...................................................................................................................................... 122
15.4 P-DIP 14 PIN ...................................................................................................................................... 123
15.5 SOP 28 PIN......................................................................................................................................... 124
15.6 SOP 24 PIN......................................................................................................................................... 125
15.7 SOP 20 PIN......................................................................................................................................... 126
15.8 SOP 18 PIN......................................................................................................................................... 127
15.9 SOP 14 PIN......................................................................................................................................... 128
15.10 SSOP 28 PIN..................................................................................................................................... 129
15.11 SSOP 24 PIN..................................................................................................................................... 130
15.12 SSOP 20 PIN..................................................................................................................................... 131
15.13 SSOP 16 PIN..................................................................................................................................... 132
15.14 QFN 16 PIN ...................................................................................................................................... 133
16 MARKING DEFINITION...................................................................................................................... 134
16.1 INTRODUCTION.............................................................................................................................. 134
16.2 MARKING INDETIFICATION SYSTEM........................................................................................ 134
16.3 MARKING EXAMPLE...................................................................................................................... 135
16.4 DATECODE SYSTEM ...................................................................................................................... 135
SONiX TECHNOLOGY CO., LTD Page 7 Version 1.7
Page 8
SN8P2200 Series
1 PRODUCT OVERVIEW
1.1 FEATURES
USB 1.1 Low-Speed 8-Bit Micro-Controller
Memory configuration
♦
OTP ROM size: 6K * 16 bits.
RAM size: 256 * 8 bits.
8 levels stack buffer
♦
I/O pin configuration
♦
Bi-directional: P0, P1, P5. T1 input from P0.1.
Wake-up: P0/P1 level change. T2 input from P0.2.
Pull-up resistors: P0, P1, P5
Open-drain: P1.0, P1.1.
External interrupt: P0.0 controlled by PEDGE.
Timer capture input pin: P0.1, P0.2 controlled
by TnG1,0.
Low Speed USB 1.1.
♦
Conforms to USB HID specification, Version 1.1.
3.3V regulator output for USB D- pin external
1.5k ohm pull-up resistor.
Integrated USB transceiver.
Supports 1 low speed USB device address and
4 data endpoints (include endpoint 0).
Powerful instructions
♦
One clocks per instruction cycle (1T)
Most of instructions are one cycle only.
All ROM area JMP instruction.
All ROM area CALL address instruction.
All ROM area lookup table function (MOVC)
) Features Selection Table
CHIP
SN8P2204
SN8P2203
SN8P2202
SN8P22021
SN8P2201
ROM RAM STACK
6K*16 256*8 8
6K*16 256*8 8 V V V V 2 1 19 11 SKDIP24/SOP24/SSOP24
6K*16 256*8 8 V V V V 2 1 13 8 PDIP18/SOP18/SSOP20
6K*16 256*8 8 V V V V 2 1 15 10 SOP20
6K*16 256*8 8 V V - - 2 1 9 6 PDIP14/SOP14/SSOP16/QFN16
TIMER PWM
T0 TC0 T1 T2
V V V V 2 1 23 15
Two PS/2 interface.
♦
6 interrupt sources.
♦
Three internal interrupts: T0, TC0, USB, T1, T2.
One external interrupt: INT0.
Two 8-bit timer captures.
♦
One channel PWM output. (PWM)
♦
One channel Buzzer output. (BZ0)
♦
Two 8-bit timer counters. (T0, TC0)
♦
0.5 sec RTC.
♦
On chip watchdog timer.
♦
Three system clocks.
♦
External high clock: Crystal type 6MHz.
Internal high RC 6MHz.
Internal low clock: RC type 16KHz @3V, 32KHz (5V).
Four operating modes.
♦
Normal mode: Both high and low clocks active.
Slow mode: Low clock only.
Sleep: Both high and low clocks stop.
Green mode: Periodical wakeup by timer.
Package (Chip form support)
♦
SK-DIP/P-DIP: 28/24/18/14
SOP: 28/24/20/18/14
SSOP: 28/24/20/16
QFN: 16
PS/2
BZ
I/O
WAKE-UP
PIN NO.
PACKAGE
SKDIP28/SOP28/SSOP28
SONiX TECHNOLOGY CO., LTD Page 8 Version 1.7
Page 9
1.2 SYSTEM BLOCK DIAGRAM
INTERNAL
PC
IR
FLAGS
ACC
ALU
OTP
ROM
EXTERNAL
HIGH OSC.
TIMING GENERATOR
SYSTEM REGISTERS
6M RC
RAM
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
LVD
INTERNAL
LOW RC
WATCHDOG TIMER
3.3v REGULATOR VREG
D+
USB ENGINE
D-
PS2_1 SCLK
PS2_1 SDATA
PS2_2 SCLK
INTERRUPT
CONTROL
P0 P5P1
TIMER & COUNTER
PS2_2 SDATA
PWM 0BUZZER 0
PWM0BUZZER0
SONiX TECHNOLOGY CO., LTD Page 9 Version 1.7
Page 10
1.3 PIN ASSIGNMENT
SN8P2204K (SK-DIP 28 pins)
SN8P2204S (SOP 28 pins)
SN8P2204X (SSOP 28 pins)
P1.4/RST/VPP 12 17 D-/SDATA
SN8P2203K (SK-DIP 24 pins)
SN8P2203S (SOP 24 pins)
SN8P2203X (SSOP 24 pins)
P1.4/RST/VPP 10 15 D-/SDATA
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
P1.0 1 U 28 P5.4/BZ0/PWM0
P1.1 2 27 P5.3
P1.5 3 26 P5.2
P1.6 4 25 P5.1
P1.7 5 24 P5.0
P0.4 6 23 P5.5
P0.3 7 22 P5.6
P0.2/T2IN 8 21 P5.7
P0.1/T1IN 9 20 P0.6
P0.0/INT0 10 19 P0.5
VSS 11 18 D+/SCLK
VREG 13 16 VDD
P1.3/XIN 14 15 P1.2/XOUT
SN8P2204K
SN8P2204S
SN8P2204X
P1.0 1 U 24 P5.4/BZ0/PWM0
P1.1 2 23 P5.3
P1.5 3 22 P5.2
P1.6 4 21 P5.1
P1.7 5 20 P5.0
P0.2/T2IN 6 19 P5.5
P0.1/T1IN 7 18 P5.6
P0.0/INT0 8 17 P5.7
VSS 9 16 D+/SCLK
VREG 11 14 VDD
P1.3/XIN 12 13 P1.2/XOUT
SN8P2203K
SN8P2203S
SN8P2203X
SONiX TECHNOLOGY CO., LTD Page 10 Version 1.7
Page 11
SN8P2202P (P-DIP 18 pins)
SN8P2202S (SOP 18 pins)
SN8P2202X (SSOP 20 pins)
SN8P22021S (SOP 20 pins)
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
P1.0 1 U 18 P5.4/BZ0/PWM0
P1.1 2 17 P5.3
P0.2/T2IN 3 16 P5.2
P0.1/T1IN 4 15 P5.1
P0.0/INT0 5 14 P5.0
VSS 6 13 D+/SCLK
P1.4/RST/VPP 7 12 D-/SDATA
VREG 8 11 VDD
P1.3/XIN 9 10 P1.2/XOUT
SN8P2202P
SN8P2202S
NC 1 U 20 NC
P1.0 2 19 P5.4/BZ0/PWM0
P1.1 3 18 P5.3
P0.2/T2IN 4 17 P5.2
P0.1/T1IN 5 16 P5.1
P0.0/INT0 6 15 P5.0
VSS 7 14 D+/SCLK
P1.4/RST/VPP 8 13 D-/SDATA
VREG 9 12 VDD
P1.3/XIN 10 11 P1.2/XOUT
SN8P2202X
P1.1 1 U 20 P1.0
P1.5 2 19 P5.4/BZ0/PWM0
P1.6 3 18 P5.3
P0.2/T2IN 4 17 P5.2
P0.1/T1IN 5 16 P5.1
P0.0/INT0 6 15 P5.0
VSS 7 14 D+/SCLK
P1.4/RST/VPP 8 13 D-/SDATA
VREG 9 12 VDD
P1.3/XIN 10 11 P1.2/XOUT
SN8P22021S
SONiX TECHNOLOGY CO., LTD Page 11 Version 1.7
Page 12
SN8P2201P (P-DIP 14 pins)
SN8P2201S (SOP 14 pins)
SN8P2201X (SSOP 16 pins)
SN8P2201J (QFN 16 pins)
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
P1.0 1 U 14 P5.4/BZ0/PWM0
P1.1 2 13 P5.1
P0.0/INT0 3 12 P5.0
VSS 4 11 D+/SCLK
P1.4/RST/VPP 5 10 D-/SDATA
VREG 6 9 VDD
P1.3/XIN 7 8 P1.2/XOUT
SN8P2201P
SN8P2201S
NC 1 U 16 NC
P1.0 2 15 P5.4/BZ0/PWM0
P1.1 3 14 P5.1
P0.0/INT0 4 13 P5.0
VSS 5 12 D+/SCLK
P1.4/RST/VPP 6 11 D-/SDATA
VREG 7 10 VDD
P1.3/XIN 8 9 P1.2/XOUT
SN8P2201X
P1.0 1
P1.1 2 11 D-/SDATA
P0.1 3
P0.0/INT0 4 9 P1.2/XOUT
P5.4/BZ0/PWM0
P5.2
P5.1
P5.0
16 15 14 13
●
SN8P2201J
5678
VSS
P1.4/RST/VPP
12
10 VDD
VREG
P1.3/XIN
D+/SCLK
SONiX TECHNOLOGY CO., LTD Page 12 Version 1.7
Page 13
SN8P2200 Series
1.4 PIN DESCRIPTIONS
PIN NAME TYPE DESCRIPTION
VDD, VSS P Power supply input pins for digital circuit.
P0.0: Port 0.0 bi-direction pin.
P0.0/INT0 I/O
P0.1/T1IN I/O
P0.2/T2IN I/O
P0[6:3] I/O
P1.0 I/O
P1.1 I/O
P1.2/XOUT I/O
P1.3/XIN I/O
P1.4/RST/VPP I, P
P1[7:5] I/O
P5.0 I/O
P5.1 I/O
P5.4/BZ0/PWM0 I/O
P5[7:2] I/O
VREG O 3.3V voltage output from USB 3.3V regulator.
D+, D- I/O USB differential data line.
SCLK, SDATA I/O PS/2 clock and data lines.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
INT0: External interrupt 0 input pin.
P0.1: Port 0.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
T1IN: T1 timer capture input pin.
P0.2: Port 0.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
T2IN: T2 timer capture input pin.
P0: Port 0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P1.0: Port 1.0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Open-Drain function controlled by “P1OC” register.
Built wakeup function.
P1.1: Port 1.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Open-Drain function controlled by “P1OC” register.
Built wakeup function.
XOUT: Oscillator output pin while external crystal enable.
P1.2: Port 1.2 bi-direction pin under internal 16M RC and external RC.
Schmitt trigger structure and built-in pull-up resisters as input mode.
Built wakeup function.
XIN: Oscillator input pin while external oscillator enable (crystal and RC).
P1.3: Port 1.3 bi-direction pin under internal 16M RC.
Schmitt trigger structure and built-in pull-up resisters as input mode.
RST is system external reset input pin under Ext_RST mode.
Schmitt trigger structure, active “low”, normal stay to “high”.
P1.4 is input only pin without pull-up resistor under P1.4 mode. Add the 100
ohm external resistor on P1.4, when it is set to be input pin.
Built wakeup function.
OTP 12.3V power input pin in programming mode.
P1: Port 1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P5.0: Port 5.0 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P5.1: Port 5.1 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
P5.4: Port 5.4 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
BZ0: 1/2 TC0 counter output pin.
PWM0: PWM0 output.
P5: Port 5 bi-direction pin.
Schmitt trigger structure and built-in pull-up resisters as input mode.
USB 1.1 Low-Speed 8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 13 Version 1.7
Page 14
1.5 PIN CIRCUIT DIAGRAMS
Port 0, 1, 5 structure:
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
Pull-Up
Port 1.0,Port 1.1 structure:
Pin
Port 1.2, 1.3 structure:
Pin
PnM
PnM
P1OC
Pull-Up
Pull-Up
PnM, PnUR
PnM, PnUR
Open-Drain
Output
Latch
Output
Latch
Input Bus
Output Bus
Input Bus
Output Bus
Port 1.4 structure:
Pin
Oscillator
Code Option
Pin
PnM
PnM, PnUR
Ext. Reset
Code Option
Output
Latch
Int. Bus
Int. Rst
Input Bus
Output Bus
Int. Osc.
SONiX TECHNOLOGY CO., LTD Page 14 Version 1.7
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2 CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
2.1.1 PROGRAM MEMORY (ROM)
) 6K words ROM
0000H
0001H
.
.
0007H
0008H
0009H User program
.
.
000FH
0010H
0011H
.
.
.
.
.
17FCH
17FDH
17FEH
17FFH
General purpose area
General purpose area
ROM
Reset vector
Interrupt vector
Reserved
User reset vector
Jump to user start address
User interrupt vector
End of user program
SONiX TECHNOLOGY CO., LTD Page 15 Version 1.7
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.1.1
RESET VECTOR (0000H)
A one-word vector address area is used to execute system reset.
) Power On Reset (NT0=1, NPD=0).
) Watchdog Reset (NT0=0, NPD=0).
) External Reset (NT0=1, NPD=1).
After power on reset, external reset or watchdog timer overflow reset, then the chip will restart the program from
address 0000h and all system registers will be set as default values. It is easy to know reset status from NT0, NPD
flags of PFLAG register. The following example shows the way to define the reset vector in the program memory.
¾ Example: Defining Reset Vector
…
START:
… ; User program
…
ORG 0 ; 0000H
JMP START ; Jump to user program address.
ORG 10H
; 0010H, The head of user program.
ENDP ; End of program
SONiX TECHNOLOGY CO., LTD Page 16 Version 1.7
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.1.2
INTERRUPT VECTOR (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program
counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the
program memory.
Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is a
unique buffer and only one level.
¾ Example: Defining Interrupt Vector. The interrupt service routine is following ORG 8.
.CODE
…
…
…
…
START: ; The head of user program.
… ; User program
…
JMP START ; End of user program
…
ENDP ; End of program
ORG 0 ; 0000H
JMP START ; Jump to user program address.
ORG 8 ; Interrupt vector.
PUSH ; Save ACC and PFLAG register to buffers.
POP ; Load ACC and PFLAG register from buffers.
RETI
; End of interrupt service routine
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
¾ Example: Defining Interrupt Vector. The interrupt service routine is following user program.
.CODE
ORG 0 ; 0000H
JMP START ; Jump to user program address.
…
JMP MY_IRQ ; 0008H, Jump to interrupt service routine address.
START: ; 0010H, The head of user program.
… ; User program.
…
…
JMP START ; End of user program.
…
MY_IRQ: ;The head of interrupt service routine.
…
…
…
ENDP ; End of program.
Note: It is easy to understand the rules of SONIX program from demo programs given above. These
points are as following:
1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.
2. The address 0008H is interrupt vector.
3. User’s program is a loop routine for main purpose application.
ORG 8 ; Interrupt vector.
ORG 10H
PUSH ; Save ACC and PFLAG register to buffers.
POP ; Load ACC and PFLAG register from buffers.
RETI ; End of interrupt service routine.
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.1.3
LOOK-UP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register is pointed to middle byte address (bit 8~bit 15) and Z register is pointed
to low byte address (bit 0~bit 7) of ROM. After MOVC instruction executed, the low-byte data will be stored in ACC and
high-byte data stored in R register.
¾ Example: To look up the ROM data located “TABLE1”.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
NOP ;
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
Note: The Y register will not increase automatically when Z register crosses boundary from 0xFF to
0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register
overflows, Y register must be added one. The following INC_YZ macro shows a simple method
to process Y and Z registers automatically.
¾ Example: INC_YZ macro.
INC_YZ MACRO
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Y+1
NOP ; Not overflow
@@:
ENDM
INCMS Z ; Z+1
JMP @F ; Z is not overflow.
INCMS Y ; Z overflow (FFH Æ 00), Æ Y=Y+1
;
; Increment the index address for next address.
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
¾ Example: Modify above example by “INC_YZ” macro.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
INC_YZ
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
… ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
The other example of loop-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.
¾ Example: Increase Y and Z register by B0ADD/ADD instruction.
B0MOV Y, #TABLE1$M ; To set lookup table’s middle address.
B0MOV Z, #TABLE1$L ; To set lookup table’s low address.
GETDATA: ;
MOVC ; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
…
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H
DW 2012H
…
;
B0MOV A, BUF ; Z = Z + BUF.
B0ADD Z, A
B0BTS1 FC ; Check the carry flag.
JMP GETDATA ; FC = 0
INCMS Y ; FC = 1. Y+1.
NOP
; Increment the index address for next address.
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.1.4
JUMP TABLE DESCRIPTION
The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC
value to get one new PCL. If PCL is overflow after PCL+ACC, PCH adds one automatically. The new program counter
(PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the
value of the accumulator (A).
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
¾ Example: Jump table.
ORG 0X0100 ; The jump table is from the head of the ROM boundary
B0ADD PCL, A ; PCL = PCL + ACC, PCH + 1 when PCL overflow occurs.
JMP A0POINT ; ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump
table to the right position automatically. The side effect of this macro maybe wastes some ROM size.
¾ Example: If “jump table” crosses over ROM boundary will cause errors.
@JMP_A MACRO VAL
IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00)
JMP ($ | 0XFF)
ORG ($ | 0XFF)
ENDIF
ADD PCL, A
ENDM
Note: “VAL” is the number of the jump table listing number.
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
¾ Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.
B0MOV A, BUF0 ; “BUF0” is from 0 to 4.
@JMP_A 5 ; The number of the jump table listing is five.
JMP A0POINT ; ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
JMP A4POINT ; ACC = 4, jump to A4POINT
If the jump table position is across a ROM boundary (0x00FF~0x0100), the “@JMP_A” macro will adjust the jump table
routine begin from next RAM boundary (0x0100).
¾ Example: “@JMP_A” operation.
; Before compiling program.
ROM address
B0MOV A, BUF0 ; “BUF0” is from 0 to 4.
@JMP_A 5 ; The number of the jump table listing is five.
0X00FD JMP A0POINT ; ACC = 0, jump to A0POINT
0X00FE JMP A1POINT ; ACC = 1, jump to A1POINT
0X00FF JMP A2POINT ; ACC = 2, jump to A2POINT
0X0100 JMP A3POINT ; ACC = 3, jump to A3POINT
0X0101 JMP A4POINT ; ACC = 4, jump to A4POINT
; After compiling program.
ROM address
B0MOV A, BUF0 ; “BUF0” is from 0 to 4.
@JMP_A 5 ; The number of the jump table listing is five.
0X0100 JMP A0POINT ; ACC = 0, jump to A0POINT
0X0101 JMP A1POINT ; ACC = 1, jump to A1POINT
0X0102 JMP A2POINT ; ACC = 2, jump to A2POINT
0X0103 JMP A3POINT ; ACC = 3, jump to A3POINT
0X0104 JMP A4POINT ; ACC = 4, jump to A4POINT
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.1.5CHECKSUM CALCULATION
The last ROM address are reserved area. User should avoid these addresses (last address) when calculate the
Checksum value.
¾ Example: The demo program shows how to calculated Checksum from 00H to the end of user’s code.
MOV A,#END_USER_CODE$L
B0MOV END_ADDR1, A ; Save low end address to end_addr1
MOV A,#END_USER_CODE$M
B0MOV END_ADDR2, A ; Save middle end address to end_addr2
CLR Y ; Set Y to 00H
CLR Z ; Set Z to 00H
@@:
MOVC
B0BSET FC ; Clear C flag
ADD DATA1, A ; Add A to Data1
MOV A, R
ADC DATA2, A ; Add R to Data2
JMP END_CHECK ; Check if the YZ address = the end of code
AAA:
INCMS Z ; Z=Z+1
JMP @B ; If Z != 00H calculate to next address
JMP Y_ADD_1 ; If Z = 00H increase Y
END_CHECK:
MOV A, END_ADDR1
CMPRS A, Z ; Check if Z = low end address
JMP AAA ; If Not jump to checksum calculate
MOV A, END_ADDR2
CMPRS A, Y ; If Yes, check if Y = middle end address
JMP AAA ; If Not jump to checksum calculate
JMP CHECKSUM_END ; If Yes checksum calculated is done.
Y_ADD_1:
INCMS Y ; Increase Y
NOP
JMP @B ; Jump to checksum calculate
CHECKSUM_END:
…
…
END_USER_CODE: ; Label of program end
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.2 CODE OPTION TABLE
Code Option Content Function Description
IHRC_6M
High_Clk
Watch_Dog
Fcpu
Reset_Pin
Security
IHRC_RTC
6MHz 6MHz crystal /resonator for external high clock oscillator.
Always_On
Enable
Disable Disable Watchdog function.
Fhosc/1 Instruction cycle is oscillator clock.
Fhosc/2 Instruction cycle is 2 oscillator clocks.
Fhosc/4 Instruction cycle is 4 oscillator clocks.
Reset Enable External reset pin.
P14 Enable P1.4 input only without pull-up resister.
Enable Enable ROM code Security function.
Disable Disable ROM code Security function.
Note: Fcpu code option is only available for High Clock. Fcpu of slow mode is Flosc/4.
High speed internal 6MHz RC. XIN/XOUT become to P1.3/P1.2
bi-direction I/O pins.
High speed internal 6MHz RC with 0.5sec RTC. XIN/XOUT connect with
external 32768 crystal.
Watchdog timer is always on enable even in power down and green
mode.
Enable watchdog timer. Watchdog timer stops in power down mode and
green mode.
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Page 25
2.1.3 DATA MEMORY (RAM)
) 256 X 8-bit RAM
Address
000h
“
“
“
“
“
BANK 0
BANK1
07Fh
080h
“
“
“
“
“
0FFh
100h
“
“
“
“
“
17Fh
SN8P2200 Series
RAM location
General purpose area
System register
End of bank 0 area
General purpose area
USB 1.1 Low-Speed 8-Bit Micro-Controller
BANK 0
80h~FFh of Bank 0 store
system registers (128
bytes).
BANK1
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.4 SYSTEM REGISTER
2.1.4.1
SYSTEM REGISTER TABLE
0 1 2 3 4 5 6 7 8 9 A B C D E F
- - R Z Y - PFLAG RBANK - - - - - - - -
8
- - - - - - - - - - - - - - - -
9
UDA UE0R UE1R UE2R UE3R UDP0 UDR0 UDP1 UDR1
A
- - - - - - - - P0M - - - - -
B
- P1M - - - P5M - - INTRQ INTEN OSCM - WDTR TC0R PCL PCH
C
P0 P1 - - - P5 - - T0M T0C TC0M TC0C - - - STKP
D
P0UR P1UR - - - P5UR - @YZ - P1OC - - - - - -
E
STK7L STK7H STK6L
F
STK6
STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H
H
2.1.4.2
SYSTEM REGISTER DESCRIPTION
R = Working register and ROM look-up data buffer. Y, Z = Working, @YZ and ROM addressing register.
PFLAG = ROM page and special flag register. RBANK = RAM bank selection register.
UDA = USB control register. UE0R~UE3R = Endpoint 0~3 control registers.
UDP0 = USB FiFo 0 address pointer. UDR0 = USB FiFo 0 data buffer by UDP0 point to.
UDP1 = USB FiFo 1 address pointer. UDR1 = USB FiFo 1 data buffer by UDP1 point to.
USTATUS = USB status register. UPID = USB bus control register.
T1M = T1 mode register. T1C = T1 counting register.
T2M = T2 mode register. T2C = T2 counting register.
PS2M = PS2 control register. PEDGE = P0.0 edge direction register.
PnM = Port n input/output mode register. INTEN = Interrupt enable register.
INTRQ = Interrupt request register. WDTR = Watchdog timer clear register.
OSCM = Oscillator mode register. PCH, PCL = Program counter.
TC0R = TC0 auto-reload data buffer. T0M = T0 mode register.
Pn = Port n data buffer. TC0M = TC0 mode register.
T0C = T0 counting register. STKP = Stack pointer buffer.
TC0C = TC0 counting register. @YZ = RAM YZ indirect addressing index pointer.
PnUR = Port n pull-up resister control register. STK0~STK3 = Stack 0 ~ stack 3 buffer.
P1OC = Port 1 open-drain control register.
USTAT
US
UPID T1M T1C T2M T2C PS2M
- PEDGE
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.4.3
BIT DEFINITION of SYSTEM REGISTER
Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Remarks
082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 R/W R
083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R/W Z
084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R/W Y
086H NT0 NPD C DC Z R/W PFLAG
087H RBNKS0 R/W RBANK
0A0H UDE UDA6 UDA5 UDA4 UDA3 UDA2 UDA1 UDA0 R/W UDA
0A1H UE0E UE0S UE0DO UE0DI UE0C3 UE0C2 UE0C1 UE0C0 R/W UE0R
0A2H UE1E FFS1 UE1DO UE1DI UE1C3 UE1C2 UE1C1 UE1C0 R/W UE1R
0A3H UE2E FFS2 UE2DO UE2DI UE2C3 UE2C2 UE2C1 UE2C0 R/W UE2R
0A4H UE3E FFS3 UE3DO UE3DI UE3C3 UE3C2 UE3C1 UE3C0 R/W UE3R
0A5H UDP04 UDP03 UDP02 UDP01 UDP00 R/W UDP0
0A6H UDR07 UDR06 UDR05 UDR04 UDR03 UDR02 UDR01 UDR00 R/W UDR0
0A7H UDP14 UDP13 UDP12 UDP11 UDP10 R/W UDP1
0A8H UDR17 UDR16 UDR15 UDR14 UDR13 UDR12 UDR11 UDR10 R/W UDR1
0A9H FFS0 USPND URST UEP0OC4 UEP0OC3 UEP0OC2 UEP0OC1 UEP0OC00 R/W USTATUS
0AAH EP3STALL EP2STALL EP1STALL EP0STALL UBDE DDP DDN W UPID
0ABH T1ENB T1rate2 T1rate1 T1rate0 T1G1 T1G0 R/W T1M
0ACH T1C7 T1C6 T1C5 T1C4 T1C3 T1C2 T1C1 T1C0 R/W T1C
0ADH T2ENB T2rate2 T2rate1 T2rate0 T2G1 T2G0 R/W T2M
0AEH T2C7 T2C6 T2C5 T2C4 T2C3 T2C2 T2C1 T2C0 R/W T2C
0AFH PS2ENB SDA SCK SDAM SCKM R/W PS2M
0B8H P06M P05M P04M P03M P02M P01M P00M R/W P0M
0BFH P00G1 P00G0 R/W PEDGE
0C1H P17M P16M P15M P13M P12M P11M P10M R/W P1M
0C5H P57M P56M P55M P54M P53M P52M P51M P50M R/W P5M
0C8H USBIRQ TC0IRQ T0IRQ T2IRQ T1IRQ P00IRQ R/W INTRQ
0C9H USBIEN TC0IEN T0IEN T2IEN T1IEN P00IEN R/W INTEN
0CAH CPUM1 CPUM0 CLKMD STPHX R/W OSCM
0CCH WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0 W WDTR
0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R
0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W PCL
0CFH PC12 PC11 PC10 PC9 PC8 R/W PCH
0D0H P06 P05 P04 P03 P02 P01 P00 R/W P0
0D1H P17 P16 P15 P14 P13 P12 P11 P10 R/W P1
0D5H P57 P56 P55 P54 P53 P52 P51 P50 R/W P5
0D8H T0ENB T0rate2 T0rate1 T0rate0 T0TB R/W T0M
0D9H T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R/W T0C
0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 TC0CKS ALOAD0 TC0OUT PWM0OUT R/W TC0M
0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 R/W TC0C
0DFH GIE STKPB2 STKPB1 STKPB0 R/W STKP
0E0H P06R P05R P04R P03R P02R P01R P00R W P0UR
0E1H P17R P16R P15R P13R P12R P11R P10R W P1UR
0E5H P57R P56R P55R P54R P53R P52R P51R P50R W P5UR
0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 R/W @YZ
0E9H P11OC P10OC W P1OC
0F0H S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 R/W STK7L
0F1H S7PC12 S7PC11 S7PC10 S7PC9 S7PC8 R/W STK7H
0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 R/W STK6L
0F3H S6PC12 S6PC11 S6PC10 S6PC9 S6PC8 R/W STK6H
0F4H S5PC7 S5PC6 S5PC5 S5PC4 S5PC3 S5PC2 S5PC1 S5PC0 R/W STK5L
0F5H S5PC12 S5PC11 S5PC10 S5PC9 S5PC8 R/W STK5H
0F6H S4PC7 S4PC6 S4PC5 S4PC4 S4PC3 S4PC2 S4PC1 S4PC0 R/W STK4L
0F7H S4PC12 S4PC11 S4PC10 S4PC9 S4PC8 R/W STK4H
0F8H S3PC7 S3PC6 S3PC5 S3PC4 S3PC3 S3PC2 S3PC1 S3PC0 R/W STK3L
0F9H S3PC12 S3PC11 S3PC10 S3PC9 S3PC8 R/W STK3H
0FAH S2PC7 S2PC6 S2PC5 S2PC4 S2PC3 S2PC2 S2PC1 S2PC0 R/W STK2L
0FBH S2PC12 S2PC11 S2PC10 S2PC9 S2PC8 R/W STK2H
0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R/W STK1L
0FDH S1PC12 S1PC11 S1PC10 S1PC9 S1PC8 R/W STK1H
0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R/W STK0L
0FFH S0PC12 S0PC11 S0PC10 S0PC9 S0PC8 R/W STK0H
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Page 28
Note:
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
1. To avoid system error, please be sure to put all the “0” and “1” as it indicates in the above
table.
2. All of register names had been declared in SN8ASM assembler.
3. One-bit name had been declared in SN8ASM assembler with “F” prefix code.
4. “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions are only available to the “R/W” registers.
5. For detail description, please refer to the “System Register Quick Reference Table”.
SONiX TECHNOLOGY CO., LTD Page 28 Version 1.7
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.4.4
ACCUMULATOR
The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If
the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.
ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing
mode.
¾ Example: Read and write ACC value.
; Read ACC data and store in BUF data memory.
MOV BUF, A
; Write a immediate data into ACC.
MOV A, #0FH
; Write ACC data from BUF data memory.
MOV A, BUF
; or
B0MOV A, BUF
The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be saved to
other data memories. “PUSH”, “POP” save and load ACC, PFLAG data into buffers.
¾ Example: Protect ACC and working registers.
INT_SERVICE:
PUSH ; Save ACC and PFLAG to buffers.
… .
…
POP ; Load ACC and PFLAG from buffers.
RETI ; Exit interrupt service vector
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
2.1.4.5
PROGRAM FLAG
The PFLAG register contains the arithmetic status of ALU operation, system reset status and LVD detecting status.
NT0, NPD bits indicate system reset status including power on reset, LVD reset, reset by external pin active and
watchdog reset. C, DC, Z bits indicate the result status of ALU operation.
086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PFLAG
Read/Write R/W R/W - - - R/W R/W R/W
After reset - - - - - 0 0 0
Bit [7:6] NT0, NPD: Reset status flag.
Bit 2 C: Carry flag
Bit 1 DC: Decimal carry flag
Bit 0 Z: Zero flag
Note: Refer to instruction set table for detailed information of C, DC and Z flags.
NT0 NPD - - - C DC Z
NT0 NPD Reset Status
0 0 Watch-dog time out
0 1 Reserved
1 0 Reset by LVD
1 1 Reset by external Reset Pin
1 = Addition with carry, subtraction without borrowing, rotation with shifting out logic “1”, comparison result
≥ 0.
0 = Addition without carry, subtraction with borrowing signal, rotation with shifting out logic “0”, comparison
result < 0.
1 = Addition with carry from low nibble, subtraction without borrow from high nibble.
0 = Addition without carry from low nibble, subtraction with borrow from high nibble.
1 = The result of an arithmetic/logic/branch operation is zero.
0 = The result of an arithmetic/logic/branch operation is not zero.
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2.1.4.6
PROGRAM COUNTER
The program counter (PC) is a 13-bit binary counter separated into the high-byte 5 and the low-byte 8 bits. This
counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program
counter is automatically incremented with each instruction during program execution.
Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction
is executed, the destination address will be inserted to bit 0 ~ bit 12.
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PC
After
reset
) ONE ADDRESS SKIPPING
There are nine instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one
address skipping function. If the result of these instructions is true, the PC will add 2 steps to skip next instruction.
If the condition of bit test instruction is true, the PC will add 2 steps to skip next instruction.
JMP C0STEP ; Else jump to C0STEP.
…
…
C0STEP: NOP
B0MOV A, BUF0 ; Move BUF0 value to ACC.
JMP C1STEP ; Else jump to C1STEP.
…
…
C1STEP: NOP
If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.
JMP C0STEP ; Else jump to C0STEP.
…
…
C0STEP: NOP
- - - PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
- - - 0 0 0 0 0 0 0 0 0 0 0 0 0
PCH PCL
B0BTS1
B0BTS0
CMPRS
FC ; To skip, if Carry_flag = 1
FZ ; To skip, if Zero flag = 0.
A, #12H ; To skip, if ACC = 12H.
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If the destination increased by 1, which results overflow of 0xFF to 0x00, the PC will add 2 steps to skip next
instruction.
INCS instruction:
JMP C0STEP ; Jump to C0STEP if ACC is not zero.
…
…
C0STEP: NOP
INCMS instruction:
JMP C0STEP ; Jump to C0STEP if BUF0 is not zero.
…
…
C0STEP: NOP
If the destination decreased by 1, which results underflow of 0x00 to 0xFF, the PC will add 2 steps to skip next
instruction.
DECS instruction:
JMP C0STEP ; Jump to C0STEP if ACC is not zero.
…
…
C0STEP: NOP
DECMS instruction:
JMP C0STEP ; Jump to C0STEP if BUF0 is not zero.
…
…
C0STEP: NOP
INCS
INCMS
DECS
DECMS
BUF0
BUF0
BUF0
BUF0
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) MULTI-ADDRESS JUMPING
Users can jump around the multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate
multi-address jumping function. Program Counter supports “ADD M,A”, ”ADC M,A” and “B0ADD M,A” instructions
for carry to PCH when PCL overflow automatically. For jump table or others applications, users can calculate PC value
by the three instructions and don’t care PCL overflow problem.
Note: PCH only support PC up counting result and doesn’t support PC down counting. When PCL is
carry after PCL+ACC, PCH adds one automatically. If PCL borrow after PCL–ACC, PCH keeps value and
not change.
¾ Example: If PC = 0323H (PCH = 03H, PCL = 23H)
; PC = 0323H
MOV A, #28H
B0MOV PCL, A ; Jump to address 0328H
…
; PC = 0328H
MOV A, #00H
B0MOV PCL, A ; Jump to address 0300H
…
¾ Example: If PC = 0323H (PCH = 03H, PCL = 23H)
; PC = 0323H
B0ADD PCL, A ; PCL = PCL + ACC, the PCH cannot be changed.
JMP A0POINT ; If ACC = 0, jump to A0POINT
JMP A1POINT ; ACC = 1, jump to A1POINT
JMP A2POINT ; ACC = 2, jump to A2POINT
JMP A3POINT ; ACC = 3, jump to A3POINT
…
…
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2.1.4.7
Y, Z REGISTERS
The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.
z can be used as general working registers
z can be used as RAM data pointers with @YZ register
z can be used as ROM data pointer with the MOVC instruction for look-up table
084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Y
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset - - - - - - - -
083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Z
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset - - - - - - - -
¾ Example: Uses Y, Z register as the data pointer to access data in the RAM address 025H of bank0.
B0MOV Y, #00H ; To set RAM bank 0 for Y register
B0MOV Z, #25H ; To set location 25H for Z register
B0MOV A, @YZ ; To read a data into ACC
¾ Example: Uses the Y, Z register as data pointer to clear the RAM data.
B0MOV Y, #0 ; Y = 0, bank 0
B0MOV Z, #07FH ; Z = 7FH, the last address of the data memory area
CLR_YZ_BUF:
CLR @YZ ; Clear @YZ to be zero
DECMS Z ; Z – 1, if Z= 0, finish the routine
JMP CLR_YZ_BUF ; Not zero
CLR @YZ
END_CLR: ; End of clear general purpose data memory area of bank 0
…
YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0
ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0
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2.1.4.8
R REGISTERS
R register is an 8-bit buffer. There are two major functions of the register.
z Can be used as working register
z For store high-byte data of look-up table
(MOVC instruction executed, the high-byte data of specified ROM address will be stored in R register and the
low-byte data will be stored in ACC).
082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
R
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset - - - - - - - -
Note: Please refer to the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.
RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0
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2.2 ADDRESSING MODE
2.2.1 IMMEDIATE ADDRESSING MODE
The immediate addressing mode uses an immediate data to set up the location in ACC or specific RAM.
¾ Example: Move the immediate data 12H to ACC.
MOV A, #12H ; To set an immediate data 12H into ACC.
¾ Example: Move the immediate data 12H to R register.
B0MOV R, #12H ; To set an immediate data 12H into R register.
Note: In immediate addressing mode application, the specific RAM must be 0x80~0x87 working register.
2.2.2 DIRECTLY ADDRESSING MODE
The directly addressing mode moves the content of RAM location in or out of ACC.
¾ Example: Move 0x12 RAM location data into ACC.
B0MOV A, 12H ; To get a content of RAM location 0x12 of bank 0 and save in
ACC.
¾ Example: Move ACC data into 0x12 RAM location.
B0MOV 12H, A ; To get a content of ACC and save in RAM location 12H of
bank 0.
2.2.3 INDIRECTLY ADDRESSING MODE
The indirectly addressing mode is to access the memory by the data pointer registers (Y/Z).
¾ Example: Indirectly addressing mode with @YZ register.
B0MOV Y, #0 ; To clear Y register to access RAM bank 0.
B0MOV Z, #12H ; To set an immediate data 12H into Z register.
B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location
; 012H into ACC.
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2.3 STACK OPERATION
2.3.1 OVERVIEW
The stack buffer has 8-level. These buffers are designed to push and pop up program counter’s (PC) data when
interrupt service routine and “CALL” instruction are executed. The STKP register is a pointer designed to point active
level in order to push or pop up data from stack buffer. The STKnH and STKnL are the stack buffers to store program
counter (PC) data.
RET /
RETI
CALL /
INTERRUPT
PCH
PCL
STACK Level
STKP - 1STKP + 1
STKP = 7
STKP = 6
STKP = 5
STKP
STKP = 4
STKP = 3
STKP = 2
STKP = 1
STKP = 0
STACK Buffer
High Byte
STK7H
STK6H
STK5H
STKP
STK4H
STK3H
STK2H
STK1H
STK0H
STACK Buffer
Low Byte
STK7L
STK6L
STK5L
STK4L
STK3L
STK2L
STK1L
STK0L
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2.3.2 STACK REGISTERS
The stack pointer (STKP) is a 3-bit register to store the address used to access the stack buffer, 13-bit data memory
(STKnH and STKnL) set aside for temporary storage of stack addresses.
The two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). Push
operation decrements the STKP and the pop operation increments each time. That makes the STKP always point to
the top address of stack buffer and write the last program counter value (PC) into the stack buffer.
The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt
service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer
(STKnH and STKnL) are located in the system register area bank 0.
0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STKP
Read/Write R/W - - - - R/W R/W R/W
After reset 0 - - - - 1 1 1
Bit[2:0] STKPBn: Stack pointer (n = 0 ~ 2)
Bit 7 GIE: Global interrupt control bit.
¾ Example: Stack pointer (STKP) reset, we strongly recommended to clear the stack pointers in the
beginning of the program.
MOV A, #00000111B
B0MOV STKP, A
0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STKnH
Read/Write - - - R/W R/W R/W R/W R/W
After reset - - - 0 0 0 0 0
0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STKnL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
STKn = STKnH , STKnL (n = 7 ~ 0)
GIE - - - - STKPB2 STKPB1 STKPB0
0 = Disable.
1 = Enable. Please refer to the interrupt chapter.
- - - SnPC12 SnPC11 SnPC10 SnPC9 SnPC8
SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0
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2.3.3 STACK OPERATION EXAMPLE
The two kinds of Stack-Save operations refer to the stack pointer (STKP) and write the content of program counter (PC)
to the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP decreases and points to
the next available stack location. The stack buffer stores the program counter about the op-code address. The
Stack-Save operation is as the following table.
Stack Level
STKPB2 STKPB1 STKPB0 High Byte Low Byte
0
1
2
3
4
5
6
7
8
> 8
There are Stack-Restore operations correspond to each push operation to restore the program counter (PC). The RETI
instruction uses for interrupt service routine. The RET instruction is for CALL instruction. When a pop operation occurs,
the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter
(PC) to the program counter registers. The Stack-Restore operation is as the following table.
Stack Level
STKPB2 STKPB1 STKPB0 High Byte Low Byte
8
7
6
5
4
3
2
1
0
STKP Register Stack Buffer
1 1 1 Free Free
1 1 0 STK0H STK0L
1 0 1 STK1H STK1L
1 0 0 STK2H STK2L
0 1 1 STK3H STK3L
0 1 0 STK4H STK4L
0 0 1 STK5H STK5L
0 0 0 STK6H STK6L
1 1 1 STK7H STK7L
1 1 0 - -
STKP Register Stack Buffer
1 1 1 STK7H STK7L
0 0 0 STK6H STK6L
0 0 1 STK5H STK5L
0 1 0 STK4H STK4L
0 1 1 STK3H STK3L
1 0 0 STK2H STK2L
1 0 1 STK1H STK1L
1 1 0 STK0H STK0L
1 1 1 Free Free
Description
Stack Over, error
Description
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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3 RESET
3.1 OVERVIEW
The system would be reset in three conditions as following.
z Power on reset
z Watchdog reset
z Brown out reset
z External reset (only supports external reset pin enable situation)
When any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared.
After reset status released, the system boots up and program starts to execute from ORG 0. The NT0, NPD flags
indicate system reset status. The system can depend on NT0, NPD status and go to different paths by program.
086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PFLAG
Read/Write R/W R/W - - - R/W R/W R/W
After reset - - - - - 0 0 0
Bit [7:6] NT0, NPD: Reset status flag.
NT0 NPD - - - C DC Z
NT0 NPD Condition Description
0 0 Watchdog reset Watchdog timer overflow.
0 1 Reserved 1 0 Power on reset and LVD reset. Power voltage is lower than LVD detecting level.
1 1 External reset External reset pin detect low level status.
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Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset
successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of
different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client
terminal application, users have to take care the power on reset time for the master terminal requirement. The reset
timing diagram is as following.
Power
External Reset
Watchdog Reset
System Status
VDD
VSS
VDD
VSS
Watchdog Normal Run
Watchdog Stop
System Normal Run
System Stop
LVD Detect Level
Power On
Delay Time
External Reset
Low Detect
External Reset
High Detect
External
Reset Delay
Time
Watchdog
Overflow
Watchdog
Reset Delay
Time
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3.2 POWER ON RESET
The power on reset depend no LVD operation for most power-up situations. The power supplying to system is a rising
curve and needs some time to achieve the normal voltage. Power on reset sequence is as following.
z Power-up: System detects the power voltage up and waits for power stable.
z External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
z System initialization: All system registers is set as initial conditions and system is ready.
z Oscillator warm up: Oscillator operation is successfully and supply to system clock.
z Program executing: Power on sequence is finished and program executes from ORG 0.
3.3 WATCHDOG RESET
Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.
Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer
overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and
returns normal mode. Watchdog reset sequence is as following.
z Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the
system is reset.
z System initialization: All system registers is set as initial conditions and system is ready.
z Oscillator warm up: Oscillator operation is successfully and supply to system clock.
z Program executing: Power on sequence is finished and program executes from ORG 0.
Watchdog timer application note is as following.
z Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
z Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
z Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.
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3.4 BROWN OUT RESET
3.4.1 BROWN OUT DESCRIPTION
The brown out reset is a power dropping condition. The power drops from normal voltage to low voltage by external
factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well
or executing program error.
VDD
System Work
Well Area
V1
V2
VSS
Brown Out Reset Diagram
The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power
range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset
diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate
the system working area. The above area is the system work well area. The below area is the system work error area
called dead-band. V1 doesn’t touch the below area and not effect the system operation. But the V2 and V3 is under the
below area and may induce the system error occurrence. Let system under dead-band includes some conditions.
DC application:
The power source of DC application is usually using battery. When low battery condition and MCU drive any loading,
the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system
reset voltage. That makes the system under dead-band.
AC application:
In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC
noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating
induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power
situation.
The power on duration and power down duration are longer in AC application. The system power on sequence protects
the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power,
the VDD drops slowly and through the dead-band for a while.
V3
System Work
Error Area
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3.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION
To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system
executing rate and power level. Different system executing rates have different system minimum operating voltage.
The electrical characteristic section shows the system voltage to executing rate relationship.
System Mini.
Vdd (V)
Normal Operating
Area
Operating Voltage.
Dead-Band Area
Reset Area
System Rate (Fcpu)
System Reset
Voltage.
Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is
decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even
higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system
reset voltage.
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3.4.3 BROWN OUT RESET IMPROVEMENT
How to improve the brown reset condition? There are some methods to improve brown out reset as following.
z LVD reset
z Watchdog reset
z Reduce the system executing rate
z External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)
Note:
1. The “ Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can
completely improve the brown out reset, DC low battery and AC slow power down conditions.
2. For AC power application and enhance EFT performance, the system clock is 4MHz/4 (1 mips)
and use external reset (“ Zener diode reset circuit”, “Voltage bias reset circuit”, “External reset
IC”). The structure can improve noise effective and get good EFT characteristic.
LVD reset:
Power
System Status
VDD
VSS
System Normal Run
System Stop
LVD Detect Voltage
Power is below LVD Detect
Voltage and System Reset.
Power On
Delay Time
The LVD (low voltage detector) is built-in Sonix 8-bit MCU to be brown out reset protection. When the VDD drops and
is below LVD detect voltage, the LVD would be triggered, and the system is reset. The LVD detect level is different by
each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to
improve brown out reset is depend on application requirement and environment. If the power variation is very deep,
violent and trigger the LVD, the LVD can be the protection. If the power variation can touch the LVD detect level and
make system work error, the LVD can’t be the protection and need to other reset methods. More detail LVD information
is in the electrical characteristic section.
Watchdog reset:
The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear
at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the
watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t
be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of
watchdog timer triggers the system to reset, and the system return to normal mode after reset sequence. This method
also can improve brown out reset condition and make sure the system to return normal mode.
If the system reset by watchdog and the power is still in dead-band, the system reset sequence won’t be successful
and the system stays in reset status until the power return to normal range.
Reduce the system executing rate:
If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band.
The lower system rate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue
and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue.
This way needs to modify whole program timing to fit the application requirement.
External reset circuit:
The external reset methods also can improve brown out reset and is the complete solution. There are three external
reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External
reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under
power dropping and under dead-band. The external reset information is described in the next section.
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3.5 EXTERNAL RESET
External reset function is controlled by “Reset_Pin” code option. Set the code option as “Reset” option to enable
external reset function. External reset pin is Schmitt Trigger structure and low level active. The system is running when
reset pin is high level voltage input. The reset pin receives the low voltage and the system is reset. The external reset
operation actives in power on and normal running mode. During system power-up, the external reset pin must be high
level input, or the system keeps in reset status. External reset sequence is as following.
z External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is
not high level, the system keeps reset status and waits external reset pin released.
z System initialization: All system registers is set as initial conditions and system is ready.
z Oscillator warm up: Oscillator operation is successfully and supply to system clock.
z Program executing: Power on sequence is finished and program executes from ORG 0.
The external reset can reset the system during power on duration, and good external reset circuit can protect the
system to avoid working at unusual power condition, e.g. brown out reset in AC power application…
3.6 EXTERNAL RESET CIRCUIT
3.6.1 Simply RC Reset Circuit
VDD
R1
47K ohm
R2
S
T
R
C1
100 ohm
0.1uF
This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into
reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from
the timing difference.
MCU
VSS
VCC
GND
Note: The reset circuit is no any protection against unusual power or brown out reset.
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3.6.2 Diode & RC Reset Circuit
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
VDD
C1
R1
47K ohm
R2
100 ohm
R
S
VSS
T
MCU
VCC
GND
DIODE
0.1uF
This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal.
The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct
higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can
improve slight brown out reset condition.
Note: The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to
limit any current flowing into reset pin from external capacitor C in the event of reset pin
breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).
3.6.3 Zener Diode Reset Circuit
VDD
R1
33K ohm
Vz
R2
10K ohm
The zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition
completely. Use zener voltage to be the active level. When VDD voltage level is above “Vz + 0.7V”, the C terminal of
the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of
the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by zener
specification. Select the right zener voltage to conform the application.
B
R3
40K ohm
E
Q1
R
S
T
C
MCU
VSS
VCC
GND
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3.6.4 Voltage Bias Reset Circuit
R1
47K ohm
R2
10K ohm
SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
VDD
E
B
Q1
R
S
T
C
R3
2K ohm
MCU
VSS
VCC
GND
The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely.
The operating voltage is not accurate as zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When
VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high
voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor
outputs low voltage and MCU is in reset mode.
Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the
circuit diagram condition, the MCU’s reset pin level varies with VDD voltage variation, and the differential voltage is
0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the
reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external
reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power
system, the current must be considered to whole system power consumption.
Note: Under unstable power condition as brown out reset, “Zener diode rest circuit” and “Voltage bias
reset circuit” can protects system no any error occurrence as power dropping. When power drops
below the reset detect voltage, the system reset would be triggered, and then system executes
reset sequence. That makes sure the system work well under unstable power situation.
3.6.5 External Reset IC
VDD
Bypass
Capacitor
VDD
Reset
0.1uF
RST
IC
R
T
S
MCU
VSS
VSS
VCC
GND
The external reset circuit also use external reset IC to enhance MCU reset performance. This is a high cost and good
effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can
improve all power variation.
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
4 SYSTEM CLOCK
4.1 OVERVIEW
The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is
generated from the external oscillator circuit or on-chip 6MHz high-speed RC oscillator circuit (IHRC 6MHz). The
low-speed clock is generated from on-chip low-speed RC oscillator circuit (ILRC 16KHz @3V, 32KHz @5V).
Both the high-speed clock and the low-speed clock can be system clock (Fosc). The system clock in slow mode is
divided by 4 to be the instruction cycle (Fcpu).
) Normal Mode (High Clock): Fcpu = Fhosc / N, N = 1 ~ 4, Select N by Fcpu code option.
) Slow Mode (Low Clock): Fcpu = Flosc/4.
4.2 CLOCK BLOCK DIAGRAM
STPHX HOSC
XIN
XOUT
z HOSC: High_Clk code option.
z Fhosc: External high-speed clock (only 6MHz) / Internal high-speed RC clock (6MHz).
z Flosc: Internal low-speed RC clock (about 16KHz@3V, 32KHz@5V).
z Fosc: System clock source.
z Fcpu: Instruction cycle.
Fhosc. Fcpu = Fhosc/1 ~ Fhosc/4
CPUM[1:0]
Flosc. Fcpu = Flosc/4
Fcpu Code Option
Fosc
Fosc
CLKMD
Fcpu
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
4.3 OSCM REGISTER
The OSCM register is an oscillator control register. It controls oscillator status, system mode.
0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OSCM
Read/Write - - - R/W R/W R/W R/W -
After reset - - - 0 0 0 0 -
Bit 1 STPHX: External high-speed oscillator control bit.
0 = External high-speed oscillator free run.
1 = External high-speed oscillator free run stop. Internal low-speed RC oscillator is still running.
Bit 2 CLKMD: System high/Low clock mode control bit.
0 = Normal (dual) mode. System clock is high clock.
1 = Slow mode. System clock is internal low clock.
Bit[4:3] CPUM[1:0]: CPU operating mode control bits.
00 = normal.
01 = sleep (power down) mode.
10 = green mode.
11 = reserved.
¾ Example: Stop high-speed oscillator
B0BSET FSTPHX ; To stop external high-speed oscillator only.
¾ Example: When entering the power down mode (sleep mode), both high-speed oscillator and internal
low-speed oscillator will be stopped.
B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
0 0 0 CPUM1 CPUM0 CLKMD STPHX 0
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
4.4 SYSTEM HIGH CLOCK
The system high clock is from internal 6MHz oscillator RC type or external oscillator. The high clock type is controlled
by “High_Clk” code option.
High_Clk Code Option Description
IHRC_6M
IHRC_RTC
6M The high clock is external oscillator and only for 6MHz.
4.4.1 INTERNAL HIGH RC
The chip is built-in RC type internal high clock (6MHz) controlled by “IHRC_6M” or “IHRC_RTC” code options. In
“IHRC_6M” mode, the system clock is from internal 6MHz RC type oscillator and XIN / XOUT pins are general-purpose
I/O pins. In “IHRC_RTC” mode, the system clock is from internal 6MHz RC type oscillator and XIN / XOUT pins are
connected with external 32768 crystal for real time clock (RTC).
z IHRC: High clock is internal 6MHz oscillator RC type. XIN/XOUT pins are general purpose I/O pins.
z IHRC_RTC: High clock is internal 6MHz oscillator RC type. XIN/XOUT pins are connected with external 32768Hz
crystal/ceramic oscillator for RTC clock source.
The RTC period is 0.5 sec and RTC timer is T0. Please consult “T0 Timer” chapter to apply RTC function.
The high clock is internal 6MHz oscillator RC type. XIN and XOUT pins are general
purpose I/O pins.
The high clock is internal 6MHz oscillator RC type. XIN and XOUT pins connect with
32768Hz crystal for RTC clock source.
4.4.2 EXTERNAL HIGH CLOCK
External high clock is only support 6MHz Crystal/Ceramic. The high clock oscillator module is controlled by High_Clk
code option.
CRYSTAL/CERAMIC
4.4.2.1
Crystal/Ceramic devices are driven by XIN, XOUT pins. 6M option is for high speed 6MHz. In IHRC_RTC mode,
XIN/XOUT is connected with 32768Hz crystal for 0.5 sec RTC.
XIN
CRYSTAL
C
20pF
X
C
20pF
T
U
O
MCU
VDD
VSS
VCC
GND
Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of
micro-controller.
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
4.5 SYSTEM LOW CLOCK
The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator
uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common
condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relation between the RC
frequency and voltage is as the following figure.
Internal Low RC Frequency
45.00
40.00
35.00
30.00
25.00
20.00
15.00
Freq. (KHz)
10.00
5.00
0.00
2.12.533.13.33.544.555.566.57
7.52
10.64
14.72
16.00
17.24
18.88
22.24
25.96
29.20
32.52
35.40
38.08
40.80
ILRC
VDD (V)
The internal low RC supports watchdog clock source and system slow mode controlled by CLKMD.
) Flosc = Internal low RC oscillator (about 16KHz @3V, 32KHz @5V).
) Slow mode Fcpu = Flosc / 4
There are two conditions to stop internal low RC. One is power down mode, and the other is green mode of 32K mode
and watchdog disable. If system is in 32K mode and watchdog disable, only 32K oscillator actives and system is under
low power consumption.
¾ Example: Stop internal low-speed oscillator by power down mode.
B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed
; oscillator called power down mode (sleep mode).
Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0, CPUM1
(32K, watchdog disable) bits of OSCM register.
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USB 1.1 Low-Speed 8-Bit Micro-Controller
4.5.1 SYSTEM CLOCK MEASUREMENT
Under design period, the users can measure system clock speed by software instruction cycle (Fcpu). This way is
useful in RC mode.
¾ Example: Fcpu instruction cycle of external oscillator.
B0BSET P0M.0 ; Set P0.0 to be output mode for outputting Fcpu toggle signal.
@@:
B0BSET P0.0 ; Output Fcpu toggle signal in low-speed clock mode.
B0BCLR P0.0 ; Measure the Fcpu frequency by oscilloscope.
JMP @B
Note: Do not measure the RC frequency directly from XIN; the probe impendence will affect the RC
frequency.
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SN8P2200 Series
USB 1.1 Low-Speed 8-Bit Micro-Controller
5 SYSTEM OPERATION MODE
5.1 OVERVIEW
The chip is featured with low power consumption by switching around four different modes as following.
z High-speed mode
z Low-speed mode
z Power-down mode (Sleep mode)
z Green mode
Power Down Mode
P0, P1 Wake-up Function Active.
USB Bus.
External Reset Circuit Active.
(Sleep Mode)
CPUM1, CPUM0 = 01.
CLKMD = 1
Slow Mode
P0, P1 Wake-up Function Active.
T0 Timer Time Out.
USB Bus.
P0, P1 Wake-up Function Active.
T0 Timer Time Out.
USB Bus.
External Reset Circuit Active.
Normal Mode
CLKMD = 0
CPUM1, CPUM0 = 10.
Green Mode
External Reset Circuit
Active.
System Mode Switching Diagram
Operating mode description
MODE NORMAL SLOW GREEN
EHOSC Running By STPHX By STPHX Stop
IHRC Running By STPHX By STPHX Stop
ILRC Running Running Running Stop
EHOSC with RTC Running By STPHX Running Stop
IHRC with RTC Running By STPHX Stop Stop
ILRC with RTC Running Running Stop Stop
CPU instruction Executing Executing Stop Stop
T0 timer *Active *Active *Active Inactive * Active if T0ENB=1
TC0 timer *Active *Active Inactive Inactive * Active if TC0ENB=1
Watchdog timer
Internal interrupt All active All active T0 All inactive
External interrupt All active All active All active All inactive
Wakeup source - -
z EHOSC: External high clock
z IHRC: Internal high clock (16M RC oscillator)
z ILRC: Internal low clock (16K RC oscillator at 3V, 32K at 5V)
By Watch_Dog
Code option
By Watch_Dog
Code option
By Watch_Dog
Code option
P0, P1, T0
Reset
POWER DOWN
(SLEEP)
By Watch_Dog
Code option
P0, P1, Reset
Refer to code option
REMARK
description
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USB 1.1 Low-Speed 8-Bit Micro-Controller
5.2 SYSTEM MODE SWITCHING EXAMPLE
¾ Example: Switch normal/slow mode to power down (sleep) mode.
B0BSET FCPUM0 ; Set CPUM0 = 1.
Note: During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.
¾ Example: Switch normal mode to slow mode.
B0BSET FCLKMD ;To set CLKMD = 1, Change the system into slow mode
B0BSET FSTPHX ;To stop external high-speed oscillator for power saving.
¾ Example: Switch slow mode to normal mode (The external high-speed oscillator is still running).
B0BCLR FCLKMD ;To set CLKMD = 0
¾ Example: Switch slow mode to normal mode (The external high-speed oscillator stops).
If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for
external clock stable.
B0BCLR FSTPHX ; Turn on the external high-speed oscillator.
MOV A, #27 ; If VDD = 5V, internal RC=32KHz (typical) will delay
B0MOV Z, A
@@: DECMS Z ; 0.125ms X 81 = 10.125ms for external clock stable
JMP @B
;
B0BCLR FCLKMD ; Change the system back to the normal mode
¾ Example: Switch normal/slow mode to green mode.
B0BSET FCPUM1 ; Set CPUM1 = 1.
Note: If T0 timer wakeup function is disabled in the green mode, only the wakeup pin and reset pin can
wakeup the system backs to the previous operation mode.
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USB 1.1 Low-Speed 8-Bit Micro-Controller
¾ Example: Switch normal/slow mode to green mode and enable T0 wake-up function.
; Set T0 timer wakeup function.
B0BCLR FT0IEN ; To disable T0 interrupt service
B0BCLR FT0ENB ; To disable T0 timer
MOV A,#20H ;
B0MOV T0M,A ; To set T0 clock = Fcpu / 64
MOV A,#74H
B0MOV T0C,A ; To set T0C initial value = 74H (To set T0 interval = 10 ms)
B0BCLR FT0IEN ; To disable T0 interrupt service
B0BCLR FT0IRQ ; To clear T0 interrupt request
; Go into green mode
B0BCLR FCPUM0 ;To set CPUMx = 10
B0BSET FCPUM1
Note: During the green mode with T0 wake-up function, the wakeup pin and T0 wakeup the system back
to the last mode. T0 wake-up period is controlled by program.
¾ Example: Switch normal/slow mode to green mode and enable T0 wake-up function with RTC.
; Set T0 timer wakeup function with 0.5 sec RTC.
; Go into green mode
B0BCLR FCPUM0 ;To set CPUMx = 10
B0BSET FCPUM1
B0BSET FT0ENB ; To enable T0 timer
B0BSET FT0ENB ; To enable T0 timer
B0BSET FT0TB ; To enable RTC function
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5.3 WAKEUP
5.3.1 OVERVIEW
Under power down mode (sleep mode) or green mode, program doesn’t execute. The wakeup trigger can wake the
system up to normal mode or slow mode. The wakeup trigger sources are external trigger (P0, P1 level change),
internal trigger (T0 timer overflow) and USB bus toggle.
z Power down mode is waked up to normal mode. The wakeup trigger is only external trigger (P0, P1 level change
and USB bus toggle)
z Green mode is waked up to last mode (normal mode or slow mode). The wakeup triggers are external trigger (P0,
P1 level change), internal trigger (T0 timer overflow) and USB bus toggle.
5.3.2 WAKEUP TIME
When the system is in power down mode (sleep mode), the high clock oscillator stops. When waked up from power
down mode, MCU waits for 4 internal 6MHz clock or 2048 external 6MHz clocks as the wakeup time to stable the
oscillator circuit. After the wakeup time, the system goes into the normal mode.
Note: Wakeup from green mode is no wakeup time because the clock doesn’t stop in green mode.
The value of the wakeup time is as the following.
“IHRC_6M” and “IHRC_RTC” mode:
The Wakeup time = 1/Fosc * 4 (sec)
“6M_X’tal” mode:
The Wakeup time = 1/Fosc * 2048 (sec) + high clock start-up time
Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.
¾ Example: In “IHRC_6M”, “IHRC_RTC” modes and power down mode (sleep mode), the system is waked
up. After the wakeup time, the system goes into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 4 = 0.6 us (Fosc = 6MHz)
¾ Example: In 6M_X’tal mode and power down mode (sleep mode), the system is waked up. After the
wakeup time, the system goes into normal mode. The wakeup time is as the following.
The wakeup time = 1/Fosc * 2048 = 0.341 ms (Fosc = 6MHz)
The total wakeup time = 0.341 ms + oscillator start-up time
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6 INTERRUPT
6.1 OVERVIEW
This MCU provides 6 interrupt sources, including 5 internal interrupt (T0/TC0/USB/T1/T2) and one external interrupt
(INT0). The external interrupt can wakeup the chip while the system is switched from power down mode to high-speed
normal mode. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other
interrupt request. On the contrast, when interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’
request. All of the interrupt request signals are stored in INTRQ register.
INTEN Interrupt Enable Register
INT0 Trigger
T0 Time Out
TC0 Time Out
USB Process End
T1 Trigger
T2 Trigger
Note: The GIE bit must enable during all interrupt operation.
INTRQ
2-Bit
Latchs
P00IRQ
T0IRQ
TC0IRQ
USBIRQ
T1IRQ
T2IRQ
Interrupt
Enable
Gating
Interrupt Vector Address (0008H)
Global Interrupt Request Signal
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6.2 INTEN INTERRUPT ENABLE REGISTER
INTEN is the interrupt request control register including one internal interrupts, one external interrupts enable control
bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the stack is
incremented and program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service
routine when the returning interrupt service routine instruction (RETI) is executed.
0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTEN
Read/Write - R/W R/W R/W - R/W R/W R/W
After reset - 0 0 0 - 0 0 0
Bit 0 P00IEN: External P0.0 interrupt (INT0) control bit.
0 = Disable INT0 interrupt function.
1 = Enable INT0 interrupt function.
Bit 1 T1IEN: T1 timer capture interrupt control bit.
0 = Disable T1 interrupt function.
1 = Enable T1 interrupt function.
Bit 2 T2IEN: T2 timer capture interrupt control bit.
0 = Disable T2 interrupt function.
1 = Enable T2 interrupt function.
Bit 4 T0IEN: T0 timer interrupt control bit.
0 = Disable T0 interrupt function.
1 = Enable T0 interrupt function.
Bit 5 TC0IEN: TC0 timer interrupt control bit.
0 = Disable TC0 interrupt function.
1 = Enable TC0 interrupt function.
Bit 6 USBIEN: USB interrupt control bit.
0 = Disable USB interrupt function.
1 = Enable USB interrupt function.
- USBIEN TC0IEN T0IEN - T2IEN T1IEN P00IEN
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6.3 INTRQ INTERRUPT REQUEST REGISTER
INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of the
interrupt requests occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by
programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests
occurring by the register and do the routine corresponding of the interrupt request.
0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTRQ
Read/Write - R/W R/W R/W - R/W R/W R/W
After reset - 0 0 0 - 0 0 0
Bit 0 P00IRQ: External P0.0 interrupt (INT0) request flag.
0 = None INT0 interrupt request.
1 = INT0 interrupt request.
Bit 1 T1IRQ: T1 timer interrupt request flag.
0 = None T1 interrupt request.
1 = T1 interrupt request.
Bit 2 T2IRQ: T2 timer interrupt request flag.
0 = None T2 interrupt request.
1 = T2 interrupt request.
Bit 4 T0IRQ: T0 timer interrupt request flag.
0 = None T0 interrupt request.
1 = T0 interrupt request.
Bit 5 TC0IRQ: TC0 timer interrupt request flag.
0 = None TC0 interrupt request.
1 = TC0 interrupt request.
Bit 6 USBIRQ: USB timer interrupt request flag.
0 = None USB interrupt request.
1 = USB interrupt request.
- USBIRQ TC0IRQ T0IRQ - T2IRQ T1IRQ P00IRQ
6.4 GIE GLOBAL INTERRUPT OPERATION
GIE is the global interrupt control bit. All interrupts start work after the GIE = 1 It is necessary for interrupt service
request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and
the stack add 1 level.
0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STKP
Read/Write R/W - - - - R/W R/W R/W
After reset 0 - - - - 1 1 1
Bit 7 GIE: Global interrupt control bit.
¾ Example: Set global interrupt control bit (GIE).
B0BSET FGIE ; Enable GIE
Note: The GIE bit must enable during all interrupt operation.
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GIE - - - - STKPB2 STKPB1 STKPB0
0 = Disable global interrupt.
1 = Enable global interrupt.
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SN8P2200 Series
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6.5 PUSH, POP ROUTINE
When any interrupt occurs, system will jump to ORG 8 and execute interrupt service routine. It is necessary to save
ACC, PFLAG data. The chip includes “PUSH”, “POP” for in/out interrupt service routine. The two instruction save and
load ACC, PFLAG data into buffers and avoid main routine error after interrupt service routine finishing.
¾ Note: ”PUSH”, “POP” instructions save and load ACC/PFLAG without (NT0, NPD). PUSH/POP buffer is
an unique buffer and only one level.
¾ Example: Store ACC and PAFLG data by PUSH, POP instructions when interrupt service routine
executed.
ORG 0
JMP START
ORG 8
JMP INT_SERVICE
ORG 10H
START:
…
INT_SERVICE:
PUSH ; Save ACC and PFLAG to buffers.
…
…
POP ; Load ACC and PFLAG from buffers.
RETI ; Exit interrupt service vector
…
ENDP
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6.6 INT0 (P0.0) INTERRUPT OPERATION
When the INT0 trigger occurs, the P00IRQ will be set to “1” no matter the P00IEN is enable or disable. If the P00IEN =
1 and the trigger event P00IRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG
8). If the P00IEN = 0 and the trigger event P00IRQ is still set to be “1”. Moreover, the system won’t execute interrupt
vector even when the P00IRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt
situation.
If the interrupt trigger direction is identical with wake-up trigger direction, the INT0 interrupt request flag (INT0IRQ) is
latched while system wake-up from power down mode or green mode by P0.0 wake-up trigger. System inserts to
interrupt vector (ORG 8) after wake-up immediately.
Note: INT0 interrupt request can be latched by P0.0 wake-up trigger.
Note: The interrupt trigger direction of P0.0 is control by PEDGE register.
0BFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PEDGE
Read/Write - - - R/W R/W - - -
After reset - - - 1 0 - - -
Bit[4:3] P00G[1:0]: P0.0 interrupt trigger edge control bits.
00 = reserved.
01 = rising edge.
10 = falling edge.
11 = rising/falling bi-direction (Level change trigger).
¾ Example: Setup INT0 interrupt request and bi-direction edge trigger.
MOV A, #18H
B0MOV PEDGE, A ; Set INT0 interrupt trigger as bi-direction edge.
B0BSET FP00IEN ; Enable INT0 interrupt service
B0BCLR FP00IRQ ; Clear INT0 interrupt request flag
B0BSET FGIE ; Enable GIE
- - - P00G1 P00G0 - - -
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¾ Example: INT0 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FP00IRQ ; Check P00IRQ
JMP EXIT_INT ; P00IRQ = 0, exit interrupt vector
B0BCLR FP00IRQ ; Reset P00IRQ
… ; INT0 interrupt service routine
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6.7 T0 INTERRUPT OPERATION
When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the
T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the
trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the
operation under multi-interrupt situation.
¾ Example: T0 interrupt request setup.
B0BCLR FT0IEN ; Disable T0 interrupt service
B0BCLR FT0ENB ; Disable T0 timer
MOV A, #20H ;
B0MOV T0M, A ; Set T0 clock = Fcpu / 64
MOV A, #74H ; Set T0C initial value = 74H
B0MOV T0C, A ; Set T0 interval = 10 ms
B0BSET FT0IEN ; Enable T0 interrupt service
B0BCLR FT0IRQ ; Clear T0 interrupt request flag
B0BSET FT0ENB ; Enable T0 timer
B0BSET FGIE ; Enable GIE
¾ Example: T0 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FT0IRQ ; Check T0IRQ
JMP EXIT_INT ; T0IRQ = 0, exit interrupt vector
B0BCLR FT0IRQ ; Reset T0IRQ
MOV A, #74H
B0MOV T0C, A ; Reset T0C.
… ; T0 interrupt service routine
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6.8 TC0 INTERRUPT OPERATION
When the TC0C counter overflows, the TC0IRQ will be set to “1” no matter the TC0IEN is enable or disable. If the
TC0IEN and the trigger event TC0IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC0IEN = 0, the trigger event TC0IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC0IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾ Example: TC0 interrupt request setup.
B0BCLR FTC0IEN ; Disable TC0 interrupt service
B0BCLR FTC0ENB ; Disable TC0 timer
MOV A, #20H ;
B0MOV TC0M, A ; Set TC0 clock = Fcpu / 64
MOV A, #74H ; Set TC0C initial value = 74H
B0MOV TC0C, A ; Set TC0 interval = 10 ms
B0BSET FTC0IEN ; Enable TC0 interrupt service
B0BCLR FTC0IRQ ; Clear TC0 interrupt request flag
B0BSET FTC0ENB ; Enable TC0 timer
B0BSET FGIE ; Enable GIE
¾ Example: TC0 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FTC0IRQ ; Check TC0IRQ
JMP EXIT_INT ; TC0IRQ = 0, exit interrupt vector
B0BCLR FTC0IRQ ; Reset TC0IRQ
MOV A, #74H
B0MOV TC0C, A ; Reset TC0C.
… ; TC0 interrupt service routine
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6.9 USB INTERRUPT OPERATION
When the USB process finished, the USBIRQ will be set to “1” no matter the USBIEN is enable or disable. If the
USBIEN and the trigger event USBIRQ is set to be “1”. As the result, the system will execute the interrupt vector. If
the USBIEN = 0, the trigger event USBIRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector
even when the USBIEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾ Example: USB interrupt request setup.
B0BCLR FUSBIEN ; Disable USB interrupt service
B0BCLR FUSBENB ; Disable USB timer
B0BCLR FUSBIRQ ; Clear USB interrupt request flag
B0BSET FUSBIEN ; Enable USB interrupt service
… ; USB initialize.
… ; USB operation.
B0BSET FUSBENB ; Enable USB timer
B0BSET FGIE ; Enable GIE
¾ Example: USB interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
PUSH ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
POP ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FUSBIRQ ; Check USBIRQ
JMP EXIT_INT ; USBIRQ = 0, exit interrupt vector
B0BCLR FUSBIRQ ; Reset USBIRQ
… ; USB interrupt service routine
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6.10 T1 INTERRUPT OPERATION
When the T1C counter stops by T1 pulse width measurement finished, the T1IRQ will be set to “1” no matter the T1IEN
is enable or disable. If the T1IEN and the trigger event T1IRQ is set to be “1”. As the result, the system will execute
the interrupt vector. If the T1IEN = 0, the trigger event T1IRQ is still set to be “1”. Moreover, the system won’t execute
interrupt vector even when the T1IEN is set to be “1”. Users need to be cautious with the operation under
multi-interrupt situation.
¾ Example: T1 interrupt request setup.
B0BCLR FT1IEN ; Disable T1 interrupt service
B0BCLR FT1ENB ; Disable T1 timer
MOV A, #20H ;
B0MOV T1M, A ; Set T1 clock = Fcpu / 64 and falling edge trigger.
CLR T1C
B0BSET FT1IEN ; Enable T1 interrupt service
B0BCLR FT1IRQ ; Clear T1 interrupt request flag
B0BSET FT1ENB ; Enable T1 timer
B0BSET FGIE ; Enable GIE
¾ Example: T1 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
PUSH ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
POP ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FT1IRQ ; Check T1IRQ
JMP EXIT_INT ; T1IRQ = 0, exit interrupt vector
B0BCLR FT1IRQ ; Reset T1IRQ
B0MOV A, T1C
B0MOV T1CBUF, A ; Save pulse width.
CLR T1C
… ; T1 interrupt service routine
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6.11 T2 INTERRUPT OPERATION
When the T2C counter stops by T2 pulse width measurement finished, the T2IRQ will be set to “1” no matter the T2IEN
is enable or disable. If the T2IEN and the trigger event T2IRQ is set to be “1”. As the result, the system will execute
the interrupt vector. If the T2IEN = 0, the trigger event T2IRQ is still set to be “1”. Moreover, the system won’t execute
interrupt vector even when the T2IEN is set to be “1”. Users need to be cautious with the operation under
multi-interrupt situation.
¾ Example: T2 interrupt request setup.
B0BCLR FT2IEN ; Disable T2 interrupt service
B0BCLR FT2ENB ; Disable T2 timer
MOV A, #20H ;
B0MOV T2M, A ; Set T2 clock = Fcpu / 64 and falling edge trigger.
CLR T2C
B0BSET FT2IEN ; Enable T2 interrupt service
B0BCLR FT2IRQ ; Clear T2 interrupt request flag
B0BSET FT2ENB ; Enable T2 timer
B0BSET FGIE ; Enable GIE
¾ Example: T2 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
PUSH ; Push routine to save ACC and PFLAG to buffers.
…
EXIT_INT:
POP ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
B0BTS1 FT2IRQ ; Check T2IRQ
JMP EXIT_INT ; T2IRQ = 0, exit interrupt vector
B0BCLR FT2IRQ ; Reset T2IRQ
B0MOV A, T2C
B0MOV T2CBUF, A ; Save pulse width.
CLR T2C
… ; T2 interrupt service routine
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6.12 MULTI-INTERRUPT OPERATION
Under certain condition, the software designer uses more than one interrupt requests. Processing multi-interrupt
request requires setting the priority of the interrupt requests. The IRQ flags of interrupts are controlled by the interrupt
event. Nevertheless, the IRQ flag “1” doesn’t mean the system will execute the interrupt vector. In addition, which
means the IRQ flags can be set “1” by the events without enable the interrupt. Once the event occurs, the IRQ will be
logic “1”. The IRQ and its trigger event relationship is as the below table.
Interrupt Name Trigger Event Description
P00IRQ P0.0 trigger controlled by PEDGE
T0IRQ T0C overflow
TC0IRQ TC0C overflow
USBIRQ USB process finished
T1IRQ T1C stop counting.
T2IRQ T2C stop counting.
For multi-interrupt conditions, two things need to be taking care of. One is to set the priority for these interrupt requests.
Two is using IEN and IRQ flags to decide which interrupt to be executed. Users have to check interrupt control bit and
interrupt request flag in interrupt routine.
¾ Example: Check the interrupt request under multi-interrupt operation
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
INTP00CHK: ; Check INT0 interrupt request
B0BTS1 FP00IEN ; Check P00IEN
JMP INTT0CHK ; Jump check to next interrupt
B0BTS0 FP00IRQ ; Check P00IRQ
JMP INTP00
INTT0CHK: ; Check T0 interrupt request
B0BTS1 FT0IEN ; Check T0IEN
JMP INTTC0CHK ; Jump check to next interrupt
B0BTS0 FT0IRQ ; Check T0IRQ
JMP INTT0 ; Jump to T0 interrupt service routine
INTTC0CHK: ; Check TC0 interrupt request
B0BTS1 FTC0IEN ; Check TC0IEN
JMP INTTC1CHK ; Jump check to next interrupt
B0BTS0 FTC0IRQ ; Check TC0IRQ
JMP INTTC0 ; Jump to TC0 interrupt service routine
INTUSBCHK: ; Check USB interrupt request
B0BTS1 FUSBIEN ; Check USBIEN
JMP INTT1CHK ; Jump check to next interrupt
B0BTS0 FUSBIRQ ; Check USBIRQ
JMP INTUSB ; Jump to USB interrupt service routine
INTT1CHK: ; Check T1 interrupt request
B0BTS1 FT1IEN ; Check T1IEN
JMP INTT2CHK ; Jump check to next interrupt
B0BTS0 FT1IRQ ; Check T1IRQ
JMP INTT1 ; Jump to T1 interrupt service routine
INTT2CHK: ; Check T2 interrupt request
B0BTS1 FADCIEN ; Check T2IEN
JMP INT_EXIT ; Jump to exit of IRQ
B0BTS0 FT2IRQ ; Check T2IRQ
JMP INTT2 ; Jump to T2 interrupt service routine
INT_EXIT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector
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7 I/O PORT
7.1 I/O PORT MODE
The port direction is programmed by PnM register. All I/O ports can select input or output direction.
0B8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P0M
Read/Write - R/W R/W R/W R/W R/W R/W R/W
After reset - 0 0 0 0 0 0 0
0C1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1M
Read/Write R/W R/W R/W - R/W R/W R/W R/W
After reset 0 0 0 - 0 0 0 0
0C5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P5M
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit[7:0] PnM[7:0]: Pn mode control bits. (n = 0~5).
0 = Pn is input mode.
1 = Pn is output mode.
Note:
1. Users can program them by bit control instructions (B0BSET, B0BCLR).
2. P1.4 is input only pin, so there is no P1.4 mode control bit.
¾ Example: I/O mode selecting
CLR P0M ; Set all ports to be input mode.
CLR P1M
CLR P5M
MOV A, #0FFH ; Set all ports to be output mode.
B0MOV P0M, A
B0MOV P1M, A
B0MOV P5M, A
B0BCLR P1M.2 ; Set P1.2 to be input mode.
B0BSET P1M.2 ; Set P1.2 to be output mode.
- P06M P05M P04M P03M P02M P01M P00M
P17M P16M P15M - P13M P12M P12M P10M
P57M P56M P55M P54M P53M P52M P51M P50M
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7.2 I/O PULL UP REGISTER
0E0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P0UR
Read/Write - - - - - W W W
After reset - 1 1 1 1 0 0 0
0E1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1UR
Read/Write W W W - W W W W
After reset 0 0 0 - 0 0 0 0
0E5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P5UR
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
Note: P1.4 is an input only pin without pull-up resister, so there is no P1.4 pull-up resistor control bit.
Note: When set P1.4 to input mode, please add the series external 100 ohm on it.
Note: P03~P06 are input I/O with pull up resistor, so there has no P03R~P06R pull up resistor control bit.
¾ Example: I/O Pull up Register
MOV A, #0FFH ; Enable Port0, 1, 5 Pull-up register,
B0MOV P0UR, A ;
B0MOV P1UR, A
B0MOV P5UR, A
- - - - - P02R P01R P00R
P17R P16R P15R - P13R P12R P11R P10R
P57R P56R P55R P54R P53R P52R P51R P50R
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7.3 I/O OPEN-DRAIN REGISTER
P1.0/P1.1 is built-in open-drain function. P1.0/P1.1 must be set as output mode when enable P1.0/P1.1 open-drain
function. Open-drain external circuit is as following.
MCU1
MCU2
U
VCC
Pull-up Resistor
Open-drain pin Open-drain pin
U
The pull-up resistor is necessary. Open-drain output high is driven by pull-up resistor. Output low is sunken by MCU’s
pin.
Note: P1.0/P1.1 open-drain function can be 2nd PS/2 interface on chip. More detail information refer to
PS/2 chapter.
0E9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1OC
Read/Write - - - - - - W W
After reset - - - - - - 0 0
Bit [1:0] P1nOC: Port 1 open-drain control bit
0 = Disable open-drain mode
1 = Enable open-drain mode
¾ Example: Enable P1.0 to open-drain mode and output high.
B0BSET P1.0 ; Set P1.0 buffer high.
B0BSET P10M ; Enable P1.0 output mode.
MOV A, #01H ; Enable P1.0 open-drain function.
B0MOV P1OC, A
Note: P1OC is write only register. Setting P10OC must be used “MOV” instructions.
¾ Example: Disable P1.0 to open-drain mode and output low.
MOV A, #0 ; Disable P1.0 open-drain function.
B0MOV P1OC, A
Note: After disable P1.0 open-drain function, P1.0 mode returns to last I/O mode.
- - - - - - P11OC P10OC
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7.4 I/O PORT DATA REGISTER
0D0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P0
Read/Write - R/W R/W R/W R/W R/W R/W R/W
After reset - 0 0 0 0 0 0 0
0D1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1
Read/Write R R/W R/W R R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
0D5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P5
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Note: The P14 keeps “1” when external reset enable by code option.
¾ Example: Read data from input port.
B0MOV A, P0 ; Read data from Port 0
B0MOV A, P1 ; Read data from Port 1
B0MOV A, P5 ; Read data from Port 5
¾ Example: Write data to output port.
MOV A, #0FFH ; Write data FFH to all Port.
B0MOV P0, A
B0MOV P1, A
B0MOV P5, A
¾ Example: Write one bit data to output port.
B0BSET P1.3 ; Set P1.3 and P5.5 to be “1”.
B0BSET P5.5
B0BCLR P1.3 ; Set P1.3 and P5.5 to be “0”.
B0BCLR P5.5
- P06 P05 P04 P03 P02 P01 P00
P17 P16 P15 P14 P13 P12 P11 P10
P57 P56 P55 P54 P53 P52 P51 P50
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8 TIMERS
8.1 WATCHDOG TIMER
The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into
the unknown status by noise interference, WDT overflow signal raises and resets MCU. Watchdog clock controlled by
code option and the clock source is internal low-speed oscillator (16KHz @3V, 32KHz @5V).
Watchdog overflow time = 8192 / Internal Low-Speed oscillator (sec).
VDD Internal Low RC Freq. Watchdog Overflow Time
3V 16KHz 512ms
5V 32KHz 256ms
Note: If watchdog is “Always_On” mode, it keeps running event under power down mode or green
mode.
Watchdog clear is controlled by WDTR register. Moving 0x5A data into WDTR is to reset watchdog timer.
0CCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WDTR
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
¾ Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
…
CALL SUB1
CALL SUB2
…
…
…
JMP MAIN
WDTR7 WDTR6 WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 WDTR0
MOV A,#5AH ; Clear the watchdog timer.
B0MOV WDTR,A
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Watchdog timer application note is as following.
z Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.
z Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.
z Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the
watchdog timer function.
¾ Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top
of the main routine of the program.
Main:
… ; Check I/O.
… ; Check RAM
Err: JMP $ ; I/O or RAM error. Program jump here and don’t
; clear watchdog. Wait watchdog timer overflow to reset IC.
Correct: ; I/O and RAM are correct. Clear watchdog timer and
; execute program.
B0BSET FWDRST ; Only one clearing watchdog timer of whole program.
…
CALL SUB1
CALL SUB2
…
…
…
JMP MAIN
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8.2 TIMER 0 (T0)
8.2.1 OVERVIEW
The T0 is an 8-bit binary up timer and event counter. If T0 timer occurs an overflow (from FFH to 00H), it will continue
counting and issue a time-out signal to trigger T0 interrupt to request interrupt service.
The main purposes of the T0 timer is as following.
) 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
) RTC timer: Generates interrupts at real time intervals based on the selected clock source. RTC function is only
available in High_Clk code option = "IHRC_RTC".
) Green mode wakeup function: T0 can be green mode wake-up time as T0ENB = 1. System will be wake-up by
T0 time out.
T0 Rate
(Fcpu/2~Fcpu/256)
T0ENB
Internal Data Bus
Load
Fcpu
CPUM0,1
RTC
T0ENB
Note: In RTC mode, the T0 interval time is fixed at 0.5 sec and T0C is 256 counts.
T0C 8-Bit Binary Up Counting Counter
T0TB
T0 Time Out
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8.2.2 T0M MODE REGISTER
0D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T0M
Read/Write R/W R/W R/W R/W - - - R/W
After reset 0 0 0 0 - - - 0
Bit 0 T0TB: RTC clock source control bit.
Bit [6:4] T0RATE[2:0]: T0 internal clock select bits.
Bit 7 T0ENB: T0 counter control bit.
Note: T0RATE is not available in RTC mode. The T0 interval time is fixed at 0.5 sec.
T0ENB T0rate2 T0rate1 T0rate0 - - - T0TB
0 = Disable RTC (T0 clock source from Fcpu).
1 = Enable RTC.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
0 = Disable T0 timer.
1 = Enable T0 timer.
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8.2.3 T0C COUNTING REGISTER
T0C is an 8-bit counter register for T0 interval time control.
0D9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T0C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
The equation of T0C initial value is as following.
¾ Example: To set 1ms interval time for T0 interrupt. High clock is internal 6MHz. Fcpu=Fosc/1. Select
T0RATE=010 (Fcpu/64).
The basic timer table interval time of T0.
T0RATE T0CLOCK
000 Fcpu/256 10.923 ms 42.67 us
001 Fcpu/128 5.461 ms 21.33 us
010 Fcpu/64 2.731 ms 10.67 us
011 Fcpu/32 1.365 ms 5.33 us
100 Fcpu/16 0.683 ms 2.67 us
101 Fcpu/8 0.341 ms 1.33 us
110 Fcpu/4 0.171 ms 0.67 us
111 Fcpu/2 0.085 ms 0.33 us
Note: In RTC mode, T0C is 256 counts and generatesT0 0.5 sec interval time. Don’t change T0C value in
RTC mode.
T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0
T0C initial value = 256 - (T0 interrupt interval time * input clock)
T0C initial value = 256 - (T0 interrupt interval time * input clock)
= 256 - (1ms * 6MHz / 1 / 64)
= 256 - (10
= 162
= A2H
High speed mode (Fcpu = 6MHz / 1)
Max overflow interval One step = max/256
-3
* 6 * 106 / 1 / 64)
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8.2.4 T0 TIMER OPERATION SEQUENCE
T0 timer operation sequence of setup T0 timer is as following.
) Stop T0 timer counting, disable T0 interrupt function and clear T0 interrupt request flag.
B0BCLR FT0ENB ; T0 timer.
B0BCLR FT0IEN ; T0 interrupt function is disabled.
B0BCLR FT0IRQ ; T0 interrupt request flag is cleared.
) Set T0 timer rate.
MOV A, #0xxx0000b ;The T0 rate control bits exist in bit4~bit6 of T0M. The
; value is from x000xxxxb~x111xxxxb.
B0MOV T0M,A ; T0 timer is disabled.
) Set T0 clock source from Fcpu or RTC.
B0BCLR FT0TB ; Select T0 Fcpu clock source.
or
B0BSET FT0TB ; Select T0 RTC clock source.
) Set T0 interrupt interval time.
) Set T0 timer function mode.
) Enable T0 timer.
MOV A,#7FH
B0MOV T0C,A ; Set T0C value.
B0BSET FT0IEN ; Enable T0 interrupt function.
B0BSET FT0ENB ; Enable T0 timer.
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8.3 TIMER/COUNTER 0 (TC0)
8.3.1 OVERVIEW
The TC0 is an 8-bit binary up counting timer with double buffers. TC0 has two clock sources including internal clock
and external clock for counting a precision time. The internal clock source is from Fcpu. The external clock is INT0 from
P0.0 pin (Falling edge trigger). Using TC0M register selects TC0C’s clock source from internal or external. If TC0 timer
occurs an overflow, it will continue counting and issue a time-out signal to trigger TC0 interrupt to request interrupt
service. TC0 overflow time is 0xFF to 0X00 normally. Under PWM mode, TC0 overflow is decided by PWM cycle
controlled by ALOAD0 and TC0OUT bits.
The main purposes of the TC0 timer is as following.
) 8-bit programmable up counting timer: Generates interrupts at specific time intervals based on the selected
clock frequency.
) External event counter: Counts system “events” based on falling edge detection of external clock signals at the
INT0 input pin.
) Buzzer output
) PWM output
TC0OUT
Internal P5.4 I/O Circuit
ALOAD0
Auto. Reload
Buzzer
TC0 / 2
P5.4
TC0 Time Out
Up Counting
Reload Value
INT0
(Schmitter Trigger)
TC0 Rate
(Fcpu/2~Fcpu/256)
Fcpu
TC0CKS TC0ENB
CPUM0,1
TC0R Reload
Data Buffer
Load
TC0C
8-Bit Binary Up
Counting Counter
Compare
ALOAD0, TC0OUT
R
PWM
S
PWM0OUT
TC0 Time Out
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8.3.2 TC0M MODE REGISTER
0DAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC0M
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit 0 PWM0OUT: PWM output control bit.
Bit 1 TC0OUT: TC0 time out toggle signal output control bit. Only valid when PWM0OUT = 0.
0 = Disable, P5.4 is I/O function.
1 = Enable, P5.4 is output TC0OUT signal.
Bit 2 ALOAD0: Auto-reload control bit. Only valid when PWM0OUT = 0.
Bit 3 TC0CKS: TC0 clock source select bit.
Bit [6:4] TC0RATE[2:0]: TC0 internal clock select bits.
Bit 7 TC0ENB: TC0 counter control bit.
Note: When TC0CKS=1, TC0 became an external event counter and TC0RATE is useless. No more P0.0
interrupt request will be raised. (P0.0IRQ will be always 0).
TC0ENB TC0rate2 TC0rate1 TC0rate0 TC0CKS ALOAD0 TC0OUT PWM0OUT
0 = Disable PWM output.
1 = Enable PWM output. PWM duty controlled by TC0OUT, ALOAD0 bits.
0 = Disable TC0 auto-reload function.
1 = Enable TC0 auto-reload function.
0 = Internal clock (Fcpu or Fosc).
1 = External clock from P0.0/INT0 pin.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
0 = Disable TC0 timer.
1 = Enable TC0 timer.
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8.3.3 TC0C COUNTING REGISTER
TC0C is an 8-bit counter register for TC0 interval time control.
0DBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC0C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
The equation of TC0C initial value is as following.
N is TC0 overflow boundary number. TC0 timer overflow time has six types (TC0 timer, TC0 event counter, TC0 Fcpu
clock source, TC0 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC0 overflow time
and valid value as follow table.
TC0CKS PWM0 ALOAD0 TC0OUT
¾ Example: To set 1ms interval time for TC0 interrupt. TC0 clock source is Fcpu (TC0KS=0) and no PWM
output (PWM0=0). High clock is internal 6MHz. Fcpu=Fosc/1. Select TC0RATE=010 (Fcpu/64).
The basic timer table interval time of TC0.
TC0RATE TC0CLOCK
000 Fcpu/256 10.923 ms 42.67 us
001 Fcpu/128 5.461 ms 21.33 us
010 Fcpu/64 2.731 ms 10.67 us
011 Fcpu/32 1.365 ms 5.33 us
100 Fcpu/16 0.683 ms 2.67 us
101 Fcpu/8 0.341 ms 1.33 us
110 Fcpu/4 0.171 ms 0.67 us
111 Fcpu/2 0.085 ms 0.33 us
TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0
TC0C initial value = N - (TC0 interrupt interval time * input clock)
N
0 x x 256 0x00~0xFF 00000000b~11111111b Overflow per 256 count
1 0 0 256 0x00~0xFF 00000000b~11111111b Overflow per 256 count
0
1 - - - 256 0x00~0xFF 00000000b~11111111b Overflow per 256 count
1 0 1 64 0x00~0x3F xx000000b~xx111111b Overflow per 64 count
1 1 0 32 0x00~0x1F xxx00000b~xxx11111b Overflow per 32 count
1 1 1 16 0x00~0x0F xxxx0000b~xxxx1111b Overflow per 16 count
TC0C valid
value
TC0C value
binary type
Remark
TC0C initial value = N - (TC0 interrupt interval time * input clock)
= 256 - (1ms * 6MHz / 1 / 64)
-3
= 256 - (10
* 6 * 106 / 1 / 64)
= 162
= A2H
High speed mode (Fcpu = 6MHz / 1)
Max overflow interval One step = max/256
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8.3.4 TC0R AUTO-LOAD REGISTER
TC0 timer is with auto-load function controlled by ALOAD0 bit of TC0M. When TC0C overflow occurring, TC0R value
will load to TC0C by system. It is easy to generate an accurate time, and users don’t reset TC0C during interrupt
service routine.
TC0 is double buffer design. If new TC0R value is set by program, the new value is stored in 1
overflow occurs, the new value moves to real TC0R buffer. This way can avoid TC0 interval time error and glitch in
PWM and Buzzer output.
Note: Under PWM mode, auto-load is enabled automatically. The ALOAD0 bit is selecting overflow
boundary.
0CDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TC0R
TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0
Read/Write W W W W W W W W
After reset 0 0 0 0 0 0 0 0
The equation of TC0R initial value is as following.
TC0R initial value = N - (TC0 interrupt interval time * input clock)
N is TC0 overflow boundary number. TC0 timer overflow time has six types (TC0 timer, TC0 event counter, TC0 Fcpu
clock source, TC0 Fosc clock source, PWM mode and no PWM mode). These parameters decide TC0 overflow time
and valid value as follow table.
TC0CKS PWM0 ALOAD0 TC0OUT
0 x x 256 0x00~0xFF 00000000b~11111111b
1 0 0 256 0x00~0xFF 00000000b~11111111b
0
1 - - - 256 0x00~0xFF 00000000b~11111111b
1 0 1 64 0x00~0x3F xx000000b~xx111111b
1 1 0 32 0x00~0x1F xxx00000b~xxx11111b
1 1 1 16 0x00~0x0F xxxx0000b~xxxx1111b
N
TC0R valid
value
TC0R value
binary type
¾ Example: To set 1ms interval time for TC0 interrupt. TC0 clock source is Fcpu (TC0KS=0) and no PWM
output (PWM0=0). High clock is internal 6MHz. Fcpu=Fosc/1. Select TC0RATE=010 (Fcpu/64).
TC0R initial value = N - (TC0 interrupt interval time * input clock)
= 256 - (1ms * 6MHz / 1 / 64)
-3
= 256 - (10
* 6 * 106 / 1 / 64)
= 162
= A2H
st
buffer. Until TC0
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8.3.5 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)
Buzzer output (TC0OUT) is from TC0 timer/counter frequency output function. By setting the TC0 clock frequency, the
clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0OUT frequency is
divided by 2 from TC0 interval time. TC0OUT frequency is 1/2 TC0 frequency. The TC0 clock has many combinations
and easily to make difference frequency. The TC0OUT frequency waveform is as following.
1 2 3 4
TC0 Overflow Clock
1 2 3 4
TC0OUT (Buzzer) Output Clock
¾ Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The
TC0OUT frequency is 0.5KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 1KHz. The
TC0 clock source is from external oscillator clock. T0C rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110.
TC0C = TC0R = 131.
MOV A,#01100000B
B0MOV TC0M,A ; Set the TC0 rate to Fcpu/4
MOV A,#131 ; Set the auto-reload reference value
B0MOV TC0C,A
B0MOV TC0R,A
B0BSET FTC0OUT ; Enable TC0 output to P5.4 and disable P5.4 I/O function
B0BSET FALOAD1 ; Enable TC0 auto-reload function
B0BSET FTC0ENB ; Enable TC0 timer
Note: Buzzer output is enable, and “PWM0OUT” must be “0”.
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8.3.6 TC0 TIMER OPERATION SEQUENCE
TC0 timer operation includes timer interrupt, event counter, TC0OUT and PWM. The sequence of setup TC0 timer is
as following.
) Stop TC0 timer counting, disable TC0 interrupt function and clear TC0 interrupt request flag.
B0BCLR FTC0ENB ; TC0 timer, TC0OUT and PWM stop.
B0BCLR FTC0IEN ; TC0 interrupt function is disabled.
B0BCLR FTC0IRQ ; TC0 interrupt request flag is cleared.
) Set TC0 timer rate. (Besides event counter mode.)
MOV A, #0xxx0000b ;The TC0 rate control bits exist in bit4~bit6 of TC0M. The
; value is from x000xxxxb~x111xxxxb.
B0MOV TC0M,A ; TC0 interrupt function is disabled.
) Set TC0 timer clock source.
; Select TC0 internal / external clock source.
B0BCLR FTC0CKS ; Select TC0 internal clock source.
or
B0BSET FTC0CKS ; Select TC0 external clock source.
) Set TC0 timer auto-load mode.
B0BCLR FALOAD0 ; Enable TC0 auto reload function.
or
B0BSET FALOAD0 ; Disable TC0 auto reload function.
) Set TC0 interrupt interval time, TC0OUT (Buzzer) frequency or PWM duty cycle.
; Set TC0 interrupt interval time, TC0OUT (Buzzer) frequency or PWM duty.
; In PWM mode, set PWM cycle.
or
or
or
) Set TC0 timer function mode.
or
or
) Enable TC0 timer.
MOV A,#7FH ; TC0C and TC0R value is decided by TC0 mode.
B0MOV TC0C,A ; Set TC0C value.
B0MOV TC0R,A ; Set TC0R value under auto reload mode or PWM mode.
B0BCLR FALOAD0 ; ALOAD0, TC0OUT = 00, PWM cycle boundary is
B0BCLR FTC0OUT ; 0~255.
B0BCLR FALOAD0 ; ALOAD0, TC0OUT = 01, PWM cycle boundary is
B0BSET FTC0OUT ; 0~63.
B0BSET FALOAD0 ; ALOAD0, TC0OUT = 10, PWM cycle boundary is
B0BCLR FTC0OUT ; 0~31.
B0BSET FALOAD0 ; ALOAD0, TC0OUT = 11, PWM cycle boundary is
B0BSET FTC0OUT ; 0~15.
B0BSET FTC0IEN ; Enable TC0 interrupt function.
B0BSET FTC0OUT ; Enable TC0OUT (Buzzer) function.
B0BSET FPWM0OUT ; Enable PWM function.
B0BSET FTC0ENB ; Enable TC0 timer.
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8.4 PWM0 MODE
8.4.1 OVERVIEW
PWM function is generated by TC0 timer counter and output the PWM signal to PWM0OUT pin (P5.4). The 8-bit
counter counts modulus 256, 64, 32, 16 controlled by ALOAD0, TC0OUT bits. The value of the 8-bit counter (TC0C) is
compared to the contents of the reference register (TC0R). When the reference register value (TC0R) is equal to the
counter value (TC0C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The
low-to-high ratio (duty) of the PWM0 output is TC0R/256, 64, 32, 16.
PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to
change the PWM’s duty cycle is to modify the TC0R.
Note: TC0 is double buffer design. Modifying TC0R to change PWM duty by program, there is no glitch
and error duty signal in PWM output waveform. Users can change TC0R any time, and the new reload
value is loaded to TC0R buffer at TC0 overflow.
MAX. PWM
ALOAD0 TC0OUT PWM duty range TC0C valid value TC0R valid bits value
0 0 0/256~255/256 0x00~0xFF 0x00~0xFF 11.719K Overflow per 256 count
0 1 0/64~63/64 0x00~0x3F 0x00~0x3F 46.875K Overflow per 64 count
1 0 0/32~31/32 0x00~0x1F 0x00~0x1F 93.75K Overflow per 32 count
1 1 0/16~15/16 0x00~0x0F 0x00~0x0F 187.5K Overflow per 16 count
Frequency
(Fcpu = 6MHz)
The Output duty of PWM is with different TC0R. Duty range is from 0/256~255/256.
0 1 128 254 255
…… ……
0 1 128 254 255
…… ……
Remark
TC0 Clock
TC0R=00H
TC0R=01H
TC0R=80H
TC0R=FFH
High
High
High
Low
Low
Low
Low
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8.4.2 TCxIRQ and PWM Duty
In PWM mode, the frequency of TC0IRQ is depended on PWM duty range. From following diagram, the TC0IRQ
frequency is related with PWM duty.
TC0 Overflow,
TC0IRQ = 1
0xFF
TC0C Value
0x00
PWM0 Output
(Duty Range 0~255)
TC0 Overflow,
TC0IRQ = 1
0xFF
TC0C Value
0x00
PWM0 Output
(Duty Range 0~63)
0xFF
TC0C Value
0x00
PWM0 Output
(Duty Range 0~31)
0xFF
TC0C Value
TC0 Overflow,
TC0IRQ = 1
TC0 Overflow,
TC0IRQ = 1
0x00
PWM0 Output
(Duty Range 0~15)
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8.4.3 PWM Duty with TCxR Changing
In PWM mode, the system will compare TC0C and TC0R all the time. When TC0C<TC0R, the PWM will output logic
“High”, when TC0C≧TC0R, the PWM will output logic “Low”. If TC0C is changed in certain period, the PWM duty will
change in next PWM period. If TC0R is fixed all the time, the PWM waveform is also the same.
TC0C = TC0R
TC0C overflow
and TC0IRQ set
0xFF
TC0C Value
0x00
PWM0 Output
Period
1 2 3 4 5 6 7
Above diagram is shown the waveform with fixed TC0R. In every TC0C overflow PWM output “High, when TC0C≧
TC0R PWM output ”Low”. If TC0R is changing in the program processing, the PWM waveform will became as following
diagram.
TC0C < TC0R
PWM Low > High
TC0C > = TC0R
PWM High > Low
TC0C overflow
and TC0IRQ set
TC0C Value
0xFF
0x00
Update New TC0R!
Old TC0R < TC0C < New TC0R
Old TC0R Old TC0RNew TC0R New TC0R
Update New TC0R!
New TC0R < TC0C < Old TC0R
PWM0 Output
Period
1
1st PWM
2
Update PWM Duty
3
2nd PWM
4
Update PWM Duty
5
3th PWM
In period 2 and period 4, new Duty (TC0R) is set. TC0 is double buffer design. The PWM still keeps the same duty in
period 2 and period 4, and the new duty is changed in next period. By the way, system can avoid the PWM not
changing or H/L changing twice in the same cycle and will prevent the unexpected or error operation.
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8.4.4 PWM PROGRAM EXAMPLE
¾ Example: Setup PWM0 output from TC0 to PWM0OUT (P5.4). The clock source is internal 6MHz. Fcpu =
Fosc/1. The duty of PWM is 30/256. The PWM frequency is about 6KHz. The PWM clock source is from
external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C = TC0R = 30.
MOV A,#01100000B
B0MOV TC0M,A ; Set the TC0 rate to Fcpu/4
MOV A,#30 ; Set the PWM duty to 30/256
B0MOV TC0C,A
B0MOV TC0R,A
B0BCLR FTC0OUT ; Set duty range as 0/256~255/256.
B0BCLR FALOAD0
B0BSET FPWM0OUT ; Enable PWM0 output to P5.4 and disable P5.4 I/O function
B0BSET FTC0ENB ; Enable TC0 timer
Note: The TC0R is write-only register. Don’t process them using INCMS, DECMS instructions.
¾ Example: Modify TC0R registers’ value.
MOV A, #30H ; Input a number using B0MOV instruction.
B0MOV TC0R, A
INCMS BUF0 ; Get the new TC0R value from the BUF0 buffer defined by
NOP ; programming.
B0MOV A, BUF0
B0MOV TC0R, A
Note: The PWM can work with interrupt request.
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8.5 T1, T2 8-BIT TIMER CAPTURE
8.5.1 OVERVIEW
The T1, T2 are 8-bit binary up timer captures for external pulse width, period measurement. Timer capture’s trigger
edge is controlled by TnG1, 0 and supports four types (falling edge, rising edge, positive pulse with, negative pulse
width). If 2
value is input signal’s positive/negative pulse width or period.
T1 input signal is from P0.1 and T2 is from P0.2. P0.1 and P0.2 must be set as input mode for timer capture input
function. P0.1 and P0.2 in timer capture input mode has wake-up function from power down mode and green mode.
Note: T2 operation is equal to T1 operation. Use “Tn” to mean “T1” and “T2” in follow sections.
The main purposes of the Tn 8-bit timer capture.
) Input signal period (frequency inverse)measurement: When select Tn trigger edge to falling (TnG1,0 = 00) or
) Input signal plus width measurement: When select Tn trigger edge as positive pulse width (TnG1,0 = 10) or
nd
edge trigger occurrence, the interrupt request flag is set and timer counter stops counting. The counter
rising (TnG1,0 = 01) edge, Tn timer capture can measure input signal’s period. The period is frequency inverse.
negative pulse width (TnG1,0 = 11), Tn timer capture can measure input signal’s positive and negative pulse
width.
TnIRQ=0, TnC Starts to Count.
Tn Rate
(Fcpu/2~Fcpu/256)
TnIRQ=1, TnC Stops Counting.
TnENB
TnIRQ Cleared by
Firmware
External Input Signal
Trigger Edge Selection
Fcpu
00
01
10
11
CPUM0,1
TnG1,0
TnC Counts
Trigger
TnC
8-Bit Binary Up
Counting Counter
TnIRQ = 1
TnC Stops
Trigger
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8.5.2 TnM MODE REGISTER
0ABH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T1M
Read/Write R/W R/W R/W R/W - - R/W R/W
After reset 0 0 0 0 - - 0 0
0ADH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T2M
Read/Write R/W R/W R/W R/W - - R/W R/W
After reset 0 0 0 0 - - 0 0
Bit 7 TnENB: Tn counter control bit.
Bit [6:4] TnRATE[2:0]: Tn timer internal clock select bits.
Bit [1:0] TnG1,0: Tn timer capture trigger selection.
T1ENB T1RATE2 T1RATE1 T1RATE0 - - T1G1 T1G0
T2ENB T2RATE2 T2RATE1 T2RATE0 - - T2G1 T2G0
0 = Disable Tn timer capture.
1 = Enable Tn timer capture.
000 = fcpu/256.
001 = fcpu/128.
…
110 = fcpu/4.
111 = fcpu/2.
00 = Falling edge trigger for period measurement.
01 = Rising edge trigger for period measurement.
10 = Rising edge start and falling stop for positive pulse width measurement.
11 = Falling edge start and rising stop for negative pulse width measurement.
8.5.3 Tn COUNTING REGISTER
Tn counting register is an 8-bit register and increase one by one when Tn timer active.
0ACH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T1C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
0AEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
T2C
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
T1C7 T1C6 T1C5 T1C4 T1C3 T1C2 T1C1 T1C0
T2C7 T2C6 T2C5 T2C4 T2C3 T2C2 T2C1 T2C0
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8.5.4 Tn TIMER CAPTURE OPERATION
Tn timer capture is using input edge trigger Tn timer count and stop. Time base is controlled by TnRATE2~0 bits. After
TnENB is set (TnENB=1), first edge input from external signal starts Tn counter. Second edge stops Tn counter and
set TnIRQ as “1”. TnC value is the result of pulse width or period. The next edge input can’t restart Tn timer when
TnIRQ = 1. TnIRQ must be cleared by firmware and Tn timer actives to catch next signal. TnRATE decides timer
capture clock rate from system clock (Fcpu). The one count period is the unit time of TnC. The product of multiplication
from TnC value multiplied by Tn unit time is result of input signal’s pulse width or period. Tn timer capture operating
sequence is as following.
Set TnIEN
Set Tn Trigger Edge
(TnG1,0)
Tn Mode and
Function Setting.
Set TnRATE
Clear TnC and
TnIRQ
Set TnENB
Start Edge input Stop Edge input
TnC Count
Clear TnC and
TnIRQ
TnC Application
Program.
TnIRQ=1.
TnC Stop.
Before using Tn timer capture, have to know input signal information (eg. pulse width or period range) to decide Tn
time base. The time base value selection has to avoid TnC overflow (0x00>0xFF>0x00) and make sure TnC result in
8-bit range. If TnC is overflow, TnIRQ wouldn’t be set and Tn keeps counting. When stop edge trigger occurrence,
TnIRQ is set. TnC overflow occurs one time, the result is over 8-bit range, so the TnC is not correct value. Time base
selection is very important. Please refer to the table as following.
High speed mode (Fcpu = 6MHz / 1)
TnRATE TnCLOCK
000 Fcpu/256 10.923 ms 42.67 us 42.67us~10.923 ms 23.44KHz~91.55Hz
001 Fcpu/128 5.461 ms 21.33 us 21.33us~5.461 ms 46.88KHz~183.12Hz
010 Fcpu/64 2.731 ms 10.67 us 10.67us~2.731 ms 93.72KHz~366.67Hz
011 Fcpu/32 1.365 ms 5.33 us 5.33us~1.365 ms 187.62KHz~732.6Hz
100 Fcpu/16 0.683 ms 2.67 us 2.67us~0.683 ms 374.53KHz~1.46KHz
101 Fcpu/8 0.341 ms 1.33 us 1.33us~0.341 ms 751.88KHz~2.94KHz
110 Fcpu/4 0.171 ms 0.67 us 0.67us~0.171 ms 1.49MHz~5.85KHz
111 Fcpu/2 0.085 ms 0.33 us 0.33us~0.085 ms 3.03MHz~11.76KHz
Tn max interval
TnC = FFh
Tn unit time = max/256
TnC=01h
Pulse width and period
measure range.
Frequency measure
range.
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8.5.5 Tn INPUT PERIOD MEASUREMENT
Tn edge trigger as falling edge and rising edge is period measurement function. Input period measurement is equal to
input frequency measure. The period is the frequency inverse. Falling to falling of signal includes one high pulse and
one low pulse. The combination of high and low pulses is a full cycle signal. Rising to rising edge is the same. Set Tn
time base and select Tn edge as falling edge or rising edge, the Tn function is to measure input signal’s period
(frequency).
z Falling edge trigger period measurement waveform.
Falling edge trigger.
Tn start to count.
TnIRQ=0
Tn Input Signal
Falling edge trigger.
Tn stop counting.
TnIRQ=1.
Tn Timer Counter
z Rising edge trigger period measurement waveform.
Rising edge trigger.
Tn start to count.
TnIRQ=0
Tn Input Signal
Tn Timer Counter
Rising edge trigger.
Tn stop counting.
TnIRQ=1.
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¾ Example: Using T1 to measure P0.1/T1IN input 10KHz frequency. T1RATE is Fcpu/8. Fhosc=6MHz,
Fcpu=Fhosc/1=6MHz. T1 edge trigger is falling edge.
; Set T1 mode.
CLR T1C ; Clear T1 counter buffers.
B0BCLR FT1IRQ ; Clear T1IRQ.
MOV A, #01010000h ; Set T1RATE = Fcpu/8.
B0MOV T1M, A ; Set T1 edge is falling edge.
B0BSET FT1ENB ; Enable T1 timer.
; Start to measure P0.1/T1IN input frequency.
Chk_T1IRQ:
B0BTS1 FT1IRQ ; Check T1IRQ set status..
JMP Chk_T1IRQ
B0MOV A, T1C ; T1C=75
B0MOV T1CBUF, A ; Save T1C.
… ; Application program.
CLR T1C ; Clear T1C.
B0BCLR FT1IRQ ; Clear T1IRQ.
JMP Chk_T1IRQ ; Measure next signal.
The T1C = 75. Time base is 1.33us in T1RATE=101 (Fcpu/8) and Fcpu = 6MHz.
Input frequency = 1 / (1.33us * 75) = 10.025KHz ≈ 10KHz
Above example is using polling to check TnIRQ. Tn supports interrupt function. When TnIEN=1 and TnIRQ=1, program
counter (PC) points to interrupt vector (ORG 8) and process interrupt service routine.
ORG 8
JMP ISR ; Go to interrupt service routine.
ORG 10 ; User’s program.
… ; T1 setting.
B0BSET FT1IEN ; Enable T1 interrupt function.
… ; main program.
ISR:
PUSH ; Save ACC and PFLGA.
Chk_T1IRQ:
B0BTS1 FT1IRQ ; Check T1IRQ set status..
JMP Chk_T1IRQ
B0MOV A, T1C ; T1C=75
B0MOV T1CBUF, A ; Save T1C.
… ; Application program.
CLR T1C ; Clear T1C.
B0BCLR FT1IRQ ; Clear T1IRQ for next frequency measurement.
…
POP ; Reload ACC and PFLAG.
RETI ; Exit interrupt service routine.
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8.5.6 Tn INPUT PULSE WIDTH MEASUREMENT
Tn timer includes pulse width measurement. Select trigger edge direction to decide positive and negative pulse width
measurement. TnG1, 0 = 10 is positive pulse width measurement. Rising edge starts Tn timer and falling edge stop Tn
counting. TnG1, 0 = 11 is negative pulse width measurement. Falling edge starts Tn timer and rising edge stop Tn
counting. End of pulse width measurement, TnIRQ=1 and cleared by firmware for next pulse width measurement.
z Positive pulse width measurement waveform.
Rising edge trigger.
Tn start to count.
TnIRQ=0
Tn Input Signal
Falling edge trigger.
Tn stop counting.
TnIRQ=1.
Tn Timer Counter
z Negative pulse width measurement waveform.
Falling edge trigger.
Tn start to count.
TnIRQ=0
Tn Input Signal
Tn Timer Counter
Rising edge trigger.
Tn stop counting.
TnIRQ=1.
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¾ Example: Using T1 to measure P0.1/T1IN input 120us high pulse width. T1RATE is Fcpu/8. Fhosc=6MHz,
Fcpu=Fhosc/1=6MHz. T1 edge trigger is falling edge.
; Set T1 mode.
CLR T1C ; Clear T1 counter buffers.
B0BCLR FT1IRQ ; Clear T1IRQ.
MOV A, #01010010h ; Set T1RATE = Fcpu/8.
B0MOV T1M, A ; Set T1G1, T1G0 = 10 positive pulse measurement.
B0BSET FT1ENB ; Enable T1 timer.
; Start to measure P0.1/T1IN input frequency.
Chk_T1IRQ:
B0BTS1 FT1IRQ ; Check T1IRQ set status..
JMP Chk_T1IRQ
B0MOV A, T1C ; T1C=90
B0MOV T1CBUF, A ; Save T1C.
… ; Application program.
CLR T1C ; Clear T1C.
B0BCLR FT1IRQ ; Clear T1IRQ.
JMP Chk_T1IRQ ; Measure next signal.
The T1C = 90. Time base is 1.33us in T1RATE=101 (Fcpu/8) and Fcpu = 6MHz.
Positive pulse width = 1.33us * 90 = 119.7 us ≈ 120 us
Above example is using polling to check TnIRQ. Tn supports interrupt function. When TnIEN=1 and TnIRQ=1, program
counter (PC) points to interrupt vector (ORG 8) and process interrupt service routine.
ORG 8
JMP ISR ; Go to interrupt service routine.
ORG 10 ; User’s program.
… ; T1 setting.
B0BSET FT1IEN ; Enable T1 interrupt function.
… ; main program.
ISR:
PUSH ; Save ACC and PFLGA.
Chk_T1IRQ:
B0BTS1 FT1IRQ ; Check T1IRQ set status..
JMP Chk_T1IRQ
B0MOV A, T1C ; T1C=90
B0MOV T1CBUF, A ; Save T1C.
… ; Application program.
CLR T1C ; Clear T1C.
B0BCLR FT1IRQ ; Clear T1IRQ for next frequency measurement.
…
POP ; Reload ACC and PFLAG.
RETI ; Exit interrupt service routine.
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9 UNIVERSAL SERIAL BUS (USB)
9.1 OVERVIEW
The USB is the answer to connectivity for the PC architecture. A fast, bi-directional, isochronous, low-cost, dynamically
attachable serial interface is consistent with the requirements of the PC platform of today and tomorrow. The SONIX
USB microcontrollers are optimized for human-interface computer peripherals such as a mouse, joystick, and game
pad.
USB Specification Compliance
— Conforms to USB Low speed specifications, Version 1.1.
— Conforms to USB HID Specification, Version 1.11.
— Supports 1 low-speed USB device address.
— Supports 1 control endpoint and 3 interrupt endpoints.
— Integrated USB transceiver.
— 5V to 3.3V regulator for supply IC power and pull-up resistor on D- when the USB function enable.
9.2 USB MACHINE
The USB machine allows the microcontroller to communicate with the USB host. The hardware handles the following
USB bus activity independently of the microcontroller.
The USB machine will do:
‧ Translate the encoded received data and format the data to be transmitted on the bus.
‧ CRC checking and generation by hardware. If CRC is not correct, hardware will not send any response to USB host.
‧ Send and update the data toggle bit (Data1/0) automatically by hardware.
‧ Send appropriate ACK/NAK/STALL handshakes control by USB control registers.
‧ SETUP, IN, or OUT Token type identification. Set the appropriate bit once a valid token is received.
‧ Place valid received data in the appropriate endpoint FIFOs.
‧ Bit stuffing/unstuffing.
‧ Address checking. Ignore the transactions not addressed to the device.
‧ Endpoint checking. Check the endpoint’s request from USB host, and set the appropriate bit of registers.
‧ Send the ACK handshake to the OUT token response automatically by hardware.
Firmware is required to handle the rest of the following tasks:
‧ Coordinate enumeration by decoding USB device requests.
‧ Fill and empty the FIFOs.
‧ Suspend/Resume coordination.
‧ Remote wake up function.
‧ Determine the right interrupt request of USB communication.
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9.3 USB INTERRUPT
The USB function will accept the USB host command and generate the relative interrupts, and the program counter will
go to 0x08 vector. Firmware is required to check the USB status bit to realize what request comes from the USB host.
The USB function interrupt is generated when:
‧ The endpoint 0 is set to accept a SETUP token.
‧ The device receives an ACK handshake after a successful read transaction (IN) from the host.
‧ If the endpoint is in ACK OUT modes, an interrupt is generated when data is received.
‧ The USB host send USB suspend request to the device.
‧ USB bus reset event occurs.
‧ The USB endpoints interrupt after a USB transaction complete is on the bus.
‧ The USB resume when the USB bus is placed in the suspend state.
The following examples show how to avoid the error of reading or writing the endpoint FIFOs and to do the right USB
request routine according to the flag.
Example: Save the UDP0, UDP1, ACC and Status flag when interrupt request occurs. To avoid the error when
read or write data in the endpoints FIFOs.
ORG 0x8
PUSH ; Save ACC and status flag
mov a, UDP0 ; Save the UDP0 register value to UDP0_TEMP
mov UDP0_TEMP, a
mov a, UDP1 ; Save the UDP1 register value to UDP1_TEMP
mov UDP1_TEMP,
…
…
mov a, UDP0_TEMP
mov UDP0, a ; Load the UDP0_TEMP register value to UDP0
mov a, UDP1_TEMP
mov UDP1, a ; Load the UDP1_TEMP register value to UDP1
POP ; Load the ACC and status flag
RETI
Example: Defining USB Interrupt Request. The interrupt service routine is following ORG 8.
ORG 0x8
b0bts0 UStatus.6 ; check Device suspend
jmp USB_Suspend ; USB suspend occurs, jump to USB_Suspend routine
b0bts0 UStatus.5 ; check Bus Reset
jmp Bus_Reset ; Jump to Bus_Reset routine
b0bts1 UE0R.5 ; check EP0_In_Token
jmp EP0_In ; Jump to EP0 In Token routine.
b0bts0 UE0R.6 ; check EP0_Out_Token or Setup token
jmp EP0_Setup ; Jump to Setup routine.
b0bclr UE0R.5 ; Clear out token flag
RETI
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9.4 USB ENUMERATION
A typical USB enumeration sequence is shown below.
1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device
descriptor.
2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.
3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor
over the USB bus, via the on-chip FIFO.
4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a
new USB address to the device.
5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence
completes.
6. The host sends a request for the Device descriptor using the new USB address.
7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.
8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB
bus.
9. The host generates control reads from the device to request the Configuration and Report descriptors.
10. Once the device receives a Set Configuration request, its functions may now be used.
11. Firmware should take appropriate action for Endpoint 1~3 transactions, which may occur from this point.
9.5 USB REGISTERS
9.5.1 USB DEVICE ADDRESS REGISTER
The USB Device Address Register (UDA) contains a 7-bit USB device address and one bit to enable the USB function.
This register is cleared during a reset, setting the USB device address to zero and disable the USB function.
0A0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
UDA UDE UDA6 UDA5 UDA4 UDA3 UDA2 UDA1 UDA0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit [6:0] UDA [6:0]: These bits must be set by firmware during the USB enumeration process (i.e., SetAddress) to
the non-zero address assigned by the USB host.
Bit 7 UDE: Device Function Enable. This bit must be enabled by firmware to enable the USB device function.
After the bit is set, the D- will pull up automatically to indicate the low speed device to the USB host.
0 = Disable USB device function.
1 = Enable USB device function.
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9.5.2 USB ENDPOINT 0 ENABLE REGISTER
An endpoint 0 (EP0) is used to initialize and control the USB device. EP0 is bi-directional (Control pipe), as the device,
can both receive and transmit data, which provides to access the device configuration information and allows generic
USB status and control accesses.
0A1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
UE0R UE0E UE0S UE0DO UE0DI UE0C3 UE0C2 UE0C1 UE0C0
Read/Write R/W R R/W R/W R/W R/W R/W R/W
After reset 0 0 0 0 0 0 0 0
Bit [3:0] UE0C [3:0]: Indicate the number of data bytes in a transaction: For IN transactions, firmware loads the
count with the number of bytes to be transmitted to the host from the endpoint 0 FIFO.
Bit 4 UE0DI: Indicate endpoint 0 data ready to host (IN token).
0 = Data is ready in EP0 FIFO for USB host drawing out. Firmware set the bit zero to indicate that data is
ready. Hardware will send an ACK to complete the transaction and set the bit to 1 after the IN token
transaction.
1 = Data is not ready in EP0 FIFO for IN token. Hardware will send NAK handshakes response to any IN
token sent to this endpoint. In addition, set this bit and the bit 3 of UPID register will send the STALL
handshake response to any IN token sent to this endpoint.
Bit 5 UE0DO: Indicate endpoint 0 data ready from host (OUT token).
0 = Data doesn’t finish carrying.
1 = Data carries successfully, and data is ready in EP0 FIFO.
Bit 6 UE0S: The Bit indicates that the USB function receives the Setup packet or OUT packet.
0 = A valid OUT packet has been received.
1 = A valid SETUP packet has been received.
Bit 7 UE0E: USB endpoint 0 function enable bit.
0 = disable USB endpoint 0 function.
1 = enable USB endpoint 0 function.
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