SONiX SN8P1702, SN8P1704, SN8P1706, SN8P1708 User Manual

SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1700 Series

USER’S MANUAL

General Release Specification

SN8P1702 SN8P1704 SN8P1706 SN8P1707 SN8P1708

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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

AMENDMENT HISTORY

Version Date Description

VER 1.90 Sep. 2002 V1.90 first issue VER 1.93 Feb. 2003 1. Extend chip operating temperature from “0°C ~ +70°C” to “-20°C ~ +70°C”.

2. Change the description of ADD M,A instruction from “M  M+A” to “M  A+M”

3. Add ADC grade table.

4. Remove “Support hardware multiplier (MUL)” in SN8P1702 FEATURES section.

5. Change “Four internal interrupts” to “Three internal interrupts” in SN8P1704 FEATURES section.

6. Change “ACC can’t be access by “B0MOV” instruction” to “ACC can’t be access by

“B0MOV” instruction during the instant addressing mode”.

7. Correct the description of STKnH.

8. Change “special register is located at 08h~FFh” to “special register is located at

80h~FFh”.

9. Correct the bit definition of INTEN register.

10. Correct the description of “TC0 CLOCK FREQUENCY OUTPUT” section.

11. Correct the description of “TC1 CLOCK FREQUENCY OUTPUT” section.

12. SCKMD = 1 means SIO is in SLAVE mode. SCKMD = 0 means SIO is in MASTER

mode.

13. Remove “SIO clock and SPI clock are compatible”.

14. Modify ADB’s output data table.

15. Correct an error of template code: “b0bclr FWDRST”  “b0bset FWDRST”.

16. Add a notice about OSCM register access cycle.

17. SN8P1702/SN8A1702A don’t provide “MUL, PUSH, POP” instruction.

18. Add a notice about OSCM register access cycle.

VER 1.94 Sep. 2003 1. Correct EOC description.

2. Correct watchdog timer overflow time.

3. Correct POP operand.

4. Correct ADCKS table.

5. Add new section about checksum calculate must avoid 04H~07H.

6. Reserved Last 16 word ROM addresses

7. Add SIOM table and SIO rate note

8. Remove register bit description

9. Modify TC0M description

10. Modify TC1M description

11. Modify PWM description

12. Modify ADC Frequency description

13. Change Code option table to Chapter 2

14. Add ADC current consumption

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

15. Add LVD detect voltage

16. Remove approval sheet.

17. Remove PCB layout notice section.

18. Add MASK/OTP relative table.

19. Modify the description of INTRQ register.

20. Modify the calculation formula of SIOR and SIO clock.

VER 1.95 Jul. 2004 1. Change the minimal different voltage between AVREFH and AVREFL form “1.2V” to

“2.0V”.

2. Modify ADC programming notice.

3. In EOC bit description: Change “reset ADENB bit” to “reset ADS” bit.

4. Modify some electrical characteristics: Varef,

Vani, add Tast

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8-bit micro-controller build-in 12-bit ADC

Table of Contents

AMENDMENT HISTORY.............................................................................................................. 2

1

PRODUCT OVERVIEW ................................................................................................... 11

GENERAL DESCRIPTION ......................................................................................................... 11

FEATURES SELECTION TABLE....................................................................................... 11

MASK/OTP RELATIVE TABLE................................................................................................. 11

ADC GRADE TABLE............................................................................................................. 11

SN8P1702 FEATURES...............................................................................................................12

SN8P1704 FEATURES...............................................................................................................13

SN8P1707/SN8P1708 FEATURES ............................................................................................ 15

SYSTEM BLOCK DIAGRAM ...................................................................................................... 16

PIN ASSIGNMENT..................................................................................................................... 17

PIN DESCRIPTIONS.................................................................................................................. 22

PIN CIRCUIT DIAGRAMS .......................................................................................................... 22

2

3

CODE OPTION TABLE................................................................................................... 23

ADDRESS SPACES........................................................................................................ 24

PROGRAM MEMORY (ROM)..................................................................................................... 24

OVERVIEW............................................................................................................................. 24

USER RESET VECTOR ADDRESS (0000H).......................................................................... 26

INTERRUPT VECTOR ADDRESS (0008H)............................................................................ 26

CHECKSUM CALCULATION.................................................................................................. 28

GENERAL PURPOSE PROGRAM MEMORY AREA.............................................................. 29

LOOKUP TABLE DESCRIPTION............................................................................................ 29

JUMP TABLE DESCRIPTION................................................................................................. 31

DATA MEMORY (RAM).............................................................................................................. 33

OVERVIEW............................................................................................................................. 33

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8-bit micro-controller build-in 12-bit ADC

RAM BANK SELECTION ........................................................................................................ 35

WORKING REGISTERS............................................................................................................. 36

H, L REGISTERS.................................................................................................................... 36

Y, Z REGISTERS.................................................................................................................... 37

X REGISTERS........................................................................................................................ 38

R REGISTERS........................................................................................................................ 38

PROGRAM FLAG....................................................................................................................... 39

CARRY FLAG ......................................................................................................................... 39

DECIMAL CARRY FLAG......................................................................................................... 39

ZERO FLAG............................................................................................................................ 39

ACCUMULATOR ........................................................................................................................ 40

STACK OPERATIONS................................................................................................................41

OVERVIEW............................................................................................................................. 41

STACK REGISTERS............................................................................................................... 42

STACK OPERATION EXAMPLE............................................................................................. 43

PROGRAM COUNTER............................................................................................................... 44

ONE ADDRESS SKIPPING .................................................................................................... 45

MULTI-ADDRESS JUMPING.................................................................................................. 46

4

ADDRESSING MODE...................................................................................................... 47

OVERVIEW................................................................................................................................. 47

IMMEDIATE ADDRESSING MODE........................................................................................ 47

DIRECTLY ADDRESSING MODE .......................................................................................... 47

INDIRECTLY ADDRESSING MODE....................................................................................... 47

TO ACCESS DATA in RAM BANK 0 ....................................................................................... 48

TO ACCESS DATA in RAM BANK 1 ....................................................................................... 48

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SYSTEM REGISTER....................................................................................................... 49

OVERVIEW................................................................................................................................. 49

SYSTEM REGISTER ARRANGEMENT (BANK 0)..................................................................... 49

BYTES of SYSTEM REGISTER.............................................................................................. 49

BITS of SYSTEM REGISTER ................................................................................................. 51

SN8P1700

8-bit micro-controller build-in 12-bit ADC

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7

POWER ON RESET ........................................................................................................ 55

OVERVIEW................................................................................................................................. 55

EXTERNAL RESET DESCRIPTION........................................................................................... 56

LOW VOLTAGE DETECTOR (LVD) DESCRIPTION.................................................................. 57

OSCILLATORS................................................................................................................ 58

OVERVIEW................................................................................................................................. 58

CLOCK BLOCK DIAGRAM..................................................................................................... 58

OSCM REGISTER DESCRIPTION......................................................................................... 59

EXTERNAL HIGH-SPEED OSCILLATOR............................................................................... 60

OSCILLATOR MODE CODE OPTION.................................................................................... 60

OSCILLATOR DEVIDE BY 2 CODE OPTION......................................................................... 60

OSCILLATOR SAFE GUARD CODE OPTION ....................................................................... 60

SYSTEM OSCILLATOR CIRCUITS........................................................................................ 61

External RC Oscillator Frequency Measurement .................................................................... 62

INTERNAL LOW-SPEED OSCILLATOR.................................................................................... 63

SYSTEM MODE DESCRIPTION................................................................................................ 64

OVERVIEW............................................................................................................................. 64

NORMAL MODE.....................................................................................................................64

SLOW MODE.......................................................................................................................... 64

POWER DOWN MODE........................................................................................................... 64

SYSTEM MODE CONTROL....................................................................................................... 65

SN8P1700 SYSTEM MODE BLOCK DIAGRAM..................................................................... 65

SYSTEM MODE SWITCHING ................................................................................................ 66

WAKEUP TIME........................................................................................................................... 67

OVERVIEW............................................................................................................................. 67

HARDWARE WAKEUP........................................................................................................... 67

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TIMERS COUNTERS....................................................................................................... 68

WATCHDOG TIMER (WDT)....................................................................................................... 68

BASIC TIMER 0 (T0) .................................................................................................................. 69

SN8P1700

8-bit micro-controller build-in 12-bit ADC

OVERVIEW............................................................................................................................. 69

T0M REGISTER DESCRIPTION ............................................................................................ 69

T0C COUNTING REGISTER.................................................................................................. 70

T0 BASIC TIMER OPERATION SEQUENCE......................................................................... 71

TIMER COUNTER 0 (TC0)......................................................................................................... 72

OVERVIEW............................................................................................................................. 72

TC0M MODE REGISTER........................................................................................................ 73

TC0C COUNTING REGISTER................................................................................................ 74

TC0R AUTO-LOAD REGISTER.............................................................................................. 75

TC0 TIMER COUNTER OPERATION SEQUENCE................................................................ 76

TC0 CLOCK FREQUENCY OUTPUT (BUZZER).................................................................... 78

TC0OUT FREQUENCY TABLE.................................................................................................. 79

TIMER COUNTER 1 (TC1)......................................................................................................... 81

OVERVIEW............................................................................................................................. 81

TC1M MODE REGISTER........................................................................................................ 82

TC1C COUNTING REGISTER................................................................................................ 83

TC1R AUTO-LOAD REGISTER.............................................................................................. 84

TC1 TIMER COUNTER OPERATION SEQUENCE................................................................ 85

TC1 CLOCK FREQUENCY OUTPUT (BUZZER).................................................................... 87

PWM FUNCTION DESCRIPTION.............................................................................................. 88

OVERVIEW............................................................................................................................. 88

PWM PROGRAM DESCRIPTION........................................................................................... 89

9

INTERRUPT..................................................................................................................... 90

OVERVIEW................................................................................................................................. 90

INTEN INTERRUPT ENABLE REGISTER ................................................................................. 91

INTRQ INTERRUPT REQUEST REGISTER.............................................................................. 91

INTERRUPT OPERATION DESCRIPTION................................................................................ 92

GIE GLOBAL INTERRUPT OPERATION ............................................................................... 92

INT0 (P0.0) INTERRUPT OPERATION .................................................................................. 93

INT1 (P0.1) INTERRUPT OPERATION .................................................................................. 93

INT2 (P0.2) INTERRUPT OPERATION .................................................................................. 94

T0 INTERRUPT OPERATION................................................................................................. 95

TC0 INTERRUPT OPERATION.............................................................................................. 96

TC1 INTERRUPT OPERATION.............................................................................................. 97

SIO INTERRUPT OPERATION............................................................................................... 98

MULTI-INTERRUPT OPERATION.......................................................................................... 99

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8-bit micro-controller build-in 12-bit ADC

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OVERVIEW............................................................................................................................... 101

SIOM MODE REGISTER.......................................................................................................... 102

SIOB DATA BUFFER................................................................................................................103

SIOR REGISTER DESCRIPTION ............................................................................................ 103

SIO MASTER OPERATING DESCRIPTION ............................................................................ 104

RISING EDGE TRANSMITTER/RECEIVER MODE.............................................................. 104

FALLING EDGE TRANSMITTER/RECEIVER MODE........................................................... 105

RISING EDGE RECEIVER MODE........................................................................................ 106

FALLING EDGE RECEIVER MODE ..................................................................................... 107

SIO SLAVE OPERATING DESCRIPTION................................................................................ 108

RISING EDGE TRANSMITTER/RECEIVER MODE.............................................................. 109

FALLING EDGE TRANSMITTER/RECEIVER MODE........................................................... 110

RISING EDGE RECEIVER MODE........................................................................................ 111

FALLING EDGE RECEIVER MODE ..................................................................................... 112

SIO INTERRUPT OPERATION DESCRIPTION....................................................................... 113

SERIAL INPUT/OUTPUT TRANSCEIVER (SIO)................................................ 101

1

OVERVIEW............................................................................................................................... 114

I/O PORT FUNCTION TABLE .................................................................................................. 115

PULL-UP RESISTERS.............................................................................................................. 116

I/O PORT DATA REGISTER .................................................................................................... 119

2

OVERVIEW............................................................................................................................... 121

ADM REGISTER....................................................................................................................... 122

ADR REGISTERS..................................................................................................................... 122

ADB REGISTERS..................................................................................................................... 122

ADC CONVERTING TIME........................................................................................................ 124

ADC CIRCUIT........................................................................................................................... 125

I/O PORT............................................................................................................. 114

8-CHANNEL ANALOG TO DIGITAL CONVERTER........................................... 121

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8-bit micro-controller build-in 12-bit ADC

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3

OVERVIEW............................................................................................................................... 126

DAM REGISTER....................................................................................................................... 126

D/A CONVERTER OPERATION .............................................................................................. 127

4

TEMPLATE CODE.................................................................................................................... 128

CHIP DECLARATION IN ASSEMBLER.................................................................................... 133

PROGRAM CHECK LIST ......................................................................................................... 133

5

7-BIT DIGITAL TO ANALOG CONVERTER ...................................................... 126

CODING ISSUE .................................................................................................. 128

INSTRUCTION SET TABLE ............................................................................... 134

1

6

ABSOLUTE MAXIMUM RATING.............................................................................................. 135

STANDARD ELECTRICAL CHARACTERISTIC....................................................................... 135

SN8P1700 Series (OTP)....................................................................................................... 135

7

P-DIP18 PIN ............................................................................................................................. 136

SOP18 PIN ............................................................................................................................... 137

SSOP20 PIN............................................................................................................................. 138

S-DIP28 PIN ............................................................................................................................. 139

SOP28 PIN ............................................................................................................................... 140

QFP 44 PIN............................................................................................................................... 141

SSOP 48 PIN............................................................................................................................ 142

ELECTRICAL CHARACTERISTIC ..................................................................... 135

PACKAGE INFORMATION ................................................................................ 136

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8-bit micro-controller build-in 12-bit ADC

P-DIP 48 PIN ............................................................................................................................ 143

P-DIP 40 PIN ............................................................................................................................ 144

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

1

PRODUCT OVERVIEW

GENERAL DESCRIPTION

The SN8P1700 is a series of 8-bit micro-controller including SN8P1702, SN8P1704, SN8P1706, SN8P1707 and SN8P1708. This series is utilized with CMOS technology fabrication and featured with low power consumption and high performance by its unique electronic structure.

These chips are designed with the excellent IC structure including the large program memory OTP ROM, the massive data memory RAM, one 8-bit basic timer (T0), two 8-bit timer counters (TC0, TC1), a watchdog timer, up to seven interrupt sources (T0, TC0, TC1, SIO, INT0, INT1, INT2), a 7-bit DAC converter, an 8-channel ADC converter with 8-bit/12-bit resolution, two channel PWM output (PWM0, PWM1), tw0 channel buzzer output (BZ0, BZ1) and 8-level stack buffers. Besides, the user can choose desired oscillator configurations for the controller. There are four oscillator configurations to select for generating system clock, including High/Low Speed crystal, ceramic resonator or cost-saving RC. SN8P1700 series also includes an internal RC oscillator for slow mode controlled by programming.

FEATURES SELECTION TABLE

CHIP ROM RAM Stack

SN8P1702 1K*16 64 - V - 12 4ch - 1 - 3 SN8P1704 2K*16 128 - V V 18 5ch 1ch 2 1 8 SKDIP28/SOP28 SN8P1706 V V V 30 8ch 1ch 2 1 9 DIP40 SN8P1707 V V V 33 8ch 1ch 2 1 9 QFP44 SN8P1708

4K*16 256

8

Timer PWM Wakeup

T0 TC0 TC1

V V V 33 8ch 1ch 2 1 9 DIP48/SSOP48

I/O ADC DAC

Buzzer

SIO

Pin no.

Package

DIP18/SOP18

Table 1-1. Selection Table of SN8P1700

MASK/OTP Relative Table

Mask Version Package Form OTP Chip for Verification Assembler Declaration SN8A1702A DIP18/SOP18/SSOP20 SN8P1702 CHIP SN8P1702 SN8A1704A SKDIP28/SOP28 SN8P1704 CHIP SN8P1704 SN8A1706A DIP40 SN8P1706 CHIP SN8P1706 SN8A1707A QFP44 SN8P1707 CHIP SN8P1707 SN8A1708A DIP48/SSOP48 SN8P1708 CHIP SN8P1708

Note: Recommend SN8P1702A to replace SN8P1702 in new design. Refer SN8P1702A datasheet for details.

Table 1-2. MASK/OTP Relative Table

ADC GRADE TABLE

CHIP PARAMETER MIN MAX UNITS REMARK

SN8P170X

SN8P170X-12

Resolution 12 Bits

No Mission Code 8 12 Bits

Differential Nonlinearity (DNL) 16 LSB

Resolution 12 Bits

No Mission Code 10 12 Bits

Differential Nonlinearity (DNL) 4 LSB

Table 1-3. ADC Grade Table

170X:

1702~1708

170X:

1702~1708

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1702 FEATURES

Memory configuration

♦

OTP ROM size: 1K * 16 bits. One internal interrupts: TC0.

RAM size: 64 * 8 bits. One external interrupts: INT0.

I/O pin configuration (Total 12 pins)

♦ Input only: P0 Bi-directional: P1, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs. External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz

One 8-bit timer counters. (TC0).

♦

On chip watchdog timer.

♦

Eight levels stack buffer.

♦ Sleep mode: Both high and low clock stop

59 powerful instructions

♦ Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. PDIP 18 pins All ROM area lookup table function (MOVC) SOP 18 pins / SSOP20 (MASK type only)

Notice:

1. Declare “CHIP SN8P1702” in assembler.

2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information

3. Call @SET_PUR macro at least one time to avoid sleep mode fail.

Two interrupt sources

♦

An 4-channel ADC with 8-bit/12-bit resolution

♦

One channel PWM output. (PWM0)

♦

One channel Buzzer output. (BZ0)

♦

Dual clock system offers three operating modes

♦

Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and low clock active Slow mode: Low clock only

Package (Chip form support)

♦

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1704 FEATURES

Memory configuration

♦

OTP ROM size: 2K * 16 bits. Three internal interrupts: TC0, TC1, SIO.

RAM size: 128 * 8 bits. Three external interrupts: INT0, INT1, INT2.

I/O pin configuration (Total 18 pins)

♦ Input only: P0 Bi-directional: P1, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs.

Two 8-bit timer counters. (TC0, TC1).

♦

On chip watchdog timer.

♦

Eight levels stack buffer.

♦ Internal low clock: RC type 16KHz(3V), 32KHz(5V)

60 powerful instructions

♦ Four clocks per instruction cycle Slow mode: Low clock only All of instructions are one word length. Sleep mode: Both high and low clock stop Most of instructions are one cycle only. All ROM area lookup table function (MOVC) Support hardware multiplier (MUL). SOP 28 pins SKDIP 28 pins

Notice:

1. Declare “CHIP SN8P1704” in assembler.

2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information

3. Call @SET_PUR macro at least one time to avoid sleep mode fail.

Six interrupt sources

♦

A 5-channel ADC with 8-bit/12-bit resolution.

♦

One channel DAC with 7-bit resolution.

♦

SIO function.

♦

Two channel PWM output. (PWM0, PWM1)

♦

Two channel Buzzer output. (BZ0, BZ1)

♦

Dual clock system offers three operating modes

♦ External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz

Normal mode: Both high and low clock active

Package (Chip form support)

♦

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1706 FEATURES

Memory configuration

♦

OTP ROM size: 4K * 16 bits. Four internal interrupts: T0, TC0, TC1, SIO.

RAM size: 256 * 8 bits (bank 0 and bank 1). Three external interrupts: INT0, INT1, INT2.

I/O pin configuration (Total 30 pins)

♦ Input only: P0 Bi-directional: P1, P2, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P2, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs.

An 8-bit basic timer. (T0).

♦

Two 8-bit timer counters. (TC0, TC1).

♦

On chip watchdog timer.

♦

Eight levels stack buffer.

♦ Internal low clock: RC type 16KHz(3V), 32KHz(5V)

60 powerful instructions

♦ Four clocks per instruction cycle Slow mode: Low clock only All of instructions are one word length. Sleep mode: Both high and low clock stop Most of instructions are one cycle only. All ROM area lookup table function (MOVC) Support hardware multiplier (MUL). P-DIP 40 pins

Notice:

1. Declare “CHIP SN8P1706” in assembler.

2. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information

Seven interrupt sources

♦

An 8-channel ADC with 8-bit/12-bit resolution.

♦

One channel DAC 7bit resolution.

♦

SIO function.

♦

Two channel PWM output. (PWM0, PWM1)

♦

Two channel Buzzer output. (BZ0, BZ1)

♦

Dual clock system offers three operating modes

♦ External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz

Normal mode: Both high and low clock active

Package (Chip form support)

♦

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1707/SN8P1708 FEATURES

Memory configuration

♦

OTP ROM size: 4K * 16 bits. Four internal interrupts: T0, TC0, TC1, SIO.

RAM size: 256 * 8 bits (bank 0 and bank 1). Three external interrupts: INT0, INT1, INT2.

I/O pin configuration (Total 33 pins)

♦ Input only: P0 Bi-directional: P1, P2, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P2, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs.

An 8-bit basic timer. (T0).

♦

Two 8-bit timer counters. (TC0, TC1).

♦

On chip watchdog timer.

♦

Eight levels stack buffer.

♦ Internal low clock: RC type 16KHz(3V), 32KHz(5V)

60 powerful instructions

♦ Four clocks per instruction cycle Slow mode: Low clock only All of instructions are one word length. Sleep mode: Both high and low clock stop Most of instructions are one cycle only. All ROM area lookup table function (MOVC)

Support hardware multiplier (MUL).

Notice:

1. Declare “CHIP SN8P1707” for SN8P1707 in assembler.

2. Declare “CHIP SN8P1708” for SN8P1708 in assembler.

3. Use @SET_PUR macro to control pull-up resister. Refer I/O chapter for detailed information

Seven interrupt sources

♦

An 8-channel ADC with 8-bit/12-bit resolution.

♦

One channel DAC with 7-bit resolution.

♦

SIO function.

♦

Two channel PWM output. (PWM0, PWM1)

♦

Two channel Buzzer output. (BZ0, BZ1)

♦

Dual clock system offers three operating modes

♦ External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz

Normal mode: Both high and low clock active

Package (Chip form support)

♦

QPF 44 pins (SN8P1707) SSOP 48 pins (SN8P1708) PDIP 48 pins (SN8P1708)

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SYSTEM BLOCK DIAGRAM

Internal

PC

IR

FLAGS

ALU

ACC

INTERRUPT

INTERRUPT CONTROL

CONTROL

OTP

OTP ROM

ROM

SYSTEM REGISTER

SIO

SIO TX/RX

TX/RX

H-OSC

TIMING GENERATOR

RAM

Internal CLK

CLK

TIMER & COUNTER

Low Volt

Detector

Watch-Dog

Timer

PWM0

PWM1

DAC

ADC

PWM0/Buzzer0

PWM1/Buzzer1

DAO

AIN0~AIN7

PORT 0

PORT 2PORT 1 PORT 4 PORT 5

Figure 1-1.Simplified System Block Diagram

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

PIN ASSIGNMENT

Format Description：SN8P17XXY

OTP Type:

SN8P1702 (SOP 18PIN) SN8P1702 (PDIP 18PIN)

MASK Type:

SN8A1702A (SOP 18PIN) SN8A1702A (PDIP 18PIN) SN8A1702A (SSOP 20PIN)

P0.0/INT0 1 U 18VDD RST 2 17XIN P1.1 3 16XOUT P1.0 4 15P5.0 VSS 5 14P5.1 P4.3/AIN3 6 13P5.2 P4.2/AIN2 7 12P5.3 P4.1/AIN1 8 11P5.4/BZ0/PWM0 P4.0/AIN0 9 10VDD

SN8A1702AP SN8A1702AS

 Only MASK type support SSOP20 package

Y

= Q > QFP，P > PDIP，K > SKDIP，S > SOP，X> SSOP

P0.0/INT0 1 U 18 VDD/VPP RST 2 17 XIN P1.1 3 16 XOUT P1.0 4 15 P5.0 VSS 5 14 P5.1 P4.3/AIN3 6 13 P5.2 P4.2/AIN2 7 12 P5.3 P4.1/AIN1 8 11 P5.4/BZ0/PWM0 P4.0/AIN0 9 10 VDD

SN8P1702P SN8P1702S

VSS 1 U 20P1.0

VSS 2 19P1.1 P4.3/AIN3 3 18RST P4.2/AIN2 4 17P0.0/INT0 P4.1/AIN1 5 16VDD P4.0/AIN0 6 15XIN

AVREFH 7 14XOUT

VDD 8 13P5.0 P5.3 9 12P5.1

P5.2 10 11P5.4/BZ0/PWM0

SN8A1702AX

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

OTP Type:

SN8P1704 (SOP 28PIN) SN8P1704 (SKDIP 28PIN)

P1.4 1 U 28 RST P1.3 2 27 P0.2/INT2

VDD 3 26 P0.1/INT1

P1.2 4 25 P0.0/INT0 P1.1 5 24 VDD/VPP P1.0 6 23 XIN

VSS 7 22 XOUT P4.4/AIN4 8 21 VSS P4.3/AIN3 9 20 P5.0/SCK P4.2/AIN2 10 19 P5.1/SI P4.1/AIN1 11 18 P5.2/SO P4.0/AIN0 12 17 P5.3/BZ1/PWM1

AVREFH 13 16 P5.4/BZ0/PWM0

VDD 14 15 DAO

SN8P1704K SN8P1704S

MASK Type:

SN8A1704A (SOP 28PIN) SN8A1704A (SKDIP 28PIN)

P1.4 1 U 28 RST

P1.3 2 27 P0.2/INT2

VDD 3 26 P0.1/INT1

P1.2 4 25 P0.0/INT0

P1.1 5 24 VDD

P1.0 6 23 XIN

VSS 7 22 XOUT P4.4/AIN4 8 21 VSS P4.3/AIN3 9 20 P5.0/SCK P4.2/AIN2 10 19 P5.1/SI P4.1/AIN1 11 18 P5.2/SO P4.0/AIN0 12 17 P5.3/BZ1/PWM1

AVREFH 13 16 P5.4/BZ0/PWM0

VDD 14 15 DAO

SN8A1704AK SN8A1704AS

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8-bit micro-controller build-in 12-bit ADC

OTP Type:

SN8P1706 (P-DIP 40PIN)

P1.5 1 U 40 RST P1.4 2 39 P0.2/INT2 P1.3 3 38 P0.1/INT1 VDD 4 37 P0.0/INT0 P1.2 5 36 VDD/VPP P1.1 6 35 XIN P1.0 7 34 XOUT P2.0 8 33 VSS P2.1 9 32 P2.4 P2.2 10 31 P5.0/SCK P2.3 11 30 P5.1/SI

VSS 12 29 P5.2/SO P4.7/AIN7 13 28 P5.3/BZ1/PWM1 P4.6/AIN6 14 27 P5.4/BZ0/PWM0 P4.5/AIN5 15 26 P5.5 P4.4/AIN4 16 25 P5.6 P4.3/AIN3 17 24 P5.7 P4.2/AIN2 18 23 DAO P4.1/AIN1 19 22 VDD P4.0/AIN0 20 21 AVREFH

SN8P1706P

MASK Type:

SN8A1706A (P-DIP 40PIN)

P1.5 1 U 40 RST

P1.4 2 39 P0.2/INT2

P1.3 3 38 P0.1/INT1

VDD 4 37 P0.0/INT0

P1.2 5 36 NC

P1.1 6 35 XIN

P1.0 7 34 XOUT

P2.0 8 33 VSS

P2.1 9 32 P2.4

P2.2 10 31 P5.0/SCK

P2.3 11 30 P5.1/SI

AVREFL 12 29 P5.2/SO P4.7/AIN7 13 28 P5.3/BZ1/PWM1 P4.6/AIN6 14 27 P5.4/BZ0/PWM0 P4.5/AIN5 15 26 P5.5 P4.4/AIN4 16 25 P5.6 P4.3/AIN3 17 24 P5.7 P4.2/AIN2 18 23 DAO P4.1/AIN1 19 22 VDD P4.0/AIN0 20 21 AVREFH

SN8A1706AP

 For OTP type (SN8P1706) compatible issue, please connect AVREFL pin of MASK type (SN8A1706A) to

the analog ground of PCB. The voltage level of AVREFL pin is the valid lowest ADC input voltage. By the way, the AVREFH is the valid highest ADC input voltage.

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8-bit micro-controller build-in 12-bit ADC

OTP Type:

SN8P1707 (QFP 44PIN)

VPP/VDD 1 P0.0/INT0 2 32 P5.5 P0.1/INT1 3 31 P5.6 P0.2/INT2 4 30 P5.7

MASK Type:

SN8A1707A (QFP 44PIN)

XIN

XOUT

VSS

P2.7

P2.6

P2.5

P2.4

P5.0/SCK

P5.1/SI

P5.2/SO

P5.3/BZ1/PWM1

44 43 42 41 40 39 38 37 36 35 34

33 P5.4/BZ0/PWM0

O

RST 5 29 DAO P1.5 6 SN8P1707Q 28 VDD P1.4 7 27 AVREFH P1.3 8 26 P4.0/AIN0 VDD 9 25 P4.1/AIN1 P1.2 10 24 P4.2/AIN2 P1.1 11 23 P4.3/AIN3

12 13 14 15 16 17 18 19 20 21 22

P1.0

P2.0

P2.1

P2.2

P2.3

VSS

AVSS

P4.7/AIN7

P4.6/AIN6

P4.5/AIN5

P4.4/AIN4

P0.0/INT0 2 32 P5.5 P0.1/INT1 3 31 P5.6 P0.2/INT2 4 30 P5.7

RST 5 29 DAO P1.5 6 SN8A1707AQ 28 VDD P1.4 7 27 AVREFH P1.3 8 26 P4.0/AIN0 VDD 9 25 P4.1/AIN1 P1.2 10 24 P4.2/AIN2 P1.1 11 23 P4.3/AIN3

 For OTP type (SN8P1707) compatible issue, please connect AVREFL pin of MASK type (SN8A1707A) to

the analog ground of PCB. The voltage level of AVREFL pin is the valid lowest ADC input voltage. By the way, the AVREFH is the valid highest ADC input voltage.

XIN

XOUT

VSS

P2.7

P2.6

P2.5

P2.4

P5.0/SCK

P5.1/SI

44 43 42 41 40 39 38 37 36 35 34

NC 1

33 P5.4/BZ0/PWM0

O

12 13 14 15 16 17 18 19 20 21 22

P1.0

P2.0

P2.1

P2.2

P2.3

VSS

AVREFL

P4.7/AIN7

P4.6/AIN6

P5.2/SO

P5.3/BZ1/PWM1

P4.5/AIN5

P4.4/AIN4

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8-bit micro-controller build-in 12-bit ADC

OTP Type:

SN8P1708 (SSOP 48PIN) SN8P1708 (P-DIP 48PIN)

P2.5 1 U 48 P2.4 P2.6 2 47 P5.0/SCK P2.7 3 46 P5.1/SI

VSS 4 45 P5.2/SO VSS 5 44 P5.3/BZ1/PWM1

XOUT 6 43 VSS

XIN 7 42 P5.4/BZ0/PWM0

VPP/VDD 8 41 P5.5 P0.0/INT0 9 40 P5.6 P0.1/INT1 10 39 P5.7 P0.2/INT2 11 38 DAO

RST 12 37 VDD P1.5 13 36 AVDD P1.4 14 35 AVREFH P1.3 15 34 P4.0/AIN0 VDD 16 33 P4.1/AIN1

VSS 17 32 P4.2/AIN2 P1.2 18 31 P4.3/AIN3 P1.1 19 30 P4.4/AIN4 P1.0 20 29 P4.5/AIN5 P2.0 21 28 P4.6/AIN6 P2.1 22 27 P4.7/AIN7 P2.2 23 26 AVSS P2.3 24 25 VSS

SN8P1708P SN8P1708X

MASK Type:

SN8A1708A (SSOP 48PIN) SN8A1708A (P-DIP 48PIN)

P2.5 1 U 48 P2.4 P2.6 2 47 P5.0/SCK P2.7 3 46 P5.1/SI

VSS 4 45 P5.2/SO

VSS 5 44 P5.3/BZ1/PWM1

XOUT 6 43 VSS

XIN 7 42 P5.4/BZ0/PWM0

NC 8 41 P5.5 P0.0/INT0 9 40 P5.6 P0.1/INT1 10 39 P5.7 P0.2/INT2 11 38 DAO

RST 12 37 VDD P1.5 13 36 AVDD P1.4 14 35 AVREFH P1.3 15 34 P4.0/AIN0 VDD 16 33 P4.1/AIN1

VSS 17 32 P4.2/AIN2 P1.2 18 31 P4.3/AIN3 P1.1 19 30 P4.4/AIN4 P1.0 20 29 P4.5/AIN5 P2.0 21 28 P4.6/AIN6 P2.1 22 27 P4.7/AIN7 P2.2 23 26 AVREFL P2.3 24 25 VSS

SN8A1708AP SN8A1708AX

 For OTP type (SN8P1708) compatible issue, please connect AVREFL pin of MASK type (SN8A1708A) to

the analog ground of PCB. The voltage level of AVREFL pin is the valid lowest ADC input voltage. By the way, the AVREFH is the valid highest ADC input voltage.

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8-bit micro-controller build-in 12-bit ADC

PIN DESCRIPTIONS

PIN NAME TYPE DESCRIPTION

VDD, VSS P Power supply input pins for digital circuit.

AVDD, AVSS P Power supply input pins for analog circuit.

VPP/VDD P OTP ROM programming pin. Connect to VDD in normal operation.

RST I System reset input pin. Schmitt trigger structure, active “low”, normal stay to “high”. XIN, XOUT I, O External oscillator pins. RC mode from XIN. P0.0 / INT0 I Port 0.0 and shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up resisters. P0.1 / INT1 I Port 0.1 and shared with INT1 trigger pin (Schmitt trigger) / Built-in pull-up resisters. P0.2 / INT2 I Port 0.2 and shared with INT2 trigger pin (Schmitt trigger) / Built-in pull-up resisters.

P1.0 ~ P1.5 I/O Port 1.0~Port 1.5 bi-direction pins / Built-in pull-up resisters. P2.0 ~ P2.7 I/O Port 2.0~Port 2.7 bi-direction pins / Built-in pull-up resisters. P4.0 ~ P4.7 I/O Port 4.0~Port 4.7 bi-direction pins / Built-in pull-up resisters.

P5.0 / SCK I/O Port 5.0 bi-direction pin and SIO’s clock input/output / Built-in pull-up resisters.

P5.1 / SI I/O Port 5.1 bi-direction pin and SIO’s data input / Built-in pull-up resisters.

P5.2 / SO I/O Port 5.2 bi-direction pin and SIO’s data output / Built-in pull-up resisters.

P5.3 / BZ1 / PWM1 I/O P5.4 / BZ0 / PWM0 I/O

P5.5 ~ P5.7 I/O Port 5.5~Port 5.7 bi-direction pins / Built-in pull-up resisters.

AVREFH I A/D converter high analog reference voltage.

AIN0 ~ AIN7 I Analog signal input pins for ADC converter.

DAO O 5-bit DAC signal output pin.

Port 5.3 bi-direction pin, TC1 ÷ 2 signal output pin for buzzer or PWM1 output pin. Built-in pull-up resisters. Port 5.4 bi-direction pin, TC0 ÷ 2 signal output pin for buzzer or PWM0 output pin. Built-in pull-up resisters.

Table 1-4. SN8P1700 Pin Description

PIN CIRCUIT DIAGRAMS

Port1, 2, 4, 5 structure

Po rt0 stru ctu re

PUR

Int. bus

 Note: All of the latch output circuits are push-pull structures.

Int. bus

Figure 1-2. Pin Circuit Diagram

PnM

PUR

PnM

Latch

Int. bus

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8-bit micro-controller build-in 12-bit ADC

2

Notice : The OSG working voltage and the frequency relation table:

The min. working voltage will be affect by the OSG option. It is very important to check this code option.

CODE OPTION TABLE

Code Option Content Function Description

RC Low cost RC for external high clock oscillator

Low frequency, power saving crystal (e.g. 32.768K) for external high clock oscillator

Table 2-1. Code Option Table of SN8P1700

High_Clk

High_Clk / 2

OSG

Watch_Dog

LVD

Security

32K X’tal

12M X’tal High speed crystal /resonator (e.g. 12M) for external high clock oscillator

4M X’tal Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator

Enable External high clock divided by two, Fosc = high clock / 2

Disable Fosc = high clock

Enable Enable Oscillator Safe Guard function

Disable Disable Oscillator Safe Guard function

Enable Enable Watch Dog function

Disable Disable Watch Dog function

Enable Enable the low voltage detect

Disable Disable the low voltage detect

Enable Enable ROM code Security function

Disable Disable ROM code Security function

Turn on the OSG will improve the EMI performance. But the side effect is an increase in the working voltage.

OSC. Freq.(Mhz)

1 2.4 2.2 2 2.4 2.2 4 2.5 2.2 6 2.5 2.3

8 2.6 2.4 10 2.8 2.6 12 3 2.7 16 3.5 2.8 18 3.7 3 20 4.1 3.2

Notice : The system working frequency is only warranty under 16Mhz.

OSG ON (Volt) OSG OFF(Volt)

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8-bit micro-controller build-in 12-bit ADC

3

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

ROM Maps for SN8P1700 devices provide OTP memory that programmable by user. SN8P1702 has 1K x 16-bit program memory, SN8P1704 has 2K x 16-bit program memory and SN8P1706, SN8P1707 and SN8P1708 have 4K x 16-bit program memory. The SN8P1700 program memory is able to fetch instructions through 12-bit wide PC (Program Counter) and can look up ROM data by using ROM code registers (R, X, Y, Z). In standard configuration, the device’s 4,096 x 16-bit program memory has four areas:

 1-word reset vector addresses  1-word Interrupt vector addresses  5-words reserved area  4K words (SN8P1706, SN8P1707, SN8P1708)

2K words (SN8P1704) 1K words (SN8P1702)

All of the program memory is partitioned into three coding areas. The 1 vector area), the 2 from 0008H to 0FFEH. The address 08H is the interrupt enter address point.

nd

area is a reserved area 04H ~07H, the 3rd area is for the interrupt vector and the user code area

0000H 0001H Jump to user start address 0002H Jump to user start address 0003H 0004H 0005H 0006H 0007H 0008H 0009H User program

. .

000FH

0010H 0011H

.

. 03FEH 03FFH

General purpose area

ROM

Reset vector

Reserved

Interrupt vector

Reserved

st

area is located from 00H to 03H(The Reset

User reset vector

Jump to user start address

User interrupt vector

End of user program

Figure 3-1. ROM Address Structure (SN8P1702)

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8-bit micro-controller build-in 12-bit ADC

0000H 0001H Jump to user start address 0002H Jump to user start address 0003H 0004H 0005H 0006H 0007H 0008H 0009H User program

.

. 000FH

0010H 0011H

.

. 07FEH 07FFH

General purpose area

ROM

Reset vector

Reserved

Interrupt vector

Reserved

User reset vector

Jump to user start address

User interrupt vector

End of user program

Figure 3-2. ROM Address Structure (SN8P1704)

0000H 0001H Jump to user start address 0002H Jump to user start address 0003H 0004H 0005H 0006H 0007H 0008H 0009H User program

.

. 000FH

0010H 0011H

.

. 0FFEH 0FFFH

Figure 3-3. ROM Address Structure (SN8P1706/SN8P1707/SN8P1708)

General purpose area

ROM

Reset vector

Reserved

Interrupt vector

Reserved

User reset vector

Jump to user start address

User interrupt vector

End of user program

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8-bit micro-controller build-in 12-bit ADC

USER RESET VECTOR ADDRESS (0000H)

A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory.

 Example: After power on reset, external reset active or reset by watchdog timer overflow. CHIP SN8P1708

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0001H ~ 0007H are reserved

ORG 10H START: ; 0010H, The head of user program.

. ; User program . . .

ENDP

; End of program

INTERRUPT VECTOR ADDRESS (0008H)

A 1-word vector address area is used to execute interrupt request. If any interrupt service is executed, the program counter (PC) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory.

 Example 1: This demo program includes interrupt service routine and the user program is behind the

interrupt service routine.

CHIP SN8P1708

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0001H ~ 0007H are reserved

ORG 8

START: ; The head of user program.

B0XCH A, ACCBUF PUSH . . . POP B0XCH A, ACCBUF RETI

. . . . JMP START

ENDP

; Interrupt service routine ; B0XCH doesn’t change C, Z flag ; Push 80H ~ 87H system registers

; Pop 80H ~ 87H system registers ; End of interrupt service routine

; User program

; End of user program

; End of program

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8-bit micro-controller build-in 12-bit ADC

 Example 2: The demo program includes interrupt service routine and the address of interrupt service

routine is in a special address of general-purpose area.

CHIP SN8P1708

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0001H ~ 0007H are reserved

ORG 08 JMP MY_IRQ ; 0008H, Jump to interrupt service routine address

ORG 10H START: ; 0010H, The head of user program.

. ; User program . . .

MY_IRQ: ;The head of interrupt service routine

 Remark: It is easy to get the rules of SONIX program from demo programs given above. These points are

as following.

1. The address 0000H is a “JMP” instruction to make the program go to general-purpose ROM area. The 0004H~0007H are reserved. Users have to skip 0004H~0007H addresses. It is very important and necessary.

2. The interrupt service starts from 0008H. Users can put the whole interrupt service routine from 0008H (Example1) or to put a “JMP” instruction in 0008H then place the interrupt service routine in other

general-purpose ROM area (Example2) to get more modularized coding style.

JMP START

B0XCH A, ACCBUF PUSH . . . POP B0XCH A, ACCBUF RETI

ENDP

; End of user program

; B0XCH doesn’t change C, Z flag ; Push 80H ~ 87H system registers

; Pop 80H ~ 87H system registers ; End of interrupt service routine ; End of program

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

CHECKSUM CALCULATION

The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses (0004H~0007H and last address) when calculate the Checksum value.

 Example:

The demo program shows how to avoid 0004H~0007H when calculated Checksum from 00H to the end of

user’s code MOV A,#END_USER_CODE$L B0MOV END_ADDR1,A ;save low end address to end_addr1 MOV A,#END_USER_CODE$M

B0MOV END_ADDR2,A ;save middle end address to end_addr2 CLR Y ;set Y to ooH CLR Z ;set Z to 00H @@: CALL YZ_CHECK ;call function of check yz value MOVC ; B0BSET FC ;clear C glag ADD DATA1,A ;add A to Data1 MOV A,R ADC DATA2,A ;add R to Data2 JMP END_CHECK ;check if the YZ address = the end of code AAA: INCMS Z ;Z=Z+1 JMP @B ;if Z!= 00H calculate to next address JMP Y_ADD_1 ;if Z=00H increase Y END_CHECK: MOV A,END_ADDR1 CMPRS A,Z ;check if Z = low end address JMP AAA ;if Not jump to checksum calculate MOV A,END_ADDR2 CMPRS A,Y ;if Yes, check if Y = middle end address JMP AAA ;if Not jump to checksum calculate JMP CHECKSUM_END ;if Yes checksum calculated is done. YZ_CHECK: ;check if YZ=0004H MOV A,#04H CMPRS A,Z ;check if Z=04H RET ;if Not return to checksum calculate MOV A,#00H CMPRS A,Y ;if Yes, check if Y=00H RET ;if Not return to checksum calculate INCMS Z ;if Yes, increase 4 to Z INCMS Z INCMS Z INCMS Z RET ;set YZ=0008H then return Y_ADD_1: INCMS Y ;increase Y NOP JMP @B ;jump to checksum calculate CHECKSUM_END: ………. ………. END_USER_CODE: ;Label of program end

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8-bit micro-controller build-in 12-bit ADC

GENERAL PURPOSE PROGRAM MEMORY AREA

The 4089 instruction’s op-code and look-up table data. The SN8P1700 includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, X, Y, Z).

The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table function and look-up table function, the program counter can’t leap over the boundary by program counter automatically. Users need to modify the PCH value to “PCH+1” as the PCL overflow (from 0FFH to 000H).

 Notice: 1:The SN8P1702’s ROM size is about 1K words and the SN8P1704’s ROM size is about 2K words.

1

-word at ROM locations 0010H~0FFEH are used as general-purpose memory. The area is stored

LOOKUP TABLE DESCRIPTION

In the ROM’s data lookup function, the X register is pointed to the highest 8-bit, Y register to the middle 8-bit and Z register to the lowest 8-bit data of ROM address. After MOVC instruction is executed, the low-byte data of ROM then will be stored in ACC and high-byte data stored in R register.

 Example: To look up the ROM data located “TABLE1”.

B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address B0MOV Z, #TABLE1$L ; To set lookup table1’s low address. MOVC ; To lookup data, R = 00H, ACC = 35H ;

; @@: . . ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H ; “ DW 2012H ; “

 CAUSION: The Y register can't increase automatically if Z register cross boundary from 0xFF to 0x00.

Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflow, Y

register must be added one. The following INC_YZ macro shows a simple method to process Y and Z

registers automatically.

 Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users

can omit “B0MOV X, #TABLE1$H”. SONiX ICE support more larger program memory addressing

capability. So make sure X register is “0” to avoid unpredicted error in loop-up table operation.

INCMS Z ; Z+1 JMP @F ; Not overflow INCMS Y ; Z overflow (FFH  00),  Y=Y+1 NOP ; Not overflow

MOVC ; To lookup data, R = 51H, ACC = 05H.

; Increment the index address for next address

 Example: INC_YZ Macro

INC_YZ MACRO INCMS Z ; Z+1 JMP @F ; Not overflow

INCMS Y ; Y+1 NOP ; Not overflow @@: ENDM

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The other coding style of loop-up table is to add Y or Z index register by accumulator. Be careful if carry happen. Refer following example for detailed information:

 Example: Increase Y and Z register by B0ADD/ADD instruction

B0MOV Y, #TABLE1$M ; To set lookup table’s middle address. B0MOV Z, #TABLE1$L ; To set lookup table’s low address.

GETDATA: ; MOVC ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 . . . . ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H ; “ DW 2012H ; “

B0MOV A, BUF ; Z = Z + BUF. B0ADD Z, A

B0BTS1 FC ; Check the carry flag. JMP GETDATA ; FC = 0 INCMS Y ; FC = 1. Y+1. NOP

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JUMP TABLE DESCRIPTION

The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. The way is easy to make a multi-stage program.

When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software. If the jump table leaps over the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program memory page (xx00H). Here one page mean 256 words.

 Example : If PC = 0323H (PCH = 03H、PCL = 23H)

ORG 0X0100 ; The jump table is from the head of the ROM boundary B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed.

JMP A0POINT ; ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT

In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will point to a wrong address 0x0000 and crash system operation. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H).

 Example: If “jump table” crosses over ROM boundary will cause errors.

ROM Address

. . . .

. . 0X00FD 0X00FE

0X00FF 0X0100 0X0101

. .

SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro is maybe wasting some ROM size. Notice the maximum jmp table number for this macro is limited under 254.

@JMP_A MACRO VAL IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) JMP ($ | 0XFF) ORG ($ | 0XFF) ENDIF ADD PCL, A ENDM

 Note: “VAL” is the number of the jump table listing number.

B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed. JMP A0POINT ; ACC = 0 JMP A1POINT ; ACC = 1 JMP A2POINT JMP A3POINT ; ACC = 3

; ACC = 2  jump table cross boundary here

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8-bit micro-controller build-in 12-bit ADC

 Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.

B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A 5 ; The number of the jump table listing is five. JMP A0POINT ; If ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT JMP A4POINT ; ACC = 4, jump to A4POINT

If the jump table position is from 00FDH to 0101H, the “@JMP_A” macro will make the jump table to start from 0100h.

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DATA MEMORY (RAM)

OVERVIEW

The SN8P1700 has internally built-in the data memory up to 256 bytes for storing the general-purpose data. For SN8P1702

 48 * 8-bit general purpose area in bank 0  128 * 8-bit system special register area

For SN8P1704

 128 * 8-bit general purpose area in bank 0  128 * 8-bit system special register area

For SN8P1706/SN8P1707/SN8P1708

 128 * 8-bit general purpose area in bank 0  128 * 8-bit general purpose area in bank 1  128 * 8-bit system special register area

The memory is separated into bank 0 and bank 1. The user can program RAM bank selection bits of RBANK register to access all data in any of the two RAM banks. The bank 0, using the first 128-byte location assigned as general-purpose area, and the remaining 128-byte in bank 0 as system register. The bank 1, using the first 128-byte location assigned as general-purpose area, and others useless.

BANK 0

000h 000h~03Fh of Bank 0 = To store general-

“ purpose data (64 bytes). “ “ “

“ 03Fh 080h 080h~0FFh of Bank 0 = To store system

“ registers (128 bytes).

“

0FFh

Figure 3-4. RAM Location of SN8P1702

RAM location

General purpose area

System register

End of bank 0 area

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BANK 0

BANK 1

Figure 3-6 RAM Location of SN8P1706/SN8P1707/SN8P1708

 Note: The undefined locations of system register area are logic “high” after executing read instruction

“MOV A, M”.

000h 000h~03Fh of Bank 0 = To store general-

“ purpose data (128 bytes).

“

07Fh 080h 080h~0FFh of Bank 0 = To store system

“ registers (128 bytes).

“

0FFh

Figure 3-5. RAM Location of SN8P1704

000h 000h~07Fh of Bank 0 = To store general-

“ purpose data (128 bytes).

“

07Fh 080h 080h~0FFh of Bank 0 = To store system

“ registers (128 bytes).

“

0FFh 100h Bank 1 = To store general-purpose data.

“

17Eh 17Fh

RAM location

General purpose area

System register

End of bank 0 area

RAM location

General purpose area

System register

End of bank 0 area

General purpose area

End of bank 1 area

Bank 1 has 128 bytes RAM.

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RAM BANK SELECTION

The RBANK is a 1-bit register located at 87H in RAM bank 0. The user can access RAM data by using this register pointing to working RAM bank for ACC to read/write RAM data.

RBANK initial value = xxxx xxx0

087H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RBANK

- - - - - - - R/W

RBNKSn: RAM bank selecting control bit. 0 = bank 0, 1 = bank 1.

 Example: RAM bank selecting.

; BANK 0 CLR RBANK ; b0bclr FRBNKS0 . ; BANK 1 MOV A, #1 ; b0bset FRBNKS0 B0MOV RBANK, A .

 Note: “B0MOV” instruction can access the RAM of bank 0 in other bank situation directly.

 Example: Access RAM bank 0 in RAM bank 1.

; BANK 1 B0BSET RBNKS0 ; Get into RAM bank 1 B0MOV A, BUF0 ; Read BUF0 data. BUF0 is in RAM bank0. MOV BUF1, A ; Write BUF0 data to BUF1. BUF1 is in RAM bank1. . . . MOV A, BUF1 ; Read BUF1(bank1) data and store in ACC. B0MOV BUF0, A ; Write ACC data to BUF0(bank0).

Under bank 1 situation, using “B0MOV” instruction is an easy way to access RAM bank 0 data. User can make a habit to read/write system register (0087H~00FFH). Then user can access system registers without switching RAM bank.

 Example: To Access the system registers in bank 1 situation.

; BANK 1 B0BSET RBNKS0 ; Switch the Ram Bank into bank 1 . . MOV A, #0FFH ; Set all pins of P1 to be logic high. B0MOV P1, A ; Operate the bank 0 special register by the b0mov instruction . ; while the RAM system in the bank1. B0MOV A, P0 ; Read P0 data in the Bank 0 and store into BUF1 in the bank 1. MOV BUF1, A ;

0 0 0 0 0 0 0 RBNKS0

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WORKING REGISTERS

The locations 80H to 85H of RAM bank 0 in data memory stores the specially defined registers such as register H, L, R, X, Y, Z, respectively shown in the following table. These registers can use as the general purpose of working buffer and be used to access ROM’s and RAM’s data. For instance, all of the ROM’s table can be looked-up with R, X, Y and Z registers. The data of RAM memory can be indirectly accessed with H, L, Y and Z registers.

80H 81H 82H 83H 84H 85H

RAM

R/W R/W R/W R/W R/W R/W

H, L REGISTERS

The H and L are 8-bit register with two major functions. One is to use the registers as working register. The other is to use the registers as data pointer to access RAM’s data. The @HL that is data point_0 index buffer located at address E6H in RAM bank_0. It employs H and L registers to addressing RAM location in order to read/write data through ACC. The Lower 4-bit of H register is pointed to RAM bank number and L register is pointed to RAM address number, respectively. The higher 4-bit data of H register is truncated in RAM indirectly access mode.

H initial value = 0000 0000

081H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

H

R/W R/W R/W R/W R/W R/W R/W R/W

L initial value = 0000 0000

080H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

L

R/W R/W R/W R/W R/W R/W R/W R/W

 Example: If want to read a data from RAM address 20H of bank_0, it can use indirectly addressing mode to

B0MOV H, #00H ; To set RAM bank 0 for H register B0MOV L, #20H ; To set location 20H for L register B0MOV A, @HL ; To read a data into ACC

 Example: Clear general-purpose data memory area of bank 0 using @HL register.

CLR H ; H = 0, bank 0 MOV A, #07FH B0MOV L, A ; L = 7FH, the last address of the data memory area CLR_HL_BUF: CLR @HL ; Clear @HL to be zero DECMS L ; L – 1, if L = 0, finish the routine JMP CLR_HL_BUF ; Not zero

CLR @HL END_CLR: ; End of clear general purpose data memory area of bank 0 . . . .

HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBIT0

LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0

access data as following.

L H R Z Y X

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Y, Z REGISTERS

The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. First, Y and Z registers can be used as working registers. Second, these two registers can be used as data pointers for @YZ register. Third, the registers can be address ROM location in order to look-up ROM data.

Y initial value = 0000 0000

084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Y

R/W R/W R/W R/W R/W R/W R/W R/W

Z initial value = 0000 0000

083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Z

R/W R/W R/W R/W R/W R/W R/W R/W

The @YZ that is data point_1 index buffer located at address E7H in RAM bank 0. It employs Y and Z registers to addressing RAM location in order to read/write data through ACC. The Lower 4-bit of Y register is pointed to RAM bank number and Z register is pointed to RAM address number, respectively. The higher 4-bit data of Y register is truncated in RAM indirectly access mode.

 Example: If want to read a data from RAM address 25H of bank 1, it can use indirectly addressing mode to

B0MOV Y, #01H ; To set RAM bank 1 for Y register B0MOV Z, #25H ; To set location 25H for Z register B0MOV A, @YZ ; To read a data into ACC

 Example: Clear general-purpose data memory area of bank 1 using @YZ register.

MOV A, #1 B0MOV Y, A ; Y = 1, bank 1 MOV A, #07FH B0MOV Z, A ; Y = 7FH, the last address of the data memory area

CLR_YZ_BUF: CLR @YZ ; Clear @YZ to be zero

DECMS Z ; Y – 1, if Y= 0, finish the routine JMP CLR_YZ_BUF ; Not zero

CLR @YZ END_CLR: ; End of clear general purpose data memory area of bank 0 .

 Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about Y, Z register look-up table application.

YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0

ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0

access data as following.

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X REGISTERS

There are two major functions of the X register. First, X register can be used as working registers. Second, the X registers must be clear in order to look-up the ROM data. The SN8P1700’s program counter only has 12-bit. In look-up table function, the users can omit X register.

X initial value = 0000 0000

085H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X

R/W R/W R/W R/W R/W R/W R/W R/W

 Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about X register look-up table application.

XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0

R REGISTERS

There are two major functions of the R register. First, R register can be used as working registers. Second, the R registers can be store high-byte data of look-up ROM data. After MOVC instruction executed, the high-byte data of a ROM address will be stored in R register and the low-byte data stored in ACC.

R initial value = 0000 0000

082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

R

R/W R/W R/W R/W R/W R/W R/W R/W

 Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.

RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0

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PROGRAM FLAG

The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is carry, borrow occurrence, then these flags will be set to PFLAG register.

PFLAG initial value = xxxx x000

086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PFLAG

- - - - - R/W R/W R/W

- - - - - C DC Z

CARRY FLAG

C = 1: If executed arithmetic addition with occurring carry signal or executed arithmetic subtraction without borrowing signal or executed rotation instruction with shifting out logic “1”. C = 0: If executed arithmetic addition without occurring carry signal or executed arithmetic subtraction with borrowing signal or executed rotation instruction with shifting out logic “0”.

DECIMAL CARRY FLAG

DC = 1: If executed arithmetic addition with occurring carry signal from low nibble or executed arithmetic subtraction without borrow signal from high nibble. DC = 0: If executed arithmetic addition without occurring carry signal from low nibble or executed arithmetic subtraction with borrow signal from high nibble.

ZERO FLAG

Z = 1: After operation, the content of ACC is zero. Z = 0: After operation, the content of ACC is not zero.

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ACCUMULATOR

The ACC is an 8-bits data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.

ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing mode.

 Example: Read and write ACC value.

; Read ACC data and store in BUF data memory MOV BUF, A

. .

; Write a immediate data into ACC MOV A, #0FH

. .

; Write ACC data from BUF data memory MOV A, BUF

. .

The PUSH and POP instructions don’t store ACC value as any interrupt service executed. ACC must be exchanged to another data memory defined by users. Thus, once interrupt occurs, these data must be stored in the data memory based on the user’s program as follows.

 Example: ACC and working registers protection.

ACCBUF EQU 00H ; ACCBUF is ACC data buffer in bank 0. INT_SERVICE:

B0XCH A, ACCBUF

PUSH. . ; Push instruction . . . . POP ; Pop instruction

B0XCH A, ACCBUF ; Re-load ACC

RETI ; Exit interrupt service vector

 Notice: To save and re-load ACC data must be used “B0XCH” instruction, or the PLAGE value maybe

modified by ACC.

; B0XCH doesn’t change C, Z flag

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STACK OPERATIONS

OVERVIEW

The stack buffer of SN8P1700 has 8-level high area and each level is 12-bits length. This buffer is designed to save and restore program counter’s (PC) data when interrupt service is executed. The STKP register is a pointer designed to point active level in order to save or restore data from stack buffer for kernel circuit. The STKnH and STKnL are the 12-bit stack buffers to store program counter (PC) data.

STACK BUFFER

PCL

PCLPCL

STK0L

RET /

RET / RETI

RETI

CALL /

CALL / interrupt

interrupt

STKP = 7

PCH

PCHPCH

STK0H

STKP + 1

STKP - 1

STKP - 1STKP - 1

STKP = 6

STKP = 5

STKP = 4

STKP = 3

STKP = 2

STKP = 1

STKP = 0

STKP

STKPSTKP

STK1H

STK2H

STK3H

STK4H

STK5H

STK6H

STK7H

STKP

STKPSTKP

Figure 3-7 Stack-Save and Stack-Restore Operation

STK1L

STK2L

STK3L

STK4L

STK5L

STK6L

STK7L

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STACK REGISTERS

The stack pointer (STKP) is a 4-bit register to store the address used to access the stack buffer, 12-bits data memory (STKnH and STKnL) set aside for temporary storage of stack addresses.

The two stack operations are writing to the top of the stack (Stack-Save) and reading (Stack-Restore) from the top of stack. Stack-Save operation decrements the STKP and the Stack-Resotre operation increments one time. That makes the STKP always points to the top address of stack buffer and writes the last program counter value (PC) into the stack buffer.

The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0.

STKP (stack pointer) initial value = 0xxx 1111

0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKP

R/W - - - R/W R/W R/W R/W

STKPBn: Stack pointer. (n = 0 ~ 3) GIE: Global interrupt control bit. 0 = disable, 1 = enable. More detail information is in interrupt chapter.

 Example: Stack pointer (STKP) reset routine.

MOV A, #00001111B B0MOV STKP, A

STKn (stack buffer) initial value = xxxx xxxx xxxx xxxx, STKn = STKnH + STKnL (n = 7 ~ 0)

0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKnH

- - - - R/W R/W R/W R/W

0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKnL

R/W R/W R/W R/W R/W R/W R/W R/W

STKnH: Store PCH data as interrupt or call executing. The n expressed 0 ~7. STKnL: Store PCL data as interrupt or call executing. The n expressed 0 ~7.

GIE - - - STKPB3 STKPB2 STKPB1 STKPB0

- - - - SnPC11 SnPC10 SnPC9 SnPC8

SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0

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STACK OPERATION EXAMPLE

The two kinds of Stack-Save operations to reference the stack pointer (STKP) and write the program counter contents (PC) into the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP is decremented and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as following table.

Stack Level

0 1 2 3 4 5 6 7

>8

STKPB3 STKPB2 STKPB1 STKPB0 High Byte Low Byte

1 1 1 1 STK0H STK0L 1 1 1 0 STK1H STK1L 1 1 0 1 STK2H STK2L 1 1 0 0 STK3H STK3L 1 0 1 1 STK4H STK4L 1 0 1 0 STK5H STK5L 1 0 0 1 STK6H STK6L 1 0 0 0 STK7H STK7L

- - - - - -

Table 3-1. STKP, STKnH and STKnL relative of Stack-Save Operation

STKP Register Stack Buffer

Description

-

Stack Overflow

There is a Stack-Restore operation corresponding each push operation to restore the program counter (PC). The RETI instruction is for interrupt service routine. The RET instruction is for CALL instruction. When a Stack-Restore operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as following table.

Stack Level

7 6 5 4 3 2 1 0

STKPB3 STKPB2 STKPB1 STKPB0 High Byte Low Byte

1 0 0 0 STK7H STK7L 1 0 0 1 STK6H STK6L 1 0 1 0 STK5H STK5L 1 0 1 1 STK4H STK4L 1 1 0 0 STK3H STK3L 1 1 0 1 STK2H STK2L 1 1 1 0 STK1H STK1L 1 1 1 1 STK0H STK0L

Table 3-2. STKP, STKnH and STKnL relative of Stack-Restore Operation

STKP Register Stack Buffer

Description

-

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PROGRAM COUNTER

The program counter (PC) is a 12-bit binary counter separated into the high-byte 4 bits and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program execution.

Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 11.

PC Initial value = xxxx 0000 0000 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PC

PCH Initial value = xxxx 0000

PCL Initial value = 0000 0000

- - - - 0 0 0 0 0 0 0 0 0 0 0 0

0CFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PCH

- - - - R/W R/W R/W R/W

0CEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PCL

R/W R/W R/W R/W R/W R/W R/W R/W

- - - - PC11 PC10 PC9 PC8

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PCH PCL

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ONE ADDRESS SKIPPING

There are 9 instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is matched, the PC will add 2 steps to skip next instruction.

If the condition of bit test instruction is matched, the PC will add 2 steps to skip next instruction.

JMP C0STEP ; Else jump to C0STEP. . C0STEP: NOP

B0MOV A, BUF0 ; Move BUF0 value to ACC. JMP C1STEP ; Else jump to C1STEP.

. C1STEP: NOP

If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.

JMP C0STEP ; Else jump to C0STEP. . C0STEP: NOP

If the result after increasing or decreasing by 1 is 0xFF or 0x00, the PC will add 2 steps to skip next instruction.

INCS instruction:

JMP C0STEP ; Jump to C0STEP if ACC is not zero. … C0STEP: NOP

INCMS instruction:

JMP C0STEP ; Jump to C0STEP if BUF0 is not zero. … C0STEP: NOP

DECS instruction:

JMP C0STEP ; Jump to C0STEP if ACC is not zero. … C0STEP: NOP

DECMS instruction:

JMP C0STEP ; Jump to C0STEP if BUF0 is not zero. … C0STEP: NOP

B0BTS1

B0BTS0

CMPRS

INCS

INCMS

DECS

DECMS

FC ; Skip next instruction, if Carry_flag = 1

FZ ; Skip next instruction, if Zero flag = 0.

A, #12H ; Skip next instruction, if ACC = 12H.

BUF0

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MULTI-ADDRESS JUMPING

Users can jump round multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate multi-address jumping function. If carry signal occurs after execution of ADD PCL, A, the carry signal will not affect PCH register.

 Example: If PC = 0323H (PCH = 03H、PCL = 23H)

; PC = 0323H MOV A, #28H B0MOV PCL, A ; Jump to address 0328H . . . . ; PC = 0328H . . MOV A, #00H B0MOV PCL, A ; Jump to address 0300H

 Example: If PC = 0323H (PCH = 03H、PCL = 23H)

; PC = 0323H B0ADD PCL, A ; PCL = PCL + ACC, the PCH cannot be changed. JMP A0POINT ; If ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT . . ;

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4

ADDRESSING MODE

OVERVIEW

The SN8P1700 provides three addressing modes to access RAM data, including immediate addressing mode, directly addressing mode and indirectly address mode. The main purpose of the three different modes is described in the following:

IMMEDIATE ADDRESSING MODE

The immediate addressing mode uses an immediate data to set up the location (MOV A, #I, B0MOV M,#I) in ACC or specific RAM.

Immediate addressing mode

MOV A, #12H ; To set an immediate data 12H into ACC

DIRECTLY ADDRESSING MODE

The directly addressing mode uses address number to access memory location (MOV A,12H, MOV 12H,A).

Directly addressing mode

B0MOV A, 12H ; To get a content of location 12H of bank 0 and save in ACC

INDIRECTLY ADDRESSING MODE

The indirectly addressing mode is to set up an address in data pointer registers (Y/Z) and uses MOV instruction to read/write data between ACC and @YZ register (MOV A,@YZ, MOV @YZ,A).

 Example: Indirectly addressing mode with @YZ register

CLR Y ; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.

MOV A, #01H B0MOV Y, A ; To set Y = 1 for accessing RAM bank 1. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.

MOV A, #0FH B0MOV Y, A ; To set Y = 15 for accessing RAM bank 15. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location 012H ; Into ACC.

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TO ACCESS DATA in RAM BANK 0

In the RAM bank 0, this area memory can be read/written by these three access methods.

 Example 1: To use RAM bank0 dedicate instruction (Such as B0xxx instruction).

B0MOV A, 12H ; To move content from location 12H of RAM bank 0 to ACC

 Example 2: To use directly addressing mode (Through RBANK register).

B0MOV RBANK, #00H ; To set RAM bank = 0 MOV A, 12H ; To move content from location 12H of RAM bank 0 to ACC

 Example 3: To use indirectly addressing mode with @YZ register.

CLR Y ; To clear Y register for accessing RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.

TO ACCESS DATA in RAM BANK 1

In the RAM bank 1, this area memory can be read/written by these two access methods.

 Example 1: To use directly addressing mode (Through RBANK register).

B0MOV RBANK, #01H ; To set RAM bank = 1 MOV A, 12H ; To move content from location 12H of RAM bank 0 to ACC

 Example 2: To use indirectly addressing mode with @YZ register.

MOV A, #01H B0MOV Y, A ; To set Y = 1 for accessing RAM bank 1. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.

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5

SYSTEM REGISTER

OVERVIEW

The system special register is located at 80h~FFh. The main purpose of system registers is to control the peripheral hardware of the chip. Using system registers can control I/O ports, SIO, ADC, PWM, timers and counters by programming. The Memory map provides an easy and quick reference source for writing application program. To accessing these system registers is controlled by the select memory bank (RBANK = 0) or the bank 0 read/write instruction (B0MOV, B0BSET, B0BCLR…).

SYSTEM REGISTER ARRANGEMENT (BANK 0)

BYTES of SYSTEM REGISTER

SN8P1702

0 1 2 3 4 5 6 7 8 9 A B C D E F

- - R Z Y - PFLAG - - - - - - - - -

8

- - - - - - - - - - - - - - - -

9

- - - - - - - - - - - - - - - -

A

- ADM ADB ADR - - - - - - - - - - - -

B

P1W P1M - - P4M P5M - - INTRQ INTEN OSCM - - TC0R PCL PCH

C

P0 P1 - - P4 P5 - - - - TC0M TC0C - - - STKP

D

- - - - - - - @YZ - - - - - - - -

E

STK7 STK7 STK6 STK6 STK5 STK5 STK4 STK4 STK3 STK3 STK2 STK2 STK1 STK1 STK0 STK0

F

Table 5-1. System Register Arrangement of SN8P1702

SN8P1704

0 1 2 3 4 5 6 7 8 9 A B C D E F

- - R Z Y - PFLAG - - - - - - - - -

8

- - - - - - - - - - - - - - - -

9

- - - - - - - - - - - - - - - -

A

DAM ADM ADB ADR SIOM SIOR SIOB - - - - - - - - -

B

P1W P1M - - P4M P5M - - INTRQ INTEN OSCM - - TC0R PCL PCH

C

P0 P1 - - P4 P5 - - - - TC0M TC0C TC1M TC1C TC1R STKP

D

- - - - - - - @YZ - - - - - - - -

E

STK7 STK7 STK6 STK6 STK5 STK5 STK4 STK4 STK3 STK3 STK2 STK2 STK1 STK1 STK0 STK0

F

Table 5-2. System Register Arrangement of SN8P1704

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1706/SN8P1707/SN8P1708

0 1 2 3 4 5 6 7 8 9 A B C D E F

L H R Z Y X PFLAG RBANK - - - - - - - -

8

- - - - - - - - - - - - - - - -

9

- - - - - - - - - - - - - - - -

A

DAM ADM ADB ADR SIOM SIOR SIOB - - - - - - - - -

B

P1W P1M P2M - P4M P5M - - INTRQ INTEN OSCM - - TC0R PCL PCH

C

P0 P1 P2 - P4 P5 - - T0M T0C TC0M TC0C TC1M TC1C TC1R STKP

D

- - - - - - @HL @YZ - - - - - - - -

E

STK7L STK7H STK6L STK6H STK5L STK5H STK4L STK4H STK3L STK3H STK2L STK2H STK1L STK1H STK0L STK0H

F

Table 5-3. System Register Arrangement of SN8P1706/SN8P1707/SN8P1708

Description

 Note:

L, H = Working & @HL addressing register. R = Working register and ROM lookup data buffer.

X = Working and ROM address register. Y, Z = Working, @YZ and ROM addressing register.

PFLAG = ROM page and special flag register. RBANK = RAM Bank Select register.

DAM = DAC’s mode register. ADM = ADC’s mode register.

ADB = ADC’s data buffer. ADR = ADC’s resolution selects register.

SIOM = SIO mode control register. SIOR = SIO’s clock reload buffer.

SIOB = SIO’s data buffer. P1W = Port 1 wakeup register.

PnM = Port n input/output mode register. Pn = Port n data buffer.

INTRQ = Interrupts’ request register. INTEN = Interrupts’ enable register.

OSCM = Oscillator mode register. PCH, PCL = Program counter.

T0M = Timer 0 mode register. TC0M = Timer/Counter 0 mode register.

T0C = Timer 0 counting register. TC0C = Timer/Counter 0 counting register.

TC1M = Timer/Counter 1 mode register. TC0R = Timer/Counter 0 auto-reload data buffer.

TC1C = Timer/Counter 1 counting register. TC1R = Timer/Counter 1 auto-reload data buffer. STKP = Stack pointer buffer. STK0~STK7 = Stack 0 ~ stack 7 buffer.

@HL = RAM HL indirect addressing index pointer. @YZ = RAM YZ indirect addressing index pointer.

a). All of register names had been declared in SONiX 8-bit MCU assembler. b). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code. c). It will get logic “H” data, when use instruction to check empty location. d). The low nibble of ADR register is read only. e). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers.

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

BITS of SYSTEM REGISTER

SN8P1702 System register table

Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Remarks

082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 R/W R 083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R/W Z 084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R/W Y

086H - - - - - C DC Z R/W PFLAG 0B1H ADENB ADS EOC GCHS - 0 CHS1 CHS0 R/W ADM mode register 0B2H ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 R ADB data buffer 0B3H - ADCKS ADLEN 0 ADB3 ADB2 ADB1 ADB0 R/W ADR register 0C0H 0 0 0 0 0 0 P11W P10W W P1W wakeup register 0C1H 0 0 0 0 0 0 P11M P10M R/W P1M I/O direction 0C4H 0 0 0 0 P43M P42M P41M P40M R/W P4M I/O direction 0C5H 0 0 0 P54M P53M P52M P51M P50M R/W P5M I/O direction 0C8H 0 0 TC0IRQ 0 0 0 0 P00IRQ R/W INTRQ 0C9H 0 0 TC0IEN 0 0 0 0 P00IEN R/W INTEN

0CAH 0 WDRST WDRate 0 CPUM0 CLKMD STPHX 0 R/W OSCM 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W PCL 0CFH - - - - - PC10 PC9 PC8 R/W PCH

0D0H - - - - - - - P00 R P0 data buffer 0D1H - - - - - - P11 P10 R/W P1 data buffer 0D4H - - - - P43 P42 P41 P40 R/W P4 data buffer 0D5H - - - P54 P53 P52 P51 P50 R/W P5 data buffer

0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 0 ALOAD0 TC0OUT 0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 R/W TC0C 0DFH GIE - - - STKPB3 STKPB2 STKPB1 STKPB0 R/W STKP stack pointer

0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 R/W @YZ index pointer 0F0H S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 R/W STK7L 0F1H - - - - - S7PC10 S7PC9 S7PC8 R/W STK7H 0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 R/W STK6L 0F3H - - - - - S6PC10 S6PC9 S6PC8 R/W STK6H

“ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “

“ “ “ “ “ “ “ “ “ “ “ 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R/W STK1L 0FDH - - - - - S1PC10 S1PC9 S1PC8 R/W STK1H

0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R/W STK0L 0FFH - - - - - S0PC10 S0PC9 S0PC8 R/W STK0H

PWM0OUT

R/W TC0M

Table 5-4. Bit System Register Table of SN8P1702

Note: a). To avoid system error, please be sure to put all the “0” as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code. d). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers.

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1704 System register table

Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Remarks

082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 R/W R 083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R/W Z 084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R/W Y 086H - - - - - C DC Z R/W PFLAG

0B0H DAENB DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0 R/W DAM data register 0B1H ADENB ADS EOC GCHS - CHS2 CHS1 CHS0 R/W ADM mode register 0B2H ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 R ADB data buffer 0B3H - ADCKS ADLEN 0 ADB3 ADB2 ADB1 ADB0 R/W ADR register 0B4H SENB START SRATE1 SRATE0 0 SCKMD SEDGE TXRX R/W SIOM mode register 0B5H SIOR7 SIOR6 SIOR5 SIOR4 SIOR3 SIOR2 SIOR1 SIOR0 W SIOR reload buffer 0B6H SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOB0 R/W SIOB data buffer

0C0H 0 0 0 P14W P13W P12W P11W P10W W P1W wakeup register

0C2H 0 0 0 0 0 0 0 0 R/W P2M I/O direction 0C1H 0 0 0 P14M P13M P12M P11M P10M R/W P1M I/O direction 0C4H 0 0 0 P44M P43M P42M P41M P40M R/W P4M I/O direction 0C5H 0 0 0 P54M P53M P52M P51M P50M R/W P5M I/O direction 0C8H 0 TC1IRQ TC0IRQ 0 SIOIRQ P02IRQ P01IRQ P00IRQ R/W INTRQ 0C9H 0 TC1IEN TC0IEN 0 SIOIEN P02IEN P01IEN P00IEN R/W INTEN

0CAH 0 WDRST WDRate 0 CPUM0 CLKMD STPHX 0 R/W OSCM 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W PCL 0CFH - - - - PC11 PC10 PC9 PC8 R/W PCH

0D0H - - - - - P02 P01 P00 R P0 data buffer 0D1H - - - P14 P13 P12 P11 P10 R/W P1 data buffer 0D4H - - - P44 P43 P42 P41 P40 R/W P4 data buffer 0D5H - - - P54 P53 P52 P51 P50 R/W P5 data buffer

0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 0 ALOAD0 TC0OUT 0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 R/W TC0C 0DCH TC1ENB TC1rate2 TC1rate1 TC1rate0 0 ALOAD1 TC1OUT 0DDH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 R/W TC1C 0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R 0DFH GIE - - - STKPB3 STKPB2 STKPB1 STKPB0 R/W STKP stack pointer

0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 R/W @YZ index pointer 0F0H S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 R/W STK7L

0F1H - - - - S7PC11 S7PC10 S7PC9 S7PC8 R/W STK7H 0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 R/W STK6L 0F3H - - - - S6PC11 S6PC10 S6PC9 S6PC8 R/W STK6H

“ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “

“ “ “ “ “ “ “ “ “ “ “ 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R/W STK1L 0FDH - - - - S1PC11 S1PC10 S1PC9 S1PC8 R/W STK1H

0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R/W STK0L 0FFH - - - - S0PC11 S0PC10 S0PC9 S0PC8 R/W STK0H

PWM0OUT

PWM1OUT

R/W TC0M

R/W TC1M

Table 5-5. Bit System Register Table of SN8P1704

Note: a). To avoid system error, please be sure to put all the “0” as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code. d). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers. e). For detail description please refer file of “System Register Quick Reference Table”

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SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1706 System register table

Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Remarks

080H LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 R/W L 081H HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBIT0 R/W H 082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 R/W R 083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R/W Z 084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R/W Y 085H XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0 R/W X 086H - - - - - C DC Z R/W PFLAG 087H - - - - - - - RBNKS0 R/W RBANK

0B0H DAENB DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0 R/W DAM data register 0B1H ADENB ADS EOC GCHS - CHS2 CHS1 CHS0 R/W ADM mode register 0B2H ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 R ADB data buffer 0B3H - ADCKS ADLEN 0 ADB3 ADB2 ADB1 ADB0 R/W ADR register 0B4H SENB START SRATE1 SRATE0 0 SCKMD SEDGE TXRX R/W SIOM mode register 0B5H SIOR7 SIOR6 SIOR5 SIOR4 SIOR3 SIOR2 SIOR1 SIOR0 W SIOR reload buffer 0B6H SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOB0 R/W SIOB data buffer

0C0H 0 0 P15W P14W P13W P12W P11W P10W W P1W wakeup register 0C1H 0 0 P15M P14M P13M P12M P11M P10M R/W P1M I/O direction 0C2H 0 0 0 P24M P23M P22M P21M P20M R/W P2M I/O direction 0C4H P47M P46M P45M P44M P43M P42M P41M P40M R/W P4M I/O direction 0C5H P57M P56M P55M P54M P53M P52M P51M P50M R/W P5M I/O direction 0C8H 0 TC1IRQ TC0IRQ T0IRQ SIOIRQ P02IRQ P01IRQ P00IRQ R/W INTRQ 0C9H 0 TC1IEN TC0IEN T0IEN SIOIEN P02IEN P01IEN P00IEN R/W INTEN

0CAH 0 WDRST Wdrate 0 CPUM0 CLKMD STPHX 0 R/W OSCM 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W PCL 0CFH - - - - PC11 PC10 PC9 PC8 R/W PCH

0D0H - - - - - P02 P01 P00 R P0 data buffer

0D1H - - P15 P14 P13 P12 P11 P10 R/W P1 data buffer

0D2H - - - P24 P23 P22 P21 P20 R/W P2 data buffer

0D4H P47 P46 P45 P44 P43 P42 P41 P40 R/W P4 data buffer

0D5H P57 P56 P55 P54 P53 P52 P51 P50 R/W P5 data buffer

0D8H T0ENB T0rate2 T0rate1 T0rate0 0 0 0 0 R/W T0M

0D9H T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R/W T0C 0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 0 ALOAD0 TC0OUT 0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 R/W TC0C 0DCH TC1ENB TC1rate2 TC1rate1 TC1rate0 0 ALOAD1 TC1OUT 0DDH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 R/W TC1C 0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R 0DFH GIE - - - STKPB3 STKPB2 STKPB1 STKPB0 R/W STKP stack pointer

0E6H @HL7 @HL6 @HL5 @HL4 @HL3 @HL2 @HL1 @HL0 R/W @HL index pointer

0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 R/W @YZ index pointer

0F0H S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 R/W STK7L

0F1H - - - - S7PC11 S7PC10 S7PC9 S7PC8 R/W STK7H

0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 R/W STK6L

0F3H - - - - S6PC11 S6PC10 S6PC9 S6PC8 R/W STK6H

“ “ “ “ “ “ “ “ “ “ “

“ “ “ “ “ “ “ “ “ “ “ 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R/W STK1L 0FDH - - - - S1PC11 S1PC10 S1PC9 S1PC8 R/W STK1H

0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R/W STK0L 0FFH - - - - S0PC11 S0PC10 S0PC9 S0PC8 R/W STK0H

PWM0OUT

PWM1OUT

R/W TC0M

R/W TC1M

Table 5-6. Bit System Register Table of SN8P1706

Note: a). To avoid system error, please be sure to put all the “0” as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code. d). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers. e). For detail description please refer file of “System Register Quick Reference Table”

SONiX TECHNOLOGY CO., LTD Page 53 Revision 1.95

SN8P1700

8-bit micro-controller build-in 12-bit ADC

SN8P1707/ SN8P1708 System register table

Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Remarks

080H LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 R/W L 081H HBIT7 HBIT6 HBIT5 HBIT4 HBIT3 HBIT2 HBIT1 HBIT0 R/W H 082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 R/W R 083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R/W Z 084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R/W Y 085H XBIT7 XBIT6 XBIT5 XBIT4 XBIT3 XBIT2 XBIT1 XBIT0 R/W X 086H - - - - - C DC Z R/W PFLAG 087H - - - - - - - RBNKS0 R/W RBANK

0B0H DAENB DAB6 DAB5 DAB4 DAB3 DAB2 DAB1 DAB0 R/W DAM data register 0B1H ADENB ADS EOC GCHS - CHS2 CHS1 CHS0 R/W ADM mode register 0B2H ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 R ADB data buffer 0B3H - ADCKS ADLEN 0 ADB3 ADB2 ADB1 ADB0 R/W ADR register 0B4H SENB START SRATE1 SRATE0 0 SCKMD SEDGE TXRX R/W SIOM mode register 0B5H SIOR7 SIOR6 SIOR5 SIOR4 SIOR3 SIOR2 SIOR1 SIOR0 W SIOR reload buffer 0B6H SIOB7 SIOB6 SIOB5 SIOB4 SIOB3 SIOB2 SIOB1 SIOB0 R/W SIOB data buffer

0C0H 0 0 P15W P14W P13W P12W P11W P10W W P1W wakeup register 0C1H 0 0 P15M P14M P13M P12M P11M P10M R/W P1M I/O direction 0C2H P27M P26M P25M P24M P23M P22M P21M P20M R/W P2M I/O direction 0C4H P47M P46M P45M P44M P43M P42M P41M P40M R/W P4M I/O direction 0C5H P57M P56M P55M P54M P53M P52M P51M P50M R/W P5M I/O direction 0C8H 0 TC1IRQ TC0IRQ T0IRQ SIOIRQ P02IRQ P01IRQ P00IRQ R/W INTRQ

0C9H 0 TC1IEN TC0IEN T0IEN SIOIEN P02IEN P01IEN P00IEN R/W INTEN 0CAH 0 WDRST Wdrate 0 CPUM0 CLKMD STPHX 0 R/W OSCM 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W PCL 0CFH - - - - PC11 PC10 PC9 PC8 R/W PCH

0D0H - - - - - P02 P01 P00 R P0 data buffer

0D1H - - P15 P14 P13 P12 P11 P10 R/W P1 data buffer

0D2H P27 P26 P25 P24 P23 P22 P21 P20 R/W P2 data buffer

0D4H P47 P46 P45 P44 P43 P42 P41 P40 R/W P4 data buffer

0D5H P57 P56 P55 P54 P53 P52 P51 P50 R/W P5 data buffer

0D8H T0ENB T0rate2 T0rate1 T0rate0 0 0 0 0 R/W T0M

0D9H T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0 R/W T0C 0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 0 ALOAD0 TC0OUT 0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 R/W TC0C 0DCH TC1ENB TC1rate2 TC1rate1 TC1rate0 0 ALOAD1 TC1OUT 0DDH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 R/W TC1C 0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R 0DFH GIE - - - STKPB3 STKPB2 STKPB1 STKPB0 R/W STKP stack pointer

0E6H @HL7 @HL6 @HL5 @HL4 @HL3 @HL2 @HL1 @HL0 R/W @HL index pointer

0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 R/W @YZ index pointer

0F0H S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 R/W STK7L

0F1H - - - - S7PC11 S7PC10 S7PC9 S7PC8 R/W STK7H

0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 R/W STK6L

0F3H - - - - S6PC11 S6PC10 S6PC9 S6PC8 R/W STK6H

“ “ “ “ “ “ “ “ “ “ “

“ “ “ “ “ “ “ “ “ “ “ 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R/W STK1L 0FDH - - - - S1PC11 S1PC10 S1PC9 S1PC8 R/W STK1H

0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R/W STK0L 0FFH - - - - S0PC11 S0PC10 S0PC9 S0PC8 R/W STK0H

PWM0OUT

PWM1OUT

R/W TC0M

R/W TC1M

Table 5-7. Bit System Register Table of SN8P1707/ SN8P1708

Note: a). To avoid system error, please be sure to put all the “0” as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code. d). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers. e). For detail description please refer file of “System Register Quick Reference Table”

SONiX TECHNOLOGY CO., LTD Page 54 Revision 1.95

SN8P1700

8-bit micro-controller build-in 12-bit ADC

6

OVERVIEW

SN8P1700 provides two system resets. One is external reset and the other is low voltage detector (LVD). The external reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built in internal circuit. When one of the reset devices occurs, the system will reset and the system registers become initial value. The timing diagram is as following.

POWER ON RESET

VDD

External Reset

LVD

LVD Detect Level

External Reset Detect Level

End of LVD Reset

Internal Reset Signal

Figure 6-1 Power on Reset Timing Diagram

Notice : The working current of the LVD is about 100uA.

End of External Reset

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EXTERNAL RESET DESCRIPTION

The external reset is a low level active device. The reset pin receives the low voltage and resets the system. When the voltage detects high level, it stops resetting the system. Users can use an external reset circuit to control system operation. It is necessary that the VDD must be stable.

VDD

External Reset

Internal Reset Signal

Figure 6-2 External Reset Timing Diagram

Users must to be sure the VDD stable earlier than external reset (Figure 5-2) or the external reset will fail. The external reset circuit is a simple RC circuit as following.

R

20K ohm

C

0.1uF

External Reset Detect Level

End of External ResetSystem Reset

VDD RST

MCU

VSS

VCC

GND

Figure 6-3. External Reset Circuit

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In worse-power condition as brown out reset. The reset pin may keep high level but the VDD is low voltage. That makes the system reset fail and chip error. To connect a diode from reset pin to VDD is a good solution. The circuit can force the capacitor to release electric charge and drop the voltage, and solve the error.

DIODE

R 20K ohm

C

0.1uF

VDD

RST

MCU

VSS

VCC

GND

Figure 6-4. External Reset Circuit with Diode

LOW VOLTAGE DETECTOR (LVD) DESCRIPTION

The LVD is a low voltage detector. It detects VDD level and reset the system as the VDD lower than the desired voltage. The detect level is 2.4V. If the VDD lower than 2.4V, the system resets. The LVD function is controlled by code option. Users can turn on it for special application like worse power condition. LVD work with external reset function. They are OR active.

VDD

LVD

The LVD can protect system to work well under brownout reset. But it is a high consumptive circuit. In 3V condition, the LVD consumes about 100uA. It is a very large consumption for battery system. So the LVD supports AC system well.

 Notice: LVD is selected by code option.

System Reset

LVD Detect Level

End of LVD Reset

Figure 6-5. LVD Timing Diagram

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7

OSCILLATORS

OVERVIEW

The SN8P1700 highly performs the dual clock micro-controller system. The dual clocks are high-speed clock and low-speed clock. The high-speed clock frequency is supplied through the external oscillator circuit. The low-speed clock frequency is supplied through on-chip RC oscillator circuit.

The external high-speed clock and the internal low-speed clock can be system clock (Fosc). And the system clock is divided by 4 to be the instruction cycle (Fcpu).

Fcpu = Fosc / 4

The system clock is required by the following peripheral modules:

 Basic timer (T0)  Timer counter 0 (TC0)  Timer counter 1 (TC1)  Watchdog timer  Serial I/O interface (SIO)  AD converter  PWM output (PWM0, PWM1)  Buzzer output (TC0OUT, TC1OUT)

CLOCK BLOCK DIAGRAM

HXRC(1:0) is code option

•00= RC

•01 =32 Khz Oscillator

•10 = High Speed Oscillator (>10Mhz)

XIN

XOUT

•10 = High Speed Oscillator (>10Mhz)

•11 = Standard Oscillator (4Mhz)

•11 = Standard Oscillator (4Mhz) STPHX HXRC

STPHX HXRC

HXOSC.

CPUM0

LXOSC.

fh

OSG : Oscillator Safe Guard

1 : Disable --System Default

fl

0 : Enable

Divided by 2

1 : Disable

1 : Disable 0 : Enable

0 : Enable

Divided by 2OSG

Divided by 2Divided by 2OSGOSG

CLKMD

Divided by 4

Divided by 4Divided by 4

fosc/4 CPUM0

fcpu

CPUM0

Figure 7-1. Clock Block Diagram

 HXOSC: External high-speed clock.  LXOSC: Internal low-speed clock.  OSG: Oscillator safe guard.

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OSCM REGISTER DESCRIPTION

The OSCM register is a oscillator control register. It can control oscillator select, system mode, watchdog timer clock source and rate.

OSCM initial value = 000x 000x

0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCM

- R/W R/W - R/W R/W R/W -

STPHX: Eternal high-speed oscillator control bit. 0 = free run, 1 = stop. This bit just only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC oscillator is still running. CLKMD: System high/Low speed mode select bit. 0 = normal (dual) mode, 1 = slow mode. CPUM0: CPU operating mode control bit. 0 = normal, 1 = sleep (power down) mode to turn off both high/low clock.

 Notice: The bit 7 of OSCM register must be “0”, or the system will be error.

0 WDRST Wdrate 0 CPUM0 CLKMD STPHX 0

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EXTERNAL HIGH-SPEED OSCILLATOR

SN8P1700 can be operated in four different oscillator modes. There are external RC oscillator modes, high crystal/resonator mode (12M code option), standard crystal/resonator mode (4M code option) and low crystal mode (32K code option). For different application, the users can select one of satiable oscillator mode by programming code option to generate system high-speed clock source after reset.

 Example: Stop external high-speed oscillator.

B0BSET FSTPHX ; To stop external high-speed oscillator only.

B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode).

OSCILLATOR MODE CODE OPTION

SN8P1700 has four oscillator modes for different applications. These modes are 4M, 12M, 32K and RC. The main purpose is to support different oscillator types and frequencies. High-speed crystal needs more current but the low one doesn’t. For crystals, there are three steps to select. If the oscillator is RC type, to select “RC” and the system will divide the frequency by 2 automatically. User can select oscillator mode from Code Option table before compiling. The table is as follow.

Code Option Oscillator Mode Remark

00 01 10 11

RC mode Output the Fcpu square wave from Xout pin.

32K 32768Hz

12M 12MHz ~ 16MHz

4M 3.58MHz

OSCILLATOR DEVIDE BY 2 CODE OPTION

SN8P1700 has an external clock divide by 2 function. It is a code option called “High_Clk / 2”. If “High_Clk / 2” is enabled, the external clock frequency is divided by 8 for the Fcpu. Fcpu is equal to Fosc/8. If “High_Clk / 2” is disabled, the external clock frequency is divided by 4 for the Fcpu. The Fcpu is equal to Fosc/4.

 Note: In RC mode, “High_Clk / 2” is always enabled.

OSCILLATOR SAFE GUARD CODE OPTION

SN8P1700 builds in an oscillator safe guard (OSG) to make oscillator more stable. It is a low-pass filter circuit and stops high frequency noise into system from external oscillator circuit. This function makes system to work better under AC noisy conditions.

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SYSTEM OSCILLATOR CIRCUITS

20PF

CRYSTAL

20PF

Figure 7-2. Crystal/Ceramic Oscillator

R

C

Figure 7-3. RC Oscillator

VDD XIN XOUT VSS

MCU

External Clock Input

Figure 7-4. External clock input

 Note1: The VDD and VSS of external oscillator circuit must be from the micro-controller. Don’t connect

them from the neighbor power terminal.

  Note2: The external clock input mode can select RC type oscillator or crystal type oscillator of the code

option and input the external clock into XIN pin.

  Note3: In RC type oscillator code option situation, the external clock’s frequency is divided by 2.   Note4: The power and ground of external oscillator circuit must be connected from the micro-controller’s

VDD and VSS. It is necessary to step up the performance of the whole system.

VDD XIN XOUT VSS

MCU

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External RC Oscillator Frequency Measurement

There are two ways to get the Fosc frequency of external RC oscillator. One measures the XOUT output waveform. Under external RC oscillator mode, the XOUT outputs the square waveform whose frequency is Fcpu. The other measures the external RC frequency by instruction cycle (Fcpu). The external RC frequency is the Fcpu multiplied by 4. We can get the Fosc frequency of external RC from the Fcpu frequency. The sub-routine to get Fcpu frequency of external oscillator is as the following.



Example: Fcpu instruction cycle of external oscillator

B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle

signal.

@@: B0BSET P1.0 ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P1.0 ; Measure the Fcpu frequency by oscilloscope. JMP @B

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INTERNAL LOW-SPEED OSCILLATOR

The internal low-speed oscillator is built in the micro-controller. The low-speed clock’s source is a RC type oscillator circuit. The low-speed clock can supplies clock for system clock, timer counter, watchdog timer, SIO clock source and so on.

 Example: Stop internal low-speed oscillator.

B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode).

 Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0 bit of OSCM

register.

The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relative between the RC frequency and voltage is as following.

Internal RC vs. VDD

40 35 30 25 20 15 10

Fintrc (KHz)

5 0

1.80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50

7.329

25.338

22.003

18.668

15.333

11.998

8.663

32.008

28.673

VDD (Volts)

Figure 7-5. Internal RC vs. VDD Diagram

 Example: To measure the internal RC frequency is by instruction cycle (Fcpu). The internal RC frequency is

the Fcpu multiplied by 4. So we can get the Fosc frequency of internal RC from the Fcpu frequency.

B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle signal. B0BSET FCLKMD ; Switch the system clock to internal low-speed clock mode.

@@: B0BSET P1.0 ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P1.0 ; Measure the Fcpu frequency by oscilloscope. JMP @B

38.678

35.343

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SYSTEM MODE DESCRIPTION

OVERVIEW

The chip is featured with low power consumption by switching around three different modes as following.

 High-speed mode  Low-speed mode  Power-down mode (Sleep mode)

In actual application, the user can adjust the chip’s controller to work in these three modes by using OSCM register. At the high-speed mode, the instruction cycle (Fcpu) is Fosc/4. At the low-speed mode and 3V, the Fcpu is 16KHz/4.

NORMAL MODE

In normal mode, the system clock source is external high-speed clock. After power on, the system works under normal mode. The instruction cycle is fosc/4. When the external high-speed oscillator is 3.58MHz, the instruction cycle is

3.58MHz/4 = 895KHz. All software and hardware are executed and working. In normal mode, system can get into power down mode and slow mode.

SLOW MODE

In slow mode, the system clock source is internal low-speed RC clock. To set CLKMD = 1, the system switch to slow mode. In slow mode, the system works as normal mode but the slower clock. The system in slow mode can get into normal mode and power down mode. To set STPHX = 1 to stop the external high-speed oscillator, and then the system consumes less power.

POWER DOWN MODE

The power down mode is also called sleep mode. The chip stops working as sleeping status. The power consumption is very less almost to zero. The power down mode is usually applied to low power consuming system as battery power productions. To set CUPM0 = 1, the system gets into power down mode. The external high-speed and low-speed oscillators are turned off. The system can be waked up by P0, P1 trigger signal.

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SYSTEM MODE CONTROL

SN8P1700 SYSTEM MODE BLOCK DIAGRAM

Power Down Mode

(Sleep Mode)

P0, P1 wake-up function active.

P0, P1 wake-up function active. External reset circuit active.

External reset circuit active.

Normal Mode Slow Mode

Figure 7-6. SN8P1700 System Mode Block Diagram

Operating mode description

MODE NORMAL SLOW

HX osc. Running By STPHX Stop

LX osc. Running Running Stop

CPU instruction Executing Executing Stop

T0 timer *Active *Active Inactive TC0 timer *Active *Active Inactive TC1 timer *Active *Active Inactive

Watchdog timer Active Active Inactive

Internal interrupt All active All active All inactive

External interrupt All active All active All inactive

Wakeup source - - P0, P1, Reset

CPUM0 = 01

CLKMD = 1

CLKMD = 0

POWER DOWN

(SLEEP)

REMARK

* Active by

programm.

Table 7-1. Operating Mode Description

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SYSTEM MODE SWITCHING

Switch normal/slow mode to power down (sleep) mode. CPUM0 = 1

B0BSET FCPUM0 ; set the system into power down mode. During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.

Switch normal mode to slow mode.

B0BSET FCLKMD ;To set CLKMD = 1, Change the system into slow mode B0BSET FSTPHX ;To stop external high-speed oscillator for power saving.

Switch slow mode to normal mode If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for external clock stable.

B0BCLR FSTPHX ; Turn on the external high-speed oscillator. B0MOV Z, #27 ; If VDD = 5V, internal RC=32KHz (typical) will delay

@@: DECMS Z ; 0.125ms X 81 = 10.125ms for external clock stable JMP @B ; B0BCLR FCLKMD ; Change the system back to the normal mode

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WAKEUP TIME

OVERVIEW

The external high-speed oscillator needs a delay time from stopping to operating. The delay is very necessary and makes the oscillator to work stably. Some conditions during system operating, the external high-speed oscillator often runs and stops. Under these condition, the delay time for external high-speed oscillator restart is called wakeup time.

There are two conditions need wakeup time. One is power down mode to normal mode. The other one is slow mode to normal mode. For the first case, SN8P1700 provides 2048 oscillator clocks to be the wakeup time. But in the last case, users need to make the wakeup time by themselves.

HARDWARE WAKEUP

When the system is in power down mode (sleep mode), the external high-speed oscillator stops. For wakeup into normal, SN8P1700 provides 2048 external high-speed oscillator clocks to be the wakeup time for warming up the oscillator circuit. After the wakeup time, the system goes into the normal mode. The value of the wakeup time is as following.

The wakeup time = 1/Fosc * 2048 (sec)

 Example: In power down mode (sleep mode), the system is waked up by P0 or P1 trigger signal. After the

wakeup time, the system goes into normal mode. The wakeup time of P0, P1 w akeup function is as following.

The wakeup time = 1/Fosc * 2048 = 0.57 ms (Fosc = 3.58MHz)

The wakeup time = 1/Fosc * 2048 = 62.5 ms (Fosc=32768Hz)

Under power down mode (sleep mode), there are only I/O ports with wakeup function making the system to return normal mode. The Port 0 and Port 1 have wakeup function. Port 0’s wakeup function always enables. The Port 1 controls by the P1W register.

P1W initial value = xx00 0000

0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P1W

- - W W W W W W

P10W~P15W: Port 1 wakeup function control bits. 0 = none wakeup function, 1 = Enable each pin of Port 1 wakeup function.

 Note: For SN8P1702 the P1W register only obtains P10W and P11W. For SN8P1704 the P1W register only

obtain P10W~P14W.

0 0 P15W P14W P13W P12W P11W P10W

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8

TIMERS COUNTERS

WATCHDOG TIMER (WDT)

The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program get into the unknown status by noise interference, WDT’s overflow signal will reset this chip and restart operation. The instruction that clear the watch-dog timer (B0BSET FWDRST) should be executed at proper points in a program within a given period. If an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. In order to generate different output timings, the user can control watchdog timer by modifying Wdrate control bits of OSCM register. The watchdog timer will be disabled at green and power down modes.

OSCM initial value = 0000 000x

0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCM

- R/W R/W - R/W R/W R/W -

 Notice: The bit 7 must be “0”, or the system will be error.

Wdrate: Watchdog timer rate select bit. 0 =14 WDRST : Watch dog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer’s counter.

Wdrate

0

1

0 WDRST Wdrate - CPUM0 CLKMD STPHX -

th

, 1 = 8th.

Watchdog timer overflow time External high-speed oscillator

1 / ( fcpu ÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz

1 / ( fcpu ÷ 2

1 / ( fcpu ÷ 28 ÷ 16 ) = 4.5 ms, Fosc=3.58MHz

1 / ( fcpu ÷ 2

14

÷ 16 ) = 32 s, Fosc=32768Hz

8

÷ 16 ) = 500 ms, Fosc=32768Hz

Figure 8-1. Watchdog timer overflow time table

 Note: The watch dog timer can be enabled or disabled by the code option.

 Example: An operation of watch-dog timer is as following. To clear the w atchdog timer’s counter in the top

of the main routine of the program.

Main: B0BSET FWDRST ; Clear the watchdog timer’s counter. . . CALL SUB1 CALL SUB2 . . . . . . JMP MAIN

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BASIC TIMER 0 (T0)

OVERVIEW

The basic timer (T0) is an 8-bit binary up counter. It uses T0M register to select T0C’s input clock for counting a precision time. If the T0 timer has occur an overflow (from FFH to 00H), it will continue counting and issue a time-out signal to trigger T0 interrupt to request interrupt service. The main purposes of the T0 basic timer is as following.

 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock

frequency.

Internal data bus

T0enb

(8-T0Rate)

÷2

(8-T0Rate)

Figure 8-2. Basic Timer T0 Block Diagram

fcpu

T0M REGISTER DESCRIPTION

The T0M is the basic timer mode register which is a 8-bit read/write register and only used the high nibble. By loading different value into the T0M register, users can modify the basic timer clock dynamically as program executing.

Eight rates for T0 timer can be selected by T0RATE0 ~ T0RATE2 bits. The range is from fcpu/2 to fcpu/256. The T0M initial value is zero and the rate is fcpu/256. The bit7 of T0M called T0ENB is the control bit to start T0 timer. The combination of these bits is to determine the T0 timer clock frequency and the intervals.

T0M initial value = 0000 xxxx

0D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T0M

R/W R/W R/W R/W - - - -

T0ENB: T0 timer control bit. 0 = disable, 1 = enable. T0RATE2~T0RATE0: The T0 timer’s clock source select bits. 000 = fcpu/256, 001 = fcpu/128, … , 110 = fcpu/4, 111 = fcpu/2.

T0ENB T0RATE2 T0RATE1 T0RATE0 0 0 0 0

Internal data bus

pre_load

T0C 8-bit binary counter T0 Time ou t

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T0C COUNTING REGISTER

T0C is an 8-bit counter register for the basic timer (T0). T0C must be reset whenever the T0ENB is set “1” to start the basic timer. T0C is incremented by one with every clock pulse which frequency is determined by T0RATE0 ~ T0RATE2. When T0C has incremented to “0FFH”, it will be cleared to “00H” in next clock and an overflow generated. Under T0 interrupt service request (T0IEN) enable condition, the T0 interrupt request flag will be set “1” and the system executes the interrupt service routine. The T0C has no auto reload function. After T0C overflow, the T0C is continuing counting. Users need to reset T0C value to get a accurate time.

T0C initial value = xxxx xxxx

0D9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T0C

R/W R/W R/W R/W R/W R/W R/W R/W

T0RATE T0CLOCK

000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms

T0C7 T0C6 T0C5 T0C4 T0C3 T0C2 T0C1 T0C0

High speed mode (fcpu = 3.58MHz / 4) Low speed mode (fcpu = 32768Hz / 4)

Max overflow interval One step = max/256 Max overflow interval One step = max/256

Figure 8-3. The Timing Table of Basic Timer T0.

The equation of T0C initial value is as following.

T0C initial value = 256 - (T0 interrupt interval time * input clock)

 Example : To set 10ms interval time for T0 interrupt at 3.58MHz high-speed mode. T0C value (74H) = 256 -

(10ms * fcpu/64)

T0C initial value = 256 - (T0 interrupt interval time * input clock)

= 256 - (10ms * 3.58 * 10 = 256 - (10 = 116 = 74H

-2

* 3.58 * 106 / 4 / 64)

6

/ 4 / 64)

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T0 BASIC TIMER OPERATION SEQUENCE

The T0 basic timer’s sequence of operation can be following.

 Set the T0C initial value to setup the interval time.  Set the T0ENB to be “1” to enable T0 basic timer.  T0C is incremented by one with each clock pulse which frequency is corresponding to T0M selection.  T0C overflow when T0C from FFH to 00H.  When T0C overflow occur, the T0IRQ flag is set to be “1” by hardware.  Execute the interrupt service routine.  Users reset the T0C value and resume the T0 timer operation.

 Example: Setup the T0M and T0C.

B0BCLR FT0IEN ; To disable T0 interrupt service B0BCLR FT0ENB ; To disable T0 timer MOV A,#20H ; B0MOV T0M,A ; To set T0 clock = fcpu / 64 MOV A,#74H B0MOV T0C,A ; To set T0C initial value = 74H (To set T0 interval = 10 ms) B0BSET FT0IEN ; To enable T0 interrupt service B0BCLR FT0IRQ ; To clear T0 interrupt request B0BSET FT0ENB ; To enable T0 timer

 Example: T0 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag PUSH ; Push

B0BTS1 FT0IRQ ; Check T0IRQ JMP EXIT_INT ; T0IRQ = 0, exit interrupt vector

B0BCLR FT0IRQ ; Reset T0IRQ MOV A,#74H ; Reload T0C B0MOV T0C,A . . ; T0 interrupt service routine . . JMP EXIT_INT ; End of T0 interrupt service routine and exit interrupt vector . . . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ;Restore ACC value

RETI ; Exit interrupt vector

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TIMER COUNTER 0 (TC0)

OVERVIEW

The timer counter 0 (TC0) is used to generate an interrupt request when a specified time interval has elapsed. TC0 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC0R) into which you write the

TC0out

PWM0OUT

P5.4

P5.4TC0R reload

TC0enb

TC0R reload data buffer

data buffer

load

Aload0

Compare

Interna l P5 .4 I/O circuit

Auto. re load

R

S

Buzzer

÷2

PWM

fcpu

counter reference value, and an 8-bit counter register (TC0C) whose value is automatically incremented by counter logic.

÷2

(8-TC0R ate)

CPUM0

TC0C

TC0C 8-bit binary counter

8-bit binary counter

TC0 Time ou t

Figure 8-4. Timer Count TC0 Block Diagram

The main purposes of the TC0 timer counter is as following.

 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock

frequency.

 Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ0 pin (P5.4).  PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM0OUT pin (P5.4).

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TC0M MODE REGISTER

The TC0M is the timer counter mode register, which is an 8-bit read/write register. By loading different value into the TC0M register, users can modify the timer counter clock frequency dynamically when program executing.

Eight rates for TC0 timer can be selected by TC0RATE0 ~ TC0RATE2 bits. The range is from fcpu/2 to fcpu/256. The TC0M initial value is zero and the rate is fcpu/256. The bit7 of TC0M called TC0ENB is the control bit to start TC0 timer. The combination of these bits is to determine the TC0 timer clock frequency and the intervals.

TC0M initial value = 0000 0000

0DAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC0M

R/W R/W R/W R/W - R/W R/W R/W

TC0ENB: TC0 counter/BZ0/PWM0OUT enable bit. 0 = disable, 1 = enable. TC0RATE2~TC0RATE0: TC0 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, … , 110 = fcpu/4, 111 = fcpu/2. ALOAD0: TC0 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. TC0OUT: TC0 time-out toggle signal output control bit. 0 = To disable TC0 signal output and to enable P5.4’s I/O function, 1 = To enable TC0’s signal output and to disable P5.4’s I/O function. (Auto-disable the PWM0OUT function.) PWM0OUT: TC0’s PWM output control bit. 0 = To disable the PWM output, 1 = To enable the PWM output (The TC0OUT control bit must = 0 )

 Note: Bit3 must set to 0..

 Note: The ICE S8KC do not support the PWM0OUT and TC0OUT Function. The PWM0OUT and TC0OUT

TC0ENB TC0RATE2 TC0RATE1 TC0RATE0 0 ALOAD0 TC0OUT PWM0OUT

must use the S8KD ICE (or later) to verify the function.

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8-bit micro-controller build-in 12-bit ADC

TC0C COUNTING REGISTER

TC0C is an 8-bit counter register for the timer counter (TC0). TC0C must be reset whenever the TC0ENB is set “1” to start the timer counter. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to “0FFH”, it is will be cleared to “00H” in next clock and an overflow is generated. Under TC0 interrupt service request (TC0IEN) enable condition, the TC0 interrupt request flag will be set “1” and the system executes the interrupt service routine.

TC0C initial value = xxxx xxxx

0DBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC0C

R/W R/W R/W R/W R/W R/W R/W R/W

TC0RATE TC0CLOCK

000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms

TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0

High speed mode (fcpu = 3.58MHz / 4) Low speed mode (fcpu = 32768Hz / 4)

Max overflow interval One step = max/256 Max overflow interval One step = max/256

Table 8-1. The Timing Table of Timer Count TC0

The equation of TC0C initial value is as following.

TC0C initial value = 256 - (TC0 interrupt interval time * input clock)

 Example: To set 10ms interval time for TC0 interrupt at 3.58MHz high-speed mode. TC0C value (74H) = 256 -

(10ms * fcpu/64)

TC0C initial value = 256 - (TC0 interrupt interval time * input clock)

= 256 - (10ms * 3.58 * 10 = 256 - (10 = 116 = 74H

-2

* 3.58 * 106 / 4 / 64)

6

/ 4 / 64)

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TC0R AUTO-LOAD REGISTER

TC0R is an 8-bit register for the TC0 auto-reload function. TC0R’s value applies to TC0OUT and PWM0OUT functions.. Under TC0OUT application, users must enable and set the TC0R register. The main purpose of TC0R is as following.

 Store the auto-reload value and set into TC0C when the TC0C overflow. (ALOAD0 = 1).  Store the duty value of PWM0OUT function.

TC0R initial value = xxxx xxxx

0CDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC0R

W W W W W W W W

The equation of TC0R initial value is like TC0C as following.

 Note: The TC0R is write-only register can’t be process by INCMS, DECMS instructions.

TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0

TC0R initial value = 256 - (TC0 interrupt interval time * input clock)

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TC0 TIMER COUNTER OPERATION SEQUENCE

The TC0 timer counter’s sequence of operation can be following.

 Set the TC0C initial value to setup the interval time.  Set the TC0ENB to be “1” to enable TC0 timer counter.  TC0C is incremented by one with each clock pulse which frequency is corresponding to T0M selection.  TC0C overflow when TC0C from FFH to 00H.  When TC0C overflow occur, the TC0IRQ flag is set to be “1” by hardware.  Execute the interrupt service routine.  Users reset the TC0C value and resume the TC0 timer operation.

 Example: Setup the TC0M and TC0C without auto-reload function.

B0BCLR FTC0IEN ; To disable TC0 interrupt service B0BCLR FTC0ENB ; To disable TC0 timer MOV A,#20H ; B0MOV TC0M,A ; To set TC0 clock = fcpu / 64 MOV A,#74H ; To set TC0C initial value = 74H B0MOV TC0C,A ;(To set TC0 interval = 10 ms)

B0BSET FTC0IEN ; To enable TC0 interrupt service B0BCLR FTC0IRQ ; To clear TC0 interrupt request B0BSET FTC0ENB ; To enable TC0 timer

 Example: Setup the TC0M and TC0C with auto-reload function.

B0BCLR FTC0IEN ; To disable TC0 interrupt service B0BCLR FTC0ENB ; To disable TC0 timer MOV A,#20H ; B0MOV TC0M,A ; To set TC0 clock = fcpu / 64 MOV A,#74H ; To set TC0C initial value = 74H B0MOV TC0C,A ; (To set TC0 interval = 10 ms) B0MOV TC0R,A ; To set TC0R auto-reload register

B0BSET FTC0IEN ; To enable TC0 interrupt service B0BCLR FTC0IRQ ; To clear TC0 interrupt request B0BSET FTC0ENB ; To enable TC0 timer B0BSET ALOAD0 ; To enable TC0 auto-reload function.

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 Example: TC0 interrupt service routine without auto-reload function.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag PUSH ; Push

B0BTS1 FTC0IRQ ; Check TC0IRQ JMP EXIT_INT ; TC0IRQ = 0, exit interrupt vector

B0BCLR FTC0IRQ ; Reset TC0IRQ MOV A,#74H ; Reload TC0C B0MOV TC0C,A . . ; TC0 interrupt service routine . . JMP EXIT_INT ; End of TC0 interrupt service routine and exit interrupt

vector . . . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

 Example: TC0 interrupt service routine with auto-reload.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag PUSH ; Push

B0BTS1 FTC0IRQ ; Check TC0IRQ JMP EXIT_INT ; TC0IRQ = 0, exit interrupt vector

B0BCLR FTC0IRQ ; Reset TC0IRQ . . ; TC0 interrupt service routine . . JMP EXIT_INT ; End of TC0 interrupt service routine and exit interrupt

vector . . . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

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TC0 CLOCK FREQUENCY OUTPUT (BUZZER)

TC0 timer counter provides a frequency output function. By setting the TC0 clock frequency, the clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0 output signal divides by 2. The TC0 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency.

Figure 8-5. The TC0OUT Pulse Frequency

 Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The

TC0OUT frequency is 1KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 2KHz. The TC0 clock source is from external oscillator clock. T0C rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C = TC0R = 131.

MOV A,#01100000B B0MOV TC0M,A ; Set the TC0 rate to Fcpu/4

MOV A,#131 ; Set the auto-reload reference value B0MOV TC0C,A B0MOV TC0R,A

B0BSET FTC0OUT ; Enable TC0 output to P5.4 and disable P5.4 I/O function B0BSET FALOAD0 ; Enable TC0 auto-reload function B0BSET FTC0ENB ; Enable TC0 timer

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TC0OUT FREQUENCY TABLE

TC0R

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

Fosc = 4MHz, TC0 Rate = Fcpu/8

TC0R

0 0.2441 56 0.3125 112 0.4340 168 0.7102 224 1.9531 1 0.2451 57 0.3141 113 0.4371 169 0.7184 225 2.0161 2 0.2461 58 0.3157 114 0.4401 170 0.7267 226 2.0833 3 0.2470 59 0.3173 115 0.4433 171 0.7353 227 2.1552 4 0.2480 60 0.3189 116 0.4464 172 0.7440 228 2.2321 5 0.2490 61 0.3205 117 0.4496 173 0.7530 229 2.3148 6 0.2500 62 0.3222 118 0.4529 174 0.7622 230 2.4038 7 0.2510 63 0.3238 119 0.4562 175 0.7716 231 2.5000 8 0.2520 64 0.3255 120 0.4596 176 0.7813 232 2.6042

9 0.2530 65 0.3272 121 0.4630 177 0.7911 233 2.7174 10 0.2541 66 0.3289 122 0.4664 178 0.8013 234 2.8409 11 0.2551 67 0.3307 123 0.4699 179 0.8117 235 2.9762 12 0.2561 68 0.3324 124 0.4735 180 0.8224 236 3.1250 13 0.2572 69 0.3342 125 0.4771 181 0.8333 237 3.2895 14 0.2583 70 0.3360 126 0.4808 182 0.8446 238 3.4722 15 0.2593 71 0.3378 127 0.4845 183 0.8562 239 3.6765 16 0.2604 72 0.3397 128 0.4883 184 0.8681 240 3.9063 17 0.2615 73 0.3415 129 0.4921 185 0.8803 241 4.1667 18 0.2626 74 0.3434 130 0.4960 186 0.8929 242 4.4643 19 0.2637 75 0.3453 131 0.5000 187 0.9058 243 4.8077 20 0.2648 76 0.3472 132 0.5040 188 0.9191 244 5.2083 21 0.2660 77 0.3492 133 0.5081 189 0.9328 245 5.6818 22 0.2671 78 0.3511 134 0.5123 190 0.9470 246 6.2500 23 0.2682 79 0.3531 135 0.5165 191 0.9615 247 6.9444 24 0.2694 80 0.3551 136 0.5208 192 0.9766 248 7.8125 25 0.2706 81 0.3571 137 0.5252 193 0.9921 249 8.9286 26 0.2717 82 0.3592 138 0.5297 194 1.0081 250 10.4167 27 0.2729 83 0.3613 139 0.5342 195 1.0246 251 12.5000 28 0.2741 84 0.3634 140 0.5388 196 1.0417 252 15.6250 29 0.2753 85 0.3655 141 0.5435 197 1.0593 253 20.8333 30 0.2765 86 0.3676 142 0.5482 198 1.0776 254 31.2500 31 0.2778 87 0.3698 143 0.5531 199 1.0965 255 62.5000 32 0.2790 88 0.3720 144 0.5580 200 1.1161 33 0.2803 89 0.3743 145 0.5631 201 1.1364 34 0.2815 90 0.3765 146 0.5682 202 1.1574 35 0.2828 91 0.3788 147 0.5734 203 1.1792 36 0.2841 92 0.3811 148 0.5787 204 1.2019 37 0.2854 93 0.3834 149 0.5841 205 1.2255 38 0.2867 94 0.3858 150 0.5896 206 1.2500 39 0.2880 95 0.3882 151 0.5952 207 1.2755 40 0.2894 96 0.3906 152 0.6010 208 1.3021 41 0.2907 97 0.3931 153 0.6068 209 1.3298 42 0.2921 98 0.3956 154 0.6127 210 1.3587 43 0.2934 99 0.3981 155 0.6188 211 1.3889 44 0.2948 100 0.4006 156 0.6250 212 1.4205 45 0.2962 101 0.4032 157 0.6313 213 1.4535 46 0.2976 102 0.4058 158 0.6378 214 1.4881 47 0.2990 103 0.4085 159 0.6443 215 1.5244 48 0.3005 104 0.4112 160 0.6510 216 1.5625 49 0.3019 105 0.4139 161 0.6579 217 1.6026 50 0.3034 106 0.4167 162 0.6649 218 1.6447 51 0.3049 107 0.4195 163 0.6720 219 1.6892 52 0.3064 108 0.4223 164 0.6793 220 1.7361 53 0.3079 109 0.4252 165 0.6868 221 1.7857 54 0.3094 110 0.4281 166 0.6944 222 1.8382 55 0.3109 111 0.4310 167 0.7022 223 1.8939

TC0OUT

(KHz)

Table 8-2. TC0OUT Frequency Table for Fosc = 4MHz, TC0 Rate = Fcpu/8

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Fosc = 16MHz, TC0 Rate = Fcpu/8

TC0R

0 0.9766 56 1.2500 112 1.7361 168 2.8409 224 7.8125

1 0.9804 57 1.2563 113 1.7483 169 2.8736 225 8.0645

2 0.9843 58 1.2626 114 1.7606 170 2.9070 226 8.3333

3 0.9881 59 1.2690 115 1.7730 171 2.9412 227 8.6207

4 0.9921 60 1.2755 116 1.7857 172 2.9762 228 8.9286

5 0.9960 61 1.2821 117 1.7986 173 3.0120 229 9.2593

6 1.0000 62 1.2887 118 1.8116 174 3.0488 230 9.6154

7 1.0040 63 1.2953 119 1.8248 175 3.0864 231 10.0000

8 1.0081 64 1.3021 120 1.8382 176 3.1250 232 10.4167

9 1.0121 65 1.3089 121 1.8519 177 3.1646 233 10.8696 10 1.0163 66 1.3158 122 1.8657 178 3.2051 234 11.3636 11 1.0204 67 1.3228 123 1.8797 179 3.2468 235 11.9048 12 1.0246 68 1.3298 124 1.8939 180 3.2895 236 12.5000 13 1.0288 69 1.3369 125 1.9084 181 3.3333 237 13.1579 14 1.0331 70 1.3441 126 1.9231 182 3.3784 238 13.8889 15 1.0373 71 1.3514 127 1.9380 183 3.4247 239 14.7059 16 1.0417 72 1.3587 128 1.9531 184 3.4722 240 15.6250 17 1.0460 73 1.3661 129 1.9685 185 3.5211 241 16.6667 18 1.0504 74 1.3736 130 1.9841 186 3.5714 242 17.8571 19 1.0549 75 1.3812 131 2.0000 187 3.6232 243 19.2308 20 1.0593 76 1.3889 132 2.0161 188 3.6765 244 20.8333 21 1.0638 77 1.3966 133 2.0325 189 3.7313 245 22.7273 22 1.0684 78 1.4045 134 2.0492 190 3.7879 246 25.0000 23 1.0730 79 1.4124 135 2.0661 191 3.8462 247 27.7778 24 1.0776 80 1.4205 136 2.0833 192 3.9063 248 31.2500 25 1.0823 81 1.4286 137 2.1008 193 3.9683 249 35.7143 26 1.0870 82 1.4368 138 2.1186 194 4.0323 250 41.6667 27 1.0917 83 1.4451 139 2.1368 195 4.0984 251 50.0000 28 1.0965 84 1.4535 140 2.1552 196 4.1667 252 62.5000 29 1.1013 85 1.4620 141 2.1739 197 4.2373 253 83.3333 30 1.1062 86 1.4706 142 2.1930 198 4.3103 254 125.0000 31 1.1111 87 1.4793 143 2.2124 199 4.3860 255 250.0000 32 1.1161 88 1.4881 144 2.2321 200 4.4643 33 1.1211 89 1.4970 145 2.2523 201 4.5455 34 1.1261 90 1.5060 146 2.2727 202 4.6296 35 1.1312 91 1.5152 147 2.2936 203 4.7170 36 1.1364 92 1.5244 148 2.3148 204 4.8077 37 1.1416 93 1.5337 149 2.3364 205 4.9020 38 1.1468 94 1.5432 150 2.3585 206 5.0000 39 1.1521 95 1.5528 151 2.3810 207 5.1020 40 1.1574 96 1.5625 152 2.4038 208 5.2083 41 1.1628 97 1.5723 153 2.4272 209 5.3191 42 1.1682 98 1.5823 154 2.4510 210 5.4348 43 1.1737 99 1.5924 155 2.4752 211 5.5556 44 1.1792 100 1.6026 156 2.5000 212 5.6818 45 1.1848 101 1.6129 157 2.5253 213 5.8140 46 1.1905 102 1.6234 158 2.5510 214 5.9524 47 1.1962 103 1.6340 159 2.5773 215 6.0976 48 1.2019 104 1.6447 160 2.6042 216 6.2500 49 1.2077 105 1.6556 161 2.6316 217 6.4103 50 1.2136 106 1.6667 162 2.6596 218 6.5789 51 1.2195 107 1.6779 163 2.6882 219 6.7568 52 1.2255 108 1.6892 164 2.7174 220 6.9444 53 1.2315 109 1.7007 165 2.7473 221 7.1429 54 1.2376 110 1.7123 166 2.7778 222 7.3529 55 1.2438 111 1.7241 167 2.8090 223 7.5758

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

Table 8-3. TC0OUT Frequency Table for Fosc = 16MHz, TC0 Rate = Fcpu/8

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TIMER COUNTER 1 (TC1)

OVERVIEW

The timer counter 1 (TC1) is used to generate an interrupt request when a specified time interval has elapsed. TC1 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC1R) into which you write the

TC1out

PWM1OUT

TC1enb

TC1R reload

TC1R reload da ta b u ffer

da ta b u ffer

load

Inte rn a l P 5 .3 I/O circu it

Aload1

Inte rn a l P 5 .3 I/O circu it

Buzzer

Auto. reload P5.3

Com pare

Buzzer

÷2

R

S

PWM

fcpu

÷2

(8-TC1Rate)

CPUM0

TC1C

TC1C 8-bit binary counter

8-bit binary counter

TC1 Time out

counter reference value, and an 8-bit counter register (TC1C) whose value is automatically incremented by counter logic.

Figure 8-6. Timer Count TC1 Block Diagram

The main purposes of the TC1 timer is as following.

 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock

frequency.

 Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ1 pin (P5.3).  PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM1OUT pin (P5.3).

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TC1M MODE REGISTER

The TC1M is an 8-bit read/write timer mode register. By loading different value into the TC1M register, users can modify the timer clock frequency dynamically as program executing.

Eight rates for TC1 timer can be selected by TC1RATE0 ~ TC1RATE2 bits. The range is from fcpu/2 to fcpu/256. The TC1M initial value is zero and the rate is fcpu/256. The bit7 of TC1M called TC1ENB is the control bit to start TC1 timer. The combination of these bits is to determine the TC1 timer clock frequency and the intervals.

TC1M initial value = 0000 0000

0DCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC1M

R/W R/W R/W R/W - R/W R/W R/W

TC1ENB: TC1 counter/BZ1/PWM1OUT enable bit. 0 = disable, 1 = enable. TC1RATE2~TC1RATE0: TC1 internal clock select bits. 000 = fcpu/256, 001 = fcpu/128, … , 110 = fcpu/4, 111 = fcpu/2. ALOAD1: TC1 auto-reload function control bit. 0 = none auto-reload, 1 = auto-reload. TC1OUT: TC1 time-out toggle signal output control bit. 0 = To disable TC1 signal output and to enable P5.3’s I/O function, 1 = To enable TC1’s signal output and to disable P5.3’s I/O function. (Auto-disable the PWM1OUT function.) PWM1OUT: TC1’s PWM output control bit. 0 = To disable the PWM output, 1 = To enable the PWM output (The TC1OUT control bit must = 0 )

 Note: Bit3 must set to 0..

 Note: The S8KC ICE do not support the PWM1OUT and TC1OUT Function. The PWM1OUT and TC1OUT

TC1ENB TC1RATE2 TC1RATE1 TC1RATE0 0 ALOAD1 TC1OUT PWM1OUT

must use the S8KD ICE (or later) to verify the function.

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TC1C COUNTING REGISTER

TC1C is an 8-bit counter register for the timer counter (TC1). TC1C must be reset whenever the TC1ENB is set “1” to start the timer. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to “0FFH”, it is will be cleared to “00H” in next clock and an overflow is generated. Under TC1 interrupt service request (TC1IEN) enable condition, the TC1 interrupt request flag will be set “1” and the system executes the interrupt service routine.

TC1C initial value = xxxx xxxx

0DDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC1C

R/W R/W R/W R/W R/W R/W R/W R/W

The interval time of TC1 basic timer table.

TC1RATE

000 fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms

TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0

TC1CLOC

K

High speed mode (fcpu = 3.58MHz / 4) Low speed mode (fcpu = 32768Hz / 4)

Max overflow interval One step = max/256 Max overflow interval One step = max/256

Table 8-4. The Timing Table of Timer Count TC1

The equation of TC1C initial value is as following.

TC1C initial value = 256 - (TC1 interrupt interval time * input clock)

 Example: To set 10ms interval time for TC1 interrupt at 3.58MHz high-speed mode. TC1C value (74H) = 256 -

(10ms * fcpu/64)

TC1C initial value = 256 - (TC1 interrupt interval time * input clock)

= 256 - (10ms * 3.58 * 10 = 256 - (10 = 116 = 74H

-2

* 3.58 * 106 / 4 / 64)

6

/ 4 / 64)

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TC1R AUTO-LOAD REGISTER

TC1R is an 8-bit register for the TC1 auto-reload function. TC1R’s value applies to TC1OUT and PWM1OUT functions. Under TC1OUT application, users must enable and set the TC1R register. The main purpose of TC1R is as following.

 Store the auto-reload value and set into TC1C when the TC1C overflow. (ALOAD1 = 1).  Store the duty value of PWM1OUT function.

TC1R initial value = xxxx xxxx

0DEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC1R

W W W W W W W W

The equation of TC1R initial value is like TC1C as following.

 Note: The TC1R is write-only register can’t be process by INCMS, DECMS instructions.

TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0

TC1R initial value = 256 - (TC1 interrupt interval time * input clock)

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TC1 TIMER COUNTER OPERATION SEQUENCE

The TC1 timer’s sequence of operation can be following.

 Set the TC1C initial value to setup the interval time.  Set the TC1ENB to be “1” to enable TC1 timer counter.  TC1C is incremented by one with each clock pulse which frequency is corresponding to TC1M selection.  TC1C overflow if TC1C from FFH to 00H.  When TC1C overflow occur, the TC1IRQ flag is set to be “1” by hardware.  Execute the interrupt service routine.  Users reset the TC1C value and resume the TC1 timer operation.

 Example: Setup the TC1M and TC1C without auto-reload function.

B0BCLR FTC1IEN ; To disable TC1 interrupt service B0BCLR FTC1ENB ; To disable TC1 timer MOV A,#20H ; B0MOV TC1M,A ; To set TC1 clock = fcpu / 64 MOV A,#74H ; To set TC1C initial value = 74H B0MOV TC1C,A ;(To set TC1 interval = 10 ms)

B0BSET FTC1IEN ; To enable TC1 interrupt service B0BCLR FTC1IRQ ; To clear TC1 interrupt request B0BSET FTC1ENB ; To enable TC1 timer

 Example: Setup the TC1M and TC1C with auto-reload function.

B0BCLR FTC1IEN ; To disable TC1 interrupt service B0BCLR FTC1ENB ; To disable TC1 timer MOV A,#20H ; B0MOV TC1M,A ; To set TC1 clock = fcpu / 64 MOV A,#74H ; To set TC1C initial value = 74H B0MOV TC1C,A ; (To set TC1 interval = 10 ms) B0MOV TC1R,A ; To set TC1R auto-reload register

B0BSET FTC1IEN ; To enable TC1 interrupt service B0BCLR FTC1IRQ ; To clear TC1 interrupt request B0BSET FTC1ENB ; To enable TC1 timer B0BSET ALOAD1 ; To enable TC1 auto-reload function.

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 Example: TC1 interrupt service routine without auto-reload function.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag PUSH ; Push

B0BTS1 FTC1IRQ ; Check TC1IRQ JMP EXIT_INT ; TC1IRQ = 0, exit interrupt vector

B0BCLR FTC1IRQ ; Reset TC1IRQ MOV A,#74H ; Reload TC1C B0MOV TC1C,A . . ; TC1 interrupt service routine . . JMP EXIT_INT ; End of TC1 interrupt service routine and exit interrupt

vector . . . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

 Example: TC1 interrupt service routine with auto-reload.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag PUSH ; Push

B0BTS1 FTC1IRQ ; Check TC1IRQ JMP EXIT_INT ; TC1IRQ = 0, exit interrupt vector

B0BCLR FTC1IRQ ; Reset TC1IRQ . . ; TC1 interrupt service routine . . JMP EXIT_INT ; End of TC1 interrupt service routine and exit interrupt

vector . . . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

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TC1 CLOCK FREQUENCY OUTPUT (BUZZER)

TC1 timer counter provides a frequency output function. By setting the TC1 clock frequency, the clock signal is output to P5.3 and the P5.3 general purpose I/O function is auto-disable. The TC1 output signal divides by 2. The TC1 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency.

Figure 8-7. The TC1OUT Pulse Frequency

 Example: Setup TC1OUT output from TC1 to TC1OUT (P5.3). The external high-speed clock is 4MHz. The

TC1OUT frequency is 1KHz. Because the TC1OUT signal is divided by 2, set the TC1 clock to 2KHz. The TC1 clock source is from external oscillator clock. TC1 rate is Fcpu/4. The TC1RATE2~TC1RATE1 = 110. TC1C = TC1R = 131.

MOV A,#01100000B B0MOV TC1M,A ; Set the TC1 rate to Fcpu/4

MOV A,#131 ; Set the auto-reload reference value B0MOV TC1C,A B0MOV TC1R,A

B0BSET FTC1OUT ; Enable TC1 output to P5.3 and disable P5.3 I/O function B0BSET FALOAD1 ; Enable TC1 auto-reload function B0BSET FTC1ENB ; Enable TC1 timer

 Note: The TC1OUT frequency table is as TC0OUT frequency table. Please consult TC0OUT frequency

table. (Table 7-2~7-5)

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PWM FUNCTION DESCRIPTION

OVERVIEW

PWM function is generated by TC0/TC1 timer counter and output the PWM signal to PWM0OUT pin (P5.4)/ PWM1OUT pin (P5.3). The 8-bit counter counts modulus 256, from 0-255, inclusive. The value of the 8-bit counter is compared to the contents of the reference register (TC0R/TC1R). When the reference register value (TC0R/TC1R) is equal to the counter value (TC0C/TC1C), the PWM output goes low. When the counter reaches zero, the PWM output is forced high. The low-to-high ratio (duty) of the PWM0/PWM1 output is TC0R/256 and TC1R/256.

All PWM outputs remain inactive during the first 256 input clock signals. Then, when the counter value (TC0C/TC1C) changes from FFH back to 00H, the PWM output is forced to high level. The pulse width ratio (duty cycle) is defined by the contents of the reference register (TC0R/TC1R) and is programmed in increments of 1:256. The 8-bit PWM data register TC0R/TC1R is write only register.

PWM output can be held at low level by continuously loading the reference register with 00H. Under PWM operating, to change the PWM’s duty cycle is to modify the TC0R/TC1R.

Reference Register Value

(TC0R/TC1R)

0000 0000 0/256 0000 0001 1/256 0000 0010 2/256

. .

. . 1000 0000 128/256 1000 0001 129/256

. .

. . 1111 1110 254/256 1111 1111 255/256

Duty

Table 8-5. The PWM Duty Cycle Table

01 128 ..... 254 255.....

TC0/TC1 Clock

TC0R/TC1R = 00H

TC0R/TC1R = 01H

TC0R/TC1R = 80H

TC0R/TC1R = FFH

01 128 ..... 254 255..........

High

Low

01 128 ..... 254 255.....

01 128 ..... 254 255..........

Figure 8-8 The Output of PWM with different TC0R/TC1R.

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PWM PROGRAM DESCRIPTION

 Example: Setup PWM0 output from TC0 to PWM0OUT (P5.4). The external high-speed oscillator clock is

4MHz. The duty of PWM is 30/256. The PWM frequency is about 1KHz. The PWM clock source is from external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110. TC0C = TC0R = 30.

MOV A,#01100000B B0MOV TC0M,A ; Set the TC0 rate to Fcpu/4 B0MOV TC0M,A ; Set the TC0 rate to Fcpu/4 MOV A,#0x00 ;First Time Initial TC0

MOV A,#30 ; Set the PWM duty to 30/256 B0MOV TC0R,A

B0BCLR FTC0OUT ; Disable TC0OUT function. B0BSET FPWM0OUT ; Enable PWM0 output to P5.4 and disable P5.4 I/O function B0BSET FTC0ENB ; Enable TC0 timer

 Note1: The TC0R and TC1R are write-only registers. Don’t process them using INCMS, DECMS

instructions.

 Note2: Set TC0C at initial is to make first duty-cycle correct. After TC0 is enabled, don’t modify TC0R

value to avoid duty cycle error of PWM output.

 Example: Modify TC0R/TC1R registers’ value.

MOV A, #30H ; Input a number using B0MOV instruction. B0MOV TC0R, A

INCMS BUF0 ; Get the new TC0R value from the BUF0 buffer defined by B0MOV A, BUF0 ; programming. B0MOV TC0R, A

 Note3: That is better to set the TC0C and TC0R value together when PWM0 duty modified. It protects the

PWM0 signal no glitch as PWM0 duty changing. That is better to set the TC1C and TC1R value together when PWM1 duty modified. It protects the PWM1 signal no glitch as PWM1 duty changing.

 Note4: The TC0OUT function must be set “0” when PWM0 output enable. The TC1OUT function must be

set “0” when PWM1 output enable.

 Note5: The PWM can work with interrupt request.

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9

INTERRUPT

OVERVIEW

The SN8P1700 provides 7 external interrupts (INT0 ~ INT2). These external interrupts can wakeup the chip from power down mode to high-speed normal mode. The external clock input pins of INT0/INT1/INT2 are shared with P0.0/P0.1/P0.2 pins. Once interrupt service is executed, the GIE bit in STKP register will clear to “0” for stopping other interrupt request. When interrupt service exits, the GIE bit will set to “1” to accept the next interrupts’ request. All of the interrupt request signals are stored in INTRQ register. The user can program the chip to check INTRQ’s content for setting executive priority.

The interrupt trigger edge : INT0 ~ INT2 = falling edge

T0 time out

1

interrupt sources, including four internal interrupts (T0, TC0, TC1 & SIO) and three

INTEN Interrupt enable register

T0IRQ

TC0 time out

TC1 time out

SIO time out

INT2 trigger

 Note: 1.For SN8P1702 only obtain one internal interrupt P00 and one external interrupt TC0.  Note: 2.The GIE bit must enable and all interrupt operations work.

INTRQ 7-bit Latchs

Figure 9-1. The 7 Interrupts of SN8P1700

TC0IRQ

TC1IRQ

SIOIRQ

P00IRQINT0 trigger

P01IRQINT1 trigger

P02IRQ

Interrupt vector address (0008H)

Interrupt enable gating

Global interrupt request signal

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INTEN INTERRUPT ENABLE REGISTER

INTEN is the interrupt request control register including four internal interrupts, three external interrupts and SIO interrupt enable control bits. One of the register to be set “1” is to enable the interrupt request function. Once of the interrupt occur, the program jump to ORG 8 to execute interrupt service routines. The program exits the interrupt service routine when the returning interrupt service routine instruction (RETI) is executed.

INTEN initial value = x000 0000

0C9H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTEN

- R/W R/W R/W R/W R/W R/W R/W

P00IEN : External P0.0 interrupt control bit. 0 = disable, 1 = enable. P01IEN : External P0.1 interrupt control bit. 0 = disable, 1 = enable. P02IEN : External P0.2 interrupt control bit. 0 = disable, 1 = enable. SIOIEN : SIO interrupt control bit. 0 = disable, 1 = enable. T0IEN : T0 timer interrupt control bit. 0 = disable, 1 = enable. TC0IEN : Timer interrupt control bit. 0 = disable, 1 = enable. TC1IEN : Timer interrupt control bit. 0 = disable, 1 = enable.

0 TC1IEN TC0IEN T0IEN SIOIEN P02IEN P01IEN P00IEN

INTRQ INTERRUPT REQUEST REGISTER

INTRQ is the interrupt request flag register. The register includes all interrupt request indication flags. Each one of these interrupt request occurs, the bit of the INTRQ register would be set “1”. The INTRQ value needs to be clear by programming after detecting the flag. In the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request.

INTRQ initial value = x000 0000

0C8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTRQ

- R/W R/W R/W R/W R/W R/W R/W

P00IRQ : External P0.0 interrupt request bit. 0 = non-request, 1 = request. P01IRQ : External P0.1 interrupt request bit. 0 = non-request, 1 = request. P02IRQ : External P0.2 interrupt request bit. 0 = non-request, 1 = request. SIOIRQ : SIO interrupt request bit. 0 = non-request, 1 = request. T0IRQ : T0 timer interrupt request control bit. 0 = non request, 1 = request. TC0IRQ : TC0 timer interrupt request controls bit. 0 = non request, 1 = request. TC1IRQ : TC1 timer interrupt request controls bit. 0 = non request, 1 = request.

When interrupt occurs, the related request bit of INTRQ register will be set to “1” no matter the related enable bit of INTEN register is enabled or disabled. If the related bit of INTEN = 1 and the related bit of INTRQ is also set to be “1”. As the result, the system will execute the interrupt vector (ORG 8). If the related bit of INTEN = 0, moreover, the system won’t execute interrupt vector even when the related bit of INTRQ is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.

0 TC1IRQ TC0IRQ T0IRQ SIOIRQ P02IRQ P01IRQ P00IRQ

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INTERRUPT OPERATION DESCRIPTION

SN8P1700 provides 7 interrupts. The operation of the 7 interrupts is as following.

GIE GLOBAL INTERRUPT OPERATION

GIE is the global interrupt control bit. All interrupts start work after the GIE = 1. It is necessary for interrupt service request. One of the interrupt requests occurs, and the program counter (PC) points to the interrupt vector (ORG 8) and the stack add 1 level.

STKP initial value = 0xxx 1111

0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKP

R/W - - - R/W R/W R/W R/W

GIE: Global interrupt control bit. 0 = disable, 1 = enable.

 Example: Set global interrupt control bit (GIE).

B0BSET FGIE ; Enable GIE

 Note: The GIE bit must enable and all interrupt operations work.

GIE - - - STKPB3 STKPB2 STKPB1 STKPB0

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INT0 (P0.0) INTERRUPT OPERATION

The INT0 is triggered by falling edge. When the INT0 trigger occurs, the P00IRQ will be set to “1” however the P00IEN is enable or disable. If the P00IEN = 1, the trigger event will make the P00IRQ to be “1” and the system enter interrupt vector. If the P00IEN = 0, the trigger event will make the P00IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.

 Example: INT0 interrupt request setup.

B0BSET FP00IEN ; Enable INT0 interrupt service B0BCLR FP00IRQ ; Clear INT0 interrupt request flag B0BSET FGIE ; Enable GIE

 Example: INT0 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag PUSH ; Push

B0BTS1 FP00IRQ ; Check P00IRQ JMP EXIT_INT ; P00IRQ = 0, exit interrupt vector

B0BCLR FP00IRQ ; Reset P00IRQ . . ; INT0 interrupt service routine . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

 Note: The PUSH and POP instruction only save L,H,R,Z,Y,X,PFLAG and RBANK registers but A register.

User must save register A by B0XCH instruction when PUSH command is used.

INT1 (P0.1) INTERRUPT OPERATION

The INT1 is triggered by falling edge. When the INT1 trigger occurs, the P01IRQ will be set to “1” however the P01IEN is enable or disable. If the P01IEN = 1, the trigger event will make the P01IRQ to be “1” and the system enter interrupt vector. If the P01IEN = 0, the trigger event will make the P01IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.

 Example: INT1 interrupt request setup.

B0BSET FP01IEN ; Enable INT1 interrupt service B0BCLR FP01IRQ ; Clear INT1 interrupt request flag B0BSET FGIE ; Enable GIE

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 Example: INT1 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag PUSH ; Push

B0BTS1 FP01IRQ ; Check P01IRQ JMP EXIT_INT ; P01IRQ = 0, exit interrupt vector

B0BCLR FP01IRQ ; Reset P01IRQ . . ; INT1 interrupt service routine . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

INT2 (P0.2) INTERRUPT OPERATION

The INT2 is triggered by falling edge. When the INT2 trigger occurs, the P02IRQ will be set to “1” however the P02IEN is enable or disable. If the P02IEN = 1, the trigger event will make the P02IRQ to be “1” and the system enter interrupt vector. If the P02IEN = 0, the trigger event will make the P02IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.

 Example: INT2 interrupt request setup.

B0BSET FP02IEN ; Enable INT2 interrupt service B0BCLR FP02IRQ ; Clear INT2 interrupt request flag B0BSET FGIE ; Enable GIE

 Example: INT2 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF PUSH ; Push

B0BTS1 FP02IRQ ; Check P02IRQ JMP EXIT_INT ; P02IRQ = 0, exit interrupt vector

B0BCLR FP02IRQ ; Reset P02IRQ . . ; INT2 interrupt service routine . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

; B0XCH doesn

’ t change C, Z flag

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T0 INTERRUPT OPERATION

When the T0C counter occurs overflow, the T0IRQ will be set to “1” however the T0IEN is enable or disable. If the T0IEN = 1, the trigger event will make the T0IRQ to be “1” and the system enter interrupt vector. If the T0IEN = 0, the trigger event will make the T0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.

 Example: T0 interrupt request setup.

B0BCLR FT0IEN ; Disable T0 interrupt service B0BCLR FT0ENB ; Disable T0 timer MOV A, #20H ; B0MOV T0M, A ; Set T0 clock = Fcpu / 64 MOV A, #74H ; Set T0C initial value = 74H B0MOV T0C, A ; Set T0 interval = 10 ms

B0BSET FT0IEN ; Enable T0 interrupt service B0BCLR FT0IRQ ; Clear T0 interrupt request flag B0BSET FT0ENB ; Enable T0 timer

B0BSET FGIE ; Enable GIE

 Example: T0 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF PUSH ; Push

B0BTS1 FT0IRQ ; Check T0IRQ JMP EXIT_INT ; T0IRQ = 0, exit interrupt vector

B0BCLR FT0IRQ ; Reset T0IRQ MOV A, #74H B0MOV T0C, A ; Reset T0C. . . ; T0 interrupt service routine . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

; B0XCH doesn

’ t change C, Z flag

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TC0 INTERRUPT OPERATION

When the TC0C counter occurs overflow, the TC0IRQ will be set to “1” however the TC0IEN is enable or disable. If the TC0IEN = 1, the trigger event will make the TC0IRQ to be “1” and the system enter interrupt vector. If the TC0IEN = 0, the trigger event will make the TC0IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.

 Example: TC0 interrupt request setup.

B0BCLR FTC0IEN ; Disable TC0 interrupt service B0BCLR FTC0ENB ; Disable TC0 timer MOV A, #20H ; B0MOV TC0M, A ; Set TC0 clock = Fcpu / 64 MOV A, #74H ; Set TC0C initial value = 74H B0MOV TC0C, A ; Set TC0 interval = 10 ms

B0BSET FTC0IEN ; Enable TC0 interrupt service B0BCLR FTC0IRQ ; Clear TC0 interrupt request flag B0BSET FTC0ENB ; Enable TC0 timer

B0BSET FGIE ; Enable GIE

 Example: TC0 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF PUSH ; Push

B0BTS1 FTC0IRQ ; Check TC0IRQ JMP EXIT_INT ; TC0IRQ = 0, exit interrupt vector

B0BCLR FTC0IRQ ; Reset TC0IRQ MOV A, #74H B0MOV TC0C, A ; Reset TC0C. . . ; TC0 interrupt service routine . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

; B0XCH doesn

’ t change C, Z flag

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TC1 INTERRUPT OPERATION

When the TC1C counter occurs overflow, the TC1IRQ will be set to “1” however the TC1IEN is enable or disable. If the TC1IEN = 1, the trigger event will make the TC1IRQ to be “1” and the system enter interrupt vector. If the TC1IEN = 0, the trigger event will make the TC1IRQ to be “1” but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.

 Example: TC1 interrupt request setup.

B0BCLR FTC1IEN ; Disable TC1 interrupt service B0BCLR FT C1ENB ; Disable TC1 timer MOV A, #20H ; B0MOV TC1M, A ; Set TC1 clock = Fcpu / 64 MOV A, #74H ; Set TC1C initial value = 74H B0MOV TC1C, A ; Set TC1 interval = 10 ms

B0BSET FTC1IEN ; Enable TC1 interrupt service B0BCLR FTC1IRQ ; Clear TC1 interrupt request flag B0BSET FTC1ENB ; Enable TC1 timer

B0BSET FGIE ; Enable GIE

 Example: TC1 interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF PUSH ; Push

B0BTS1 FTC1IRQ ; Check TC1IRQ JMP EXIT_INT ; TC1IRQ = 0, exit interrupt vector

B0BCLR FTC1IRQ ; Reset TC1IRQ MOV A, #74H B0MOV TC1C, A ; Reset TC1C. . . ; TC1 interrupt service routine . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

; B0XCH doesn

’ t change C, Z flag

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SIO INTERRUPT OPERATION

When the SIO finished transmitting, the SIOIRQ will be set to “1” however the SIOIEN is enable or disable. If the SIOIEN = 1, the trigger event will make the SIOIRQ to be “1” and the system enter interrupt vector. If the SIOIEN = 0, the trigger event will make the SIOIRQ to be “1” but the system will not enter interrupt vector. Users need to care for the operation under multi-interrupt situation.

 Example: SIO interrupt request setup.

B0BSET FSIOIEN ; Enable SIO interrupt service B0BCLR FSIOIRQ ; Clear SIO interrupt request flag B0BSET FGIE ; Enable GIE

 Example: SIO interrupt service routine.

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF PUSH ; Push

B0BTS1 FSIOIRQ ; Check SIOIRQ JMP EXIT_INT ; SIOIRQ = 0, exit interrupt vector

B0BCLR FSIOIRQ ; Reset SIOIRQ . . ; SIO interrupt service routine . . EXIT_INT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

; B0XCH doesn

’ t change C, Z flag

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MULTI-INTERRUPT OPERATION

In most conditions, the software designer uses more than one interrupt request. Processing multi-interrupt request needs to set the priority of these interrupt requests. The IRQ flags of the 7 interrupt are controlled by the interrupt event occurring. But the IRQ flag set doesn’t mean the system to execute the interrupt vector. The IRQ flags can be triggered by the events without interrupt enable. Just only any the event occurs and the IRQ will be logic “1”. The IRQ and its trigger event relationship is as the below table.

Interrupt Name Trigger Event Description

P00IRQ P0.0 trigger. Falling edge. P01IRQ P0.1 trigger. Falling edge. P02IRQ P0.2 trigger. Falling edge.

T0IRQ T0C overflow. TC0IRQ TC0C overflow. TC1IRQ TC1C overflow.

SIOIRQ End of SIO transmitter operating.

There are two things need to do for multi-interrupt. One is to make a good priority for these interrupt requests. Two is using IEN and IRQ flags to decide executing interrupt service routine or not. Users have to check interrupt control bit and interrupt request flag in interrupt vector. There is a simple routine as following.

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 Example: How does users check the interrupt request in multi-interrupt situation?

ORG 8 ; Interrupt vector B0XCH A, ACCBUF

PUSH ; Push INTP00CHK: ; Check INT0 interrupt request B0BTS1 FP00IEN ; Check P00IEN JMP INTP01CHK ; Jump check to next interrupt B0BTS0 FP00IRQ ; Check P00IRQ JMP INTP00 ; Jump to INT0 interrupt service routine INTP01CHK: ; Check INT1 interrupt request B0BTS1 FP01IEN ; Check P01IEN JMP INTP02CHK ; Jump check to next interrupt B0BTS0 FP01IRQ ; Check P01IRQ JMP INTP01 ; Jump to INT1 interrupt service routine INTP02CHK: ; Check INT2 interrupt request B0BTS1 FP02IEN ; Check P02IEN JMP INTT0CHK ; Jump check to next interrupt B0BTS0 FP02IRQ ; Check P02IRQ JMP INTP02 ; Jump to INT2 interrupt service routine INTT0CHK: ; Check T0 interrupt request B0BTS1 FT0IEN ; Check T0IEN JMP INTTC0CHK ; Jump check to next interrupt B0BTS0 FT0IRQ ; Check T0IRQ JMP INTT0 ; Jump to T0 interrupt service routine INTTC0CHK: ; Check TC0 interrupt request B0BTS1 FTC0IEN ; Check TC0IEN JMP INTTC1CHK ; Jump check to next interrupt B0BTS0 FTC0IRQ ; Check TC0IRQ JMP INTTC0 ; Jump to TC0 interrupt service routine INTTC1HK: ; Check TC1 interrupt request B0BTS1 FTC1IEN ; Check TC1IEN JMP INTSIOCHK ; Jump check to next interrupt B0BTS0 FTC1IRQ ; Check TC1IRQ JMP INTTC1 ; Jump to TC1 interrupt service routine INTSIOCHK: ; Check SIO interrupt request B0BTS1 FSIOIEN ; Check SIOIEN JMP INT_EXIT ; Jump to exit of IRQ B0BTS0 FSIOIRQ ; Check SIOIRQ JMP INTSIO ; Jump to SIO interrupt service routine INT_EXIT: POP ; Pop B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

; B0XCH doesn

’ t change C, Z flag

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SONiX SN8P1702, SN8P1704, SN8P1706, SN8P1708 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

PRODUCT OVERVIEW

GENERAL DESCRIPTION

FEATURES SELECTION TABLE

MASK/OTP Relative Table

ADC GRADE TABLE

SN8P1702 FEATURES

SN8P1704 FEATURES

SN8P1707/SN8P1708 FEATURES

SYSTEM BLOCK DIAGRAM

PIN ASSIGNMENT

PIN DESCRIPTIONS

PIN CIRCUIT DIAGRAMS

CODE OPTION TABLE

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

USER RESET VECTOR ADDRESS (0000H)

INTERRUPT VECTOR ADDRESS (0008H)

CHECKSUM CALCULATION

GENERAL PURPOSE PROGRAM MEMORY AREA

LOOKUP TABLE DESCRIPTION

JUMP TABLE DESCRIPTION

DATA MEMORY (RAM)

OVERVIEW

RAM BANK SELECTION

WORKING REGISTERS

H, L REGISTERS

Y, Z REGISTERS

X REGISTERS

R REGISTERS

PROGRAM FLAG

CARRY FLAG

DECIMAL CARRY FLAG

ZERO FLAG

ACCUMULATOR

STACK OPERATIONS

OVERVIEW

STACK REGISTERS

STACK OPERATION EXAMPLE

PROGRAM COUNTER

ONE ADDRESS SKIPPING

MULTI-ADDRESS JUMPING

ADDRESSING MODE

OVERVIEW

IMMEDIATE ADDRESSING MODE

DIRECTLY ADDRESSING MODE

INDIRECTLY ADDRESSING MODE

TO ACCESS DATA in RAM BANK 0

TO ACCESS DATA in RAM BANK 1

SYSTEM REGISTER

OVERVIEW

SYSTEM REGISTER ARRANGEMENT (BANK 0)

BYTES of SYSTEM REGISTER

BITS of SYSTEM REGISTER

OVERVIEW

POWER ON RESET

EXTERNAL RESET DESCRIPTION

LOW VOLTAGE DETECTOR (LVD) DESCRIPTION

OSCILLATORS

OVERVIEW

CLOCK BLOCK DIAGRAM

OSCM REGISTER DESCRIPTION

EXTERNAL HIGH-SPEED OSCILLATOR

OSCILLATOR MODE CODE OPTION

OSCILLATOR DEVIDE BY 2 CODE OPTION

OSCILLATOR SAFE GUARD CODE OPTION

SYSTEM OSCILLATOR CIRCUITS

External RC Oscillator Frequency Measurement

INTERNAL LOW-SPEED OSCILLATOR

SYSTEM MODE DESCRIPTION

OVERVIEW

NORMAL MODE

SLOW MODE

POWER DOWN MODE

SYSTEM MODE CONTROL

SN8P1700 SYSTEM MODE BLOCK DIAGRAM