SONiX SN8P1702A, SN8P1703A User Manual

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Preliminary SN8P1702A/SN8P1703A

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SN8P1700A Series

USER’S MANUAL

Preliminary

8-bit micro-controller build-in 12-bit ADC

SN8P1702A SN8P1703A

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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fai lure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of pe rsonal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.

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SONiX TECHNOLOGY CO., LTD Page 1 Revision 0.5

Preliminary SN8P1702A/SN8P1703A

AMENDMENT HISTORY

Version Date Description

VER 0.1 Jul. 2003 V1.0 Preliminary Version VER 0.2 Jul. 2003 Change watchdog overflow table

8-bit micro-controller build-in 12-bit ADC

VER 0.3 Jul. 2003

Aug. 2003

VER 0.4 Sep. 2003 1. Add SN8P1702A SSOP20 for Mask Mass production.

VER 0.5 Sep. 2003 1. Modify ADC convert time table

1. Modify selection table

2. DC current chars. Change

3. Feature change

4. Change SN8P1703 part number to SN8P1703A

5. Code option table has been relocated after pin description section.

6. Modify QTP approval sheet

7. Change Register description.

8. Add LVD typical value=1.8V in Elec. Char.

9. Add “Noise Filter” code option

2. Add TC1 Timer in Update table.

3. Modify Chap. 8 table/figure no.

4. Modify TC0/TC1 timer description and table.

5. Modify PWM description and table.

6. Modify electrical characteristic table

2. Modify the description of PEDGE register.

3. Modify the description of INTRQ register.

3. Remove approval sheet.

4. Separate the pin description section of SN8P1702A and SN8P1703A.

5. Remove PCB layout section

6. Add P-DIP 20 and Sop 20 package information.

7. Add SN8A1702B and SN8A1703A related description.

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

Table of Contents

AMENDMENT HISTORY.............................................................................................................. 2

1

PRODUCT OVERVIEW..................................................................................................... 8

GENERAL DESCRIPTION ........................................................................................................... 8

FEATURES SELECTION TABLE................................................................................................. 8

MASK/OTP RELATIVE TABLE.......................................................................................................... 8

ADC GRADE TABLE .................................................................................................................... 8

UPGRADE FROM SN8P1702 (OLD VERSION OTP)....................................................................... 9

SN8P1702A/SN8P1703A FEATURES ....................................................................................... 10

SYSTEM BLOCK DIAGRAM ...................................................................................................... 11

PIN ASSIGNMENT..................................................................................................................... 12

SN8P1702A Pin Assignment................................................................................................... 12

SN8P1703A Pin Assignment................................................................................................... 14

PIN DESCRIPTIONS.................................................................................................................. 15

PIN CIRCUIT DIAGRAMS .......................................................................................................... 15

2

3

CODE OPTION TABLE................................................................................................... 16

ADDRESS SPACES........................................................................................................ 17

PROGRAM MEMORY (ROM)..................................................................................................... 17

OVERVIEW............................................................................................................................. 17

USER RESET VECTOR ADDRESS (0000H) ......................................................................... 18

INTERRUPT VECTOR ADDRESS (0008H)............................................................................ 18

CHECKSUM CALCULATION.................................................................................................. 20

GENERAL PURPOSE PROGRAM MEMORY AREA ............................................................. 21

LOOKUP TABLE DESCRIPTION............................................................................................ 21

JUMP TABLE DESCRIPTION................................................................................................. 23

DATA MEMORY (RAM).............................................................................................................. 25

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

OVERVIEW............................................................................................................................. 25

WORKING REGISTERS............................................................................................................. 26

Y, Z REGISTERS.................................................................................................................... 26

R REGISTERS........................................................................................................................ 27

PROGRAM FLAG....................................................................................................................... 27

CARRY FLAG ......................................................................................................................... 27

DECIMAL CARRY FLAG......................................................................................................... 27

ZERO FLAG............................................................................................................................ 27

ACCUMULATOR........................................................................................................................ 28

STACK OPERATIONS................................................................................................................29

OVERVIEW............................................................................................................................. 29

STACK REGISTERS............................................................................................................... 30

STACK OPERATION EXAMPLE ............................................................................................ 31

PROGRAM COUNTER............................................................................................................... 32

ONE ADDRESS SKIPPING .................................................................................................... 33

MULTI-ADDRESS JUMPING.................................................................................................. 34

4

5

ADDRESSING MODE...................................................................................................... 35

OVERVIEW................................................................................................................................. 35

IMMEDIATE ADDRESSING MODE........................................................................................ 35

DIRECTLY ADDRESSING MODE.......................................................................................... 35

INDIRECTLY ADDRESSING MODE....................................................................................... 35

TO ACCESS DATA in RAM BANK 0....................................................................................... 36

SYSTEM REGISTER....................................................................................................... 37

OVERVIEW................................................................................................................................. 37

SYSTEM REGISTER ARRANGEMENT (BANK 0)..................................................................... 37

BYTES of SYSTEM REGISTER.............................................................................................. 37

BITS of SYSTEM REGISTER ................................................................................................. 38

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POWER ON RESET ........................................................................................................ 39

Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

OVERVIEW................................................................................................................................. 39

EXTERNAL RESET DESCRIPTION........................................................................................... 40

7

OSCILLATORS................................................................................................................ 42

OVERVIEW................................................................................................................................. 42

CLOCK BLOCK DIAGRAM..................................................................................................... 42

OSCM REGISTER DESCRIPTION......................................................................................... 43

EXTERNAL HIGH-SPEED OSCILLATOR............................................................................... 44

OSCILLATOR MODE CODE OPTION.................................................................................... 44

OSCILLATOR DEVIDE BY 2 CODE OPTION......................................................................... 44

OSCILLATOR SAFE GUARD CODE OPTION ....................................................................... 44

SYSTEM OSCILLATOR CIRCUITS........................................................................................ 45

External RC Oscillator Frequency Measurement .................................................................... 46

INTERNAL LOW-SPEED OSCILLATOR.................................................................................... 47

SYSTEM MODE DESCRIPTION................................................................................................ 48

OVERVIEW............................................................................................................................. 48

NORMAL MODE.....................................................................................................................48

SLOW MODE.......................................................................................................................... 48

GREEN MODE........................................................................................................................ 48

POWER DOWN MODE........................................................................................................... 48

SYSTEM MODE CONTROL....................................................................................................... 49

SYSTEM MODE BLOCK DIAGRAM....................................................................................... 49

SYSTEM MODE SWITCHING ................................................................................................ 50

WAKEUP TIME........................................................................................................................... 51

OVERVIEW............................................................................................................................. 51

HARDWARE WAKEUP........................................................................................................... 51

EXTERNAL WAKEUP TRIGGER CONTROL......................................................................... 52

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TIMERS COUNTERS....................................................................................................... 53

WATCHDOG TIMER (WDT)....................................................................................................... 53

T0M REGISTER............................................................................................................................. 54

TIMER COUNTER 0 (TC0)......................................................................................................... 55

OVERVIEW............................................................................................................................. 55

TC0M MODE REGISTER........................................................................................................ 56

Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

TC0C COUNTING REGISTER................................................................................................ 57

TC0 Overflow Time ................................................................................................................. 57

TC0R AUTO-LOAD REGISTER.............................................................................................. 60

TC0 TIMER COUNTER OPERATION SEQUENCE................................................................ 61

TC0 CLOCK FREQUENCY OUTPUT (BUZZER) ................................................................... 63

TC0OUT FREQUENCY TABLE.................................................................................................. 64

TIMER COUNTER 1 (TC1)......................................................................................................... 66

OVERVIEW............................................................................................................................. 66

TC1M MODE REGISTER........................................................................................................ 67

TC1C COUNTING REGISTER................................................................................................ 68

TC1 Overflow Time ................................................................................................................. 68

TC1R AUTO-LOAD REGISTER.............................................................................................. 71

TC1 TIMER COUNTER OPERATION SEQUENCE................................................................ 72

TC1 CLOCK FREQUENCY OUTPUT (BUZZER) ................................................................... 74

PWM FUNCTION DESCRIPTION.............................................................................................. 75

OVERVIEW............................................................................................................................. 75

PWM PROGRAM DESCRIPTION........................................................................................... 78

9

INTERRUPT..................................................................................................................... 79

OVERVIEW................................................................................................................................. 79

INTEN INTERRUPT ENABLE REGISTER ................................................................................. 80

INTRQ INTERRUPT REQUEST REGISTER.............................................................................. 80

INTERRUPT OPERATION DESCRIPTION................................................................................ 81

GIE GLOBAL INTERRUPT OPERATION ............................................................................... 81

INT0 (P0.0) INTERRUPT OPERATION .................................................................................. 82

TC0 INTERRUPT OPERATION.............................................................................................. 83

TC1 INTERRUPT OPERATION.............................................................................................. 84

MULTI-INTERRUPT OPERATION.......................................................................................... 85

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OVERVIEW................................................................................................................................. 87

I/O PORT FUNCTION TABLE .................................................................................................... 88

PULL-UP RESISTERS................................................................................................................ 89

I/O PORT DATA REGISTER ...................................................................................................... 92

I/O PORT............................................................................................................... 87

Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

1

OVERVIEW................................................................................................................................. 94

ADM REGISTER......................................................................................................................... 95

ADR REGISTERS....................................................................................................................... 95

ADB REGISTERS....................................................................................................................... 96

P4CON REGISTERS.................................................................................................................. 97

ADC CONVERTING TIME.......................................................................................................... 98

ADC CIRCUIT............................................................................................................................. 99

2

TEMPLATE CODE.................................................................................................................... 100

PROGRAM CHECK LIST ......................................................................................................... 104

4-CHANNEL ANALOG TO DIGITAL CONVERTER............................................. 94

CODING ISSUE .................................................................................................. 100

1

3

4

ABSOLUTE MAXIMUM RATING.............................................................................................. 106

STANDARD ELECTRICAL CHARACTERISTIC....................................................................... 106

5

P-DIP18 PIN ............................................................................................................................. 107

SOP18 PIN ............................................................................................................................... 108

P-DIP 20 PIN ............................................................................................................................ 109

INSTRUCTION SET TABLE ............................................................................... 105

ELECTRICAL CHARACTERISTIC..................................................................... 106

PACKAGE INFORMATION ................................................................................ 107

SOP 20 PIN .............................................................................................................................. 110

SSOP20 PIN............................................................................................................................. 111

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

1

PRODUCT OVERVIEW

GENERAL DESCRIPTION

The SN8P1702A/SN8P1703A is a series of 8-bit micro-controller. This chip is utilized with CMOS technology fabrication and featured with low power consumption and high performance by its unique electronic structure.

This chip is designed with the excellent IC structure including the large program memory OTP ROM, the massive data memory RAM, two 8-bit timer counters (TC0, TC1), a watchdog timer, three interrupt sources (TC0, TC1, INT0), an 4-channel ADC converter with 8-bit/12-bit resolution, two channels high speed PWM output (PWM0, PWM1), two channels buzzer output (BZ0, BZ1) and 8-level stack buffers.

Besides, the user can choose desired oscillator configurations for the controller. There are four oscillator configurations to select for generating system clock, including High/Low Speed crystal, ceramic resonator or cost-saving RC. This series also includes an internal RC oscillator for slow mode controlled by programming.

FEATURES SELECTION TABLE

CHIP ROM RAM Stack

Timer PWM Wakeup

T0 TC0 TC1

I/O AVref ADC

Buzzer Pin no.

Package

SN8P1702A 1K*16 128 - V V 12 - 4ch 2 3 SN8P1703A 1K*16 128

8

- V V 13 V 4ch 2 3

Table 1-1. Selection Table of SN8P1702A/SN8P1703A

DIP18/SOP18/SSOP20 DIP20/SOP20/SSOP20

MASK/OTP Relative Table

MASK Part Number Package Form SN8A1702A DIP18/SOP18 /SSOP20 SN8P1702A CHIP SN8P1702A SN8A1702B DIP18/SOP18 /SSOP20 SN8P1702A CHIP SN8P1702AOTP SN8A1703A DIP20/SOP20 /SSOP20 SN8P1703A CHIP SN8P1703A

OTP Chip for Verification

Assembler Declaration

ADC GRADE TABLE

CHIP PARAMETER MIN MAX UNITS

SN8P1702A SN8P1703A

Differential No linearity (DNL) 16 LSB

SN8P1702A-12 SN8P1703A-12

Differential No linearity (DNL) 4 LSB

Resolution 12 Bits

No Mission Code 8 12 Bits

Resolution 12 Bits

No Mission Code 10 12 Bits

Table 1-2. ADC Grade Table

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

UPGRADE FROM SN8P1702 (Old version OTP)

Chip SN8P1702 SN8P1702A SN8P1702A SN8P1703A

Assembly Declaration CHIP SN8P1702 CHIP SN8P1702A CHIP SN8P1702AOTP CHIP SN8P1703A

Standby current (3V) 3uA < 1uA < 1uA < 1uA 4MHz Operating (3V) 1.5mA < 1mA < 1mA < 1mA 4MHz Operating (5V) 7mA < 3mA < 3mA < 3mA

Green Mode - Yes Yes Yes

P0.0 Interrupt Edge Falling Falling/Rising/Both Falling/Rising/Both Falling/Rising/Both

P1 wake up Low Level Level change Level change Level change

AVREFH NO Only SSOP20 Only SSOP20 Yes

ADC Channel 4 4 4 4

P4CON register - - Yes Yes

RAM size 64 64 128 128

GPIO 12 12 12 13 TC1 Timer - - Yes Yes Fast PWM - - Yes Yes

Pull-up Resistor By Port By Port By Pin By Pin Pull-up Register @SET_PUR @SET_PUR PnUR PnUR

SN8P1702 Pin

Compatible

WDT clock source High Clock High Clock

Internal RC always ON and WDT clock source fixed at internal RC

Power On Delay

at 4MHz/3V

MASK Type SN8A1702A SN8A1702A SN8A1702B SN8A1703A

Package

 Notice: The SN8P1702 is not recommended for the new design.

Yes Yes Yes No

High Clock Internal RC

- - Yes Yes

~70ms ~200ms ~200ms ~200ms

PDIP18/SOP18 PDIP18/SOP18/SSOP20 PDIP18/SOP18/SSOP20 PDIP20/SOP20/SSOP20

High Clock Internal RC

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

SN8P1702A/SN8P1703A FEATURES

Memory configuration

♦

OTP ROM size: 1K * 16 bits. Two internal interrupts: TC0, TC1

RAM size: 128 * 8 bits. One external interrupts: INT0.

I/O pin configuration

♦ Input only: P0 Bi-directional: P1, P4, P5 Wakeup: P0, P1 Pull-up resisters: P0, P1, P4, P5 External interrupt: P0 P4 pins shared with ADC inputs. External high clock: RC type up to 10 MHz External high clock: Crystal type up to 16 MHz

Two 8-bit timer counters. (TC0, TC1).

♦

On chip watchdog timer.

♦

Eight levels stack buffer.

♦ Sleep mode: Both high and internal low clock stop

59 powerful instructions

♦ Four clocks per instruction cycle All of instructions are one word length. Most of instructions are one cycle only. SN8P1702A -- PDIP 18 / SOP 18 / SSOP20 All ROM area lookup table function (MOVC) SN8P1703A-- PDIP 20 / SOP 20 / SSOP20

Three interrupt sources

♦

An 4-channel 12-bit ADC

♦

Two channel high speed PWM output.

♦

Two channel Buzzer output. (BZ0/BZ1)

♦

Dual clock system offers four operating modes

♦

Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and internal low cloc k active Slow mode: Internal low clock only

Green mode: Periodical wake-up by timer

Package (Chip form support)

♦

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Preliminary SN8P1702A/SN8P1703A

SYSTEM BLOCK DIAGRAM

8-bit micro-controller build-in 12-bit ADC

PORT 0

PC

OTP

IR

FLAGS

ALU

ACC

INTERRUPT CONT ROL

PO RT 1 PORT 4 PO RT 5

ROM

S YSTEM R E GIST E R

H-OSC

TIMIN G GENERATOR

RAM

Internal CLK

TIME R & COUNTER

Low Volt

Dete ctor

Watch-Dog

Timer

PWM0

PWM1

ADC

PWM0/Buzzer0

PWM1/Buzzer1

AIN0~AIN3

Figure 1-1.Simplified System Block Diagram

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Preliminary SN8P1702A/SN8P1703A

PIN ASSIGNMENT

Format Description：SN8P170XAY

Y

= P > PDIP， S > SOP，X> SSOP

SN8P1702A Pin Assignment

OTP Type:

SN8P1702AS (SOP 18PIN) / SN8P1702AP (PDIP 18PIN)

Pin compatible to the MASK version (SN8A1702AS/SN8A1702AP)

P0.0/INT0 1 U 18 VDD RST 2 17 XIN P1.1 3 16 XOUT P1.0 4 15 P5.0 VSS 5 14 P5.1 P4.3/AIN3 6 13 P5.2 P4.2/AIN2 7 12 P5.3/BZ1/PWM1 P4.1/AIN1 8 11 P5.4/BZ0/PWM0 P4.0/AIN0 9 10 VDD

SN8P1702AP SN8P1702AS

SN8P1702AX (SSOP 20PIN)

Pin compatible to the MASK version (SN8A1702AX)

VSS 1 U 20 P1.0 VSS 2 19 P1.1 P4.3/AIN2 3 18 RST P4.2/AIN1 4 17 P0.0/INT0 P4.1/AIN1 5 16 VDD P4.0/AIN0 6 15 XIN AVREFH 7 14 XOUT VDD 8 13 P5.0 P5.3/BZ1/PWM1 9 12 P5.1 P5.2 10 11 P5.4/BZ0/PWM0

SN8P1702AX

OLD Version OTP Type:

SN8P1702S (SOP 18PIN) / SN8P1702P (PDIP 18PIN)

P0.0/INT0 1 U 18 VDD/VPP RST 2 17 XIN P1.1 3 16 XOUT P1.0 4 15 P5.0 VSS 5 14 P5.1 P4.3/AIN3 6 13 P5.2 P4.2/AIN2 7 12 P5.3/BZ1/PWM1 P4.1/AIN1 8 11 P5.4/BZ0/PWM0 P4.0/AIN0 9 10 VDD

SN8P1702P SN8P1702S

 Notice: The SN8P1702 is not recommended for the new design.

8-bit micro-controller build-in 12-bit ADC

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Preliminary SN8P1702A/SN8P1703A

MASK Type:

SN8A1702AS (SOP 18PIN) / SN8A1702AP (PDIP 18PIN) SN8A1702BS (SOP 18PIN) / SN8A1702BP (PDIP 18PIN)

P0.0/INT0 1 U 18 VDD RST 2 17 XIN P1.1 3 16 XOUT P1.0 4 15 P5.0 VSS 5 14 P5.1 P4.3/AIN3 6 13 P5.2 P4.2/AIN2 7 12 P5.3 P4.1/AIN1 8 11 P5.4/BZ0/PWM0 P4.0/AIN0 9 10 VDD

SN8A1702AP SN8A1702AS SN8A1702BP SN8A1702BS

SN8A1702AX (SSOP 20PIN)

VSS 1 U 20 P1.0 VSS 2 19 P1.1 P4.3/AIN2 3 18 RST P4.2/AIN1 4 17 P0.0/INT0 P4.1/AIN1 5 16 VDD P4.0/AIN0 6 15 XIN AVREFH 7 14 XOUT VDD 8 13 P5.0 P5.3 9 12 P5.1 P5.2 10 11 P5.4/BZ0/PWM0

SN8A1702AX SN8A1702BX

8-bit micro-controller build-in 12-bit ADC

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

SN8P1703A Pin Assignment

OTP Type:

SN8P1703AS (SOP 20PIN) / SN8P1703AP (PDIP 20PIN) / SN8P1703AX (SSOP 20PIN)

P0.0/INT0 1 U 20 VDD RST 2 19 XIN P1.1 3 18 XOUT P1.0 4 17 P5.0 VSS 5 16 P5.1 P4.3/AIN3 6 15 P5.2 P4.2/AIN2 7 14 P5.3/BZ1/PWM1 P4.1/AIN1 8 13 P5.4/BZ0/PWM0 P4.0/AIN0 9 12 P5.5 AVREFH 10 11 VDD

SN8P1703AP SN8P1703AS SN8P1703AX

MASK Type:

SN8A1703AS (SOP 20PIN) / SN8A1703AP (PDIP 20PIN) / SN8A1703AX (SSOP 20PIN)

P0.0/INT0 1 U 20 VDD RST 2 19 XIN P1.1 3 18 XOUT P1.0 4 17 P5.0 VSS 5 16 P5.1 P4.3/AIN3 6 15 P5.2 P4.2/AIN2 7 14 P5.3/BZ1/PWM1 P4.1/AIN1 8 13 P5.4/BZ0/PWM0 P4.0/AIN0 9 12 P5.5 AVREFH 10 11 VDD

SN8A1703AP SN8A1703AS SN8A1703AX

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

PIN DESCRIPTIONS

PIN NAME TYPE DESCRIPTION

VDD, VSS P Power supply input pins for digital circuit.

RST I System reset input pin. Schmitt trigger structure, active “low”, normal stay to “high”. XIN, XOUT I, O External oscillator pins. RC mode from XIN. P0.0 / INT0 I Port 0.0 and shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up resisters.

P1.0 ~ P1.1 I/O Port 1.0~Port 1.1 bi-direction pins / Built-in pull-up resisters. P4.0 ~ P4.3 I/O Port 4.0~Port 4.3 bi-direction pins / Built-in pull-up resisters.

P5.0~P5.2, P5.5 I/O Port 5.0~Port 5.2, P5.5 bi-direction pins / Built-in pull-up resisters.

P5.3 / BZ1 / PWM1 I/O P5.4 / BZ0 / PWM0 I/O

Port 5.3 bi-direction pin, TC1÷2 signal output pin for buzzer or PWM1 output pin. Built-in pull-up resisters. Port 5.4 bi-direction pin, TC0÷2 signal output pin for buzzer or PWM0 output pin. Built-in pull-up resisters.

AVREFH I A/D converter high analog reference voltage.

AIN0 ~ AIN3 I Analog signal input pins for ADC converter.

Table 1-3. Pin Description

PIN CIRCUIT DIAGRAMS

Port1, 4, 5 structure

Port0 structure

PUR

Int. bus

PnM

Figure 1-2. Pin Circuit Diagram

 Note: All of the latch output circuits are push-pull structures.

PnM

PUR

PnM

Latch

Int. bus

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

2

CODE OPTION TABLE

Code Option Content Function Description

RC Low cost RC for external high clock oscillator

Low frequency, power saving crystal (e.g. 32.768K) for external high clock oscillator

Force Watch Dog Timer clock source come from INT 16K RC. Also INT 16K RC never stop both in power down and green mode that means Watch Dog Timer will always enable both in power down and green mode.

High_Clk

High_Clk / 2

OSG

Watch_Dog

Security

TC0_Counter

TC1_Counter

Noise Filter Low Power

INT_16K_RC

32K X’tal

12M X’tal High speed crystal /resonator (e.g. 12M) for external high clock oscillator

4M X’tal Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator

Enable External high clock divided by two, Fosc = high clock / 2

Disable Fosc = hi gh clock

Enable Enable Oscillator Safe Guard function

Disable Disable Os cillator Safe Guard function

Enable Enable Watch Dog function

Disable Disable Watch Dog function

Enable Enable ROM code Security function

Disable Disable ROM code Security function

8-bit TC0 as 8-bit counter. 6-bit TC0 as 6-bit counter. 5-bit TC0 as 5-bit counter. 4-bit TC0 as 4-bit counter. 8-bit TC1 as 8-bit counter. 6-bit TC1 as 6-bit counter. 5-bit TC1 as 5-bit counter. 4-bit TC1 as 4-bit counter.

Enable Enable Noise Filter function to enhance EMI performance

Disable Disable Noise Filter function

Enable Enable Low Power function to save Operating current

Disable Disable Low Power function

Always ON

By_CPUM Enable or Disable internal 16K(at 3V) RC clock by CPUM registe r

Table 2-1. Code Option Table of SN8P1702A/SN8P1703A

Notice:

 In high noisy environment, enable “Noise Filter”, “OSG” and disable “Low Power” is strongly

recommended.

 The side effect is to increase the lowest valid working voltage level if enable “Noise Filter” or

“OSG” or “Low Power” code option.

 Enable “Low Power” option will reduce operating current except in 32K X’tal or slow mode.

 If users select “32K X’tal” in “High_Clk” option, assembler will force “OSG” to be enabled.  If users select “RC” in “High_Clk” option, assembler will force “High_Clk / 2” to be enabled.

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

3

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

ROM Maps for SN8P1702A/SN8P1703A devices provide 1K x 16-bit program memory. The SN8P1702A/SN8P1703A program memory is able to fetch instructions through 12-bit wide PC (Program Counter) and can look up ROM data by using ROM code registers (R, X, Y, Z). In standard configuration, the device’s 1,024 x 16-bit program memory has four areas:

 1-word reset vector addresses  1-word Interrupt vector addresses  5-words reserved area  1K words (SN8P1702)

All of the program memory is partitioned into three coding areas. The first area is located from 00H to 03H(The Reset vector area), the second area is a reserved area 04H ~07H, the third area is for the interrupt vector and the user code area from 0008H to 03FEH. The address 08H is the interrupt enter address point.

0000H 0001H Jump to user start address 0002H Jump to user start address 0003H 0004H 0005H 0006H 0007H 0008H 0009H User program

.

. 000FH 0010H 0011H

.

03FEH 03FFH

General purpose area

ROM

Reset vector

Reserved

Interrupt vector

Reserved

User reset vector

Jump to user start address

User interrupt vector

End of user program

Figure 3-1. ROM Address Structure

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

USER RESET VECTOR ADDRESS (0000H)

A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory.

 Example: After power on reset, external reset active or reset by watchdog timer overflow. CHIP SN8P1702A

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0001H ~ 0007H are reserved

ORG 10H START: ; 0010H, The head of user program.

. ; User program . . .

ENDP

; End of program

INTERRUPT VECTOR ADDRESS (0008H)

A 1-word vector address area is used to execute interrupt request. If any interrupt service is executed, the program counter (PC) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory.

 Example 1: This demo program includes interrupt service routine and the user program is behind the

interrupt service routine.

CHIP SN8P1702A

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0001H ~ 0007H are reserved

ORG 8 B0XCH A, ACCBUF B0MOV A, PFLAG B0MOV PFLAGBUF, A . . . B0MOV A, PFLAGBUF B0MOV PFLAG, A B0XCH A, ACCBUF

START: ; The head of user program.

RETI

. . . . JMP START

ENDP

; Interrupt service routine ; B0XCH doesn’t change C, Z flag

; Save PFLAG register in a buffer

; Restore PFLAG register from buffer ; B0XCH doesn’t change C, Z flag ; End of interrupt service routine

; User program

; End of user program ; End of program

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 Example 2: The demo program includes interrupt service routine and the address of interrupt service

routine is in a special address of general-purpose area.

CHIP SN8P1702A

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0001H ~ 0007H are reserved

ORG 08 JMP MY_IRQ ; 0008H, Jump to interrupt service routine address

ORG 10H START: ; 0010H, The head of user program.

. ; User program . . .

MY_IRQ: ; The head of interrupt service routine B0XCH A, ACCBUF B0MOV A, PFLAG B0MOV PFLAGBUF, A . . . B0MOV A, PFLAGBUF B0MOV PFLAG, A B0XCH A, ACCBUF

 Remark: It is easy to get the rules of SONIX program from demo programs given above. These points are

as following.

1. The address 0000H is a “JMP” instruction to make the program go to general-purpose ROM area. The 0004H~0007H are reserved. Users have to skip 0004H~0007H addresses. It is very important and necessary.

2. The interrupt service starts from 0008H. Users can put the whole interrupt service routine from 0008H (Example1) or to put a “JMP” instruction in 0008H then place the interrupt service routine in other general-purpose ROM area (Example2) to get more modularized coding style.

JMP START

RETI ENDP

; End of user program

; B0XCH doesn’t change C, Z flag ; Save PFLAG register in a buffer

; Restore PFLAG register from buffer ; B0XCH doesn’t change C, Z flag ; End of interrupt service routine

; End of program

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8-bit micro-controller build-in 12-bit ADC

CHECKSUM CALCULATION

The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses (0004H~0007H and last address) when calculate the Checksum value.

 Example:

The demo program shows how to avoid 0004H~0007H when calculated Checksum from 00H to the end of

user’s code MOV A,#END_USER_CODE$L B0MOV END_ADDR1,A ; save low end address to end_addr1 MOV A,#END_USER_CODE$M B0MOV END_ADDR2,A ; Save middle end address to end_addr2 CLR Y ; Set Y to 00H CLR Z ; Set Z to 00H @@: CALL YZ_CHECK ; Call function of check yz value MOVC ; B0BSET FC ; Clear C flag ADD DATA1,A ; Add A to Data1 MOV A,R ADC DATA2,A ; Add R to Data2 JMP END_CHECK ; Check if the YZ address = the end of code AAA: INCMS Z ;Z=Z+1 JMP @B ; If Z! = 00H calculate to next address JMP Y_ADD_1 ; If Z=00H increase Y END_CHECK: MOV A,END_ADDR1 CMPRS A,Z ; Check if Z = low end address JMP AAA ; If Not jump to checksum calculate MOV A,END_ADDR2 CMPRS A,Y ; If Yes, check if Y = middle end address JMP AAA ; If Not jump to checksum calculate JMP CHECKSUM_END ; If Yes checksum calculated is done. YZ_CHECK: ;check if YZ=0004H MOV A,#04H CMPRS A,Z ;check if Z=04H RET ;if Not return to checksum calculate MOV A,#00H CMPRS A,Y ;if Yes, check if Y=00H RET ;if Not return to checksum calculate INCMS Z ;if Yes, increase 4 to Z INCMS Z INCMS Z INCMS Z RET ;set YZ=0008H then return Y_ADD_1: INCMS Y ;increase Y NOP JMP @B ;jump to checksum calculate CHECKSUM_END: ………. ………. END_USER_CODE: ;Label of program end

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8-bit micro-controller build-in 12-bit ADC

GENERAL PURPOSE PROGRAM MEMORY AREA

The 992-word at ROM locations 0010H~0FEFH are used as general-purpose memory. The area is stored instruction’s op-code and look-up table data. The SN8P1702A/SN8P1703A includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, X, Y, Z).

The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table function and look-up table function, the program counter can’t leap over the boundary by program counter automatically. Users need to modify the PCH value to “PCH+1” as the PCL overflow (from 0FFH to 000H).

LOOKUP TABLE DESCRIPTION

In the ROM’s data lookup function, the X register is pointed to the highest 8-bit, Y register to the middle 8-bit and Z register to the lowest 8-bit data of ROM address. After MOVC instruction is executed, the low-byte data of ROM then will be stored in ACC and high-byte data stored in R register.

 Example: To look up the ROM data located “TABLE1”.

B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address B0MOV Z, #TABLE1$L ; To set lookup table1’s low address. MOVC ; To lookup data, R = 00H, ACC = 35H ;

; @@: MOVC ; To lookup data, R = 51H, ACC = 05H. . . ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H ; “ DW 2012H ; “

 CAUSION: The Y register can't increase automatically if Z register cross boundary from 0xFF to 0x00.

Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflow, Y

register must be added one. The following INC_YZ macro shows a simple method to process Y and Z

registers automatically.

 Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users

can omit “B0MOV X, #TABLE1$H”. SONiX ICE support more larger program memory addressing

capability. So make sure X register is “0” to avoid unpredicted error in loop-up table operation.

INCMS Z ; Z+1 JMP @F ; Not overflow INCMS Y ; Z overflow (FFH  00),  Y=Y+1 NOP ; Not overflow

; Increment the index address for next address

 Example: INC_YZ Macro

INC_YZ MACRO INCMS Z ; Z+1 JMP @F ; Not overflow

INCMS Y ; Y+1 NOP ; Not overflow @@: ENDM

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The other coding style of loop-up table is to add Y or Z index register by accumulator. Be careful if carry happen. Refer following example for detailed information:

 Example: Increase Y and Z register by B0ADD/ADD instruction

B0MOV Y, #TABLE1$M ; To set lookup table’s middle address. B0MOV Z, #TABLE1$L ; To set lookup table’s low address

GETDATA: ; MOVC ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 . . . . ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H ; “ DW 2012H ; “

B0MOV A, BUF ; Z = Z + BUF. B0ADD Z, A

B0BTS1 FC ; Check the carry flag. JMP GETDATA ; FC = 0 INCMS Y ; FC = 1. Y+1. NOP

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JUMP TABLE DESCRIPTION

The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. The way is easy to make a multi-stage program.

When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file generated by SONIX assembly software. If the jump table leaps over the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program memory page (xx00H). Here one page mean 256 words.

 Example : If PC = 0323H (PCH = 03H、PCL = 23H)

ORG 0X0100 ; The jump table is from the head of the ROM boundary B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed.

JMP A0POINT ; ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT

In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will point to a wrong address 0x0000 and crash system operation. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H).

 Example: If “jump table” crosses over ROM boundary will cause errors.

ROM Address

. . . .

. . 0X00FD 0X00FE

0X00FF 0X0100 0X0101

. .

SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro is maybe wasting some ROM size. Notice the maximum jump table number for this macro is limited fewer than 254.

@JMP_A MACRO VAL IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) JMP ($ | 0XFF) ORG ($ | 0XFF) ENDIF ADD PCL, A ENDM

 Note: “VAL” is the number of the jump table listing number.

B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed. JMP A0POINT ; ACC = 0 JMP A1POINT ; ACC = 1 JMP A2POINT ; ACC = 2  jump table cross boundary here JMP A3POINT ; ACC = 3

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 Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.

B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A 5 ; The number of the jump table listing is five. JMP A0POINT ; If ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT JMP A4POINT ; ACC = 4, jump to A4POINT

If the jump table position is from 00FDH to 0101H, the “@JMP_A” macro will make the jump table to start from 0100h.

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DATA MEMORY (RAM)

OVERVIEW

The SN8P1702A/SN8P1703A has internally built-in the data memory up to 256 bytes for storing the general-purpose data.

 128 * 8-bit general purpose area in bank 0  128 * 8-bit system special register area

The memory is separated into bank 0 and bank 1. The user can program RAM bank selection bits of RBANK register to access all data in any of the two RAM banks. The bank 0, using the first 128-byte location assigned as general-purpose area, and the remaining 128-byte in bank 0 as system register.

BANK 0

 Note: The undefined locations of system register area are logic “high” after executing read instruction

“MOV A, M”.

000h 000h~07Fh of Bank 0 = To store general-

“ purpose data (128 bytes). “ “ “

“ 07Fh 080h 080h~0FFh of Bank 0 = To store system

“ registers (128 bytes).

“

“ 0FFh

Figure 3-2. RAM Location

RAM location

General purpose area

System register

End of bank 0 area

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WORKING REGISTERS

The locations 82H to 84H of RAM bank 0 in data memory stores the specially defined registers such as register R, Z, Y, respectively shown in the following table. These registers can use as the general purpose of working buffer and be used to access ROM’s and RAM’s data. For instance, all of the ROM’s table can be looked-up with R, Y and Z registers. The data of RAM memory can be indirectly accessed with Y and Z registers.

82H 83H 84H

RAM

R/W R/W R/W

Y, Z REGISTERS

The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. First, Y and Z registers can be used as working registers. Second, these two registers can be used as data pointers for @YZ register. Third, the registers can be address ROM location in order to look-up RO M data.

Y initial value = 0000 0000

084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Y

R/W R/W R/W R/W R/W R/W R/W R/W

Z initial value = 0000 0000

083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Z

R/W R/W R/W R/W R/W R/W R/W R/W

The @YZ that is data point_1 index buffer located at address E7H in RAM bank 0. It employs Y and Z registers to addressing RAM location in order to read/write data through ACC. The Lower 4-bit of Y register is pointed to RAM bank number and Z register is pointed to RAM address number, respectively. The higher 4-bit data of Y register is truncated in RAM indirectly access mode.

 Example: If want to read a data from RAM address 25H of bank 1, it can use indirectly addressing mode to

B0MOV Y, #01H ; To set RAM bank 1 for Y register B0MOV Z, #25H ; To set location 25H for Z register B0MOV A, @YZ ; To read a data into ACC

 Example: Clear general-purpose data memory area of bank 1 using @YZ register.

MOV A, #1 B0MOV Y, A ; Y = 1, bank 1 MOV A, #07FH B0MOV Z, A ; Y = 7FH, the last address of the data memory area CLR_YZ_BUF: CLR @YZ ; Clear @YZ to be zero

DECMS Z ; Y – 1, if Y= 0, finish the routine JMP CLR_YZ_BUF ; Not zero

CLR @YZ END_CLR: ; End of clear general purpose data memory area of bank 0

 Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about Y, Z register look-up table application.

R Z Y

YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0

ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0

access data as following.

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R REGISTERS

There are two major functions of the R register. First, R register can be used as working registers. Second, the R registers can be store high-byte data of look-up ROM data. After MOVC instruction executed, the high-byte data of a ROM address will be stored in R register and the low-byte data stored in ACC.

R initial value = 0000 0000

082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

R

R/W R/W R/W R/W R/W R/W R/W R/W

 Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.

RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0

PROGRAM FLAG

The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is carry, borrow occurrence, then these flags will be set to PFLAG register.

PFLAG initial value = xxxx x000

086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PFLAG

- - - - - R/W R/W R/W

- - - - - C DC Z

CARRY FLAG

C = 1: If executed arithmetic addition with occurring carry signal or executed arithmetic subtraction without borrowing signal or executed rotation instruction with shifting out logic “1”. C = 0: If executed arithmetic addition without occurring carry signal or executed arithmetic subtraction with borrowing signal or executed rotation instruction with shifting out logic “0”.

DECIMAL CARRY FLAG

DC = 1: If executed arithmetic addition with occurring carry signal from low nibble or executed arithmetic subtraction without borrow signal from high nibble. DC = 0: If executed arithmetic addition without occurring carry signal from low nibble or executed arithmetic subtraction with borrow signal from high nibble.

ZERO FLAG

Z = 1: After operation, the content of ACC is zero. Z = 0: After operation, the content of ACC is not zero.

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ACCUMULATOR

The ACC is an 8-bits data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.

ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing mode.

 Example: Read and write ACC value.

; Read ACC data and store in BUF data memory MOV BUF, A

. .

; Write a immediate data into ACC MOV A, #0FH

. .

; Write ACC data from BUF data memory MOV A, BUF

. .

The system doesn’t store ACC and PFLAG value as any interrupt service executed. ACC must be exchanged to another data memory defined by users. Thus, once interrupt occurs, these data must be stored in the data memory based on the user’s program as follows.

 Example: ACC and working registers protection.

ACCBUF EQU 00H ; ACCBUF is ACC data buffer in bank 0. INT_SERVICE:

B0XCH A, ACCBUF B0XCH A, ACCBUF ; Store ACC value

B0MOV A, PFLAG ; Store PFLAG value B0MOV PFLAGBUF,A

.

B0MOV A, PFLAGBUF ; Re-load PFLAG value B0MOV PFLAG,A B0XCH A, ACCBUF ; Re-load ACC

B0XCH A, ACCBUF ; Re-load ACC

RETI ; Exit interrupt service vector

 Notice: To save and re-load ACC data must be used “B0XCH” instruction, or the PLAGE value maybe

modified by ACC.

; B0XCH doesn’t change C, Z flag

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STACK OPERATIONS

OVERVIEW

The stack buffer of SN8P1702A/SN8P1703A has 8-level high area and each level is 12-bits length. This buffer is designed to save and restore program counter’s (PC) data when interrupt service is executed. The STKP register is a pointer designed to point active level in order to save or restore data from stack buffer for kernel circuit. The STKnH and STKnL are the 12-bit stack buffers to store program counter (PC) data.

STACK BUFFER

PCL

PCLPCL

STK0L

RET /

RET / RETI

RETI

CALL /

CALL / interrupt

interrupt

STKP = 7

PCH

PCHPCH

STK0H

STKP + 1

STKP - 1

STKP - 1STKP - 1

STKP = 6

STKP = 5

STKP = 4

STKP = 3

STKP = 2

STKP = 1

STKP = 0

STKP

STKPSTKP

STK1H

STK2H

STK3H

STK4H

STK5H

STK6H

STK7H

STKP

STKPSTKP

Figure 3-3 Stack-Save and Stack-Restore Operation

STK1L

STK2L

STK3L

STK4L

STK5L

STK6L

STK7L

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STACK REGISTERS

The stack pointer (STKP) is a 4-bit register to store the address used to access the stack buffer, 12-bits data memory (STKnH and STKnL) set aside for temporary storage of stack addresses.

The two stack operations are writing to the top of the stack (Stack-Save) and reading (Stack-Restore) from the top of stack. Stack-Save operation decrements the STKP and the Stack-Restore operation increments one time. That makes the STKP always points to the top address of stack buffer and writes the last program counter value (PC) into the stack buffer.

The program counter (PC) value is stored in the stack buffer before a CALL instruction executed or during interrupt service routine. Stack operation is a LIFO type (Last in and first out). The stack pointer (STKP) and stack buffer (STKnH and STKnL) are located in the system register area bank 0.

STKP (stack pointer) initial value = 0xxx 1111

0DFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKP

R/W - - - R/W R/W R/W R/W

STKPBn: Stack pointer. (n = 0 ~ 3) GIE: Global interrupt control bit. 0 = disable, 1 = enable. More detail information is in interrupt chapter.

 Example: Stack pointer (STKP) reset routine.

MOV A, #00001111B B0MOV STKP, A

STKn (stack buffer) initial value = xxxx xxxx xxxx xxxx, STKn = STKnH + STKnL (n = 7 ~ 0)

0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKnH

- - - - - - R/W R/W

0F0H~0FFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

STKnL

R/W R/W R/W R/W R/W R/W R/W R/W

STKnH: Store PCH data as interrupt or call executing. The n expressed 0 ~7. STKnL: Store PCL data as interrupt or call executing. The n expressed 0 ~7.

GIE - - - STKPB3 STKPB2 STKPB1 STKPB0

- - - - - - SnPC9 SnPC8

SnPC7 SnPC6 SnPC5 SnPC4 SnPC3 SnPC2 SnPC1 SnPC0

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STACK OPERATION EXAMPLE

The two kinds of Stack-Save operations to reference the stack pointer (STKP) and write the program counter contents (PC) into the stack buffer are CALL instruction and interrupt service. Under each condition, the STKP is decremented and points to the next available stack location. The stack buffer stores the program counter about the op-code address. The Stack-Save operation is as following table.

Stack Level

0 1 2 3 4 5 6 7

>8

STKPB3 STKPB2 STKPB1 STKPB0 High Byte Low Byte

1 1 1 1 STK0H STK0L 1 1 1 0 STK1H STK1L 1 1 0 1 STK2H STK2L 1 1 0 0 STK3H STK3L 1 0 1 1 STK4H STK4L 1 0 1 0 STK5H STK5L 1 0 0 1 STK6H STK6L 1 0 0 0 STK7H STK7L

- - - - - -

Table 3-1. STKP, STKnH and STKnL relative of Stack-Save Operation

The RETI instruction is for interrupt service routine. The RET instruction is for CALL instruction. When a Stack-Restore operation occurs, the STKP is incremented and points to the next free stack location. The stack buffer restores the last program counter (PC) to the program counter registers. The Stack-Restore operation is as following table.

Stack Level

7 6 5 4 3 2 1 0

STKPB3 STKPB2 STKPB1 STKPB0 High Byte Low Byte

1 0 0 0 STK7H STK7L 1 0 0 1 STK6H STK6L 1 0 1 0 STK5H STK5L 1 0 1 1 STK4H STK4L 1 1 0 0 STK3H STK3L 1 1 0 1 STK2H STK2L 1 1 1 0 STK1H STK1L 1 1 1 1 STK0H STK0L

STKP Register Stack Buffer

Description

-

Stack Overflow

Description

-

Table 3-2. STKP, STKnH and STKnL relative of Stack-Restore Operation

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PROGRAM COUNTER

The program counter (PC) is a 12-bit binary counter separated into the high-byte 4 bits and the low-byte 8 bits. This counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. Normally, the program counter is automatically incremented with each instruction during program exe cu tion.

Besides, it can be replaced with specific address by executing CALL or JMP instruction. When JMP or CALL instruction is executed, the destination address will be inserted to bit 0 ~ bit 11.

PC Initial value = xxxx 0000 0000 0000

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PC

PCH Initial value = xxxx 0000

PCL Initial value = 0000 0000

- - - - - - 0 0 0 0 0 0 0 0 0 0

0CFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PCH

- - - - - - R/W R/W

0CEH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PCL

R/W R/W R/W R/W R/W R/W R/W R/W

- - - - - - PC9 PC8

PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PCH PCL

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ONE ADDRESS SKIPPING

There are 9 instructions (CMPRS, INCS, INCMS, DECS, DECMS, BTS0, BTS1, B0BTS0, B0BTS1) with one address skipping function. If the result of these instructions is matched, the PC will add 2 steps to skip next instruction.

If the condition of bit test instruction is matched, the PC will add 2 steps to skip next instruction.

JMP C0STEP ; Else jump to C0STEP. . C0STEP: NOP

B0MOV A, BUF0 ; Move BUF0 value to ACC. JMP C1STEP ; Else jump to C1STEP.

. C1STEP: NOP

If the ACC is equal to the immediate data or memory, the PC will add 2 steps to skip next instruction.

JMP C0STEP ; Else jump to C0STEP. . C0STEP: NOP

If the result after increasing or decreasing by 1 is 0xFF or 0x00, the PC will add 2 steps to skip next instruction.

INCS instruction:

JMP C0STEP ; Jump to C0STEP if ACC is not zero. … C0STEP: NOP

INCMS instruction:

JMP C0STEP ; Jump to C0STEP if BUF0 is not zero. … C0STEP: NOP

DECS instruction:

JMP C0STEP ; Jump to C0STEP if ACC is not zero. … C0STEP: NOP

DECMS instruction:

JMP C0STEP ; Jump to C0STEP if BUF0 is not zero. … C0STEP: NOP

B0BTS1

B0BTS0

CMPRS

INCS

INCMS

DECS

DECMS

FC ; Skip next instruction, if Carry flag = 1

FZ ; Skip next instruction, if Zero flag = 0.

A, #12H ; Skip next instruction, if ACC = 12H.

BUF0

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MULTI-ADDRESS JUMPING

Users can jump round multi-address by either JMP instruction or ADD M, A instruction (M = PCL) to activate multi-address jumping function. If carry signal occurs after execution of ADD PCL, A, the carry signal will not affect PCH register.

 Example: If PC = 0323H (PCH = 03H、PCL = 23H)

; PC = 0323H MOV A, #28H B0MOV PCL, A ; Jump to address 0328H . . . . ; PC = 0328H . . MOV A, #00H B0MOV PCL, A ; Jump to address 0300H

 Example: If PC = 0323H (PCH = 03H、PCL = 23H)

; PC = 0323H B0ADD PCL, A ; PCL = PCL + ACC, the PCH cannot be changed. JMP A0POINT ; If ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT . . ;

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4

ADDRESSING MODE

OVERVIEW

The SN8P1702A/SN8P1703A provides three addressing modes to access RAM data, including immediate addressing mode, directly addressing mode and indirectly address mode. The main purpose of the three different modes is described in the following:

IMMEDIATE ADDRESSING MODE

The immediate addressing mode uses an immediate data to set up the location (MOV A, #I, B0MOV M,#I) in ACC or specific RAM.

Immediate addressing mode

MOV A, #12H ; To set an immediate data 12H into ACC

DIRECTLY ADDRESSING MODE

The directly addressing mode uses address number to access memory location (MOV A,12H, MOV 12H,A).

Directly addressing mode

B0MOV A, 12H ; To get a content of location 12H of bank 0 and save in ACC

INDIRECTLY ADDRESSING MODE

The indirectly addressing mode is to set up an address in data pointer registers (Y/Z) and uses MOV instruction to read/write data between ACC and @YZ register (MOV A,@YZ, MOV @YZ,A).

 Example: Indirectly addressing mode with @YZ register

CLR Y ; To clear Y register to access RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.

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TO ACCESS DATA in RAM BANK 0

In the RAM bank 0, this area memory can be read/written by these three access methods.

 Example 1: To use RAM bank0 dedicate instruction (Such as B0xxx instruction).

B0MOV A, 12H ; To move content from location 12H of RAM bank 0 to ACC

 Example 3: To use indirectly addressing mode with @YZ register.

CLR Y ; To clear Y register for accessing RAM bank 0. B0MOV Z, #12H ; To set an immediate data 12H into Z register. B0MOV A, @YZ ; Use data pointer @YZ reads a data from RAM location ; 012H into ACC.

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5

SYSTEM REGISTER

OVERVIEW

The system special register is located at 80h~FFh. The main purpose of system registers is to control the peripheral hardware of the chip. Using system registers can control I/O ports, SIO, ADC, PWM, timers and counters by programming. The Memory map provides an easy and quick reference source for writing application program. To accessing these system registers is controlled by the select memory bank (RBANK = 0) or the bank 0 read/write instruction (B0MOV, B0BSET, B0BCLR…).

SYSTEM REGISTER ARRANGEMENT (BANK 0)

BYTES of SYSTEM REGISTER

SN8P1702

0 1 2 3 4 5 6 7 8 9 A B C D E F

- - R Z Y - PFLAG - - - - - - - - -

8

- - - - - - - - - - - - - - - -

9

- - - - - - - - - - - - - - P4CON -

A

- ADM ADB ADR - - - - - - - - - - - PEDGE

B

P1W P1M - - P4M P5M - - INTRQ INTEN OSCM - - TC0R PCL PCH

C

P0 P1 - - P4 P5 - - T0M - TC0M TC0C TC1M TC0C TC1R STKP

D

P0UR P1UR - - P4UR P5UR - @YZ - - - - - - - -

E

STK7 STK7 STK6 STK6 STK5 STK5 STK4 STK4 STK3 STK3 STK2 STK2 STK1 STK1 STK0 STK0

F

Table 5-1. System Register Arrangement

Description

PFLAG = ROM page and special flag register. R = Working register and ROM lookup data buffer.

ADB = ADC’s data buffer. Y, Z = Working, @YZ and ROM addressing register. PnM = Port n input/output mode register. RBANK = RAM Bank Select register.

INTRQ = Interrupts’ request register. ADM = ADC’s mode register.

OSCM = Oscillator mode register. ADR = ADC’s resolution selects register. TC0/1M = Timer/Counter 0/1 mode register. P1W = Port 1 wakeup register. TC0/1C = Timer/Counter 0/1 counting register. Pn = Port n data buffer. TC0/1R = Timer/Counter 0/1 auto-reload data buffer. PnUR= Pull-up register

STKP = Stack pointer buffer. INTEN = Interrupts’ enable register.

@HL = RAM HL indirect addressing index pointer. PCH, PCL = Program counter.

STK0~STK7 = Stack 0 ~ stack 7 buffer. @YZ = RAM YZ indirect addressing index pointer.

 Note:

a). All of register names had been declared in SONiX 8-bit MCU assembler. b). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code. c). It will get logic “H” data, when use instruction to check empty location. d). The low nibble of ADR register is read only. e). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers.

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BITS of SYSTEM REGISTER

Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W Remarks

082H RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0 R/W R 083H ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 R/W Z 084H YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0 R/W Y

086H - - - - - C DC Z R/W PFLAG 0AEH - - - - P4CON3 P4CON2 P4CON1 P4CON0 R/W P4CON 0B1H ADENB ADS EOC GCHS - - CHS1 CHS0 R/W ADM mode reg ister 0B2H ADB11 ADB10 ADB9 ADB8 ADB7 ADB6 ADB5 ADB4 R ADB data buffer

0B3H - ADCKS1 ADLEN - ADB3 ADB2 ADB1 ADB0 R/W ADR register 0BFH PEDGEN - - P00G1 P00G0 - - - R/W PEDGE

0C0H 0 0 0 0 0 0 P11W P10W W P1W wakeup register 0C1H 0 0 0 0 0 0 P11M P10M R/W P1M I/O direction 0C4H 0 0 0 0 P43M P42M P41M P40M R/W P4M I/O direction 0C5H 0 0 P55M P54M P53M P52M P51M P50M R/W P5M I/O direction 0C8H 0 TC1IRQ TC0IRQ 0 0 0 0 P00IRQ R/W INTRQ 0C9H 0 TC1IEN TC0IEN 0 0 0 0 P00IEN R/W INTEN 0CAH WTCKS WDRST WDRATE CPUM1 CPUM0 CLKMD STPHX 0 R/W OSCM 0CDH TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0 W TC0R 0CEH PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 R/W PCL 0CFH - - - - - - PC9 PC8 R/W PCH 0D0H - - - - - - - P00 R P0 data buffer 0D1H - - - - - - P11 P10 R/W P1 data buffer 0D4H - - - - P43 P42 P41 P40 R/W P4 data buffer 0D5H - - P55 P54 P53 P52 P51 P50 R/W P5 data buffer

0D8H - - - - TC1X8 TC0X8 TC0GN - R/W

0DAH TC0ENB TC0rate2 TC0rate1 TC0rate0 TC0CKS ALOAD0 TC0OUT 0DBH TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0 R/W TC0C

0DCH TC1ENB TC1rate2 TC1rate1 TC1rate0 0 ALOAD1 TC1OUT 0DDH TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0 R/W TC1C

0DEH TC1R7 TC1R6 TC1R5 TC1R4 TC1R3 TC1R2 TC1R1 TC1R0 W TC1R 0DFH GIE - - - STKPB3 STKPB2 STKPB1 STKPB0 R/W STKP stack pointer 0E0H P00R R/W P0UR 0E1H P11R P10R R/W P1UR 0E4H P43R P42R P41R P40R R/W P4UR 0E5H P55R P54R P53R P52R P51R P50R R/W P5UR 0E7H @YZ7 @YZ6 @YZ5 @YZ4 @YZ3 @YZ2 @YZ1 @YZ0 R/W @YZ index pointer

0F0H S7PC7 S7PC6 S7PC5 S7PC4 S7PC3 S7PC2 S7PC1 S7PC0 R/W STK7L

0F1H - - - - - - S7PC9 S7PC8 R/W STK7H

0F2H S6PC7 S6PC6 S6PC5 S6PC4 S6PC3 S6PC2 S6PC1 S6PC0 R/W STK6L

0F3H - - - - - - S6PC9 S6PC8 R/W STK6H

“ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “

“ “ “ “ “ “ “ “ “ “ “ 0FCH S1PC7 S1PC6 S1PC5 S1PC4 S1PC3 S1PC2 S1PC1 S1PC0 R/W STK1L 0FDH - - - - - - S1PC9 S1PC8 R/W STK1H 0FEH S0PC7 S0PC6 S0PC5 S0PC4 S0PC3 S0PC2 S0PC1 S0PC0 R/W STK0L 0FFH - - - - - - S0PC9 S0PC8 R/W STK0H

PWM0OUT

PWM1OUT

R/W TC0M

R/W TC1M

T0M

Table 5-2. Bit System Register Table

Note: a). To avoid system error, please be sure to put all the “0” as it indicates in the above table b). All of register name had been declared in SONiX 8-bit MCU assembler. c). One-bit name had been declared in SONiX 8-bit MCU assembler with “F” prefix code. d). “b0bset”, “b0bclr”, ”bset”, ”bclr” instructions only support “R/W” registers.

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6

OVERVIEW

This series provides two system resets. One is external reset and the other is low voltage detector (LVD). The external reset is a simple RC circuit connecting to the reset pin. The low voltage detector (LVD) is built in internal circuit. When one of the reset devices occurs, the system will reset and the system registers become initial value. The timing diagram is as following.

POWER ON RESET

VDD

External Reset

LVD

LVD Detect Level

External Reset Detect Level

End of LVD Reset

Internal Reset Signal

Figure 6-1 Power on Reset Timing Diagram

End of External Reset

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EXTERNAL RESET DESCRIPTION

The external reset is a low level active device. The reset pin receives the low voltage and resets the system. When the voltage detects high level, it stops resetting the system. Users can use an external reset circuit to control system operation. It is necessary that the VDD must be stable.

VDD

External Reset

Internal Reset Signal

Figure 6-2 External Reset Timing Diagram

Users must to be sure the VDD stable earlier than external reset (Figure 5-2) or the external reset will fail. The external reset circuit is a simple RC circuit as following.

R

20K ohm

C

0.1uF

External Reset Detect Level

End of External ResetSystem Reset

VDD RST

MCU

VSS

VCC

GND

Figure 6-3. External Reset Circuit

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8-bit micro-controller build-in 12-bit ADC

In worse power, condition as brown out reset. The reset pin may keep high level but the VDD is low voltage. That makes the system reset fail and chip error. To connect a diode from reset pin to VDD is a good solution. The circuit can force the capacitor to release electric charge and drop the voltage, and solve the error.

DIODE

R 20K ohm

C

0.1uF

VDD

RST

MCU

VSS

VCC

GND

Figure 6-4. External Reset Circuit with Diode

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7

OSCILLATORS

OVERVIEW

The SN8P1702A/SN8P1703A highly performs the dual clock micro-controller system. The dual clocks are high-speed clock and low-speed clock. The high-speed clock frequency is supplied through the external oscillator circuit. The low-speed clock frequency is supplied through on-chip RC oscillator circuit.

The external high-speed clock and the internal low-speed clock can be system clock (Fosc). And the system clock is divided by 4 to be the instruction cycle (Fcpu).

Fcpu = Fosc / 4

The system clock is required by the following peripheral modules:

 Timer counter 0 (TC0/TC1)  Watchdog timer  AD converter  PWM output (PWM0/PWM1)  Buzzer output (TC0OUT/TC1OUT)

CLOCK BLOCK DIAGRAM

HXRC(1:0) is code option

•00= RC

•01 =32 Khz Oscillator

•10 = High Speed Oscillator (>10Mhz)

XIN

XOUT

•10 = High Speed Oscillator (>10Mhz)

•11 = Standard Oscillator (4Mhz)

•11 = Standard Oscillator (4Mhz) STPHX HXRC

STPHX HXRC

HXOSC.

CPUM0

LXOSC.

fh

OSG : Oscillator Safe Guard

1 : Disable --System Default

fl

0 : Enable

Divided by 2

1 : Disable

1 : Disable 0 : Enable

0 : Enable

Divided by 2OSG

Divided by 2Divided by 2OSGOSG

CLKMD

Divided by 4

Divided by 4Divided by 4

fosc/4 CPUM0

fcpu

CPUM0

Figure 7-1. Clock Block Diagram

 HXOSC: External high-speed clock.  LXOSC: Internal low-speed clock.  OSG: Oscillator safe guard.

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OSCM REGISTER DESCRIPTION

The OSCM register is a oscillator control register. It can control oscillator select, system mode, watchdog timer clock source and rate.

OSCM initial value = 000x 000x

0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCM

R/W R/W R/W R/W R/W R/W R/W -

Bit1 STPHX: External high-speed oscillator control bit.

 Note: This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC

Bit2 CLKMD: System high/Low speed mode select bit.

Bit[4:3] CPUM[1:0]: CPU operating mode control bit.

Bit5 Wdrate: Watchdog timer rate select bit.

Bit6 WDRST: Watchdog timer reset bit.

Bit7 WTCKS: Watchdog clock source select bit.

WTCKS WDRST Wdrate CPUM1 CPUM0 CLKMD STPHX 0

0 = free run, 1 = stop.

oscillator is still running.

0 = normal (dual) mode, 1 = slow mode.

00 = normal, 01 = sleep (power down) mode, 10 = green mode, 11 = reserved.

0 = Fcpu ÷ 2 1 = Fcpu ÷ 2 (The detail information is in watchdog timer chapter.)

0 = Non reset, 1 = clear the watchdog timer’s counter. (The detail information is in watchdog timer chapter.)

0 = Fcpu, 1 = internal RC low clock.

14 8

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EXTERNAL HIGH-SPEED OSCILLATOR

This series can be operated in four different oscillator modes. There are external RC oscillator modes, high crystal/resonator mode (12M code option), standard crystal/resonator mode (4M code option) and low crystal mode (32K code option). For different application, the users can select one of satiable oscillator mode by programming code option to generate system high-speed clock source after reset.

 Example: Stop external high-speed oscillator.

B0BSET FSTPHX ; To stop external high-speed oscillator only.

B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode).

OSCILLATOR MODE CODE OPTION

This series has four oscillator modes for different applications. These modes are 4M, 12M, 32K and RC. The main purpose is to support different oscillator types and frequencies. High-speed crystal needs more current but the low one doesn’t. For crystals, there are three steps to select. If the oscillator is RC type, to select “RC” and the system will divide the frequency by 2 automatically. User can select oscillator mode from Code Option table before compiling. The table is as follow.

Code Option Oscillator Mode Remark

00 01 10 11

RC mode Output the Fcpu square wave from Xout pin.

32K 32768Hz

12M 12MHz ~ 16MHz

4M 3.58MHz

OSCILLATOR DEVIDE BY 2 CODE OPTION

This series has an external clock divide by 2 function. It is a code option called “High_Clk / 2”. If “High_Clk / 2” is enabled, the external clock frequency is divided by 8 for the Fcpu. Fcpu is equal to Fosc/8. If “High_Clk / 2” is disabled, the external clock frequency is divided by 4 for the Fcpu. The Fcpu is equal to Fosc/4.

 Note: In RC mode, “High_Clk / 2” is always enabled.

OSCILLATOR SAFE GUARD CODE OPTION

This series builds in an oscillator safe guard (OSG) to make oscillator more stable. It is a low-pass filter circuit and stops high frequency noise into system from external oscillator circuit. This function makes system to work better under AC noisy conditions.

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SYSTEM OSCILLATOR CIRCUITS

8-bit micro-controller build-in 12-bit ADC

20PF

CRYSTAL

20PF

Figure 7-2. Crystal/Ceramic Oscillator

R

C

Figure 7-3. RC Oscillator

VDD XIN XOUT VSS

MCU

External Clock Input

Figure 7-4. External clock input

 Note1: The VDD and VSS of external oscillator circuit must be from the micro-controller. Don’t connect

them from the neighbor power terminal.

  Note2: The external clock input mode can select RC type oscillator or crystal type oscillator of the code

option and input the external clock into XIN pin.

  Note3: In RC type oscillator code option situation, the external clock’s frequency is divided by 2.   Note4: The power and ground of external oscillator circuit must be connected from the micro-controller’s

VDD and VSS. It is necessary to step up the performance of the whole system.

VDD XIN XOUT VSS

MCU

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External RC Oscillator Frequency Measurement

There are two ways to get the Fosc frequency of external RC oscillator. One measures the XOUT output waveform. Under external RC oscillator mode, the XOUT outputs the square waveform whose frequency is Fcpu. The other measures the external RC frequency by instruction cycle (Fcpu). The external RC frequency is the Fcpu multiplied by 4. We can get the Fosc frequency of external RC from the Fcpu frequency. The sub-routine to get Fcpu frequency of external oscillator is as the following.



Example: Fcpu instruction cycle of external oscillator

B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle

signal.

@@: B0BSET P1.0 ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P1.0 ; Measure the Fcpu frequency by oscilloscope. JMP @B

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INTERNAL LOW-SPEED OSCILLATOR

The internal low-speed oscillator is built in the micro-controller. The low-speed clock’s source is a RC type oscillator circuit. The low-speed clock can supplies clock for system clock, timer counter, watchdog timer, SIO clock source and so on.

 Example: Stop internal low-speed oscillator.

B0BSET FCPUM0 ; To stop external high-speed oscillator and internal low-speed ; oscillator called power down mode (sleep mode).

 Note: The internal low-speed clock can’t be turned off individually. It is controlled by CPUM0 bit of OSCM

register.

The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 16KHz at 3V and 32KHz at 5V. The relative between the RC frequency and voltage is as following.

Internal RC vs. VDD

40 35 30 25 20 15 10

Fintrc (KHz)

5 0

1.80 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 6.00 6.50

7.329

25.338

22.003

18.668

15.333

11.998

8.663

32.008

28.673

VDD (Volts)

Figure 7-5. Internal RC vs. VDD Diagram

 Example: To measure the internal RC frequency is by instruction cycle (Fcpu). The internal RC frequency is

the Fcpu multiplied by 4. Therefore, we can get the Fosc frequency of internal RC from the Fcpu frequency.

B0BSET P1M.0 ; Set P1.0 to be output mode for outputting Fcpu toggle signal. B0BSET FCLKMD ; Switch the system clock to internal low-speed clock mode.

@@: B0BSET P1.0 ; Output Fcpu toggle signal in low-speed clock mode. B0BCLR P1.0 ; Measure the Fcpu frequency by oscilloscope. JMP @B

38.678

35.343

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SYSTEM MODE DESCRIPTION

OVERVIEW

The chip is featured with low power consumption by switching around three different modes as followi ng.

 High-speed mode  Low-speed mode  Power-down mode (Sleep mode)  Green mode

In actual application, the user can adjust the chip’s controller to work in these three modes by using OSCM register. At the high-speed mode, the instruction cycle (Fcpu) is Fosc/4. At the low-speed mode and 3V, the Fcpu is 16KHz/4.

NORMAL MODE

In normal mode, the system clock source is external high-speed clock. After power on, the system works under normal mode. The instruction cycle is fosc/4. When the external high-speed oscillator is 3.58MHz, the instruction cycle is

3.58MHz/4 = 895KHz. All software and hardware are executed and working. In normal mode, system can get into power down mode and slow mode.

SLOW MODE

In slow mode, the system clock source is internal low-speed RC clock. To set CLKMD = 1, the system switch to slow mode. In slow mode, the system works as normal mode but the slower clock. The system in slow mode can get into normal mode and power down mode. To set STPHX = 1 to stop the external high-speed oscillator, and then the system consumes less power.

GREEN MODE

The green mode is a less power consumption mode. Under green mode, there are only TC0 still counting and the other hardware stopping. The external high-speed oscillator or internal low-speed oscillator is operating. To set CPUM1 = 1 and CPUM0 = 0, the system gets into green mode. To set TC0GN = 1 (bit 1 of T0M) will enable TC0 green mode wakeup function. The system can be waked up to last system mode by TC0 timer timeout and P0 trigger signal.

The green mode provides a time-variable wakeup function. Users can decide wakeup time by setting TC0 timer. There are two channels into green mode. One is normal mode and the other is slow mode. In normal mode, the TC0 timer overflow time is very short. In slow mode, the overflow time is longer. Users can select appropriate situation for their applications. Under green mode, the power consumption is 5u amp in 3V condition.

POWER DOWN MODE

The power down mode is also called sleep mode. The chip stops working as sleeping status. The power consumption is very less almost to zero. The power down mode is usually applied to low power consuming system as battery power productions. To set CUPM0 = 1, the system gets into power down mode. The external high-speed and low-speed oscillators are turned off. The system can be waked up by P0, P1 trigger signal.

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SYSTEM MODE CONTROL

SYSTEM MODE BLOCK DIAGRAM

P0, P1 wake-up function active.

P0, P1 wake-up function active. External reset circuit active.

External reset circuit active.

Normal Mode

P0, P1 wake-up function active.

P0, P1 wake-up function active. TC0 time out.

TC0 time out. External reset circuit active.

External reset circuit active.

Power Down Mode

(Sleep Mode)

CPUM1, CPUM0 = 01

CLKMD = 1

CLKMD = 0

CPUM1, CPUM0 = 10

Green Mode

8-bit micro-controller build-in 12-bit ADC

Slow Mode

P0, P1 wake-up function active.

P0, P1 wake-up function active. TC0 time out.

TC0 time out.

External reset circuit active.

Figure 7-6. System Mode Block Diagram

Operating mode description

MODE NORMAL SLOW GREEN

POWER DOWN

(SLEEP)

REMARK

HX osc. Running By STPHX By STPHX Stop

LX osc. Running Running Running Stop

CPU instruction Executing Executing Stop Stop

TC0 timer *Active *Active *Active Inactive

* Active by

program

Watchdog timer Active Active By INT_16K_RC By INT_16K_RC

Internal interrupt External interrupt

Wakeup source - -

All active All active TC0 All inactive All active All active All active All inactive

P0, P1, TC0

Reset

P0, P1, Reset

Table 7-1. Operating Mode Description

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SYSTEM MODE SWITCHING

Switch normal/slow mode to power down (sleep) mode. CPUM0 = 1

B0BSET FCPUM0 ; Set CPUM0 = 1. During the sleep, only the wakeup pin and reset can wakeup the system back to the normal mode.

Switch normal mode to slow mode.

B0BSET FCLKMD ;To set CLKMD = 1, Change the system into slow mode B0BSET FSTPHX ;To stop external high-speed oscillator for power saving.

 Note: To stop high-speed oscillator is not necessary and user can omit it.

Switch slow mode to normal mode (The external high-speed oscillator is still running)

B0BCLR FCLKMD ;To set CLKMD = 0 Switch slow mode to normal mode (The external high-speed oscillator stops)

If external high clock stop and program want to switch back normal mode. It is necessary to delay at least 10mS for external clock stable.

B0BCLR FSTPHX ; Turn on the external high-speed oscillator. B0MOV Z, #27 ; If VDD = 5V, internal RC=32KHz (typical) will delay

@@: DECMS Z ; 0.125ms X 81 = 10.125ms for external clock stable JMP @B ; B0BCLR FCLKMD ; Change the system back to the normal mode

 Example: Go into Green mode and enable TC0 wakeup function.

; Set TC0 timer wakeup function. B0BCLR FTC0IEN ; To disable TC0 interrupt service B0BCLR FTC0ENB ; To disable TC0 timer MOV A,#20H ; B0MOV TC0M,A ; To set TC0 clock = Fcpu / 64 MOV A,#74H B0MOV TC0C,A ; To set TC0C initial value = 74H (To set TC0 interval = 10

B0BCLR FTC0IEN ; To disable TC0 interrupt service B0BCLR FTC0IRQ ; To clear TC0 interrupt request B0BSET FTC0ENB ; To enable TC0 timer B0BSET FTC0GN ; To enable TC0 wakeup function ; Go into green mode B0BCLR FCPUM0 ;To set CPUMx = 10 B0BSET FCPUM1

 Note: If TC0ENB = 0 or TC0GN = 0, TC0 will not wakeup from green mode to normal/slow mode function.

ms)

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WAKEUP TIME

OVERVIEW

The external high-speed oscillator needs a delay time from stopping to operating. The delay is very necessary and makes the oscillator to work stably. Some conditions during system operating, the external high-speed oscillator often runs and stops. Under these conditions, the delay time for external high-speed oscillator restart is called wakeup time.

There are two conditions need wakeup time. One is power down mode to normal mode. The other one is slow mode to normal mode. For the first case, SN8P1702A/SN8P1703A provides 2048 oscillator clocks to be the wakeup time. But in the last case, users need to make the wakeup time by themselves.

HARDWARE WAKEUP

When the system is in power down mode (sleep mode), the external high-speed oscillator stops. When waked up from power down mode, MCU waits for 2048 external high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode. The value of the wakeup time is as the followi ng.

The Wakeup time = 1/Fosc * 2048 (sec) + X’tal settling time

The x’tal settling time is depended on the x’tal type. Typically, it is about 2~4mS.

 Example: In power down mode (sleep mode), the system is waked up by P0 or P1 trigger signal. After the

wakeup time, the system goes into normal mode. The wakeup time of P0, P1 wakeup function is as the following.

The wakeup time = 1/Fosc * 2048 = 0.57 ms (Fosc = 3.58MHz)

The total wakeup time = 0.57ms + x’tal settling time

Under power down mode (sleep mode), there are only I/O ports with wakeup function wake the system up to normal mode. The Port 0 and Port 1 have wakeup function. Port 0 wakeup function always enables, but the Port 1 is controlled by the P1W register.

P1W initial value = xxxx xx00

0C0H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

P1W

- - - - - - W W

Bit[1:0] P11W,P10W:Port 1 wakeup function control bits.

0 = Disable each pin of Port1 wakeup function, 1 = Enable each pin of Port 1 wakeup function

0 0 0 0 0 0 P11W P10W

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EXTERNAL WAKEUP TRIGGER CONTROL

In the SN8P1702A/SN8P1703A, the wakeup trigger direction is control by PEDGE register.

PEDGE initial value = 0xx0 0xxx

0BFH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PEDGE

R/W - - R/W R/W - - -

Bit7 PEDGEN: Interrupt and wakeup trigger edge control bit.

Bit[4:3] P00G[1:0]: Port 0.0 edge select bits.

PEDGEN - - P00G1 P00G0 - - -

0 = Disable edge trigger function.

Port 0: Low-level wakeup trigger and falling edge interrupt trigger. Port 1: Low-level wakeup trigger.

1 = Enable edge trigger function.

P0.0: Wakeup and interrupt trigger is controlled by P00G1 and P00G0 bits. Port 1: Level change (falling or rising edge) wakeup trigger.

00 = reserved, 01 = rising edge, 10 = falling edge, 11 = rising/falling bi-direction.

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8

TIMERS COUNTERS

WATCHDOG TIMER (WDT)

The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program gets in the unknown status by noise interference, The WDT’s overflow signal will reset this chip and restart operation. The instruction that clear the watch-dog timer (B0BSET FWDRST) should be executed at proper points in a program within a given period. If an instruction that clears the watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. In order to generate different output timings, the user can control watchdog timer by modifying the Wdrate control bits of OSCM register. The watchdog timer will be disabled at green and power down modes.

OSCM initial value = 0000 000x

0CAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCM

R/W R/W R/W R/W R/W R/W R/W -

Bit1 STPHX: External high-speed oscillator control bit.

Bit2 CLKMD: System high/Low speed mode select bit.

Bit[4:3] CPUM[1:0]: CPU operating mode control bit.

Bit5 Wdrate: Watchdog timer rate select bit.

Bit6 WDRST: Watchdog timer reset bit.

Bit7 WTCKS: Watchdog clock source select bit.

WTCKS WDRST Wdrate CPUM1 CPUM0 CLKMD STPHX -

0 = free run, 1 = stop.

Note: This bit only controls external high-speed oscillator. If STPHX=1, the internal low-speed RC oscillator is still running.

0 = normal (dual) mode, 1 = slow mode.

00 = normal, 01 = sleep (power down) mode, 10 = green mode, 11 = reserved.

0 = Fcpu ÷ 2 1 = Fcpu ÷ 2

0 = Non reset, 1 = clear the watchdog timer’s counter. (The detail information is in watchdog timer chapter.)

0 = Fcpu, 1 = internal RC low clock.

WTCKS WTRATE CLKMD Watchdog Timer Overflow Time

14 8

0 0 0 0 1 0 0 0 1 0 1 1 1 - -

1 / ( Fcpu ÷ 2

1 / ( 16K ÷ 512 ÷ 16 ) ~ 0.5s @3V

14

÷ 16 ) = 293 ms, Fosc=3.58MHz

8

÷ 16 ) = 500 ms, Fosc=32768Hz

14

÷ 16 ) = 65.5s, Fosc=16KHz@3V

8

÷ 16 ) = 1s, Fosc=16KHz@3V

Table 8-1. Watchdog timer overflow timetable

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 Note: The watch dog timer can be enabled or disabled by the code option.

 Example: An operation of watchdog timer is as following. To clear the watchdog timer’s counter in the top

of the main routine of the program.

Main: B0BSET FWDRST ; Clear the watchdog timer’s counter. . . CALL SUB1 CALL SUB2 . . . . . . JMP MAIN

T0M Register

T0M initial value = xxxx 000x

0D8H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T0M

- - - - R/W R/W R/W -

Bit3 TC1X8: Multiple TC1 timer speed eight times. Refer TC1M register for detailed information.

0 = Disable 1 = Enable

Bit2 TC0X8: Multiple TC0 timer speed eight times. Refer TC0M register for detailed information.

0 = Disable 1 = Enable

Bit0 TC0GN: Enable TC0 green mode wakeup function

0 = Disable 1 = Enable

- - - - TC1X8 TC0X8 TC0GN -

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TIMER COUNTER 0 (TC0)

OVERVIEW

The timer counter 0 (TC0) is us e d to generate an interrupt request when a specified time interval has elapsed. TC0 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC0R) into which you write the counter reference value, and an 8-bit counter register (TC0C) whose value is automatically incremented by counter logic.

TC0out

PWM0OUT

TC0 Time out

Fcpu

INT0

(schmitter trigger)

(8-TC0Rate)

÷2

TC0CKS

TC0enb

CPUM0

TC0 R reload

TC0 R reload data buffer

data buffer

load

TC0C

TC0C 8-bit bi nary count er

8-bit bi nary count er

Internal P5.4 I/O circuit

Aload0

Compare

Internal P5.4 I/O circuit

Buzzer

Aut o. reload P5.4

Buzzer

÷2

R

S

PWM

Figure 8-1. TC0 Block Diagram

The main purposes of the TC0 timer counter is as following.

 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency.  Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ0 pin (P5.4).  PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM0OUT pin (P5.4).

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TC0M MODE REGISTER

The TC0M is the timer counter mode register, which is an 8-bit read/write register. By loading different value into the TC0M register, users can modify the timer counter clock frequency dynamically when program executin g.

Eight rates for TC0 timer can be selected by TC0RATE0 ~ TC0RATE2 and TC0X8 bits of T0M register. If TC0X8=1 the TC0 will faster 8 times than TC0X8=0 (Initial value). The bit7 of TC0M named TC0ENB is the control bit to start TC0 timer.

TC0M initial value = 0000 0000

0DAH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC0M

R/W R/W R/W R/W R/W R/W R/W R/W

Bit7 TC0ENB: TC0 counter/BZ0/PWM0OUT enable bit.

Bit [6:4] TC0RATE[2:0]: TC0 clock source selection bits. TC0X8 is bit 2 of T0M register.

TC0ENB TC0RATE2 TC0RATE1 TC0RATE0 TC0CKS ALOAD0 TC0OUT PWM0OUT

0 = disable, 1 = enable.

TC0RATE [2:0]

000 Fcpu/256 = Fosc/1024 Fosc/128 001 Fcpu/128 = Fosc/512 Fosc/64

… … … 110 Fcpu/4 = Fosc/16 Fosc/2 111 Fcpu/2 = Fosc/8 Fosc

TC0 Clock Source

TC0X8 = 0 TC0X8 = 1

Note: Fcpu = Fosc / 4

Bit3 TC0CKS: TC0 clock source select bit.

0 = Fcpu, 1 = External clock comes from INT0/P0.0 pin.

Bit2 ALOAD0: TC0 auto-reload function control bit.

0 = none auto-reload, 1 = auto-reload.

Bit1 TC0OUT: TC0 time-out toggle signal output control bit.

0 = to disable TC0 signal output and to enable P5.4’s I/O function, 1 = to enable TC0’s signal output and to disable P5.4’s I/O function. (Auto-disable the PWM0OUT function.)

Bit0 PWM0OUT: TC0’s PWM output control bit.

0 = to disable the PWM output, 1 = to enable the PWM output (The TC0OUT control bit must = 0 )

 Note: When TC0CKS=1, TC0 became an external event counter. No more P0.0 interrupt request will be

raised. (P0.0IRQ will be always 0)

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TC0C COUNTING REGISTER

TC0C is an 8-bit counter register for the timer counter (TC0). TC0C must be reset whenever the TC0ENB is set “1” to start the timer counter. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to “0FFH”, it is will be cleared to “00H” in next clock and an overflow is generated. Under TC0 interrupt service request (TC0IEN) enable condition, the TC0 interrupt request flag will be set “1” and the system executes the interrupt service routine.

TC0C initial value = xxxx xxxx

0DBH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC0C

R/W R/W R/W R/W R/W R/W R/W R/W

TC0C7 TC0C6 TC0C5 TC0C4 TC0C3 TC0C2 TC0C1 TC0C0

TC0 Overflow Time

TC0 rate is determinate by TC0Rate and Code Option TC0_Counter, TC0Rate can set TC0 clock frequency and TC0_Counter set TC0 became 8-bit, 6-bit, 5-bit or 4-bit counter. The equation of TC0C initial value is as following.

TC0C initial value = N

Which N is determinate by code option: TC0_Counter

TC0_Counter N Max. TC0C value

8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15

 Note: TheTC0C must small or equal than Max. TC0 value.

 Example: To set 10ms interval time for TC0 interrupt at Fosc = 3.58MHz

TC0C value (74H) = 256 - (10ms * fcpu/64) (TC0RATE=010, TC0_Counter=8-bit, TC0X8=0)

TC0C initial value = 256 - (TC0 interrupt interval time * input clock)

 Example: To set 1.25ms interval time for TC0 interrupt at Fosc = 3.58MHz

TC0C value (74H) = 256 - (10ms * fcpu/64) (TC0RATE=010, TC0_Counter=8-bit, TC0X8=1)

TC0C initial value = 256 - (TC0 interrupt interval time * input clock)

 Example: To set 1ms interval time for TC0 interrupt at Fosc = 3.58MHz

TC0C value (32H) = 64 - (1ms * fcpu/64) (TC0RATE=010, TC0_COunter=6-bit, TC0X8=0)

TC0C initial value = 64 - (TC0 interrupt interval time * input clock)

- (TC0 interrupt interval time * input clock)

= 256 - (10ms * 3.58 * 10 = 256 - (0.01 * 3.58 * 10 = 116 = 74H

= 256 - (1.25ms * 3.58 * 10 = 256 - (0.00125 * 3.58 * 10 = 116 = 74H

= 64 - (1ms * 3.58 * 10 = 64 - (0.001 * 3.58 * 10 = 64 - 14 = 32H

6

/ 4 / 64)

6

/ 4 / 64)

6

/ 4 / 64)

6

/ 4 / 64)

/ 32)

6

/ 32)

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TC0_Counter=8-bit, TC0X8=0

TC0RATE TC0CLOCK

000 Fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 Fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 Fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 Fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 Fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 Fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 Fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 Fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms

TC0_Counter=6-bit , TC0X8=0

TC0RATE TC0CLOCK

000 Fcpu/256 18.3 ms 286us 2000 ms 31.25 ms 001 Fcpu/128 9.15 ms 143us 1000 ms 15.63 ms 010 Fcpu/64 4.57 ms 71.5us 500 ms 7.8 ms 011 Fcpu/32 2.28 ms 35.8us 250 ms 3.9 ms 100 Fcpu/16 1.14 ms 17.9us 125 ms 1.95 ms 101 Fcpu/8 0.57 ms 8.94us 62.5 ms 0.98 ms 110 Fcpu/4 0.285 ms 4.47us 31.25 ms 0.49 ms 111 Fcpu/2 0.143 ms 2.23us 15.63 ms 0.24 ms

TC0_Counter=5-bit, TC0X8=0

TC0RATE TC0CLOCK

000 Fcpu/256 9.15 ms 286us 1000 ms 31.25 ms 001 Fcpu/128 4.57 ms 143us 500 ms 15.63 ms 010 Fcpu/64 2.28 ms 71.5us 250 ms 7.8 ms 011 Fcpu/32 1.14 ms 35.8us 125 ms 3.9 ms 100 Fcpu/16 0.57 ms 17.9us 62.5 ms 1.95 ms 101 Fcpu/8 0.285 ms 8.94us 31.25 ms 0.98 ms 110 Fcpu/4 0.143 ms 4.47us 15.63 ms 0.49 ms 111 Fcpu/2 71.25 us 2.23us 7.81 ms 0.24 ms

TC0_Counter=4-bit, TC0X8=0

TC0RATE TC0CLOCK

000 Fcpu/256 4.57 ms 286us 500 ms 31.25 ms 001 Fcpu/128 2.28 ms 143us 250 ms 15.63 ms 010 Fcpu/64 1.14 ms 71.5us 125 ms 7.8 ms 011 Fcpu/32 0.57 ms 35.8us 62.5 ms 3.9 ms 100 Fcpu/16 0.285 ms 17.9us 31.25 ms 1.95 ms 101 Fcpu/8 0.143 ms 8.94us 15.63 ms 0.98 ms 110 Fcpu/4 71.25 us 4.47us 7.81 ms 0.49 ms 111 Fcpu/2 35.63 us 2.23us 3.91 ms 0.24 ms

High speed mode (Fcpu = 3.58MHz / 4) Low speed mode (Fosc = 32768Hz / 4)

Max overflow interval One step = max/256 Max overflow interval One step = max/256

High speed mode (Fcpu = 3.58MHz / 4) Low speed mode (Fcpu = 32768Hz / 4)

Max overflow interval One step = max/64 Max overflow interval One step = max/64

High speed mode (Fcpu = 3.58MHz / 4) Low speed mode (Fcpu = 32768Hz / 4)

Max overflow interval One step = max/32 Max overflow interval One step = max/32

High speed mode (Fcpu = 3.58MHz / 4) Low speed mode (Fcpu = 32768Hz / 4)

Max overflow interval One step = max/16 Max overflow interval One step = max/16

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TC0_Counter=8-bit, TC0X8=1

TC0RATE TC0CLOCK

000 Fosc/128 9.153 ms 35.754us 1000 ms 3.91 ms 001 Fosc/64 4.58 ms 17.877us 500 ms 1.95 ms 010 Fosc/32 2.29 ms 8.939us 250 ms 0.977 ms 011 Fosc/16 1.14 ms 4.470us 125 ms 0.488 ms 100 Fosc/8 0.57 ms 2.235us 62.5 ms 0.244 ms 101 Fosc/4 0.29 ms 1.117us 31.25 ms 0.122 ms 110 Fosc/2 0.14 ms 0.587us 15.63 ms 0.061 ms 111 Fosc 71.5 us 0.279us 7.81ms 0.03 ms

TC0_Counter=6-bit , TC0X8=1

TC0RATE TC0CLOCK

000 Fosc/128 2.29 ms 35.754us 250 ms 3.91 ms 001 Fosc/64 1.14 ms 17.877us 125 ms 1.95 ms 010 Fosc/32 0.57 ms 8.939us 62.5 ms 0.977 ms 011 Fosc/16 0.29 ms 4.470us 31.25 ms 0.488 ms 100 Fosc/8 0.14 ms 2.235us 15.63 ms 0.244 ms 101 Fosc/4 71.5 us 1.117us 7.81ms 0.122 ms 110 Fosc/2 35.75 us 0.587us 3.905 ms 0.061 ms 111 Fosc 17.875 us 0.279us 1.953 ms 0.03 ms

TC0_Counter=5-bit, TC0X8=1

TC0RATE TC0CLOCK

000 Fosc/128 1.14 ms 35.754us 125 ms 3.91 ms 001 Fosc/64 0.57 ms 17.877us 62.5 ms 1.95 ms 010 Fosc/32 0.29 ms 8.939us 31.25 ms 0.977 ms 011 Fosc/16 0.14 ms 4.470us 15.63 ms 0.488 ms 100 Fosc/8 71.5 us 2.235us 7.81ms 0.244 ms 101 Fosc/4 35.75 us 1.117us 3.905 ms 0.122 ms 110 Fosc/2 17.875 us 0.587us 1.953 ms 0.061 ms 111 Fosc 8.936 us 0.279us 0.976 ms 0.03 ms

TC0_Counter=4-bit, TC0X8=1

TC0RATE TC0CLOCK

000 Fosc/128 0.57 ms 35.754us 62.5 ms 3.91 ms 001 Fosc/64 0.29 ms 17.877us 31.25 ms 1.95 ms 010 Fosc/32 0.14 ms 8.939us 15.63 ms 0.977 ms 011 Fosc/16 71.5 us 4.470us 7.81ms 0.488 ms 100 Fosc/8 35.75 us 2.235us 3.905 ms 0.244 ms 101 Fosc/4 17.875 us 1.117us 1.953 ms 0.122 ms 110 Fosc/2 8.936 us 0.587us 0.976 ms 0.061 ms 111 Fosc 4.468 us 0.279us 0.488 ms 0.03 ms

High speed mode (Fosc = 3.58MHz) Low speed mode (Fosc = 32768Hz)

Max overflow interval One step = max/256 Max overflow interval One step = max/256

High speed mode (Fosc = 3.58MHz) Low speed mode (Fosc = 32768Hz)

Max overflow interval One step = max/64 Max overflow interval One step = max/64

High speed mode (Fosc = 3.58MHz) Low speed mode (Fosc = 32768Hz)

Max overflow interval One step = max/32 Max overflow interval One step = max/32

High speed mode (Fosc = 3.58MHz) Low speed mode (Fosc = 32768Hz)

Max overflow interval One step = max/16 Max overflow interval One step = max/16

Table 8-2. The Timing Table of Timer Counter TC0

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TC0R AUTO-LOAD REGISTER

TC0R is an 8-bit register for the TC0 auto-reload function. TC0R’s value applies to TC0OUT and PWM0OUT functions. Under TC0OUT application, users must enable and set the TC0R register. The main purpose of TC0R is as following.

 Store the auto-reload value and set into TC0C when the TC0C overflow. (ALOAD0 = 1).  Store the duty value of PWM0OUT function.

TC0R initial value = xxxx xxxx

0CDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC0R

W W W W W W W W

The equation of TC0R initial value is like TC0C as following.

Which N is determinate by code option: TC0_Counter

TC0_Counter N Max. TC0R value

8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15

 Note: TheTC0R must small or equal than Max. TC0R value.  Note: The TC0R is write-only register can’t be process by INCMS, DECMS instructions.

TC0R7 TC0R6 TC0R5 TC0R4 TC0R3 TC0R2 TC0R1 TC0R0

TC0R initial value = N - (TC0 interrupt interval time * input clock)

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TC0 TIMER COUNTER OPERATION SEQUENCE

The TC0 timer counter’s sequence of operation can be following.

 Set the TC0C initial value to setup the interval time.  Set the TC0ENB to be “1” to enable TC0 timer counter.  TC0C is incremented by one with each clock pulse which frequency is corresponding to TC0M selection.  TC0C overflow when TC0C from FFH to 00H.  When TC0C overflow occur, the TC0IRQ flag is set to be “1” by hardware.  Execute the interrupt service routine.  Users reset the TC0C value and resume the TC0 timer operation.

 Example: Setup the TC0M and TC0C without auto-reload function. (TC0_Counter=8-bit)

B0BCLR FTC0X8 ; B0BCLR FTC0IEN ; To disable TC0 interrupt service B0BCLR FTC0ENB ; To disable TC0 timer MOV A,#20H ; B0MOV TC0M,A ; To set TC0 clock = Fcpu / 64 MOV A,#74H ; To set TC0C initial value = 74H B0MOV TC0C,A ;(To set TC0 interval = 10 ms)

B0BSET FTC0IEN ; To enable TC0 interrupt service B0BCLR FTC0IRQ ; To clear TC0 interrupt request B0BSET FTC0ENB ; To enable TC0 timer

 Example: Setup the TC0M and TC0C with auto-reload function. (TC0_Counter=8 -bit)

B0BCLR FTC0X8 ; To select TC0=Fcpu/2 as clock source B0BCLR FTC0IEN ; To disable TC0 interrupt service B0BCLR FTC0ENB ; To disable TC0 timer MOV A,#20H ; B0MOV TC0M,A ; To set TC0 clock = Fcpu / 64 MOV A,#74H ; To set TC0C initial value = 74H B0MOV TC0C,A ; (To set TC0 interval = 10 ms) B0MOV TC0R,A ; To set TC0R auto-reload register

B0BSET FTC0IEN ; To enable TC0 interrupt service B0BCLR FTC0IRQ ; To clear TC0 interrupt request B0BSET FTC0ENB ; To enable TC0 timer B0BSET ALOAD0 ; To enable TC0 auto-reload function.

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 Example: TC0 interrupt service routine without auto-reload function. (TC0_Counter=8-bit)

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; Store ACC value. B0MOV A, PFLAG B0MOV PFLAGBUF, A

B0BTS1 FTC0IRQ ; Check TC0IRQ JMP EXIT_INT ; TC0IRQ = 0, exit interrupt vector

B0BCLR FTC0IRQ ; Reset TC0IRQ MOV A,#74H ; Reload TC0C B0MOV TC0C,A . . ; TC0 interrupt service routine . . JMP EXIT_INT ; End of TC0 interrupt service routine and exit interrupt

vector . . . . EXIT_INT: B0MOV A, PFLAGBUF B0MOV PFLAG, A B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

 Example: TC0 interrupt service routine with auto-reload. (TC0_Counter=8-bit)

ORG 8 ; Interrupt vector JMP INT_SERVICE INT_SERVICE:

B0XCH A, ACCBUF ; Store ACC value. B0MOV A, PFLAG B0MOV PFLAGBUF, A

B0BTS1 FTC0IRQ ; Check TC0IRQ JMP EXIT_INT ; TC0IRQ = 0, exit interrupt vector

B0BCLR FTC0IRQ ; Reset TC0IRQ . . ; TC0 interrupt service routine . . JMP EXIT_INT ; End of TC0 interrupt service routine and exit interrupt

vector . . . . EXIT_INT: B0MOV A, PFLAGBUF B0MOV PFLAG, A B0XCH A, ACCBUF ; Restore ACC value.

RETI ; Exit interrupt vector

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8-bit micro-controller build-in 12-bit ADC

TC0 CLOCK FREQUENCY OUTPUT (BUZZER)

TC0 timer counter provides a frequency output function. By setting the TC0 clock frequency, the clock signal is output to P5.4 and the P5.4 general purpose I/O function is auto-disable. The TC0 output signal divides by 2. The TC0 clock has many combinations and easily to make difference frequency. This function applies as buzzer output to output multi-frequency.

Figure 8-2. The TC0OUT Pulse Frequency

 Example: Setup TC0OUT output from TC0 to TC0OUT (P5.4). The external high-speed clock is 4MHz. The

TC0OUT frequency is 1KHz. Because the TC0OUT signal is divided by 2, set the TC0 clock to 2KHz. The TC0 clock source is from external oscillator clock. TC0 rate is Fcpu/4. The TC0RATE2~TC0RATE1 = 110, TC0C = TC0R = 131, TC0X8 = 0, TC0_Counter=8-bit

B0BCLR FTC0X8 ; Set TC0X8 to 0 MOV A,#01100000B B0MOV TC0M,A ; Set the TC0 rate to Fcpu/4

MOV A,#131 ; Set the auto-reload reference value B0MOV TC0C,A B0MOV TC0R,A

B0BSET FTC0OUT ; Enable TC0 output to P5.4 and disable P5.4 I/O function B0BSET FALOAD0 ; Enable TC0 auto-reload function B0BSET FTC0ENB ; Enable TC0 timer

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Preliminary SN8P1702A/SN8P1703A

TC0OUT FREQUENCY TABLE

Fosc = 4MHz, TC0 Rate = Fcpu/8, TC0_Counter=8-bit, TC0X8=0

TC0R

0 0.2441 56 0.3125 112 0.4340 168 0.7102 224 1.9531 1 0.2451 57 0.3141 113 0.4371 169 0.7184 225 2.0161 2 0.2461 58 0.3157 114 0.4401 170 0.7267 226 2.0833 3 0.2470 59 0.3173 115 0.4433 171 0.7353 227 2.1552 4 0.2480 60 0.3189 116 0.4464 172 0.7440 228 2.2321 5 0.2490 61 0.3205 117 0.4496 173 0.7530 229 2.3148 6 0.2500 62 0.3222 118 0.4529 174 0.7622 230 2.4038 7 0.2510 63 0.3238 119 0.4562 175 0.7716 231 2.5000 8 0.2520 64 0.3255 120 0.4596 176 0.7813 232 2.6042

9 0.2530 65 0.3272 121 0.4630 177 0.7911 233 2.7174 10 0.2541 66 0.3289 122 0.4664 178 0.8013 234 2.8409 11 0.2551 67 0.3307 123 0.4699 179 0.8117 235 2.9762 12 0.2561 68 0.3324 124 0.4735 180 0.8224 236 3.1250 13 0.2572 69 0.3342 125 0.4771 181 0.8333 237 3.2895 14 0.2583 70 0.3360 126 0.4808 182 0.8446 238 3.4722 15 0.2593 71 0.3378 127 0.4845 183 0.8562 239 3.6765 16 0.2604 72 0.3397 128 0.4883 184 0.8681 240 3.9063 17 0.2615 73 0.3415 129 0.4921 185 0.8803 241 4.1667 18 0.2626 74 0.3434 130 0.4960 186 0.8929 242 4.4643 19 0.2637 75 0.3453 131 0.5000 187 0.9058 243 4.8077 20 0.2648 76 0.3472 132 0.5040 188 0.9191 244 5.2083 21 0.2660 77 0.3492 133 0.5081 189 0.9328 245 5.6818 22 0.2671 78 0.3511 134 0.5123 190 0.9470 246 6.2500 23 0.2682 79 0.3531 135 0.5165 191 0.9615 247 6.9444 24 0.2694 80 0.3551 136 0.5208 192 0.9766 248 7.8125 25 0.2706 81 0.3571 137 0.5252 193 0.9921 249 8.9286 26 0.2717 82 0.3592 138 0.5297 194 1.0081 250 10.4167 27 0.2729 83 0.3613 139 0.5342 195 1.0246 251 12.5000 28 0.2741 84 0.3634 140 0.5388 196 1.0417 252 15.6250 29 0.2753 85 0.3655 141 0.5435 197 1.0593 253 20.8333 30 0.2765 86 0.3676 142 0.5482 198 1.0776 254 31.2500 31 0.2778 87 0.3698 143 0.5531 199 1.0965 255 62.5000 32 0.2790 88 0.3720 144 0.5580 200 1.1161 33 0.2803 89 0.3743 145 0.5631 201 1.1364 34 0.2815 90 0.3765 146 0.5682 202 1.1574 35 0.2828 91 0.3788 147 0.5734 203 1.1792 36 0.2841 92 0.3811 148 0.5787 204 1.2019 37 0.2854 93 0.3834 149 0.5841 205 1.2255 38 0.2867 94 0.3858 150 0.5896 206 1.2500 39 0.2880 95 0.3882 151 0.5952 207 1.2755 40 0.2894 96 0.3906 152 0.6010 208 1.3021 41 0.2907 97 0.3931 153 0.6068 209 1.3298 42 0.2921 98 0.3956 154 0.6127 210 1.3587 43 0.2934 99 0.3981 155 0.6188 211 1.3889 44 0.2948 100 0.4006 156 0.6250 212 1.4205 45 0.2962 101 0.4032 157 0.6313 213 1.4535 46 0.2976 102 0.4058 158 0.6378 214 1.4881 47 0.2990 103 0.4085 159 0.6443 215 1.5244 48 0.3005 104 0.4112 160 0.6510 216 1.5625 49 0.3019 105 0.4139 161 0.6579 217 1.6026 50 0.3034 106 0.4167 162 0.6649 218 1.6447 51 0.3049 107 0.4195 163 0.6720 219 1.6892 52 0.3064 108 0.4223 164 0.6793 220 1.7361 53 0.3079 109 0.4252 165 0.6868 221 1.7857 54 0.3094 110 0.4281 166 0.6944 222 1.8382 55 0.3109 111 0.4310 167 0.7022 223 1.8939

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

8-bit micro-controller build-in 12-bit ADC

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

Table 8-3. TC0OUT Frequency Table for Fosc = 4MHz, TC0 Rate = Fcpu/8

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Preliminary SN8P1702A/SN8P1703A

Fosc = 16MHz, TC0 Rate = Fcpu/8, TC0_Counter=8-bit

TC0R

0 0.9766 56 1.2500 112 1.7361 168 2.8409 224 7.8125

1 0.9804 57 1.2563 113 1.7483 169 2.8736 225 8.0645

2 0.9843 58 1.2626 114 1.7606 170 2.9070 226 8.3333

3 0.9881 59 1.2690 115 1.7730 171 2.9412 227 8.6207

4 0.9921 60 1.2755 116 1.7857 172 2.9762 228 8.9286

5 0.9960 61 1.2821 117 1.7986 173 3.0120 229 9.2593

6 1.0000 62 1.2887 118 1.8116 174 3.0488 230 9.6154

7 1.0040 63 1.2953 119 1.8248 175 3.0864 231 10.0000

8 1.0081 64 1.3021 120 1.8382 176 3.1250 232 10.4167

9 1.0121 65 1.3089 121 1.8519 177 3.1646 233 10.8696 10 1.0163 66 1.3158 122 1.8657 178 3.2051 234 11.3636 11 1.0204 67 1.3228 123 1.8797 179 3.2468 235 11.9048 12 1.0246 68 1.3298 124 1.8939 180 3.2895 236 12.5000 13 1.0288 69 1.3369 125 1.9084 181 3.3333 237 13.1579 14 1.0331 70 1.3441 126 1.9231 182 3.3784 238 13.8889 15 1.0373 71 1.3514 127 1.9380 183 3.4247 239 14.7059 16 1.0417 72 1.3587 128 1.9531 184 3.4722 240 15.6250 17 1.0460 73 1.3661 129 1.9685 185 3.5211 241 16.6667 18 1.0504 74 1.3736 130 1.9841 186 3.5714 242 17.8571 19 1.0549 75 1.3812 131 2.0000 187 3.6232 243 19.2308 20 1.0593 76 1.3889 132 2.0161 188 3.6765 244 20.8333 21 1.0638 77 1.3966 133 2.0325 189 3.7313 245 22.7273 22 1.0684 78 1.4045 134 2.0492 190 3.7879 246 25.0000 23 1.0730 79 1.4124 135 2.0661 191 3.8462 247 27.7778 24 1.0776 80 1.4205 136 2.0833 192 3.9063 248 31.2500 25 1.0823 81 1.4286 137 2.1008 193 3.9683 249 35.7143 26 1.0870 82 1.4368 138 2.1186 194 4.0323 250 41.6667 27 1.0917 83 1.4451 139 2.1368 195 4.0984 251 50.0000 28 1.0965 84 1.4535 140 2.1552 196 4.1667 252 62.5000 29 1.1013 85 1.4620 141 2.1739 197 4.2373 253 83.3333 30 1.1062 86 1.4706 142 2.1930 198 4.3103 254 125.0000 31 1.1111 87 1.4793 143 2.2124 199 4.3860 255 250.0000 32 1.1161 88 1.4881 144 2.2321 200 4.4643 33 1.1211 89 1.4970 145 2.2523 201 4.5455 34 1.1261 90 1.5060 146 2.2727 202 4.6296 35 1.1312 91 1.5152 147 2.2936 203 4.7170 36 1.1364 92 1.5244 148 2.3148 204 4.8077 37 1.1416 93 1.5337 149 2.3364 205 4.9020 38 1.1468 94 1.5432 150 2.3585 206 5.0000 39 1.1521 95 1.5528 151 2.3810 207 5.1020 40 1.1574 96 1.5625 152 2.4038 208 5.2083 41 1.1628 97 1.5723 153 2.4272 209 5.3191 42 1.1682 98 1.5823 154 2.4510 210 5.4348 43 1.1737 99 1.5924 155 2.4752 211 5.5556 44 1.1792 100 1.6026 156 2.5000 212 5.6818 45 1.1848 101 1.6129 157 2.5253 213 5.8140 46 1.1905 102 1.6234 158 2.5510 214 5.9524 47 1.1962 103 1.6340 159 2.5773 215 6.0976 48 1.2019 104 1.6447 160 2.6042 216 6.2500 49 1.2077 105 1.6556 161 2.6316 217 6.4103 50 1.2136 106 1.6667 162 2.6596 218 6.5789 51 1.2195 107 1.6779 163 2.6882 219 6.7568 52 1.2255 108 1.6892 164 2.7174 220 6.9444 53 1.2315 109 1.7007 165 2.7473 221 7.1429 54 1.2376 110 1.7123 166 2.7778 222 7.3529 55 1.2438 111 1.7241 167 2.8090 223 7.5758

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

TC0R

8-bit micro-controller build-in 12-bit ADC

TC0OUT

(KHz)

TC0R

TC0OUT

(KHz)

Table 8-4TC0OUT Frequency Table for Fosc = 16MHz, TC0 Rate = Fcpu/8

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

TIMER COUNTER 1 (TC1)

OVERVIEW

The timer counter 1 (TC1) is us e d to generate an interrupt request when a specified time interval has elapsed. TC1 has a auto re-loadable counter that consists of two parts: an 8-bit reload register (TC1R) into which you write the counter

TC1out

PWM1OUT

TC1enb

TC1R reload

TC1R reload da ta b u ffer

da ta b u ffer

load

Inte rn a l P 5 .3 I/O c ircu it

Aload1

Inte rn a l P 5 .3 I/O c ircu it

Buzzer

Auto. reload P5.3

Com pare

Buzzer

÷2

R

S

PWM

fcpu

÷2

(8-TC1Rate)

CPUM0

TC1C

TC1C 8-bit binary counter

8-bit binary counter

TC1 Time out

reference value, and an 8-bit counter register (TC1C) whose value is automatically incremented by counter logic.

Figure 8-3. Timer Counter TC1 Block Diagram

The main purposes of the TC1 timer is as following.

 8-bit programmable timer: Generates interrupts at specific time intervals based on the selected clock frequency.  Arbitrary frequency output (Buzzer output): Outputs selectable clock frequencies to the BZ1 pin (P5.3).  PWM function: PWM output can be generated by the PWM1OUT bit and output to PWM1OUT pin (P5.3).

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

TC1M MODE REGISTER

The TC1M is the timer mode register, which is an 8-bit read/write register. By loading different value into the TC1M register, users can modify the timer counter clock frequency dynamically when program executing.

Eight rates for TC1 timer can be selected by TC1RATE0 ~ TC1RATE2 and TC1X8 bits of T0M register. If TC1X8=1 the TC1 will faster 8 times than TC1X8=0 (Initial value). The bit7 of TC1M named TC1ENB is the control bit to start TC1 timer.

TC1M initial value = 0000 0000

0DCH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC1M

R/W R/W R/W R/W - R/W R/W R/W

Bit7 TC1ENB: TC1 counter/BZ1/PWM1OUT enable bit.

Bit[6:4] TC1RATE[2:0]: TC1 clock source selection bits. TC1X8 is bit 3 of T0M register.

Note: Fcpu = Fosc / 4 Bit2 ALOAD1: TC1 auto-reload function control bit.

Bit1 TC01UT: TC1 time-out toggle signal output control bit.

Bit0 PWM1OUT: TC1’s PWM output control bit.

 Note: TC1 doesn’t support event counter mode because SN8P1702A and SN8P1703A hasn’t P0.1 for TC1

event counter clock input.

 Note: Bit3 must set to “0”.

TC1ENB TC1RATE2 TC1RATE1 TC1RATE0 0 ALOAD1 TC1OUT PWM1OUT

0 = disable, 1 = enable.

TC1RATE [2:0]

000 Fcpu/256 = Fosc/1024 Fosc/128 001 Fcpu/128 = Fosc/512 Fosc/64

… … … 110 Fcpu/4 = Fosc/16 Fosc/2 111 Fcpu/2 = Fosc/8 Fosc

0 = none auto-reload 1 = auto-reload.

0 = to disable TC1 signal output and to enable P5.3’s I/O function, 1 = to enable TC1’s signal output and to disable P5.3’s I/O function. (Auto-disable the PWM0OUT function.)

0 = to disable the PWM output, 1 = to enable the PWM output (The TC1OUT control bit must = 0)

TC1 Clock Source

TC1X8 = 0 TC1X8 = 1

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

TC1C COUNTING REGISTER

TC1C is an 8-bit counter register for the timer counter (TC1). TC1C must be reset whenever the TC1ENB is set “1” to start the timer. TC0C is incremented by one with a clock pulse which the frequency is determined by TC0RATE0 ~ TC0RATE2. When TC0C has incremented to “0FFH”, it is will be cleared to “00H” in next clock and an overflow is generated. Under TC1 interrupt service request (TC1IEN) enable condition, the TC1 interrupt request flag will be set “1” and the system executes the interrupt service routine.

TC1C initial value = xxxx xxxx

0DDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TC1C

R/W R/W R/W R/W R/W R/W R/W R/W

TC1C7 TC1C6 TC1C5 TC1C4 TC1C3 TC1C2 TC1C1 TC1C0

TC1 Overflow Time

TC1 rate is determinate by TC1Rate and Code Option TC1_Counter, TC1Rate can set TC1 clock frequency from Fcpu and TC1_Counter set TC1 became 8-bit, 6-bit, 5-bit or 4-bit counter. The equation of TC1C initial value is as following.

TC1C initial value = N

Which N is determinate by code option: TC1_Counter

TC1_Counter N Max. TC1C value

8-bit 256 255 6-bit 64 63 5-bit 32 31 4-bit 16 15

 Note: TheTC1C must small or equal than Max. TC1 value.

 Example: To set 10ms interval time for TC1 interrupt at Fosc = 3.58MHz

TC1C value (74H) = 256 - (10ms * fcpu/64) (TC1RATE=010, TC1_Counter=8-bit, TC1X8=0)

TC1C initial value = 256 - (TC0 interrupt interval time * input clock)

 Example: To set 1.25ms interval time for TC1 interrupt at Fosc = 3.58MHz

TC1C value (74H) = 256 - (10ms * fcpu/64) (TC1RATE=010, TC1_Counter=8-bit, TC1X8=1)

TC1C initial value = 256 - (TC0 interrupt interval time * input clock)

 Example: To set 1ms interval time for TC1 interrupt at Fosc = 3.58MHz

TC1C value (32H) = 64 - (1ms * fcpu/64) (TC1RATE=010, TC1_COunter=6-bit, TC1X8=0)

TC1C initial value = 64 - (TC0 interrupt interval time * input clock)

- (TC1 interrupt interval time * input clock)

= 256 - (10ms * 3.58 * 10 = 256 - (0.01 * 3.58 * 10 = 116 = 74H

= 256 - (1.25ms * 3.58 * 10 = 256 - (0.00125 * 3.58 * 10 = 116 = 74H

= 64 - (1ms * 3.58 * 10 = 64 - (0.001 * 3.58 * 10 = 64 - 14 = 32H

6

/ 4 / 64)

6

/ 4 / 64)

6

/ 4 / 64)

6

/ 4 / 64)

/ 32)

6

/ 32)

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Preliminary SN8P1702A/SN8P1703A

8-bit micro-controller build-in 12-bit ADC

TC1_Counter=8-bit, TC1X8=0

TC1RATE TC1CLOCK

000 Fcpu/256 73.2 ms 286us 8000 ms 31.25 ms 001 Fcpu/128 36.6 ms 143us 4000 ms 15.63 ms 010 Fcpu/64 18.3 ms 71.5us 2000 ms 7.8 ms 011 Fcpu/32 9.15 ms 35.8us 1000 ms 3.9 ms 100 Fcpu/16 4.57 ms 17.9us 500 ms 1.95 ms 101 Fcpu/8 2.28 ms 8.94us 250 ms 0.98 ms 110 Fcpu/4 1.14 ms 4.47us 125 ms 0.49 ms 111 Fcpu/2 0.57 ms 2.23us 62.5 ms 0.24 ms

TC1_Counter=6-bit , TC1X8=0

TC1RATE TC1CLOCK

000 Fcpu/256 18.3 ms 286us 2000 ms 31.25 ms 001 Fcpu/128 9.15 ms 143us 1000 ms 15.63 ms 010 Fcpu/64 4.57 ms 71.5us 500 ms 7.8 ms 011 Fcpu/32 2.28 ms 35.8us 250 ms 3.9 ms 100 Fcpu/16 1.14 ms 17.9us 125 ms 1.95 ms 101 Fcpu/8 0.57 ms 8.94us 62.5 ms 0.98 ms 110 Fcpu/4 0.285 ms 4.47us 31.25 ms 0.49 ms 111 Fcpu/2 0.143 ms 2.23us 15.63 ms 0.24 ms

TC1_Counter=5-bit, TC1X8=0

TC1RATE TC1CLOCK

000 Fcpu/256 9.15 ms 286us 1000 ms 31.25 ms 001 Fcpu/128 4.57 ms 143us 500 ms 15.63 ms 010 Fcpu/64 2.28 ms 71.5us 250 ms 7.8 ms 011 Fcpu/32 1.14 ms 35.8us 125 ms 3.9 ms 100 Fcpu/16 0.57 ms 17.9us 62.5 ms 1.95 ms 101 Fcpu/8 0.285 ms 8.94us 31.25 ms 0.98 ms 110 Fcpu/4 0.143 ms 4.47us 15.63 ms 0.49 ms 111 Fcpu/2 71.25 us 2.23us 7.81 ms 0.24 ms

TC1_Counter=4-bit, TC1X8=0