SONIX SN8P1602P, SN8P1602S, SN8P1602X, SN8P1603P, SN8P1603S Datasheet

SN8P1600

8-Bit Micro-Controller

SN8P1600 Series

USER’S MANUAL

SN8P1602 SN8P1603 SN8P1604

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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.

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SONiX TECHNOLOGY CO., LTD Revision 1.94

SN8P1600

8-bit micro-controller

AMENDENT HISTORY

Version Date Description

VER 1.90 Sep. 2002 V1.9 first issue VER 1.91 Sep. 2002 Correct some V1.9 typing errors VER 1.92 Oct. 2002 1. Correct some template code errors

2. Modify description of code option

3. Modify approval form section

4. Modify description of TC1 timer and add more explanation about PWM function

VER 1.93 Feb. 2003 1. Extend chip operating temperature from “0°C ~ +70°C” to “-20°C ~ +70°C”.

2. Change the description of ADD M,A instruction from “M  M+A” to “M  A+M”

3. Change “ACC can’t be access by “B0MOV” instruction” to “ACC can’t be access by “B0MOV” instruction during the instant addressing mode”.

4. Correct the description of STKn.

5. Correct the bit definition of INTEN register.

6. Correct the description of “TC1 CLOCK FREQUENCY OUTPUT” section.

7. Correct an error of template code: “b0bclr FWDRST”  “b0bset FWDRST”.

8. Add a notice about OSCM register access cycle.

9. Correct the table of “STANDARD ELECTRICAL CHARACTERISTICS”.

VER 1.94 Sep. 2003 1. Add new section about checksum calculate must avoid 04H~07H

2. Reserved Last 16 word ROM addresses

3. Remove register bit description

4. Modify TC0M description.

5. Modify TC1M description.

6. Modify PWM description

7. Modify slow mode current.

8. Change code option to chapter2

9. Adjust Electrical characteristic page

10. Remove approval sheet.

11. Remove PCB layout notice section.

12. Modify the description of INTRQ register.

SONiX TECHNOLOGY CO., LTD Revision 1.94

SN8P1600

8-bit micro-controller

Table of Content

AMENDENT HISTORY ............................................................................................................................... 2

1

PRODUCT OVERVIEW................................................................................................................. 8

GENERAL DESCRIPTION........................................................................................................................... 8

SELECTION TABLE..................................................................................................................................... 8

FEATURES.................................................................................................................................................... 9

SYSTEM BLOCK DIAGRAM.................................................................................................................... 10

PIN ASSIGNMENT..................................................................................................................................... 11

PIN DESCRIPTIONS................................................................................................................................... 13

PIN CIRCUIT DIAGRAMS ........................................................................................................................ 14

2

3

CODE OPTION TABLE ...............................................................................................................15

ADDRESS SPACES.......................................................................................................................16

PROGRAM MEMORY (ROM)................................................................................................................... 16

OVERVIEW .............................................................................................................................................. 16

USER RESET VECTOR ADDRESS (0000H)........................................................................................... 17

INTERRUPT VECTOR ADDRESS (0008H) ............................................................................................ 17

CHECKSUM CALCULATION................................................................................................................. 19

GENERAL PURPOSE PROGRAM MEMORY AREA.............................................................................. 20

LOOK-UP TABLE DESCRIPTION.......................................................................................................... 20

JUMP TABLE DESCRIPTION................................................................................................................. 22

DATA MEMORY (RAM) ........................................................................................................................... 24

OVERVIEW .............................................................................................................................................. 24

WORKING REGISTERS............................................................................................................................. 25

Y, Z REGISTERS....................................................................................................................................... 25

R REGISTERS........................................................................................................................................... 26

PROGRAM FLAG....................................................................................................................................... 27

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8-bit micro-controller

CARRY FLAG........................................................................................................................................... 27

DECIMAL CARRY FLAG......................................................................................................................... 27

ZERO FLAG............................................................................................................................................. 27

ACCUMULATOR ....................................................................................................................................... 28

STACK OPERATIONS ............................................................................................................................... 29

OVERVIEW .............................................................................................................................................. 29

STACK REGISTERS................................................................................................................................. 30

STACK OPERATION EXAMPLE............................................................................................................. 31

PROGRAM COUNTER............................................................................................................................... 32

ONE ADDRESS SKIPPING ..................................................................................................................... 33

MULTI-ADDRESS JUMPING ................................................................................................................. 34

4

ADDRESSING MODE................................................................................................................... 35

OVERVIEW................................................................................................................................................. 35

IMMEDIATE ADDRESSING MODE.......................................................................................................35

DIRECTLY ADDRESSING MODE .......................................................................................................... 35

INDIRECTLY ADDRESSING MODE ......................................................................................................35

5

6

SYSTEM REGISTER.................................................................................................................... 36

OVERVIEW................................................................................................................................................. 36

SYSTEM REGISTER ARRANGEMENT (BANK 0)................................................................................. 36

BYTES of SYSTEM REGISTER ................................................................................................................ 36

BITS of SYSTEM REGISTER.................................................................................................................... 37

POWER ON RESET...................................................................................................................... 38

OVERVIEW................................................................................................................................................. 38

EXTERNAL RESET DESCRIPTION......................................................................................................... 39

LOW VOLTAGE DETECTOR (LVD) DESCRIPTION............................................................................. 40

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8-bit micro-controller

7

OSCILLATORS ............................................................................................................................. 41

OVERVIEW................................................................................................................................................. 41

CLOCK BLOCK DIAGRAM .................................................................................................................... 41

OSCM REGISTER DESCRIPTION.......................................................................................................... 42

EXTERNAL HIGH-SPEED OSCILLATOR.............................................................................................. 43

OSCILLATOR MODE CODE OPTION................................................................................................... 43

OSCILLATOR DEVIDE BY 2 CODE OPTION........................................................................................ 43

OSCILLATOR SAFE GUARD CODE OPTION....................................................................................... 43

SYSTEM OSCILLATOR CIRCUITS......................................................................................................... 44

External RC Oscillator Frequency Measurement....................................................................................45

INTERNAL LOW-SPEED OSCILLATOR................................................................................................. 46

SYSTEM MODE DESCRIPTION............................................................................................................... 47

OVERVIEW .............................................................................................................................................. 47

NORMAL MODE...................................................................................................................................... 47

SLOW MODE........................................................................................................................................... 47

POWER DOWN MODE ........................................................................................................................... 47

SYSTEM MODE CONTROL...................................................................................................................... 48

SYSTEM MODE SWITCHING................................................................................................................. 49

WAKEUP TIME .......................................................................................................................................... 50

OVERVIEW .............................................................................................................................................. 50

HARDWARE WAKEUP............................................................................................................................ 50

8

TIMERS .......................................................................................................................................... 51

WATCHDOG TIMER (WDT)..................................................................................................................... 51

TIMER0 (TC0) (SN8P1602/1603 O

NLY) .................................................................................................... 52

OVERVIEW .............................................................................................................................................. 52

TC0M MODE REGISTER........................................................................................................................ 53

TC0C COUNTING REGISTER ................................................................................................................ 54

TC0 TIMER OPERATION SEQUENCE .................................................................................................. 55

TIMER1 (TC1) (SN8P1604 ONLY).............................................................................................................. 56

OVERVIEW .............................................................................................................................................. 56

TC1M MODE REGISTER........................................................................................................................ 57

TC1C COUNTING REGISTER ................................................................................................................ 58

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TC1R AUTO-LOAD REGISTER .............................................................................................................. 59

TC1 TIMER COUNTER OPERATION SEQUENCE............................................................................... 60

TC1 CLOCK FREQUENCY OUTPUT (BUZZER) .................................................................................. 62

PWM FUNCTION DESCRIPTION (SN8P1604 ONLY)............................................................................. 63

OVERVIEW .............................................................................................................................................. 63

PWM PROGRAM DESCRIPTION........................................................................................................... 64

9

INTERRUPT................................................................................................................................... 65

OVERVIEW................................................................................................................................................. 65

INTEN INTERRUPT ENABLE REGISTER .............................................................................................. 66

INTRQ INTERRUPT REQUEST REGISTER............................................................................................ 66

INTERRUPT OPERATION DESCRIPTION.............................................................................................. 67

GIE GLOBAL INTERRUPT OPERATION............................................................................................... 67

INT0 (P0.0) INTERRUPT OPERATION.................................................................................................. 68

TC0/TC1 INTERRUPT OPERATION ...................................................................................................... 69

MULTI-INTERRUPT OPERATION......................................................................................................... 70

1

0

1

0

OVERVIEW................................................................................................................................................. 71

I/O PORT FUNCTION TABLE................................................................................................................... 72

I/O PORT MODE......................................................................................................................................... 73

I/O PORT DATA REGISTER ..................................................................................................................... 74

1

I/O PORT............................................................................................................................71

EXTERNAL RESET CIRCUIT........................................................................................ 76

SN8P1602 EXTERNAL RESET CIRCUIT EXAMPLE ......................................................................................... 76

SN8P1603 E

1

2

1

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2

XTERNAL RESET CIRCUIT EXAMPLE ......................................................................................... 77

CODING ISSUE................................................................................................................. 79

SN8P1600

8-bit micro-controller

TEMPLATE CODE ..................................................................................................................................... 79

CHIP DECLARATION IN ASSEMBLER.................................................................................................. 83

PROGRAM CHECK LIST .......................................................................................................................... 83

1

3

1 1

1

3

4

ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 85

STANDARD ELECTRICAL CHARACTERISTICS.................................................................................. 85

SN8P1602................................................................................................................................................. 85

SN8P1603................................................................................................................................................. 86

SN8P1604................................................................................................................................................. 87

5

INSTRUCTION SET TABLE........................................................................................... 84

ELECTRICAL CHARACTERISTICS............................................................................ 85

PACKAGE INFORMATION ........................................................................................... 89

P-DIP 18 PIN................................................................................................................................................ 89

SOP 18 PIN .................................................................................................................................................. 90

SSOP 20 PIN................................................................................................................................................ 91

SOP28PIN .................................................................................................................................................... 92

SK-DIP28PIN............................................................................................................................................... 93

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SN8P1600

8-bit micro-controller

1

GENERAL DESCRIPTION

The SN8P1600 series is an 8-bit micro-controller utilized CMOS technology and featured with low power consumption and high performance by its unique electronic structure.

SN8P1602/ SN8P1603 is designed with the excellent IC structure including the program memory up to 1K-word OTP ROM, data memory of 48-bytes RAM, one 8-bit timer (TC0), a watchdog timer, two interrupt sources (TC0, INT0), and 4-level stack buffers.

More expansion functions come with SN8P1604, such like 4K-word OTP ROM, more data memory of 128-byte RAM, 8-bit timer named TC1, and buzzer function for different application. More details listed below.

Besides, user can choose desired oscillator configuration for the controller. There are four external oscillator configurations to select for generating system clock, including High/Low speed crystal, ceramic resonator or cost-saving RC oscillator. SN8P1600 also includes an internal RC oscillator for slow mode controlled by program.

SELECTION TABLE

PRODUCT OVERVIEW

CHIP ROM RAM I/O Stack

SN8P1602 On/Off SN8P1603 SN8P1604 4K*16 128 22

Notice: The SN8P1603 always turn the LVD (low voltage detect) on.

1K*16 48 14 V -

4

Timer PWM Wakeup

TC0 TC1

- V On/off 1 10 SKDIP28/SOP28

LVD

Buzzer Pin no.

On

- 6

Package

DIP18/SOP18/SSOP20

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SN8P1600

8-bit micro-controller

FEATURES

Memory configuration

♦

OTP ROM size: 1K * 16-bit. (SN8P1602/1603) One internal interrupt: TC0. (SN8P1602/ 1603)

RAM size: 48 * 8-bit. (SN8P1602/1603) One internal interrupt: TC1. (SN8P1604) OTP ROM size: 4K * 16-bit. (SN8P1604) One external interrupt: INT0. RAM size: 128 * 8-bit. (SN8P1604)

I/O pin configuration

♦

(SN8P1602/1603 14 pins, SN8P1604 22 pins) Input only: P0 Bi-directional: P1, P2, P5 Wakeup: P0, P1 External high clock: RC type up to 10 MHz Pull-up resisters: P0, P1, P2, P5 (SN8P1604 only) External high clock: Crystal type up to 16 MHz External interrupt: P0 Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and low clock active Slow mode: Low clock only

One 8-bit timer counters.

♦

(TC1 for SN8P1604, TC0 for others)

On chip watchdog timer.

♦

Four levels stack buffer.

♦

56 powerful instructions

♦ Four clocks per instruction cycle SOP18 (SN8P1602/1603) All of instructions are one word length. SSOP20 (SN8P1602/1603) Most of instructions are one cycle only. All ROM area lookup table function (MOVC) SKDIP28 (SN8P1604) SOP28 (SN8P1604)

Two interrupt sources

♦

One channel 8-bits PWM or Buzzer output.

♦

(SN8P1604 only) Dual clock system offers three operating modes

♦

Sleep mode: Both high and low clock stop

Package (Chip form support)

♦ P-DIP18 (SN8P1602/ 1603)

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SN8P1600

8-bit micro-controller

SYSTEM BLOCK DIAGRAM

 SN8P1602/1603

SN8P1602/SN8P1603

Internal

PC

IR ROM

FLAGS

ALU

ACC

H-OSC

TIMING GENERATOR

RAM

SYSTEM REGISTER

Internal

RC

POR

Watch

Dog

 SN8P1604

PORT 0

SN8P1604

INTERRUPT

INTERRUPT CONTROL

CONTROL

PORT 2PORT 1

PC

IR ROM

FLAGS

ALU

H-OSC

TIMING GENERATOR

RAM

TIMER & COUNTER

Internal

RC

Watch

LDV

Dog

SYSTEM REGISTER

PORT 5

TIMER & COUNTER

PORT 0

ACC

INTERRUPT

INTERRUPT CONTROL

CONTROL

PORT 2PORT 1

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SN8P1600

8-bit micro-controller

PIN ASSIGNMENT

Part Number Description： OTP Type: SN8P16XXY

Y

= Q: QFP，P: PDIP，K: SKDIP，S: SOP，X: SSOP

OTP Type:

SN8P1602P / SN8P1603P (DIP 18 pins) SN8P1602S / SN8P1603S (SOP 18 pins)

P1.2 1 U 18 P1.1 P1.3 2 17 P1.0 INT0/P0.0 3 16 XIN RST 4 15 XOUT/P1.4 VSS 5 14 VDD P2.0 6 13 P2.7 P2.1 7 12 P2.6 P2.2 8 11 P2.5 P2.3 9 10 P2.4

SN8P1602P SN8P1602S

SN8P1602X / SN8P1603X (SSOP 20 pins)

P1.2 1 U 20 P1.1 P1.3 2 19 P1.0 INT0/P0.0 3 18 XIN RST 4 17 XOUT/P1.4 VSS 5 16 VDD VSS 6 15 VDD P2.0 7 14 P2.7 P2.1 8 13 P2.6 P2.2 9 12 P2.5 P2.3 10 11 P2.4

SN8P1602X

MASK Type:

SN8A1602A: Support dice form only

, MASK Type: SN8A16XXAY

OTP

GND

PORT2[2]

PORT2[1]

PORT2[0]

PORT1[3]

PORT1[2]

PORT0[0]

VDD

PORT2[3]

PORT2[4]

PORT2[5]

PORT2[6]

PORT2[7]

XOUT

(0.00,0.00)

XIN

PORT1[1]

P_RESETB

PORT1[0]

TEST

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SN8P1600

8-bit micro-controller

OTP Type:

SN8P1604K (SKDIP 28 pins) SN8P1604S (SOP 28 pins)

P0.1 1 U 28 RST

VDD 2 27 XIN

VPP/VDD 3 26 XOUT/Fcpu

VSS 4 25 P2.7

P0.0/INT0 5 24 P2.6

P5.0 6 23 P2.5 P5.1 7 22 P2.4 P5.2 8 21 P2.3

P5.3/BZ1/PWM1 9 20 P2.2

P1.0 10 19 P2.1 P1.1 11 18 P2.0 P1.2 12 17 P1.7 P1.3 13 16 P1.6 P1.4 14 15 P1.5

SN8P1604K

SN8P1604S

MASK Type:

SN8A1604AK (SKDIP 28 pins) SN8A1604AS (SOP 28 pins)

P0.1 1 U 28 RST

VDD 2 27 XIN

P0.2 3 26 XOUT/Fcpu

VSS 4 25 P2.7

P0.0/INT0 5 24 P2.6

P5.0 6 23 P2.5 P5.1 7 22 P2.4 P5.2 8 21 P2.3

P5.3/BZ1/PWM1 9 20 P2.2

P1.0 10 19 P2.1 P1.1 11 18 P2.0 P1.2 12 17 P1.7 P1.3 13 16 P1.6 P1.4 14 15 P1.5

SN8A1604AK

SN8A1604AS

Notice: Different pins between MASK and OTP:

 Pin 3 of SN8A1604A is P0.2 but it is VPP in SN8P1604. Pull up P0.2 to VDD if no use to avoid extra power

consumption.

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SN8P1600

8-bit micro-controller

PIN DESCRIPTIONS

 SN8P1602/1603

PIN NAME TYPE DESCRIPTION

VDD, VSS P

VPP/RST I

XIN I

XOUT/P1.4 I/O

P0.0 / INT0 I P1.0 ~ P1.4 I/O P2.0 ~ P2.7 I/O

Notice : The SN8P1602/3 do not have the pull-up resistor in the input port. The user must use the external pull-up

resistor.

 SN8P1604

PIN NAME TYPE DESCRIPTION

VDD, VSS

VPP/VDD

RST

XIN

XOUT/Fcpu

P0.0/INT0

P0.1 P1.0 ~ P1.7 P2.0 ~ P2.7 P5.0 ~ P5.3

I/O External oscillator output pin. RC Mode as the Fcpu output

I/O Bi-direction pins with sleep mode Wakeup function. Built-in pull-up resisters. I/O Bi-direction pins / Built-in pull-up resisters. I/O Bi-direction pin, P5.3 as TC1 output for PWM and Buzzer function/Built-in pull-up resisters.

Power supply input pins. Place the 0.1µF bypass capacitor between the VDD and VSS pin. System reset pin. Schmitt trigger structure, low active, normal stay to “high”. External oscillator input pin. RC mode input pin. External oscillator output pin. In RC mode is P1.4 I/O. Input / Interrupt (Schmitt trigger) / Wakeup function. Bi-direction pins with sleep mode wakeup function. Bi-direction pins.

P Power supply input pins. Place the 0.1µF bypass capacitor between the VDD and VSS pin. P OTP programming pin. Keep connect to VDD during normal mode.

I System reset pin. Schmitt trigger structure, lo w active, normal stay to “high”. I External oscillator input pin. RC mode input pin.

I Input / Interrupt (Schmitt trigger) / Wakeup function / Built-in pull-up resisters. I Input / W akeup function. / Built-in pull-up resister.

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SN8P1600

8-bit micro-controller

PIN CIRCUIT DIAGRAMS

 SN8P1602/1603

Port1, 2 structure

Port0 structure

Int. bus

 Note: All of the latch output circuits are push-pull structures.

 SN8P1604

Port0 structure

Port1,2, 5 structure

PnM

Latch

PnM

Int. bus

PUR

Code Option

Int. bus

PnM, Code Option

PnM

PUR

PnM

Latch

PnM

 Note: The internal pull-up resistor of the SN8P1604 can be enabled by the code option.

Int. bus

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SN8P1600

8-bit micro-controller

2

SN8P1602

SN8P1603----------The LVD always turn on to improve the power on reset and brownout reset performance

CODE OPTION TABLE

Code Option Content Function Description

RC Low cost RC for external high clock oscillator

High_Clk

High_Clk / 2

OSG

Watch_Dog

LVD

Security

Code Option Content Function Description

High_Clk

High_Clk / 2

OSG

Watch_Dog

Security

32K X’tal

12M X’tal High speed crystal /resonator (e.g. 12M) for external high clock oscillator

4M X’tal Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator

Enable External high clock divided by two, Fosc = high clock / 2

Disable Fosc = high clock

Enable Enable Oscillator Safe Guard function

Disable Disable Oscillator Safe Guard function

Enable Enable Watch Dog function

Disable Disable Watch Dog function

Enable Enable the low voltage detect

Disable Disable the low voltage detect

Enable Enable ROM code Security function

Disable Disable ROM code Security function

RC Low cost RC for external high clock oscillator

32K X’tal

12M X’tal High speed crystal /resonator (e.g. 12M) for external high clock oscillator

4M X’tal Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator

Enable External high clock divided by two, Fosc = high clock / 2

Disable Fosc = high clock

Enable Enable Oscillator Safe Guard function

Disable Disable Oscillator Safe Guard function

Enable Enable Watch Dog function

Disable Disable Watch Dog function

Enable Enable ROM code Security function

Disable Disable ROM code Security function

Low frequency, power saving crystal (e.g. 32.768K) for external high clock oscillator

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SN8P1600

8-bit micro-controller

3

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

The SN8P1600 provides the program memory up to 1024 * 16-bit (4096 *16-bit for SN8P1604) to be addressed and is able to fetch instructions through 10-bit wide PC (Program Counter). It can look up ROM data by using ROM code registers (R, Y, Z).

 1-word reset vector addresses  1-word interrupt vector addresses  1K words general purpose area (SN8P1602/1603)  4K words general purpose area (SN8P1604)  5-words reserved area

All of the program memory is partitioned into three coding areas. The 1 vector area), the 2 from 0008H to 0FFEH. The address 08H is the interrupt enter address point.

SN8P1604 SN8P1602/SN8P160

0000H 0000H 0001H 0001H Jump to user start address 0002H 0002H Jump to user start address 0003H 0003H 0004H 0004H 0005H 0005H 0006H 0006H 0007H 0007H 0008H 0008H 0009H 0009H User program

000FH 000FH 0010H 0010H 0011H 0011H

0FFEH 03FEH 0FFFH 03FFH

nd

area is a reserved area 04H ~07H, the 3rd area is for the interrupt vector and the user code area

3

General purpose area

. . . .

General purpose area

. . . .

ROM

Reset vector

Reserved

Interrupt vector

Reserved

st

area is located from 00H to 03H(The Reset

User reset vector

Jump to user start address

User interrupt vector

End of user program

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SN8P1600

8-bit micro-controller

USER RESET VECTOR ADDRESS (0000H)

A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory.

 Example: After power on reset, external reset active or reset by watchdog timer overflow. CHIP SN8P1602

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0004H ~ 0007H are reserved

ORG 10H START: ; 0010H, The head of user program.

. ; User program . . .

ENDP ; End of program

INTERRUPT VECTOR ADDRESS (0008H)

A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory.

 Example 1: This demo program includes interrupt service routine and the user program is behind the

interrupt service routine.

CHIP SN8P1602

.DATA PFLAGBUF .CODE

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0004H ~ 0007H are reserved

ORG 8

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag B0MOV A, PFLAG B0MOV PFLAGBUF, A ; Save PFLAG register in a buffer . . B0MOV A, PFLAGBUF B0MOV PFLAG, A ; Restore PFLAG register from buffer B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag RETI ; End of interrupt service routine

START: ; The head of user program.

. ; User program . JMP START ; End of user program

ENDP

; End of program

; Interrupt service routine

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SN8P1600

8-bit micro-controller

 Example 2: The demo program includes interrupt service routine and the address of interrupt service

routine is in a special address of general-purpose area.

CHIP SN8P1602

.DATA PFLAGBUF .CODE

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0001H ~ 0007H are reserved

ORG 08 JMP MY_IRQ ; 0008H, Jump to interrupt service routine address

ORG 10H START: ; 0010H, The head of user program.

. ; User program . . JMP START ; End of user program

MY_IRQ: ;The head of interrupt service routine

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag B0MOV A, PFLAG B0MOV PFLAGBUF, A ; Save PFLAG register in a buffer . . B0MOV A, PFLAGBUF B0MOV PFLAG, A ; Restore PFLAG register from buffer B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag RETI ; End of interrupt service routine

ENDP ; End of program

 Remark: It is easy to get the rules of SONIX program from demo programs given above. These points are

as following.

1. The address 0000H is a “JMP” instruction to make the program go to general-purpose ROM area. The 0004H~0007H are reserved. Users have to skip 0004H~0007H addresses. It is very important and necessary.

 2. The interrupt service starts from 0008H. Users can put the whole interrupt service routine from 0008H

(Example1) or to put a “JMP” instruction in 0008H then place the interrupt service routine in other general-purpose ROM area (Example2) to get more modularized coding style.

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SN8P1600

8-bit micro-controller

CHECKSUM CALCULATION

The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses (0004H~0007H and last address) when calculate the Checksum value.

 Example:

The demo program shows how to avoid 0004H~0007H when calculated Checksum from 00H to the end of

user’s code MOV A,#END_USER_CODE$L B0MOV END_ADDR1,A ;save low end address to end_addr1 MOV A,#END_USER_CODE$M

B0MOV END_ADDR2,A ;save middle end address to end_addr2 CLR Y ;set Y to ooH CLR Z ;set Z to 00H @@: CALL YZ_CHECK ;call function of check yz value MOVC ; B0BSET FC ;clear C glag ADD DATA1,A ;add A to Data1 MOV A,R ADC DATA2,A ;add R to Data2 JMP END_CHECK ;check if the YZ address = the end of code AAA: INCMS Z ;Z=Z+1 JMP @B ;if Z!= 00H calculate to next address JMP Y_ADD_1 ;if Z=00H increase Y END_CHECK: MOV A,END_ADDR1 CMPRS A,Z ;check if Z = low end address JMP AAA ;if Not jump to checksum calculate MOV A,END_ADDR2 CMPRS A,Y ;if Yes, check if Y = middle end address JMP AAA ;if Not jump to checksum calculate JMP CHECKSUM_END ;if Yes checksum calculated is done. YZ_CHECK: ;check if YZ=0004H MOV A,#04H CMPRS A,Z ;check if Z=04H RET ;if Not return to checksum calculate MOV A,#00H CMPRS A,Y ;if Yes, check if Y=00H RET ;if Not return to checksum calculate INCMS Z ;if Yes, increase 4 to Z INCMS Z INCMS Z INCMS Z RET ;set YZ=0008H then return Y_ADD_1: INCMS Y ;increase Y NOP JMP @B ;jump to checksum calculate CHECKSUM_END: ………. ………. END_USER_CODE: ;Label of program end

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SN8P1600

8-bit micro-controller

GENERAL PURPOSE PROGRAM MEMORY AREA

The 1017/4089-word at ROM locations 0009H~03FEH/0FFEH are used as general-purpose memory. The area is stored instruction’s op-code and look-up table data. The SN8P1600 includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, Y, Z).

The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table function and look-up table function, the program counter can’t leap over the boundary by program counter automatically. Users need to modify the PCH value to “PCH+1” when the PCL overflows (from 0FFH to 000H).

LOOK-UP TABLE DESCRIPTION

In the ROM’s data lookup function, Y register is pointed to the bit 8~bit 15 and Z register to the bit 0~bit 7 data of ROM address. After MOVC instruction is executed, the low-byte data of ROM then will be stored in ACC and high-byte data stored in R register.

 Example: To look up the ROM data located “TABLE1”. B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address

B0MOV Z, #TABLE1$L ; To set lookup table1’s low address. MOVC ; To lookup data, R = 00H, ACC = 35H ;

; @@: . . ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H ; “ DW 2012H ; “

 CAUSION: The Y register can't increase automatically if Z register cross boundary from 0xFF to 0x00.

Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflow, Y

register must be added one. The following INC_YZ macro shows a simple method to process Y and Z

registers automatically.

 Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users

can omit “B0MOV X, #TABLE1$H”. SONiX ICE support more larger program memory addressing

capability. So make sure X register is “0” to avoid unpredicted error in loop-up table operation.

INCMS Z ; Z+1 JMP @F ; Not overflow INCMS Y ; Z overflow (FFH  00),  Y=Y+1 NOP ; Not overflow

MOVC ; To lookup data, R = 51H, ACC = 05H.

; Increment the index address for next address

 Example: INC_YZ Macro

INC_YZ MACRO INCMS Z ; Z+1 JMP @F ; Not overflow

INCMS Y ; Y+1 NOP ; Not overflow @@: ENDM

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The other coding style of loop-up table is to add Y or Z index register by accumulator. Be careful if carry happen. Refer following example for detailed information:

 Example: Increase Y and Z register by B0ADD/ADD instruction

B0MOV Y, #TABLE1$M ; To set lookup table’s middle address. B0MOV Z, #TABLE1$L ; To set lookup table’s low address.

GETDATA: ; MOVC ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 . . . . ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H ; “ DW 2012H ; “

B0MOV A, BUF ; Z = Z + BUF. B0ADD Z, A

B0BTS1 FC ; Check the carry flag. JMP GETDATA ; FC = 0 INCMS Y ; FC = 1. Y+1. NOP

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8-bit micro-controller

JUMP TABLE DESCRIPTION

The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. The way is easy to make a multi-stage program.

When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump table leaps over the ROM page boundary or the listing file gener ated by SONIX assembly software. If the jump table leaps over the ROM page boundary (e.g. from xxFFH to xx00H), move the jump table to the top of next program memory page (xx00H). Here one page mean 256 words.

 Example :

ORG 0X0100 ; The jump table is from the head of the ROM boundary B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed.

JMP A0POINT ; ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT

In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will point to a wrong address 0x0000 and crash system operation. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H).

 Example: If “jump table” crosses over ROM boundary will cause errors.

ROM Address

. . . .

. . 0X00FD 0X00FE

0X00FF 0X0100 0X0101

. .

SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size.

@JMP_A MACRO VAL IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) JMP ($ | 0XFF) ORG ($ | 0XFF) ENDIF ADD PCL, A ENDM

 Note: “VAL” is the number of the jump table listing number.

B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed. JMP A0POINT ; ACC = 0 JMP A1POINT ; ACC = 1 JMP A2POINT JMP A3POINT ; ACC = 3

; ACC = 2  jump table cross boundary here

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 Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.

B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A 5 ; The number of the jump table listing is five. JMP A0POINT ; If ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT JMP A4POINT ; ACC = 4, jump to A4POINT

If the jump table position is from 00FDH to 0101H, the “@JMP_A” macro will make the jump table to start from 0100h.

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DATA MEMORY (RAM)

OVERVIEW

The SN8P1600 has internally built-in data memory up to 48/128 bytes for storing the general-purpose data.

 48 * 8-bit general purpose area in bank 0 (SN8P1602/1603)  128 * 8-bit general purpose area in bank 0 (SN8P1604)  128 * 8-bit system register area

The memory is separated into bank 0. The bank 0 uses the first 48/128 bytes as general-purpose area, and the remaining 128 bytes as system register.

BANK 0

SN8P1604 SN8P1602/SN

8P1603

000h 000h

“ “ “ “ “ “ “ “

“ “ 07Fh 02Fh 080h 080h

“ “

“ “ 0FFh 0FFh

RAM location

General purpose area

System register

End of bank 0 area

000h~02FH/07FH of Bank 0 store general-purpose data (48 bytes /128bytes).

080h~0FFh of Bank 0 store system registers (128 bytes).

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WORKING REGISTERS

The RAM bank0 locations 82H to 84H store the specially defined registers such as register R, Y, Z, respectively shown in the following table. These registers can use as the general-purpose working buffer or access ROM’s and RAM’s data. For instance, all of the ROM table can be looked-up by R, Y and Z registers. The data of RAM memory can be indirectly accessed with Y and Z registers.

Y, Z REGISTERS

The Y and Z registers are the 8-bit buffers. There are three major functions of these registers. First, Y and Z registers can be used as working registers. Second, these two registers can be used as data pointers for @YZ register. Third, the registers can address ROM location to look up ROM data.

084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Y

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Z

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

The @YZ that is data point_1 index buffer located at address 0E7H in RAM bank 0. It employs Y and Z registers to addressing RAM location to read/write data through ACC. The Lower 4-bit of Y register points to RAM bank number and Z register to RAM address number, respectively. The higher 4-bit data of Y register is truncated in RAM indirectly access mode.

 Example: Following example uses indirectly addressing mode to access data in the RAM address 025H of

bank0.

B0MOV Y, #00H ; To set RAM bank 0 for Y register B0MOV Z, #25H ; To set location 25H for Z register B0MOV A, @YZ ; To read a data into ACC

 Example: Clear general-purpose data memory area of bank 0 using @YZ register.

B0MOV Y, #0 ; Y = 0, bank 0 B0MOV Z, #07FH ; Z = 7FH, the last address of the data memory area

CLR_YZ_BUF: CLR @YZ ; Clear @YZ to be zero

DECMS Z ; Z – 1, if Z= 0, finish the routine JMP CLR_YZ_BUF ; Not zero

CLR @YZ END_CLR: ; End of clear general purpose data memory area of bank 0 .

 Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about Y, Z register look-up table application.

YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0

ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0

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R REGISTERS

R register is an 8-bit buffer. There are two major functions of the register. First, R register can be used as working register. Second, the R register stores high-byte data of look-up ROM data. After MOVC instruction executed, the high-byte data of specified ROM address will store in R register and the low-byte data in ACC.

082H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

R

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

 Note: Please consult the “LOOK-UP TABLE DESCRIPTION” about R register look-up table application.

RBIT7 RBIT6 RBIT5 RBIT4 RBIT3 RBIT2 RBIT1 RBIT0

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PROGRAM FLAG

The PFLAG includes carry flag (C), decimal carry flag (DC) and zero flag (Z). If the result of operating is zero or there is carry, borrow occurrence, then these flags will be set to PFLAG register.

086H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PFLAG

Read/Write - - - - - R/W R/W R/W

After reset - - - - - 0 0 0

CARRY FLAG

C = 1: When executed arithmetic addition with overflow or executed arithmetic subtraction without borrow or executed rotation instruction with logic “1” shifting out. C = 0: When executed arithmetic addition without overflow or executed arithmetic subtraction with borrow or executed rotation instruction with logic “0” shifting out.

DECIMAL CARRY FLAG

DC = 1: If executed arithmetic addition with overflow of low nibble or executed arithmetic subtraction without borrow of low nibble. DC = 0: If executed arithmetic addition without overflow of low nibble or executed arithmetic subtraction with borrow of low nibble.

ZERO FLAG

Z = 1: When the content of ACC or target memory is zero after executing instructions involving a zero flag. Z = 0: When the content of ACC or target memory is not zero after executing instructions involving a zero flag.

- - - - - C DC Z

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ACCUMULATOR

The ACC is an 8-bit data register responsible for transferring or manipulating data between ALU and data memory. If the result of operating is zero (Z) or there is carry (C or DC) occurrence, then these flags will be set to PFLAG register.

ACC is not in data memory (RAM), so ACC can’t be access by “B0MOV” instruction during the instant addressing mode.

 Example: Read and write ACC value.

; Read ACC data and store in BUF data memory MOV BUF, A

. . ; Write a immediate data into ACC

MOV A, #0FH ; Write ACC data from BUF data memory MOV A, BUF

The system doesn’t store ACC and PFLAG value when interrupt executed. ACC and PFLAG data must be exchanged to other data memories defined by users. Thus, once interrupt occurs, these data must be stored in the data memory based on the user’s program as follows.

 Example: Protect ACC and working registers.

ACCBUF EQU 00H ; ACCBUF is ACC data buffer. PFLAGBUF EQU 01H ; PFLAGBUF is PFLAG data buffer.

INT_SERVICE:

B0XCH A, ACCBUF ; Store ACC value B0MOV A, PFLAG ; Store PFLAG value B0MOV PFLAGBUF,A

. . . .

B0MOV A, PFLAGBUF ; Re-load PFLAG value B0MOV PFLAG,A B0XCH A, ACCBUF ; Re-load ACC

RETI ; Exit interrupt service vector

 Note: To save and re-load ACC data must be used “B0XCH” instruction, or the PFLAG value maybe

modified by ACC.

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STACK OPERATIONS

OVERVIEW

The stack buffer of SN8P1600 has 4-level high area and each level is 10-bit length. These buffers are designed to push and pop up program counter’s (PC) data when interrupt service routine is executed. The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer of kernel circuit. The STKnH and STKnL are the 10-bit stack buffers to store program counter (PC) data.

PCL

PCLPCL

RET /

RET / RETI

RETI

CALL /

CALL / interrupt

interrupt

PCH

PCHPCH

STK3L

STK2L

STK1L

STK0L

STKP + 1

STKP - 1

STKP - 1STKP - 1

STKP = 3

STKP = 2

STKP = 1

STKP = 0

STKP

STKPSTKP

STK3H

STK2H

STK1H

STK0H

STKP

STKPSTKP

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SONIX SN8P1602P, SN8P1602S, SN8P1602X, SN8P1603P, SN8P1603S Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

SELECTION TABLE

PRODUCT OVERVIEW

FEATURES

SYSTEM BLOCK DIAGRAM

PIN ASSIGNMENT

PIN DESCRIPTIONS

PIN CIRCUIT DIAGRAMS

CODE OPTION TABLE

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

USER RESET VECTOR ADDRESS (0000H)

INTERRUPT VECTOR ADDRESS (0008H)

CHECKSUM CALCULATION

GENERAL PURPOSE PROGRAM MEMORY AREA

LOOK-UP TABLE DESCRIPTION

JUMP TABLE DESCRIPTION

DATA MEMORY (RAM)

OVERVIEW

WORKING REGISTERS

Y, Z REGISTERS

R REGISTERS

PROGRAM FLAG

CARRY FLAG

DECIMAL CARRY FLAG

ZERO FLAG

ACCUMULATOR

STACK OPERATIONS

OVERVIEW