SONIX SN8P1602BP, SN8P1602BS, SN8P1602BX Datasheet

SN8P1602B

8-Bit Micro-Controller

SN8P1602B

USER’S MANUAL

General Release Specification

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SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fai lure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of pe rsonal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.

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SONiX TECHNOLOGY CO., LTD Version 1.1

SN8P1602B

8-Bit Micro-Controller

AMENDENT HISTORY

Version Date Description

VER 1.0 Sep. 2003 V1.0 First Issue VER 1.1 Sep. 2003 1. Remove approval sheet

2. Remove PCB layout notice section.

3. Modify the description of code option no tice.

4. Add the description of PEDGE register.

5. Modify the description of INTRQ regi ster.

6. Change operating voltage range from “2.2V ~ 5.5V” to “2.4V ~ 5.5V” at Fosc=3.579545 MHz, ambient temperature = 25°C.

SONiX TECHNOLOGY CO., LTD Version 1.1

SN8P1602B

8-Bit Micro-Controller

Table of Content

AMENDENT HISTORY ............................................................................................................................... 2

1

PRODUCT OVERVIEW................................................................................................................. 8

GENERAL DESCRIPTION........................................................................................................................... 8

UPGRADE FROM SN8P1602/SN8P1603/SN8P1602A............................................................................... 8

FEATURES.................................................................................................................................................... 9

SELECTION TABLE..................................................................................................................................... 9

SYSTEM BLOCK DIAGRAM.................................................................................................................... 10

PIN ASSIGNMENT..................................................................................................................................... 11

PIN DESCRIPTIONS .................................................................................................................................. 12

PIN CIRCUIT DIAGRAMS ........................................................................................................................ 12

2

3

CODE OPTION TABLE ...............................................................................................................13

SN8P1602B.................................................................................................................................................. 13

ADDRESS SPACES.......................................................................................................................14

PROGRAM MEMORY (ROM)................................................................................................................... 14

OVERVIEW .............................................................................................................................................. 14

USER RESET VECTOR ADDRESS (0000H)........................................................................................... 15

INTERRUPT VECTOR ADDRESS (0008H) ............................................................................................ 15

CHECKSUM CALCULATION................................................................................................................. 17

GENERAL PURPOSE PROGRAM MEMORY AREA.............................................................................. 18

LOOK-UP TABLE DESCRIPTION.......................................................................................................... 18

JUMP TABLE DESCRIPTION................................................................................................................. 20

DATA MEMORY (RAM) ........................................................................................................................... 22

OVERVIEW .............................................................................................................................................. 22

WORKING REGISTERS............................................................................................................................. 23

Y, Z REGISTERS ...................................................................................................................................... 23

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8-Bit Micro-Controller

R REGISTERS........................................................................................................................................... 24

PROGRAM FLAG....................................................................................................................................... 25

RESET/WAKEUP FLAG .......................................................................................................................... 25

CARRY FLAG........................................................................................................................................... 25

DECIMAL CARRY FLAG......................................................................................................................... 25

ZERO FLAG............................................................................................................................................. 25

ACCUMULATOR ....................................................................................................................................... 26

STACK OPERATIONS............................................................................................................................... 27

OVERVIEW .............................................................................................................................................. 27

STACK REGISTERS................................................................................................................................. 28

STACK OPERATION EXAMPLE............................................................................................................. 29

PROGRAM COUNTER............................................................................................................................... 29

ONE ADDRESS SKIPPING ..................................................................................................................... 30

MULTI-ADDRESS JUMPING ................................................................................................................. 31

4

5

ADDRESSING MODE................................................................................................................... 32

OVERVIEW................................................................................................................................................. 32

IMMEDIATE ADDRESSING MODE.......................................................................................................32

DIRECTLY ADDRESSING MODE.......................................................................................................... 32

INDIRECTLY ADDRESSING MODE......................................................................................................32

SYSTEM REGISTER.................................................................................................................... 33

OVERVIEW................................................................................................................................................. 33

SYSTEM REGISTER ARRANGEMENT (BANK 0)................................................................................. 33

BYTES of SYSTEM REGISTER ................................................................................................................ 33

BITS of SYSTEM REGISTER.................................................................................................................... 34

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POWER ON RESET...................................................................................................................... 35

OVERVIEW................................................................................................................................................. 35

EXTERNAL RESET DESCRIPTION......................................................................................................... 36

LOW VOLTAGE DETECTOR (LVD) DESCRIPTION ............................................................................ 37

SN8P1602B

8-Bit Micro-Controller

7

OSCILLATORS ............................................................................................................................. 38

OVERVIEW................................................................................................................................................. 38

CLOCK BLOCK DIAGRAM .................................................................................................................... 38

OSCM REGISTER DESCRIPTION.......................................................................................................... 39

EXTERNAL HIGH-SPEED OSCILLATOR.............................................................................................. 40

OSCILLATOR MODE CODE OPTION................................................................................................... 40

OSCILLATOR DEVIDE BY 2 CODE OPTION ....................................................................................... 40

OSCILLATOR SAFE GUARD CODE OPTION....................................................................................... 40

SYSTEM OSCILLATOR CIRCUITS..................................................................................................... .... 41

External RC Oscillator Frequency Measurement....................................................................................42

INTERNAL LOW-SPEED OSCILLATOR ................................................................................................ 43

SYSTEM MODE DESCRIPTION............................................................................................................... 44

OVERVIEW .............................................................................................................................................. 44

NORMAL MODE...................................................................................................................................... 44

SLOW MODE........................................................................................................................................... 44

GREEN MODE......................................................................................................................................... 44

POWER DOWN MODE ........................................................................................................................... 44

SYSTEM MODE CONTROL...................................................................................................................... 45

SYSTEM MODE SWITCHING................................................................................................................. 46

WAKEUP TIME .......................................................................................................................................... 47

OVERVIEW .............................................................................................................................................. 47

HARDWARE WAKEUP............................................................................................................................ 47

EXTERNAL WAKEUP TRIGGER CONTROL......................................................................................... 48

8

TIMERS .......................................................................................................................................... 49

WATCHDOG TIMER (WDT)..................................................................................................................... 49

TIMER0 (TC0)............................................................................................................................................. 50

OVERVIEW .............................................................................................................................................. 50

TC0M MODE REGISTER........................................................................................................................ 51

TC0C COUNTING REGISTER................................................................................................................ 52

TC0 TIMER OPERATION SEQUENCE .................................................................................................. 53

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INTERRUPT................................................................................................................................... 54

OVERVIEW................................................................................................................................................. 54

INTEN INTERRUPT ENABLE REGISTER .............................................................................................. 55

INTRQ INTERRUPT REQUEST REGISTER............................................................................................ 55

INTERRUPT OPERATION DESCRIPTION.............................................................................................. 56

GIE GLOBAL INTERRUPT OPERATION............................................................................................... 56

INT0 (P0.0) INTERRUPT OPERATION.................................................................................................. 57

TC0 INTERRUPT OPERATION .............................................................................................................. 58

MULTI-INTERRUPT OPERATION......................................................................................................... 59

1

0

1

0

OVERVIEW................................................................................................................................................. 60

I/O PORT FUNCTION TABLE................................................................................................................... 61

I/O PORT MODE......................................................................................................................................... 61

I/O PULL UP REGISTER............................................................................................................................ 62

I/O PORT DATA REGISTER ..................................................................................................................... 62

1

TEMPLATE CODE ..................................................................................................................................... 63

PROGRAM CHECK LIST .......................................................................................................................... 67

I/O PORT............................................................................................................................ 60

CODING ISSUE................................................................................................................. 63

1

2

1 1

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ABSOLUTE MAXIMUM RATING............................................................................................................ 69

INSTRUCTION SET TABLE........................................................................................... 68

ELECTRICAL CHARACTERISTIC.............................................................................. 69

SN8P1602B

8-Bit Micro-Controller

STANDARD ELECTRICAL CHARACTERISTIC.................................................................................... 69

CHARACTERISTIC GRAPHS................................................................................................................... 70

1

4

1

4

P-DIP 18 PIN................................................................................................................................................ 73

SOP 18 PIN................................................................................................................................................... 74

SSOP 20 PIN................................................................................................................................................ 75

PACKAGE INFORMATION ........................................................................................... 73

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SN8P1602B

8-Bit Micro-Controller

1

PRODUCT OVERVIEW

GENERAL DESCRIPTION

The SN8P1602B is an 8-bit micro-controller utilized CMOS technology and featured with low power consumption and high performance by its unique electronic structure.

SN8P1602B is designed with the excellent IC structure including the program memory up to 1K-word OTP ROM, data memory of 48-bytes RAM, one 8-bit timer (TC0), a watchdog timer, two interrupt sources (TC0, INT0), and 4-level stack buffers. Besides, user can choose desired oscillator configuration for the controller. There are four external oscillator configurations to select for generating system clock, including High/Low speed crystal, ceramic resonator or cost-saving RC. SN8P1602B also includes an internal RC oscillator for slow mode controlled by programming.

UPGRADE FROM SN8P1602/SN8P1603/SN8P1602A

Item SN8P1602B SN8P1602A SN8P1602 SN8P1603

Standby Current at 3V <1uA 3 ~ 4uA 3 ~ 4uA 70uA

Pull-up resistor Yes Yes - -

Power On Reset / Brown Out Reset

Watchdog Clock Source

Watchdog Clock Source Fixed

at Internal RC and Internal RC

Clock Always Enable

Green Mode Yes Yes - -

P0.0 Interrupt Edge Falling/Rising/Both Falling/Rising/Both Falling Falling

Port 1 Wakeup Level Change Level Change Low Level Low Level

TC0 Event Counter Yes Yes - -

External Reset

Recommend Value

Power On Delay at 4Mhz ~ 200ms ~ 200ms ~ 70ms ~ 70ms

Low Power code option Yes Yes - -

LVD

Excellent Excellent - Good

High Clock Internal RC

Yes Yes - -

20K / 0.1uF 20K / 0.33uF 20K / 0.1uF 20K / 0.1uF

1.8V

Always ON

High Clock Internal RC

1.8V

Always ON

High Clock

2.4V

ON/OFF

High Clock

2.4V

Always ON

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SN8P1602B

8-Bit Micro-Controller

FEATURES

Memory configuration

♦

OTP ROM size: 1K * 16-bit. One internal interrupt: TC0.

RAM size: 48 * 8-bit. One external interrupt: INT0.

I/O pin configuration

♦ Input only: P0 Bi-directional: P1, P2, Wakeup: P0, P1 External high clock: RC type up to 10 MHz Pull-up resistors: P0, P1, P2 External high clock: Crystal type up to 16 MHz External interrupt: P0 Internal low clock: RC type 16KHz(3V), 32KHz(5V) Normal mode: Both high and low clock active Slow mode: Low clock only

On chip watchdog timer.

♦

One 8-bit timer counters.

♦

57 powerful instructions

♦ Four clocks per instruction cycle P-DIP18, SOP18, SSOP20. All of instructions are one word length. Most of instructions are one cycle only. Maximum instruction cycle is two. All ROM area JMP instruction. All ROM area lookup table function (MOVC)

Two interrupt sources

♦

Four levels stack buffer.

♦

Dual clock system offers four operating modes

♦

Sleep mode: Both high and low clock stop Green mode: Periodical wakeup by timer.

Package

♦

SELECTION TABLE

CHIP ROM RAM Stack

Timer PWM Wakeup

TC0 TC1

SN8P1602B 1K*16 48 4 V - 14 V - 6

I/O

Green

Mode

Buzzer Pin no.

Package

DIP18/SOP18

/SSOP20

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SN8P1602B

8-Bit Micro-Controller

SYSTEM BLOCK DIAGRAM

 SN8P1602B

Internal

PC

IR ROM

FLAGS

ALU

ACC

INTERRUPT

INTERRUPT CONTROL

CONTROL

H-OSC

TIMING GENERATOR

RAM

SYSTEM REGISTER

Internal

RC

Watch

TIMER & COUNTER

POR

Dog

PORT 0

PORT 2PORT 1

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SN8P1602B

8-Bit Micro-Controller

PIN ASSIGNMENT

OTP Type:

SN8P1602BP (P-DIP 18 pins) SN8P1602BS (SOP 18 pins)

P1.2 1 U 18 P1.1 P1.3 2 17 P1.0 INT0/P0.0 3 16 XIN RST/VPP 4 15 XOUT/P1.4 VSS 5 14 VDD P2.0 6 13 P2.7 P2.1 7 12 P2.6 P2.2 8 11 P2.5 P2.3 9 10 P2.4

SN8P1602BP SN8P1602BS

SN8P1602BX (SSOP 20 pins)

P1.2 1 U 20 P1.1 P1.3 2 19 P1.0 INT0/P0.0 3 18 XIN RST/VPP 4 17 XOUT/P1.4 VSS 5 16 VDD VSS 6 15 VDD P2.0 7 14 P2.7 P2.1 8 13 P2.6 P2.2 9 12 P2.5 P2.3 10 11 P2.4

SN8P1602BX

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SN8P1602B

8-Bit Micro-Controller

PIN DESCRIPTIONS

 SN8P1602B

PAD NAME TYPE DESCRIPTION

VDD, VSS P

Power supply input pins. Place the 0.1µF bypass capacitor between the VDD and VSS pin. RST: System reset input pin. Schmitt trigger structure, low active, normal stay to

RST/VPP I, P

“high”. VPP: OTP programming pin.

XIN I External oscillator input pin. RC mode input pin.

XOUT/P1.4 I/O External oscillator output pin. In RC mode is P1.4 I/O.

P0.0 / INT0 I Port 0.0 and shared with INT0 trigger pin (Schmitt trigger) / Built-in pull-up resistors. P1.0 ~ P1.4 I/O Port 1.0~Port 1.4 bi-direction pins / Built-in pull-up resistors. P2.0 ~ P2.7 I/O Port 2.0~Port 2.7 bi-direction pins / Built-in pull-up resistors.

PIN CIRCUIT DIAGRAMS

 SN8P1602B

Port1~Port2 structure

Port0 structure

PUR

Int. bus

Port1~Port2 structure

PnM, PUR

PnM

 Note: All of the latch output circuits are push-pull structures.

PUR

PnM

Latch

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SN8P1602B

A

8-Bit Micro-Controller

2

CODE OPTION TABLE

SN8P1602B

Code Option Content Function Description

RC Low cost RC for external high clock oscillator

Low frequency, power saving crystal (e.g. 32.768K) for external high clock oscillator

Enable Oscillator Safe Guard function to enhance noise immunity performance.

Force Watch Dog Timer clock source come from INT 16K RC.

lso INT 16K RC never stop both in power down and green mode that means Watch Dog Timer will always enable both in power down and green mode.

High_Clk

High_Clk / 2

OSG

Watch_Dog

Low Power

Noise Filter

Security

INT_16K_RC

32K X’tal

12M X’tal High speed crystal /resonator (e.g. 12M) for external high clock oscillator

4M X’tal Standard crystal /resonator (e.g. 3.58M) for external high clock oscillator

Enable External high clock divided by two, Fosc = high clock / 2

Disable Fosc = high clock

Enable

Disable Disable Oscillator Safe Guard function

Enable Enable Watch Dog function

Disable Disable Watch Dog function

Enable Enable Low Power function to save Operating current

Disable Disable Low Power function

Enable Enable Noise Filter function to enhance noise immunity performance

Disable Disable Noise Filter function

Enable Enable ROM code Security function

Disable Disable ROM code Security function

Always_ON

By_CPUM Enable or Disable internal 16K(at 3V) RC clock by CPUM register

Table 2-1 SN8P1602B Code Option Table

This table is for design guidance, not tested or guaranteed. Some values presented are outside specifie d operating range. This is for information only and devices are guaranteed to operate properly only within the specified range.

Code Option Lowest Operation Voltage

Enable Disable 4 MHz 16 MHz

- Noise Filter/Low Power/OSG 2.2V 2.8V

Noise Filter Low Power/OSG 2.2V 3.5V

Low Power Noise Filter/OSG 2.2V 3.8V

OSG Noise Filter/Low Power 2.2V 2.9V

Table 2-2 SN8P1602B Minimum Working Voltage vs. Code Option and clock frequency

Notice:  Under high noisy environment, enable “Noise Filter”, “OSG” and disable “Low Power” is strongly

recommended.

 The side effect is to increase the minimum working voltage if enables “Noise Filter”/“OSG”/ “Low Power”

code option. (Please refer to Characteristic Graphs)

 Enable “Low Power” option will reduce operating current during the normal operating mode.  If users select “32K X’tal” in “High_Clk” option, assembler will force “OSG” to be enabled.

 If users select “RC” in “High_Clk” option, assembler will force “High_Clk / 2” to be enabled.

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3

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

The SN8P1602B provides the program memory up to 1024 * 16-bit to be addressed and is able to fetch instructions through 10-bit wide PC (Program Counter). It can look up ROM data by using ROM code registers (R, Y, Z).

 1-word reset vector addresses  1-word interrupt vector addresses  1K words general purpose area  5-word reserved area

All of the program memory is partitioned into three coding areas. The first area is located from 00H to 03H(The Reset vector area), the second area is a reserved area 04H ~07H, the 3 area from 0008H to 03FEH/0FFEH. The address 08H is the interrupt enter address point.

0000H 0001H Jump to user start address 0002H Jump to user start address 0003H 0004H 0005H 0006H 0007H 0008H 0009H User program

.

. 000FH 0010H 0011H

.

03FEH 03FFH

General purpose area

ROM

Reset vector

Reserved

Interrupt vector

Reserved

rd

area is for the interrupt vecto r and the user code

User reset vector

Jump to user start address

User interrupt vector

End of user program

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SN8P1602B

8-Bit Micro-Controller

USER RESET VECTOR ADDRESS (0000H)

A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset, then the chip will restart the program from address 0000h and all system registers will be set as default values. The following example shows the way to define the reset vector in the program memory.

 Programming Tip: Defining Reset Vector CHIP SN8P1602B

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0004H ~ 0007H are reserved

ORG 10H START: ; 0010H, The head of user program.

. ; User program . . .

ENDP ; End of program

INTERRUPT VECTOR ADDRESS (0008H)

A 1-word vector address area is used to execute interrupt request. If any interrupt service executes, the program counter (PC) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. Users have to define the interrupt vector. The following example shows the way to define the interrupt vector in the program memory.

Programming Tip: Defining Interrupt Vector (Example 1) CHIP SN8P1602B

.DATA PFLAGBUF .CODE

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0004H ~ 0007H are reserved

ORG 8

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag B0MOV A, PFLAG B0MOV PFLAGBUF, A ; Save PFLAG register in a buffer . . B0MOV A, PFLAGBUF B0MOV PFLAG, A ; Restore PFLAG register from buffer B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag RETI ; End of interrupt service routine

START: ; The head of user program.

. ; User program . JMP START ; End of user program

ENDP

; End of program

; Interrupt service routine

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SN8P1602B

8-Bit Micro-Controller

Programming Tip: Defining Interrupt Vector (Example 2) CHIP SN8P1602B

.DATA PFLAGBUF .CODE

ORG 0 ; 0000H JMP START ; Jump to user program address.

. ; 0001H ~ 0007H are reserved

ORG 08 JMP MY_IRQ ; 0008H, Jump to interrupt service routine address

ORG 10H START: ; 0010H, The head of user program.

. ; User program . . JMP START ; End of user program

MY_IRQ: ;The head of interrupt service routine

B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag B0MOV A, PFLAG B0MOV PFLAGBUF, A ; Save PFLAG register in a buffer . . B0MOV A, PFLAGBUF B0MOV PFLAG, A ; Restore PFLAG register from buffer B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag RETI ; End of interrupt service routine

ENDP ; End of program

 Remark: It is easy to understand the rules of SONIX program from demo programs given above. These

points are as following:

1. The address 0000H is a “JMP” instruction to make the program starts from the beginning.

2. The 0004H~0007H are reserved. Users is NOT allow to use 0004H~0007H addresses. The default value might change from time to time during various production progress. We strongly suggest users DO NOT take this value into the Check Sum. For detailed information, please check the following Checksum Calculation section

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8-Bit Micro-Controller

CHECKSUM CALCULATION

The ROM addresses 0004H~0007H and last address are reserved area. User should avoid these addresses (0004H~0007H and last address) when calculate the Checksum value.

 Example:

The demo program shows how to avoid 0004H~0007H when calculated Checksum from 00H to the end of

user’s code MOV A,#END_USER_CODE$L B0MOV END_ADDR1,A ;save low end address to end_addr1 MOV A,#END_USER_CODE$M B0MOV END_ADDR2,A ;save middle end address to end_addr2 CLR Y ;set Y to 00H CLR Z ;set Z to 00H @@: CALL YZ_CHECK ;call function of check yz value MOVC ; B0BSET FC ;clear C flag ADD DATA1,A ;add A to Data1 MOV A,R ADC DATA2,A ;add R to Data2 JMP END_CHECK ;check if the YZ address = the end of code AAA: INCMS Z ;Z=Z+1 JMP @B ;if Z!= 00H calculate to next address JMP Y_ADD_1 ;if Z=00H increase Y END_CHECK: MOV A,END_ADDR1 CMPRS A,Z ;check if Z = low end address JMP AAA ;if Not jump to checksum calculate MOV A,END_ADDR2 CMPRS A,Y ;if Yes, check if Y = middle end address JMP AAA ;if Not jump to checksum calculate JMP CHECKSUM_END ;if Yes checksum calculated is done. YZ_CHECK: ;check if YZ=0004H MOV A,#04H CMPRS A,Z ;check if Z=04H RET ;if Not return to checksum calculate MOV A,#00H CMPRS A,Y ;if Yes, check if Y=00H RET ;if Not return to checksum calculate INCMS Z ;if Yes, increase 4 to Z INCMS Z INCMS Z INCMS Z RET ;set YZ=0008H then return Y_ADD_1: INCMS Y ;increase Y NOP JMP @B ;jump to checksum calculate CHECKSUM_END: ………. ………. END_USER_CODE: ;Label of program end

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GENERAL PURPOSE PROGRAM MEMORY AREA

The ROM location 0009H~03FEH are used as general-purpose memory. The area is to store both instruction’s op-code and look-up table data. The SN8P1602B includes jump table function by using program counter (PC) and look-up table function by using ROM code registers (R, Y, Z).

The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table function and look-up table function, the program counter can’t leap over the boundary by program counter automatically. Users need to modify the PCH value to “PCH+1” when the PCL overflows (from 0FFH to 000H).

LOOK-UP TABLE DESCRIPTION

In the ROM’s data lookup function, Y register is pointed to the bit 8~bit 15 and Z register to the bit 0~bit 7 data of ROM address. After MOVC instruction is executed, the low-byte data will be stored in ACC and high-byte data stored in R register.

 Example: To look up the ROM data located “TABLE1”. B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address

B0MOV Z, #TABLE1$L ; To set lookup table1’s low address. MOVC ; To lookup data, R = 00H, ACC = 35H ;

; @@: MOVC ; To lookup data, R = 51H, ACC = 05H. . . ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H ; “ DW 2012H ; “

 CAUSION: The Y register will not increase automatically when Z register crosses boundary from 0xFF to

0x00. Therefore, user must take care such situation to avoid loop-up table errors. If Z register

overflows, Y register must be added one. The following INC_YZ macro shows a simple method to process

Y and Z registers automatically.

 Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users

can omit “B0MOV X, #TABLE1$H”. SONiX ICE supports larger program memory addressing capability.

Please be sure that X register is “0” to avoid unpredicted error in loop-up table operation.

INCMS Z ; Z+1 JMP @F ; Not overflow INCMS Y ; Z overflow (FFH  00),  Y=Y+1 NOP ;

; Increment the index address for next address

 Example: INC_YZ Macro

INC_YZ MACRO INCMS Z ; Z+1 JMP @F ; Not overflow

INCMS Y ; Y+1 NOP ; Not overflow @@: ENDM

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The other example of loop-up table is to add Y or Z index register by accumulator. Please be careful if “carry” happen.

 Example: Increase Y and Z register by B0ADD/ADD instruction

B0MOV Y, #TABLE1$M ; To set lookup table’s middle address. B0MOV Z, #TABLE1$L ; To set lookup table’s low address.

GETDATA: ; MOVC ; To lookup data. If BUF = 0, data is 0x0035 ; If BUF = 1, data is 0x5105 ; If BUF = 2, data is 0x2012 . . . . ; TABLE1: DW 0035H ; To define a word (16 bits) data. DW 5105H ; “ DW 2012H ; “

B0MOV A, BUF ; Z = Z + BUF. B0ADD Z, A

B0BTS1 FC ; Check the carry flag. JMP GETDATA ; FC = 0 INCMS Y ; FC = 1. Y+1. NOP

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JUMP TABLE DESCRIPTION

The jump table operation is one of multi-address jumping function. Add low-byte program counter (PCL) and ACC value to get one new PCL. The new program counter (PC) points to a series jump instructions as a listing table. It is easy to make a multi-jump program depends on the value of the accumulator (A).

When carry flag occurs after executing of “ADD PCL, A”, it will not affect PCH register. Users have to check if the jump table crosses over the ROM page boundary or the listing file generated by SONIX assembly software. We suggest users to place the jump table at the beginning of the program memory page (xx00H) to avoid errors to occur when editing the program.

 Example :

ORG 0X0100 ; The jump table is from the head of the ROM boundary B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed.

JMP A0POINT ; ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT

In following example, the jump table starts at 0x00FD. When execute B0ADD PCL, A. If ACC = 0 or 1, the jump table points to the right address. If the ACC is larger then 1 will cause error because PCH doesn't increase one automatically. We can see the PCL = 0 when ACC = 2 but the PCH still keep in 0. The program counter (PC) will enter the wrong address 0x0000 and the system will be in a unexpected operation mode. It is important to check whether the jump table crosses over the boundary (xxFFH to xx00H). A good coding style is to put the jump table at the start of ROM boundary (e.g. 0100H).

 Example (Incorrect): If the “jump table” crosses over ROM boundary, the program will cause the

errors to occur.

ROM Address

. . . .

. . 0X00FD 0X00FE

0X00FF 0X0100 0X0101

. .

SONIX provides a macro for safe jump table function. This macro will check the ROM boundary and move the jump table to the right position automatically. The side effect of this macro maybe wastes some ROM size.

@JMP_A MACRO VAL IF (($+1) !& 0XFF00) !!= (($+(VAL)) !& 0XFF00) JMP ($ | 0XFF) ORG ($ | 0XFF) ENDIF ADD PCL, A ENDM

 Note: “VAL” is the number of the jump table listing number.

B0ADD PCL, A ; PCL = PCL + ACC, the PCH can’t be changed. JMP A0POINT ; ACC = 0 JMP A1POINT ; ACC = 1 JMP A2POINT ; ACC = 2  jump table cross boundary here JMP A3POINT ; ACC = 3

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SN8P1602B

8-Bit Micro-Controller

 Example: “@JMP_A” application in SONIX macro file called “MACRO3.H”.

B0MOV A, BUF0 ; “BUF0” is from 0 to 4. @JMP_A 5 ; The number of the jump table listing is five. JMP A0POINT ; If ACC = 0, jump to A0POINT JMP A1POINT ; ACC = 1, jump to A1POINT JMP A2POINT ; ACC = 2, jump to A2POINT JMP A3POINT ; ACC = 3, jump to A3POINT JMP A4POINT ; ACC = 4, jump to A4POINT

If the jump table position is from 00FDH to 0101H, the “@JMP_A” macro will make the jump table to start from 0100h.

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SN8P1602B

8-Bit Micro-Controller

DATA MEMORY (RAM)

OVERVIEW

The SN8P1602B has internally built-in data memory up to 48 bytes for storing the general-purpose data.  48 * 8-bit RAM The memory is separated into bank 0. The bank 0 uses the first 48 bytes as general-purpose area, and the remaining

128 bytes area as system register.

BANK 0

SN8P1602B

000h

“ “ “ “

“ 02Fh 080h

“

“ 0FFh

RAM location

General purpose area

System register

End of bank 0 area

000h~02FH/07FH of Bank 0 store general-purpose data (48 bytes /128bytes).

080h~0FFh of Bank 0 store system registers (128 bytes).

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8-Bit Micro-Controller

WORKING REGISTERS

These Y,Z registers can be used as the general-purpose working buffer or access ROM’s and RAM’s data. For instance, all of the ROM table can be looked-up by Y and Z registers. The data of RAM memory can be indirectly accessed with Y and Z registers.

Y, Z REGISTERS

The Y and Z registers are the 8-bit buffers. There are three major functions of these registers.

 can be used as general working registers  can be used as RAM data pointers with @YZ register  can be used as ROM data pointer with the MOVC instruction for look-up table

084H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Y

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Z

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

After reset 0 0 0 0 0 0 0 0

 Example: uses YZ register as the data pointer to access data in the RAM address 025H of bank0.

B0MOV Y, #00H ; To set RAM bank 0 for Y register B0MOV Z, #25H ; To set location 25H for Z register B0MOV A, @YZ ; To read a data into ACC

 Example: uses the YZ register as data pointer to clear the RAM data

B0MOV Y, #0 ; Y = 0, bank 0 B0MOV Z, #07FH ; Y = 7FH, the last address of the data memory area

CLR_YZ_BUF: CLR @YZ ; Clear @YZ to be zero

DECMS Z ; Z – 1, if Z= 0, finish the routine JMP CLR_YZ_BUF ; Not zero

CLR @YZ END_CLR: ; End of clear general purpose data memory area of bank 0 .

YBIT7 YBIT6 YBIT5 YBIT4 YBIT3 YBIT2 YBIT1 YBIT0

ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0

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SONIX SN8P1602BP, SN8P1602BS, SN8P1602BX Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

PRODUCT OVERVIEW

GENERAL DESCRIPTION

UPGRADE FROM SN8P1602/SN8P1603/SN8P1602A

FEATURES

SELECTION TABLE

SYSTEM BLOCK DIAGRAM

PIN ASSIGNMENT

PIN DESCRIPTIONS

PIN CIRCUIT DIAGRAMS

CODE OPTION TABLE

SN8P1602B

ADDRESS SPACES

PROGRAM MEMORY (ROM)

OVERVIEW

USER RESET VECTOR ADDRESS (0000H)

INTERRUPT VECTOR ADDRESS (0008H)

CHECKSUM CALCULATION

GENERAL PURPOSE PROGRAM MEMORY AREA

LOOK-UP TABLE DESCRIPTION

JUMP TABLE DESCRIPTION

DATA MEMORY (RAM)

OVERVIEW

WORKING REGISTERS

Y, Z REGISTERS