SONIX SN32F769, SN32F767, SN32F759, SN32F768, SN32F757 User Manual

SN32F760 Series

SSO

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32-Bit Cortex-M0 Micro-Controller

SN32F760/750 Series

USER’S MANUAL

SN32F769/759 SN32F768/758 SN32F767/757 SN32F766/756 SN32F765/755

SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part.

SONiX TECHNOLOGY CO., LTD Page 1 Version 2.0

SN32F760 Series

Version

Date

Description

1.0

2014/02/27

First version released.

1.1

2014/05/23

1. Fix typing errors.

2. Update 23.3 Marking Example section.

3. Update SN-LINK-V2 photos.

1.2

2015/03/06

1. Update GPIO & LCD driver characteristics in Chap 20 Electrical Characteristic.

2. Fix typing error in 16.8 LCD DISPLAY MEMORY MAP

3. Add notice for power input pads.

4. Fix typing errors.

1.3

2015/05/29

1. Update QFN46 package information.

2. Update UART baud rate sample.

1.4

2015/08/21

1. Add Note for P2.n GPIO setting if ADC function is used.

2. Update PLL recommend input/output frequency setting table.

1.5

2016/07/22

1. Fix typing errors.

2. Add Notice: HCLK MUST be equal or less than 24MHz during Flash program and erase operations.

3. Update LQFP48 package information.

1.6

2016/12/02

1. Fix typing errors.

2. Remove SN32F74X & SN32F73X.

3. Remove SYSTICKPRE[1:0]

1.7

2017/06/05

1. Remove SYS0_ANTIEFT register.

2. Fix Deep Sleep mode wake up time.

3. Update SN-LINK-V3.0 information.

1.8

2017/07/14

1. Update WDTPRE[2:0] bits description in SYS1_APBCP1 register.

2. Update TO[15:0] bits description in I2Cn_TOCTRL register.

1.9

2017/12/21

1. Update LCD drive waveform.

2. Add Note for setting the pins which are not pin-out.

2.0

2018/10/05

1. Add Boot pin description.

2. Fix maximum F

ADCLK

to 16MHz in Electrical Characteristics.

32-Bit Cortex-M0 Micro-Controller

AMENDENT HISTORY

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Table of Content

AMENDENT HISTORY ................................................................................................................................ 2

PRODUCT OVERVIEW ....................................................................................................................... 14

1.1 FEATURES ...................................................................................................................................... 14

1.2 SYSTEM BLOCK DIAGRAM ........................................................................................................ 16

1.3 CLOCK GENERATION BLOCK DIAGRAM ................................................................................ 17

1.4 PIN ASSIGNMENT ......................................................................................................................... 18

1.5 PIN DESCRIPTIONS ....................................................................................................................... 23

1.6 PIN CIRCUIT DIAGRAMS ............................................................................................................. 28

CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 30

2.1 MEMORY MAP ............................................................................................................................... 30

2.2 SYSTEM TICK TIMER ................................................................................................................... 31

2.2.1 OPERATION ............................................................................................................................ 31

2.2.2 SYSTICK USAGE HINTS AND TIPS ....................................................................................... 32

2.2.3 SYSTICK REGISTERS .............................................................................................................. 32

2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL) ................................... 32

2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD) ........................................... 32

2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL) ............................................ 33

2.2.3.4 System Tick Timer Calibration Value register (SYSTICK_CALIB) .................................. 33

2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC) ..................................................... 34

2.3.1 INTERRUPT AND EXCEPTION VECTORS ........................................................................... 34

2.3.2 NVIC REGISTERS .................................................................................................................... 35

2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER) ....................................................... 35

2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER) ................................................... 35

2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR) ..................................................... 36

2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR) ................................................. 36

2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7) ............................................... 36

2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC) .................................................. 37

2.5 CODE OPTION TABLE .................................................................................................................. 38

2.6 CORE REGISTER OVERVIEW ..................................................................................................... 39

SYSTEM CONTROL............................................................................................................................. 40

3.1 RESET .............................................................................................................................................. 40

3.1.1 POWER-ON RESET (POR) ...................................................................................................... 40

3.1.2 WATCHDOG RESET (WDT RESET) ....................................................................................... 41

3.1.3 BROWN-OUT RESET............................................................................................................... 41

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3.1.3.1 BROWN OUT DESCRIPTION ........................................................................................... 41

3.1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION ............................................... 42

3.1.3.3 BROWN-OUT RESET IMPROVEMENT .......................................................................... 42

3.1.4 EXTERNAL RESET .................................................................................................................. 43

3.1.4.1 SIMPLY RC RESET CIRCUIT ........................................................................................... 44

3.1.4.2 DIODE & RC RESET CIRCUIT ......................................................................................... 44

3.1.4.3 ZENER DIODE RESET CIRCUIT ...................................................................................... 45

3.1.4.4 VOLTAGE BIAS RESET CIRCUIT ................................................................................... 45

3.1.4.5 EXTERNAL RESET IC ....................................................................................................... 46

3.1.5 SOFTWARE RESET ................................................................................................................. 46

3.2 SYSTEM CLOCK ............................................................................................................................ 47

3.2.1 INTERNAL RC CLOCK SOURCE ........................................................................................... 47

3.2.1.1 Internal High-speed RC Oscillator (IHRC) .......................................................................... 47

3.2.1.2 Internal Low-speed RC Oscillator (ILRC) ........................................................................... 47

3.2.2 PLL ........................................................................................................................................... 48

3.2.2.1 PLL Frequency selection ...................................................................................................... 48

3.2.3 EXTERNAL CLOCK SOURCE ................................................................................................ 49

3.2.3.1 External High-speed (EHS) Clock ....................................................................................... 49

3.2.3.2 CRYSTAL/CERAMIC ......................................................................................................... 49

3.2.3.3 External Low-speed (ELS) Clock......................................................................................... 50

3.2.3.4 CRYSTAL ............................................................................................................................ 50

3.2.3.5 Bypass Mode ........................................................................................................................ 50

3.2.4 SYSTEM CLOCK (SYSCLK) SELECTION............................................................................... 51

3.2.5 CLOCK-OUT CAPABITITY ..................................................................................................... 51

3.3 SYSTEM CONTROL REGISTERS 0 .............................................................................................. 52

3.3.1 Analog Block Control register (SYS0_ANBCTRL) ................................................................... 52

3.3.2 PLL control register (SYS0_PLLCTRL) ................................................................................... 52

3.3.2.1 RECOMMEND FREQUENCY SETTING.......................................................................... 53

3.3.3 Clock Source Status register (SYS0_CSST) .............................................................................. 53

3.3.4 System Clock Configuration register (SYS0_CLKCFG) .......................................................... 54

3.3.5 AHB Clock Prescale register (SYS0_AHBCP) ......................................................................... 54

3.3.6 System Reset Status register (SYS0_RSTST) ............................................................................ 55

3.3.7 LVD Control register (SYS0_LVDCTRL) ................................................................................. 55

3.3.8 External RESET Pin Control register (SYS0_EXRSTCTRL) ................................................... 56

3.3.9 SWD Pin Control register (SYS0_SWDCTRL) ......................................................................... 56

3.4 SYSTEM CONTROL REGISTERS 1 .............................................................................................. 57

3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN) .................................................................... 57

3.4.2 APB Clock Prescale register 0 (SYS1_APBCP0) ..................................................................... 58

3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1) ..................................................................... 59

3.4.4 APB Clock Prescale register 2 (SYS1_APBCP2) ..................................................................... 61

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3.4.5 Peripheral Reset register (SYS1_PRST) ................................................................................... 61

3.4.6 Divider Dividend register (SYS1_DIVIDEND) ........................................................................ 63

3.4.7 Divider Divisor register (SYS1_DIVISOR) .............................................................................. 63

3.4.8 Divider Quotient register (SYS1_QUOTIENT) ........................................................................ 63

3.4.9 Divider Remainder register (SYS1_REMAINDER) .................................................................. 63

3.4.10 Divider Control register (SYS1_DIVCTRL) ............................................................................. 64

SYSTEM OPERATION MODE ........................................................................................................... 65

4.1 OVERVIEW ..................................................................................................................................... 65

4.2 NORMAL MODE ............................................................................................................................ 65

4.3 LOW-POWER MODES ................................................................................................................... 65

4.3.1 SLEEP MODE .......................................................................................................................... 65

4.3.2 DEEP-SLEEP MODE............................................................................................................... 66

4.3.3 DEEP POWER-DOWN (DPD) MODE .................................................................................... 66

4.3.3.1 Entering Deep power-down mode ........................................................................................ 67

4.3.3.2 Exiting Deep power-down mode .......................................................................................... 67

4.4 WAKEUP ......................................................................................................................................... 68

4.4.1 OVERVIEW .............................................................................................................................. 68

4.4.2 WAKEUP TIME ........................................................................................................................ 68

4.5 STATE MACHINE OF PMU ........................................................................................................... 69

4.6 OPERATION MODE COMPARSION TABLE .............................................................................. 70

4.7 PMU REGISTERS ........................................................................................................................... 71

4.7.1 Backup registers 0~15 (PMU_BKP0~15) ................................................................................ 71

4.7.2 Power Control register (PMU_CTRL) ..................................................................................... 71

4.7.3 I/O Latch Control register 1 (PMU_LATCHCTRL1)............................................................... 71

4.7.4 I/O Latch Control register 2 (PMU_LATCHCTRL2)............................................................... 72

4.7.5 I/O Latch Status register (PMU_LATCHST)............................................................................ 72

GENERAL PURPOSE I/O PORT (GPIO) .......................................................................................... 73

5.1 OVERVIEW ..................................................................................................................................... 73

5.2 GPIO MODE .................................................................................................................................... 73

5.3 GPIO REGISTERS ........................................................................................................................... 74

5.3.1 GPIO Port n Data register (GPIOn_DATA) (n=0,1,2,3)......................................................... 74

5.3.2 GPIO Port n Mode register (GPIOn_MODE) (n=0,1,2,3) ...................................................... 74

5.3.3 GPIO Port n Configuration register (GPIOn_CFG) (n=0,1,2,3) ............................................ 74

5.3.4 GPIO Port n Interrupt Sense register (GPIOn_IS) (n=0,1,2,3) ............................................... 76

5.3.5 GPIO Port n Interrupt Both-edge Sense register (GPIOn_IBS) (n=0,1,2,3) ........................... 76

5.3.6 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3) ............................................ 76

5.3.7 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3) ............................................ 76

5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3) ................................... 77

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5.3.9 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3) .............................................. 77

5.3.10 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3) .................................... 77

5.3.11 GPIO Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3) ............................... 77

5.3.12 GPIO Port n Open-Drain Control register (GPIOn_ODCTRL) (n=0,1,2,3) .......................... 78

PERIPHERAL FUNCTION PIN ASSIGNMENT (PFPA) ................................................................ 79

6.1 OVERVIEW ..................................................................................................................................... 79

6.2 FEATURES ...................................................................................................................................... 79

6.3 PIN ASSIGNMENT LIST ................................................................................................................ 79

6.4 PFPA REGISTERS........................................................................................................................... 80

6.4.1 PFPA for UART register (PFPA_UART) ................................................................................. 80

6.4.2 PFPA for I2C register (PFPA_I2C) ......................................................................................... 81

6.4.3 PFPA for SSP register (PFPA_SSP) ........................................................................................ 82

6.4.4 PFPA for I2S register (PFPA_I2S) .......................................................................................... 83

6.4.5 PFPA for CT16B0 register (PFPA_CT16B0) .......................................................................... 84

6.4.6 PFPA for CT16B1 register (PFPA_CT16B1) .......................................................................... 85

6.4.7 PFPA for CT16B2 register (PFPA_CT16B2) .......................................................................... 86

6.4.8 PFPA for CT32B0 register (PFPA_CT32B0) .......................................................................... 86

6.4.9 PFPA for CT32B1 register (PFPA_CT32B1) .......................................................................... 87

6.4.10 PFPA for CT32B2 register (PFPA_CT32B2) .......................................................................... 88

14+1 CHANNEL ANALOG TO DIGITAL CONVERTOR (ADC) .................................................. 90

7.1 OVERVIEW ..................................................................................................................................... 90

7.2 ADC CONVERTING TIME ............................................................................................................ 91

7.3 ADC CONTROL NOTICE ............................................................................................................... 92

7.3.1 ADC SIGNAL ............................................................................................................................ 92

7.3.2 ADC PROGRAM ...................................................................................................................... 92

7.4 ADC CIRCUIT ................................................................................................................................. 92

7.5 TEMPERATURE SENSOR (TS) ..................................................................................................... 93

7.6 ADC REGISTERS ............................................................................................................................ 94

7.6.1 ADC Management register (ADC_ADM)................................................................................. 94

7.6.2 ADC Data register (ADC_ADB) .............................................................................................. 95

7.6.3 Port 2 Control register (ADC_P2CON) ................................................................................... 95

7.6.4 ADC Interrupt Enable register (ADC_IE)................................................................................ 96

7.6.5 ADC Raw Interrupt Status register (ADC_RIS) ....................................................................... 96

16-BIT TIMER WITH CAPTURE FUNCTION ................................................................................ 97

8.1 OVERVIEW ..................................................................................................................................... 97

8.2 FEATURES ...................................................................................................................................... 97

8.3 PIN DESCRIPTION ......................................................................................................................... 97

8.4 BLOCK DIAGRAM ......................................................................................................................... 98

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8.5 TIMER OPERATION ...................................................................................................................... 99

8.5.1 Edge-aligned Up-counting Mode ............................................................................................. 99

8.5.2 Edge-aligned Down-counting Mode ....................................................................................... 100

8.5.3 Center-aligned Counting Mode .............................................................................................. 100

8.6 PWM ............................................................................................................................................... 101

8.6.1 PWM Mode 1 .......................................................................................................................... 101

8.6.2 PWM Mode 2 .......................................................................................................................... 102

8.7 CT16BN REGISTERS .................................................................................................................... 104

8.7.1 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,1,2) ........................................ 104

8.7.2 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1,2) .................................................... 104

8.7.3 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1,2) ............................................................ 105

8.7.4 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1,2) ................................................ 105

8.7.5 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0,1,2) ......................................... 105

8.7.6 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0,1,2) ............................................ 106

8.7.7 CT16Bn Match register 0~3 (CT16Bn_MR0~3) (n=0,1,2) .................................................... 107

8.7.8 CT16Bn Capture Control register (CT16Bn_CAPCTRL) (n=0,1,2) ..................................... 107

8.7.9 CT16Bn Capture 0 register (CT16Bn_CAP0) (n=0,1,2) ....................................................... 107

8.7.10 CT16Bn External Match register (CT16Bn_EM) (n=0,1,2) ............................................... 108

8.7.11 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=0,1,2) ........................................ 108

8.7.12 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0,1,2) ............................... 109

8.7.13 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,1,2) .......................................... 110

32-BIT TIMER WITH CAPTURE FUNCTION .............................................................................. 111

9.1 OVERVIEW ................................................................................................................................... 111

9.2 FEATURES .................................................................................................................................... 111

9.3 PIN DESCRIPTION ....................................................................................................................... 111

9.4 BLOCK DIAGRAM ....................................................................................................................... 112

9.5 TIMER OPERATION .................................................................................................................... 113

9.5.1 Edge-aligned Up-counting Mode ........................................................................................... 113

9.5.2 Edge-aligned Down-counting Mode ....................................................................................... 114

9.5.3 Center-aligned Counting Mode .............................................................................................. 114

9.6 PWM ............................................................................................................................................... 115

9.6.1 PWM Mode 1 .......................................................................................................................... 115

9.6.2 PWM Mode 2 .......................................................................................................................... 116

9.7 CT32BN REGISTERS .................................................................................................................... 118

9.7.1 CT32Bn Timer Control register (CT32Bn_TMRCTRL) (n=0,1,2) ........................................ 118

9.7.2 CT32Bn Timer Counter register (CT32Bn_TC) (n=0,1,2) .................................................... 118

9.7.3 CT32Bn Prescale register (CT32Bn_PRE) (n=0,1,2) ............................................................ 119

9.7.4 CT32Bn Prescale Counter register (CT32Bn_PC) (n=0,1,2) ................................................ 119

9.7.5 CT32Bn Count Control register (CT32Bn_CNTCTRL) (n=0,1,2) ......................................... 119

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9.7.6 CT32Bn Match Control register (CT32Bn_MCTRL) (n=0,1,2) ............................................ 120

9.7.7 CT32Bn Match register 0~3 (CT32Bn_MR0~3) (n=0,1,2) .................................................... 120

9.7.8 CT32Bn Capture Control register (CT32Bn_CAPCTRL) (n=0,1,2) ..................................... 121

9.7.9 CT32Bn Capture 0 register (CT32Bn_CAP0) (n=0,1,2) ....................................................... 121

9.7.10 CT32Bn External Match register (CT32Bn_EM) (n=0,1,2) .................................................. 121

9.7.11 CT32Bn PWM Control register (CT32Bn_PWMCTRL) (n=0,1,2) ........................................ 122

9.7.12 CT32Bn Timer Raw Interrupt Status register (CT32Bn_RIS) (n=0,1,2) ............................... 123

9.7.13 CT32Bn Timer Interrupt Clear register (CT32Bn_IC) (n=0,1,2) .......................................... 124

WATCHDOG TIMER (WDT) ........................................................................................................ 125

10.1 OVERVIEW ................................................................................................................................... 125

10.2 BLOCK DIAGRAM ....................................................................................................................... 126

10.3 WDT REGISTERS ......................................................................................................................... 127

10.3.1 Watchdog Configuration register (WDT_CFG) ..................................................................... 127

10.3.2 Watchdog Clock Source register (WDT_CLKSOURCE) ....................................................... 127

10.3.3 Watchdog Timer Constant register (WDT_TC)...................................................................... 127

10.3.4 Watchdog Feed register (WDT_FEED) ................................................................................. 128

REAL-TIME CLOCK (RTC) ......................................................................................................... 129

11.1 OVERVIEW ................................................................................................................................... 129

11.2 FEATURES .................................................................................................................................... 129

11.3 FUNCTIONAL DESCRIPTION .................................................................................................... 129

11.3.1 INTRODUCTION ................................................................................................................... 129

11.3.2 RESET RTC REGISTERS ....................................................................................................... 129

11.3.3 RTC FLAG ASSERTION ........................................................................................................ 129

11.3.4 RTC OPERATION .................................................................................................................. 130

11.4 BLOCK DIAGRAM ....................................................................................................................... 131

11.5 RTC REGISTERS .......................................................................................................................... 132

11.5.1 RTC Control register (RTC_CTRL) ....................................................................................... 132

11.5.2 RTC Clock Source Select register (RTC_CLKS) .................................................................... 132

11.5.3 RTC Interrupt Enable register (RTC_IE) ............................................................................... 132

11.5.4 RTC Raw Interrupt Status register (RTC_RIS) ...................................................................... 132

11.5.5 RTC Interrupt Clear register (RTC_IC) ................................................................................. 133

11.5.6 RTC Second Counter Reload Value register (RTC_SECCNTV) ............................................ 133

11.5.7 RTC Second Count register (RTC_SECCNT) ........................................................................ 133

11.5.8 RTC Alarm Counter Reload Value register (RTC_ALMCNTV) ............................................. 133

11.5.9 RTC Alarm Count register (RTC_ALMCNT) ......................................................................... 134

SPI/SSP .............................................................................................................................................. 135

12.1 OVERVIEW ................................................................................................................................... 135

12.2 FEATURES .................................................................................................................................... 135

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12.3 PIN DESCRIPTION ....................................................................................................................... 135

12.4 INTERFACE DESCRIPTION ....................................................................................................... 136

12.4.1 SPI .......................................................................................................................................... 136

12.4.2 SSI ........................................................................................................................................... 137

12.4.3 COMMUNICATION FLOW ................................................................................................... 137

12.4.3.1 SINGLE-FRAME ........................................................................................................... 137

12.4.3.2 MULTI-FRAME ............................................................................................................ 138

12.5 AUTO-SEL ..................................................................................................................................... 138

12.6 SSP REGISTERS ........................................................................................................................... 139

12.6.1 SSP n Control register 0 (SSPn_CTRL0) (n=0,1) .................................................................. 139

12.6.2 SSP n Control register 1 (SSPn_CTRL1) (n=0,1) .................................................................. 140

12.6.3 SSP n Clock Divider register (SSPn_CLKDIV) (n=0,1) ........................................................ 140

12.6.4 SSP n Status register (SSPn_STAT) (n=0,1) .......................................................................... 140

12.6.5 SSP n Interrupt Enable register (SSPn_IE) (n=0,1) .............................................................. 141

12.6.6 SSP n Raw Interrupt Status register (SSPn_RIS) (n=0,1) ...................................................... 141

12.6.7 SSP n Interrupt Clear register (SSPn_IC) (n=0,1) ................................................................ 142

12.6.8 SSP n Data register (SSPn_DATA) (n=0,1) ........................................................................... 142

12.6.9 SSP n Data Fetch register (SSPn_DF) (n=0,1) ..................................................................... 142

I2C ...................................................................................................................................................... 143

13.1 OVERVIEW ................................................................................................................................... 143

13.2 FEATURES .................................................................................................................................... 143

13.3 PIN DESCRIPTION ....................................................................................................................... 144

13.4 WAVE CHARACTERISTICS ....................................................................................................... 144

13.5 I2C MASTER MODES .................................................................................................................. 145

13.5.1 MASTER TRANSMITTER MODE .......................................................................................... 145

13.5.2 MASTER RECEIVER MODE ................................................................................................. 145

13.5.3 ARBITRATION ....................................................................................................................... 145

13.6 I2C SLAVE MODES ...................................................................................................................... 146

13.6.1 SLAVE TRANSMITTER MODE ............................................................................................. 146

13.6.2 SLAVE RECEIVER MODE .................................................................................................... 146

13.7 MONITOR MODE ......................................................................................................................... 147

13.7.1 INTERRUPT ........................................................................................................................... 147

13.7.2 LOSS of ARBITRATION ......................................................................................................... 147

13.8 I2C REGISTERS ............................................................................................................................ 148

13.8.1 I2C n Control register (I2Cn_CTRL) (n=0,1) ........................................................................ 148

13.8.2 I2C n Status register (I2Cn_STAT) (n=0,1) ........................................................................... 149

13.8.3 I2C n TX Data register (I2Cn_TXDATA) (n=0,1) ................................................................. 150

13.8.4 I2C n RX Data register (I2Cn_RXDATA) (n=0,1) ................................................................. 150

13.8.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0,1) ................................................. 150

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13.8.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0,1) ........................................ 150

13.8.7 I2C n SCL High Time register (I2Cn_SCLHT) (n=0,1) ......................................................... 151

13.8.8 I2C n SCL Low Time register (I2Cn_SCLLT) (n=0,1) ........................................................... 151

13.8.9 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0,1) .................................................... 151

13.8.10 I2C n Monitor Mode Control register (I2Cn_MMCTRL) (n=0,1) ..................................... 151

UNIVERSAL SYNCHRONOUS AND ASYNCHRONOUS RECEIVER AND TRANSMITTER

(USART) ........................................................................................................................................................ 153

14.1 OVERVIEW ................................................................................................................................... 153

14.2 FEATURES .................................................................................................................................... 153

14.3 PIN DESCRIPTION ....................................................................................................................... 153

14.4 BLOCK DIAGRAM ....................................................................................................................... 154

14.5 EIA-485/RS-485 MODES .............................................................................................................. 155

14.5.1 RS-485/EIA-485 NORMAL MULTIDROP MODE (NMM) .................................................... 155

14.5.2 RS-485/EIA-485 AUTO ADDRESS DETECTION (AAD) MODE ......................................... 155

14.5.3 RS-485/EIA-485 AUTO DIRECTION CONTROL (ADC) ...................................................... 155

14.5.4 RS485/EIA-485 DRIVER DELAY TIME................................................................................. 156

14.5.5 RS485/EIA-485 OUTPUT INVERSION ................................................................................. 156

14.5.6 RS485/EIA-485 FRAME STRUCTURE .................................................................................. 156

14.6 BAUD RATE CALCULATION .................................................................................................... 156

14.7 MODEM CONTROL (MC)............................................................................................................ 158

14.7.1 AUTO-RTS .............................................................................................................................. 158

14.7.2 AUTO-CTS.............................................................................................................................. 159

14.8 AUTO-BAUD FLOW .................................................................................................................... 159

14.8.1 AUTO-BAUD .......................................................................................................................... 159

14.8.2 AUTO-BAUD MODES ........................................................................................................... 160

14.9 SMART CARD MODE .................................................................................................................. 161

14.9.1 SMART CARD SETUP PROCEDURE ................................................................................... 161

14.10 SYNCHRONOUS MODE .......................................................................................................... 162

14.11 USART REGISTERS ................................................................................................................. 164

14.11.1 USART n Receiver Buffer register (USARTn_RB) (n=0,1) ................................................ 164

14.11.2 USART n Transmitter Holding register (USARTn_TH) (n=0,1) ........................................ 164

14.11.3 USART n Divisor Latch LSB registers (USARTn_DLL) (n =0,1) ...................................... 164

14.11.4 USART n Divisor Latch MSB register (USARTn_DLM) (n=0,1) ...................................... 164

14.11.5 USART n Interrupt Enable register (USARTn_IE) (n=0,1) ............................................... 165

14.11.6 USART n Interrupt Identification register (USARTn_II) (n=0,1) ...................................... 165

14.11.7 USART n Line Status register (USARTn_LS) (n=0,1) ........................................................ 167

14.11.8 USART n FIFO Control register (USARTn_FIFOCTRL) (n=0,1)..................................... 168

14.11.9 USART n Line Control register (USARTn_LC) (n=0,1) .................................................... 168

14.11.10 USART n Modem Control register (USARTn_MC) (n=0,1) .............................................. 169

SONiX TECHNOLOGY CO., LTD Page 10 Version 2.0

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14.11.11 USART n Modem Status register (USARTn_MS) (n=0,1) .................................................. 169

14.11.12 USART n Scratch Pad register (USARTn_SP) (n=0,1) ...................................................... 170

14.11.13 USART n Auto-baud Control register (USARTn_ABCTRL) (n=0,1) ................................. 170

14.11.14 USART n Fractional Divider register (USARTn_FD) (n=0,1) .......................................... 170

14.11.15 USART n Control register (USARTn_CTRL) (n=0,1) ........................................................ 171

14.11.16 USART n Half-duplex Enable register (USARTn_HDEN) (n=0,1) ................................... 172

14.11.17 USART n Smart card Interface Control register (USARTn_SCICTRL) (n=0,1) ............... 172

14.11.18 USART n RS485 Control register (USARTn_RS485CTRL) (n=0,1) .................................. 173

14.11.19 USART n RS485 Address Match register (USARTn_RS485ADRMATCH) (n=0,1) .......... 173

14.11.20 USART n RS485 Delay Value register (USARTn_RS485DLYV) (n=0,1) .......................... 173

14.11.21 USART n Synchronous Mode Control Register (USARTn_SYNCCTRL) (n=0,1) ............. 174

I2S ...................................................................................................................................................... 175

15.1 OVERVIEW ................................................................................................................................... 175

15.2 FEATURES .................................................................................................................................... 175

15.3 PIN DESCRIPTION ....................................................................................................................... 175

15.4 BLOCK DIAGRAM ....................................................................................................................... 176

15.4.1 I2S CLCOK CONTROL .......................................................................................................... 176

15.4.2 I2S BLOCK DIAGRAM .......................................................................................................... 176

15.5 FUNCTIONAL DESCRIPTION .................................................................................................... 177

15.5.1 I2S OPERATION .................................................................................................................... 177

15.5.2 I2S FIFO OPERAION ............................................................................................................ 179

15.5.2.1 MONO ............................................................................................................................ 179

15.5.2.2 STEREO ......................................................................................................................... 179

15.6 I2S REGISTERS............................................................................................................................. 180

15.6.1 I2S Control register (I2S_CTRL) ........................................................................................... 180

15.6.2 I2S Clock register (I2S_CLK) ................................................................................................. 181

15.6.3 I2S Status register (I2S_STATUS) .......................................................................................... 181

15.6.4 I2S Interrupt Enable register (I2S_IE) ................................................................................... 182

15.6.5 I2S Raw Interrupt Status register (I2S_RIS) .......................................................................... 182

15.6.6 I2S Interrupt Clear register (I2S_IC) ..................................................................................... 183

15.6.7 I2S RXFIFO register (I2S_RXFIFO) ..................................................................................... 183

15.6.8 I2S TXFIFO register (I2S_TXFIFO) ...................................................................................... 183

4X32 LCD DRIVER ......................................................................................................................... 184

16.1 OVERVIEW ................................................................................................................................... 184

16.2 FEATURES .................................................................................................................................... 184

16.3 PIN DESCRIPTION ....................................................................................................................... 184

16.4 BLOCK DIAGRAM ....................................................................................................................... 185

16.4.1 LCD CLOCK CONTROL ....................................................................................................... 185

SONiX TECHNOLOGY CO., LTD Page 11 Version 2.0

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16.4.2 LCD BLOCK DIAGRAM ........................................................................................................ 185

16.5 LCD TIMING ................................................................................................................................. 186

16.5.1 LCD Timing Table .................................................................................................................. 186

16.5.2 LCD Driver Waveform ........................................................................................................... 186

16.6 R-TYPE LCD APPLICATION CIRCUIT ...................................................................................... 188

16.7 C-TYPE LCD APPLICATION CIRCUIT ...................................................................................... 189

16.7.1 4C-TYPE ................................................................................................................................. 190

16.7.2 1C-Type .................................................................................................................................. 192

16.8 LCD DISPLAY MEMORY MAP .................................................................................................. 193

16.9 LCD REGISTERS .......................................................................................................................... 194

16.9.1 LCD Control register (LCD_CTRL)....................................................................................... 194

16.9.2 LCD Control register 1(LCD_CTRL1)................................................................................... 195

16.9.3 LCD C-Type Control register 1 (LCD_CCTRL1) .................................................................. 195

16.9.4 LCD C-Type Control register 2 (LCD_CCTRL2) .................................................................. 196

16.9.5 LCD Frame Counter Control register (LCD_FCC)............................................................... 196

16.9.6 LCD Raw Interrupt Status register (LCD_RIS) ..................................................................... 197

16.9.7 LCD SEG Memory register 0 (LCD_SEGM0) ....................................................................... 197

16.9.8 LCD SEG Memory register 1 (LCD_SEGM1) ....................................................................... 198

16.9.9 LCD SEG Memory register 2 (LCD_SEGM2) ....................................................................... 198

16.9.10 LCD SEG Memory register 3 (LCD_SEGM3) ................................................................... 198

FLASH ............................................................................................................................................... 200

17.1 OVERVIEW ................................................................................................................................... 200

17.2 EMBEDDED FLASH MEMORY .................................................................................................. 200

17.3 FEATURES .................................................................................................................................... 200

17.4 ORGANIZATION .......................................................................................................................... 201

17.5 READ ............................................................................................................................................. 201

17.6 PROGRAM/ERASE ....................................................................................................................... 201

17.7 EMBEDDED BOOT LOADER ..................................................................................................... 201

17.8 FLASH MEMORY CONTROLLER (FMC) .................................................................................. 202

17.8.1 CODE SECURITY (CS) .......................................................................................................... 202

17.8.2 PROGRAM FLASH MEMORY ............................................................................................... 203

17.8.3 ERASE .................................................................................................................................... 203

17.8.3.1 PAGE ERASE ................................................................................................................ 203

17.8.3.2 MASS ERASE ................................................................................................................ 203

17.9 READ PROTECTION .................................................................................................................... 203

17.10 HW CHECKSUM....................................................................................................................... 203

17.11 FMC REGISTERS ...................................................................................................................... 204

17.11.1 Flash Low Power Control register (FLASH_LPCTRL) ..................................................... 204

17.11.2 Flash Status register (FLASH_STATUS) ........................................................................... 204

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SN32F760 Series

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32-Bit Cortex-M0 Micro-Controller

17.11.3 Flash Control register (FLASH_CTRL) ............................................................................. 204

17.11.4 Flash Data register (FLASH_DATA) ................................................................................. 205

17.11.5 Flash Address register (FLASH_ADDR) ........................................................................... 205

17.11.6 Flash Checksum register (FLASH_CHKSUM) .................................................................. 205

SERIAL-WIRE DEBUG (SWD) ..................................................................................................... 206

18.1 OVERVIEW ................................................................................................................................... 206

18.2 FEATURES .................................................................................................................................... 206

18.3 PIN DESCRIPTION ....................................................................................................................... 206

18.4 DEBUG NOTE ............................................................................................................................... 206

18.4.1 LIMITATIONS ........................................................................................................................ 206

18.4.2 DEBUG RECOVERY .............................................................................................................. 206

18.4.3 INTERNAL PULL-UP/DOWN RESISTORS on SWD PINS ................................................... 207

DEVELOPMENT TOOL ................................................................................................................ 208

19.1 SN-LINK-V3 .................................................................................................................................. 209

19.2 SN32F760 STARTER-KIT ............................................................................................................ 210

ELECTRICAL CHARACTERISTIC ............................................................................................ 212

20.1 ABSOLUTE MAXIMUM RATING .............................................................................................. 212

20.2 ELECTRICAL CHARACTERISTIC ............................................................................................. 212

20.3 CHARACTERISTIC GRAPHS ..................................................................................................... 214

FLASH ROM PROGRAMMING PIN ........................................................................................... 216

PACKAGE INFORMATION ......................................................................................................... 217

22.1 LQFP 80 PIN .................................................................................................................................. 217

22.2 LQFP 64 PIN .................................................................................................................................. 218

22.3 LQFP 48 PIN .................................................................................................................................. 219

22.4 QFN 46 PIN .................................................................................................................................... 220

22.5 QFN 33 PIN 5X5 ............................................................................................................................. 221

MARKING DEFINITION ............................................................................................................... 222

23.1 INTRODUCTION .......................................................................................................................... 222

23.2 MARKING INDETIFICATION SYSTEM .................................................................................... 222

23.3 MARKING EXAMPLE ................................................................................................................. 223

23.4 DATECODE SYSTEM .................................................................................................................. 224

SONiX TECHNOLOGY CO., LTD Page 13 Version 2.0

SN32F760 Series

1



Memory configuration



Timer

Up to 64KB on-chip Flash programming memory.

3 16-bit and 3 32-bit general purpose timers with

Up to 8KB SRAM.

a total of 6 capture inputs and 21 PWMs.

4KB Boot ROM

 Working voltage 1.8V ~ 5.5V



Operation Frequency up to 50MHz

 ADC



Interrupt sources

14-channel 12-bit SAR ADC

ARM Cortex-M0 built-in Nested Vectored Interrupt

Temperature sensor inside

Controller (NVIC).



I/O pin configuration



Interface

Up to 64 General Purpose I/O (GPIO) pins with

-Two I2C controllers supporting I2C-bus specification

configurable pull-up/pull-down resistors.

with multiple address recognition and monitor mode.

GPIO pins can be used as edge and level sensitive

- USART controller with fractional baud rate

interrupt sources.

generation, and EIA-485 support.

High-current source driver (20 mA)

- UART controller with fractional baud rate generation.

-Two SPI controllers with SSP features and multi-



Programmable Watchdog Timer (WDT)

protocol capabilities.

Programmable watchdog frequency with watchdog

-I2S Function with mono and stereo audio data

clock source and divider.

supported, MSB justified data format supported, and

can operate as either master or slave.



System tick timer

24-bit timer.



System clocks

The system tick timer clock is fixed to the frequency of

-External high clock: Crystal type 10MHz~25MHz

the system clock.

-External low clock: Crystal type 32.768 KHz

The SysTick timer is intended to generate a fixed

-Internal high clock: RC type 12 MHz

10-ms interrupt.

-Internal low clock: RC type 32 KHz

-PLL allows CPU operation up to the maximum CPU



Hardware divider

rate without the need for a high-frequency crystal.

-Clock output function which can reflect the internal



Real-Time Clock (RTC)

high/low RC oscillator, HCLK, PLL output, and

external high/low clock.



LVD with separate thresholds

Reset: 1.65V for V

CORE



LCD driver

Reset: 1.8V/2.0V/2.4V/2.7V/3.0V/3.6V for VDD

Support both R-type and C-type

Interrupt: 1.8V/2.0V/2.4V/2.7V/3.0V/3.6V for VDD

4 common x 32 segment

1/3 or 1/2 bias voltage



Fcpu (Instruction cycle)

Multiple C-type LCD Voltage: 2.7 ~5.0V

F

CPU

= F

HCLK

= F

SYSCLK

/1, F

SYSCLK

/2, F

SYSCLK

/4, …,

R-type optional-bias resistor: 400K, 200K, 100K, 35K

F

SYSCLK

/512.

Support 1/2 duty, 1/3 duty, 1/4 duty



Operating modes



In-System Programming (ISP) supported

Normal, Sleep, Deep-sleep, Power-down, and Deep

power-down



Package (Chip form support)

LQFP 80/64/48 pin



Serial Wire Debug (SWD)

QFN 46/33 pin

32-Bit Cortex-M0 Micro-Controller

PRODUCT OVERVIEW

1.1 FEATURES

SONiX TECHNOLOGY CO., LTD Page 14 Version 2.0

SN32F760 Series

Chip

ROM

RAM

Boot

Loader

F

CPU

(Max

MHz)

TIMER

USART

SPI

I2C

I2S

PWM

12-bit

ADC

LCD

GPIO

with

Wakeup

Package SN32F769F

64KB

8KB

4KB

50 MHz

16-bitx3 32-bitx3

USARTx1

UARTx1

2 2 1

21

14CH

4x32

64

LQFP80

SN32F768F

64KB

8KB

4KB

50 MHz

16-bitx3 32-bitx3

USARTx1

UARTx1

2 2 1

21

11CH

4x28

57

LQFP64

SN32F767F

64KB

8KB

4KB

50 MHz

16-bitx3 32-bitx3

USARTx1

UARTx1

2 2 1

21

8CH

4x18

42

LQFP48

SN32F766J

64KB

8KB

4KB

50 MHz

16-bitx3 32-bitx3

USARTx1

UARTx1

2 2 1

21

7CH

4x17

40

QFN46

SN32F765J

64KB

8KB

4KB

50 MHz

16-bitx3 32-bitx3

UARTx2

2 2 -

21

4CH - 26

QFN33

SN32F759F

32KB

4KB

50 MHz

16-bitx3 32-bitx3

USARTx1

UARTx1

2 2 1

21

14CH

4x32

64

LQFP80

SN32F758F

32KB

4KB

50 MHz

16-bitx3 32-bitx3

USARTx1

UARTx1

2 2 1

21

11CH

4x28

57

LQFP64

SN32F757F

32KB

4KB

50 MHz

16-bitx3 32-bitx3

USARTx1

UARTx1

2 2 1

21

8CH

4x18

42

LQFP48

SN32F756J

32KB

4KB

50 MHz

16-bitx3 32-bitx3

USARTx1

UARTx1

2 2 1

21

7CH

4x17

40

QFN46

SN32F755J

32KB

4KB

50 MHz

16-bitx3 32-bitx3

UARTx2

2 2 -

21

4CH - 26

QFN33

32-Bit Cortex-M0 Micro-Controller

 Features Selection Table

SONiX TECHNOLOGY CO., LTD Page 15 Version 2.0

SN32F760 Series

TEST/DEBUG

INTERFACE

PIO0_0~15 PIO1_0~13 PIO2_0~15 PIO3_0~15

SWDIO

SWCLK

XTALOUT,

LXTALOUT

XTALIN,

LXTALIN

CLKOUT

CT16B2_PWM[2:0] CT16B2_CAP0

URX0, UTX0

USCLK0

UCTS0

URTS0

SCK0

SEL0

SDI0

SDO0

SCL0 SDA0

SCK1

SEL1

SDI1

SDO1

/RESET

ARM

CORTEX-M0

CLOCK GENERATION

FLASH ROM

Up to 64KB

SRAM

Up to 8KB

SYS

POWER CONTROL/

SYSTEM FUNCTIONS

SPI1

I2C0

USART 0

SPI0

USART 1

POWER

REGULATOR 1

ILRC

32KHz

IHRC

12MHz

LVD

Clocks

Controls

AHB-LITE BUS

AHB TO APB

BRIDGE

APB BUS

RTC

GPIO

VCORE

VDD 1.8V~5.5V

I2C1

SCL1

SDA1

URX1

UTX1

I2S

I2SBCLK

I2SWS

I2SDIN I2SDOUT I2SMCLK

BOOT LOADER

4KB

AIN0~AIN13

PMU

COM0~COM3

SEG0~SEG31

V3,V2,

CL+, CL-

LCD

WDT

16-bit TIMER 2 with PWM

ADC

CT16B1_PWM[2:0] CT16B1_CAP0

16-bit TIMER 1 with PWM

CT16B0_PWM[2:0] CT16B0_CAP0

16-bit TIMER 0 with PWM

CT32B2_PWM[3:0] CT32B2_CAP0

32-bit TIMER 2 with PWM

CT32B1_PWM[3:0] CT32B1_CAP0

32-bit TIMER 1 with PWM

CT32B0_PWM[3:0] CT32B0_CAP0

32-bit TIMER 0 with PWM

32-Bit Cortex-M0 Micro-Controller

1.2 SYSTEM BLOCK DIAGRAM

SONiX TECHNOLOGY CO., LTD Page 16 Version 2.0

SN32F760 Series

XTALOUT

XTALIN

High speed

Crystal

oscillator

1MHz~25MHz

CLKOUT

PLL

1, 2, … , 32

IHRC

12MHz

ILRC

32KHz

PLLCLKSEL

IHRC

ILRC

PLLCLKout

SYSCLK

SYSCLKSEL

CLKOUTSEL

EHS Oscillator

SSPn

Clock Prescaler

/1,2,4,8,16

WDTCLKSEL

WDT

Clock Prescaler

/1, 2, 4, 8, 16, 32

WDT_PCLK

SSPn_PCLK

HCLK

AHB clock for SSPn

SSPnCLKEN

n=0, 1

WDT

register block

WDT

clock source

SSPn

register block

SSPn

clock source

AHB clock for WDT

AHB clock for AHB to APB bridge, to AHB

matrix, to Cortex-M0 FCLK, HCLK, and

System Timer, to SYS, and to PMU

AHB clock for GPIO

GPIOCLKEN

LXTALOUT

LXTALIN

Low speed

Crystal

oscillator

32.768KHz

GPIO block

AHB

Prescaler

/1,2,4,…,512

PLLCLKout

RTCCLKSEL

ILRC

32.768KHz

/128

ADC

Clock Prescaler

/1,2,4,8,16

ADC_PCLK

AHB clock for ADC

ADCCLKEN

ADC

register block

ADC

clock source

I2S

Clock Prescaler

/1,2,3,4,8,16

I2S_PCLK

AHB clock for I2S

I2SCLKEN

I2S

register block

I2S

clock source

I2Cn

Clock Prescaler

/1,2,4,8,16

I2Cn_PCLK

AHB clock for I2Cn

I2CnCLKEN

n=0,1

I2Cn

register block

I2Cn

clock source

CT32Bn

Clock Prescaler

/1,2,4,8,16

CT32Bn_PCLK

AHB clock for CT32Bn

CT32BnCLKEN

n=0,1, 2

CT32Bn

register block

CT32Bn

clock source

CT16Bn

Clock Prescaler

/1,2,4,8,16

CT16Bn_PCLK

AHB clock for CT16Bn

CT16BnCLKEN

n=0,1, 2

CT16Bn

register block

CT16Bn

clock source

USARTn

Clock Prescaler

/1,2,4,8,16

USARTn_PCLK

AHB clock for USARTn

USARTnCLKEN

n=0,1

USARTn

register block

USARTn

clock source

AHB clock for SRAM

SRAM block

AHB clock for FLASH

FLASH block

Max 16MHz

CLKOUT Prescaler

/1,2,4,…,512

WDTCLKEN

HCLK

IHRC ILRC

32.768KHz

EHS Oscillator

RTC_PCLK

RTC

register block

RTC

clock source

AHB clock for RTC

RTCCLKEN

LCDCLK

ILRC

32.768KHz

LCD_PCLK

LCD

register block

LCD

clock source

AHB clock for LCD

LCDCLKEN

PFPA blcok

AHB clock for PFPA

I2SCLKSEL

32-Bit Cortex-M0 Micro-Controller

1.3 CLOCK GENERATION BLOCK DIAGRAM

SONiX TECHNOLOGY CO., LTD Page 17 Version 2.0

SN32F760 Series

P3.15/LXTALOUT

P3.14/LXTALIN

NC

P3.13/HXTALOUT

P3.12/HXTALIN

P3.11/CLKOUT

P3.10/RESET

P0.8/SWCLK

P0.9/SWDIO

VSS

NC

VDD

NC

P3.9/SEG11

P3.8/SEG10

P3.7/SEG9

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

AIN0/P2.0

1

●

60

P3.6/SEG8

AIN1/P2.1

2

59

P3.5/SEG7

BOOT/AIN2/P2.2

3

58

P3.4/SEG6

AIN3/P2.3

4

57

P3.3/SEG5

AIN4/P2.4

5

56

P3.2/SEG4

P2.14

6

55

P1.7/V2

P2.15

7

54

P1.6/V3

AIN5/P2.5

8

53

P1.8/CL-

AIN6/P2.6

9

52

P1.9/CL+

AIN7/P2.7

10

SN32F769F SN32F759F

51

VSS

AIN8/P2.8

11

50

P3.1/SEG3

AIN9/P2.9

12

49

P3.0/SEG2

AIN10/P2.10

13

48

P1.15/SEG1

AIN11/P2.11

14

47

P1.14/SEG0

AIN12/P2.12

15

46

P1.13/COM3

AIN13/P2.13

16

45

P1.12/COM2

VSS

17

44

P1.11/COM1

AVSS

18

43

P1.10/COM0

AVDD

19

42

VDD1/VLCD1

VDD3/VLCD3

20

41

VDD2/VLCD2

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

SEG31/P0.0

SEG30/P0.1

SEG29/P0.2

SEG28/P0.3

SEG27/P0.4

SEG26/P0.5

SEG25/P0.6

SEG24/P0.7

SEG23/P0.10

SEG22/P0.11

SEG21/P0.12

SEG20/P0.13

SEG19/P0.14

SEG18/P0.15

SEG17/P1.0

SEG16/P1.1

SEG15/P1.2

SEG14/P1.3

SEG13/P1.4

SEG12/P1.5

32-Bit Cortex-M0 Micro-Controller

1.4 PIN ASSIGNMENT

SN32F769/759F (LQFP 80 pins)

SONiX TECHNOLOGY CO., LTD Page 18 Version 2.0

SN32F760 Series

P3.15/LXTALOUT

P3.14/LXTALIN

P3.13/HXTALOUT

P3.12/HXTALIN

P3.11/CLKOUT

P3.10/RESET

P0.8/SWCLK

P0.9/SWDIO

VSS

VDD

P3.9/SEG11

P3.8/SEG10

P3.7/SEG9

P3.6/SEG8

P3.5/SEG7

P3.4/SEG6

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

AIN0/P2.0

1

●

48

P3.3/SEG5

AIN1/P2.1

2

47

P3.2/SEG4

BOOT/AIN2/P2.2

3

46

P1.7/V2

AIN3/P2.3

4

45

P1.6/V3

AIN4/P2.4

5

44

P1.8/CL-

P2.14

6

43

P1.9/CL+

P2.15

7

SN32F768F SN32F758F

42

P3.1/SEG3

AIN5/P2.5

8

41

P3.0/SEG2

AIN6/P2.6

9

40

P1.15/SEG1

AIN10/P2.10

10

39

P1.14/SEG0

AIN11/P2.11

11

38

P1.13/COM3

AIN12/P2.12

12

37

P1.12/COM2

AIN13/P2.13

13

36

P1.11/COM1

AVSS

14

35

P1.10/COM0

AVDD

15

34

VDD1/VLCD1

VDD3/VLCD3

16

33

VDD2/VLCD2

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

SEG31/P0.0

SEG30/P0.1

SEG29/P0.2

SEG28/P0.3

SEG27/P0.4

SEG26/P0.5

SEG25/P0.6

SEG24/P0.7

SEG19/P0.14

SEG18/P0.15

SEG17/P1.0

SEG16/P1.1

SEG15/P1.2

SEG14/P1.3

SEG13/P1.4

SEG12/P1.5

 Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-

power modes. Strongly recommended to set these pins as input pull-up.

32-Bit Cortex-M0 Micro-Controller

SN32F768/758F (LQFP 64 pins)

SONiX TECHNOLOGY CO., LTD Page 19 Version 2.0

SN32F760 Series

P3.15/LXTALOUT

P3.14/LXTALIN

P3.13/HXTALOUT

P3.12/HXTALIN

P3.11/CLKOUT

P3.10/RESET

P0.8/SWCLK

P0.9/SWDIO

VSS

VDD

P3.9/SEG11

P3.6/SEG8

48

47

46

45

44

43

42

41

40

39

38

37

AIN0/P2.0

1 ●

36

P3.5/SEG7

AIN1/P2.1

2

35

P3.3/SEG5

BOOT/AIN2/P2.2

3

34

P3.2/SEG4

AIN3/P2.3

4

33

P1.7/V2

AIN4/P2.4

5

SN32F767F SN32F757F

32

P1.6/V3

P2.14

6

31

P3.1/SEG3

P2.15

7

30

P3.0/SEG2

AIN5/P2.5

8

29

P1.13/COM3

AIN6/P2.6

9

28

P1.12/COM2

AIN7/P2.7

10

27

P1.11/COM1

AVSS

11

26

P1.10/COM0

AVDD

12

25

VDD12/VLCD12

13

14

15

16

17

18

19

20

21

22

23

24

VDD3/VLCD3

SEG31/P0.0

SEG30/P0.1

SEG29/P0.2

SEG28/P0.3

SEG27/P0.4

SEG26/P0.5

SEG17/P1.0

SEG16/P1.1

SEG15/P1.2

SEG14/P1.3

SEG13/P1.4

 Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-

power modes. Strongly recommended to set these pins as input pull-up.

32-Bit Cortex-M0 Micro-Controller

SN32F767/757 (LQFP 48 pins)

SONiX TECHNOLOGY CO., LTD Page 20 Version 2.0

SN32F760 Series

P3.15/LXTALOUT

P3.14/LXTALIN

P3.13/HXTALOUT

P3.12/HXTALIN

P3.11/CLKOUT

P3.10/RESET

P0.8/SWCLK

P0.9/SWDIO

VSS

VDD

P3.9/SEG11

P3.5/SEG7

P3.4/SEG6

P3.3/SEG5

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AIN0/P2.0

1 ●

32

P3.2/SEG4

AIN1/P2.1

2

31

P1.7/V2

BOOT/AIN2/P2.2

3

SN32F766J SN32F756J

30

P1.6/V3

AIN3/P2.3

4

29

P3.1/SEG3

AIN4/P2.4

5

28

P3.0/SEG2

P2.14

6

27

P1.13/COM3

P2.15

7

26

P1.12/COM2

AIN5/P2.5

8

25

P1.11/COM1

AIN6/P2.6

9

24

P1.10/COM0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

AVSS

AVDD

VDD3/VLCD3

SEG31/P0.0

SEG30/P0.1

SEG29/P0.2

SEG28/P0.3

SEG27/P0.4

SEG17/P1.0

SEG16/P1.1

SEG15/P1.2

SEG14/P1.3

SEG13/P1.4

VDD12/VLCD12

 Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-

power modes. Strongly recommended to set these pins as input pull-up.

32-Bit Cortex-M0 Micro-Controller

SN32F766/756 (QFN 46 pins)

SONiX TECHNOLOGY CO., LTD Page 21 Version 2.0

SN32F760 Series

P3.14/LXTALIN

P3.13/HXTALOUT

P3.12/HXTALIN

P3.11/CLKOUT

P3.10/RESET

P0.8/SWCLK

P0.9/SWDIO

VSS

32

31

30

29

28

27

26

25

LXTALOUT/P3.15

1 ●

24

VDD

AIN0/P2.0

2

23

P3.9

AIN1/P2.1

3

SN32F765J SN32F755J

22

P3.6

BOOT/AIN2/P2.2

4

21

P3.3

P2.14

5

20

P3.2

P2.15

6

19

P1.11

AIN7/P2.7

7

18

P1.10

AVSS

8

33 VSS

17

VDD12

9 10

11

12

13

14

15

16

AVDD

VDD3

P0.0

P0.1

P0.2

P1.0

P1.1

P1.2

 Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-

power modes. Strongly recommended to set these pins as input pull-up.

32-Bit Cortex-M0 Micro-Controller

SN32F765/755 (QFN 33 pins)

SONiX TECHNOLOGY CO., LTD Page 22 Version 2.0

SN32F760 Series

PIN NAME

TYPE

DESCRIPTION

VDD, VSS

P

Power supply input pins for digital circuit.

AVDD, AVSS

P

Power supply input pins for analog circuit.

VDD1/VLCD1

P

I/O and LCD driver power input pins for P1.6~P1.15 and P3.0~P3.9. This power input used for I/O power must be equal to VDD. This power input shall not be floating.

VDD2/VLCD2

P

I/O and LCD driver power input pins for P0.10~P0.15 and P1.0~P1.5. VDD2/VLCD2 is the I/O and LCD driver power input pin for P0.10~P0.15 and P1.0~P1.5. If VDD2 voltage is lower than VDD, user should manually force to set the I/O port P1.6 and P1.7 as input pull-down state in case of internal power collision. This power input shall not be floating.

VDD12/VLCD12

P

Double bonding pins with VDD1 and VDD2. This power input used for I/O power must be equal to VDD. This power input shall not be floating.

VDD3/VLCD3

P

I/O and LCD driver power input pins for P0.0~P0.7. If VDD3 voltage is lower than VDD, user should manually force to set the I/O port P1.6 and P1.7 as input pull-down state in case of internal power collision. This power input shall not be floating.

CL+, CL-

P

C-Type LCD charge pump capacitor

V3

P

2/3 VLCD bias voltage

V2

P

1/3 VLCD bias voltage

P0.0~P0.7

I/O

P0.0~P0.7 — Port 0 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode.

P0.8/SWCLK

I/O

P0.8 — Port 0.8 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. Built-in wakeup function. SWCLK — Serial Wire Clock pin.

P0.9/SWDIO

I/O

P0.9 — Port 0.9 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. Built-in wakeup function. SWDIO — Serial Wire Data input/output pin.

P0.10~P0.15

I/O

P0.10~P0.15 — Port 0 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode.

P1.0~P1.15

I/O

P1.0~P1.15 — Port 1 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode.

P2.0~P2.1/AIN0~1

I/O

P2.0~P2.1 — Port 2 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. AIN0~AIN1 — ADC channel input 0~13 pins.

P2.2/AIN2/BOOT

I/O

P2.0~P2.1 — Port 2 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. AIN0~AIN1 — ADC channel input 0~13 pins.

I

BOOT — Internal pull-up in Boot loader, tie LOW to keep in Boot loader or left HIGH to exit Boot loader and execute User program at boot time.

P2.3~P2.13/AIN3~13

I/O

P2.3~P2.13 — Port 2 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. AIN3~AIN13 — ADC channel input 0~13 pins.

P2.14

I/O

P2.14 — Port 2.14 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode.

32-Bit Cortex-M0 Micro-Controller

1.5 PIN DESCRIPTIONS

SONiX TECHNOLOGY CO., LTD Page 23 Version 2.0

SN32F760 Series

P2.15

I/O

P2.15 — Port 2.15 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode.

P3.0~P3.9

I/O

P3.0~P3.9 — Port 3 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode.

P3.10/RESET

I/O

P3.10 — Port 3.10 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode.

RESET — External Reset input. Schmitt trigger structure, active “Low”, normally stay “High”.

P3.11/CLKOUT

I/O

P3.11 — Port 3.11 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. CLKOUT — Clockout pin.

P3.12/HXTALIN

I/O

P3.12 — Port 3.12 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. HXTALIN — External high-speed X’tal input pin.

P3.13/HXTALOUT

I/O

P3.13 — Port 3.13 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. HXTALOUT — External high-speed X’tal output pin.

P3.14/LXTALIN

I/O

P3.14 — Port 3.14 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode. LXTALIN — External low-speed X’tal input pin.

P3.15/LXTALOUT

I/O

P3.15 — Port 3.15 bi-direction pin. Schmitt trigger structure and built-in pull-up/pull-down resisters as input mode.

LXTALOUT — External low-speed X’tal output pin.

Pin Name

Shared pins

P0.0

SEG31 / URXD0 / CT32B0_CAP0 / SCL1 / MISO0

CT16B0_PWM0 / CT16B2_PWM1 / CT32B2_PWM2

P0.1

SEG30 / UTXD0 / SDA1 / MOSI0

CT16B0_PWM1 / CT16B2_PWM2 / CT32B1_PWM0

P0.2

SEG29 / SCL0 / MISO0 / SEL1

CT16B0_CAP0 / CT32B1_CAP0 / CT16B2_PWM0/CT32B2_PWM1

P0.3

SEG28 / SDA0 / MOSI0 /

CT16B2_CAP0 / CT32B2_PWM2 / CT32B0_PWM3 / CT32B2_PWM0

P0.4

SEG27 / URXD0 / SCK0 / MISO1

CT16B0_PWM1 / CT32B0_PWM0 / CT32B1_PWM1

P0.5

SEG26 / UTXD0 / SEL0 / MOSI1

CT16B1_PWM0 / CT32B0_PWM2 / CT32B1_PWM2

P0.6

SEG25 / UTXD1 / SCL1 / MISO0

CT16B1_PWM2 / CT32B1_PWM3 / C32B2_PWM3

P0.7

SEG24 / URXD1 / SDA1 / MOSI0 / SCK1

CT16B1_CAP0 / CT32B0_PWM3 / CT32B1_PWM3

P0.8

SWCLK / CT16B0_CAP0 / CT32B1_CAP0

CT16B1_PWM1 / CT32B0_PWM1 / CT32B1_PWM2 / CT32B2_PWM0

P0.9

SWDIO / CT32B0_CAP0 / CT32B2_CAP0

CT16B0_PWM2 / CT16B2_PWM1 / CT32B0_PWM2 / CT32B1_PWM0 / CT32B2_PWM2

P0.10

SEG23 / I2SDIN / SDA0 / SEL0 / MISO1

CT16B0_PWM1 / CT16B1_PWM0 / CT32B2_CAP0

P0.11

SEG22 / I2SDOUT / SCK0

CT16B0_PWM2 / CT32B0_PWM0 / CT16B1_PWM1 /CT32B1_PWM2

P0.12

SEG21 / URXD1 / SEL0 / MOSI1 / I2SMCLK

CT16B1_PWM1 / CT16B1_CAP0

P0.13

SEG20 / UTXD1 / SCK0 / SEL1 / I2SBCLK

CT16B2_CAP0 / CT32B2_PWM0

P0.14

SEG19 / MOSI0 / SCK1 / I2SWS

32-Bit Cortex-M0 Micro-Controller

Please refer to Peripheral Function Pin Assignment (PFPA) chapters for setting of each GPIOs.

SONiX TECHNOLOGY CO., LTD Page 24 Version 2.0

SN32F760 Series

CT32B2_PWM1 / CT16B2_PWM0 / CT32B0_PWM1

P0.15

SEG18 / SCL0 / MISO0

CT32B1_PWM1 / CT16B1_PWM2 / CT32B0_PWM3 / CT32B2_PWM1 / CT32B1_CAP0

P1.0

SEG17 / URXD1 / SDA1 / MISO0 / SEL1

CT16B0_CAP0 / CT16B2_PWM2 / CT32B2_PWM3

P1.1

SEG16 / UTXD1 / SCL1 / MOSI0 / SCK1

CT16B0_PWM0 / CT32B2_PWM0 / CT32B0_CAP0

P1.2

SEG15 / UTXD0 / SDA0 / MOSI1

CT16B1_PWM2 / CT32B1_PWM1 / CT32B0_PWM3 / CT32B1_PWM3

P1.3

SEG14 / URXD0 / SCL0 / MISO1

CT32B1_CAP0 / CT16B1_PWM1 / CT32B1_PWM0

P1.4

SEG13 / UTXD1 / SDA0 / SCK0 / SEL1

CT16B2_PWM1 / CT16B2_PWM0 / CT32B2_CAP0

P1.5

SEG12 / URXD1 / SCL0 / SEL0

CT16B2_CAP0 / CT32B0_PWM1 / CT32B2_PWM1

P1.6

V3 / UCTS0 / I2SDIN / MOSI1

CT16B0_PWM2 / CT32B1_PWM2 / CT32B2_PWM2 / CT32B1_CAP0

P1.7

V2 / USCLK0 / I2SDOUT / SEL1

CT16B1_CAP0 / CT32B1_PWM3 / CT32B2_PWM0 / CT32B2_PWM3

P1.8

CL- / URTS0 / SDA1 / I2SMCLK

CT16B0_PWM0 / CT16B2_CAP0 / CT32B0_PWM0

P1.9

CL+ / SCL1 / I2SBCLK

CT16B1_PWM2 / CT16B1_PWM0 / CT32B0_PWM2

P1.10

COM0 / MISO1 / I2SWS

CT16B1_PWM3 / CT16B1_PWM1 / CT32B1_PWM1

P1.11

COM1 / SEL0 / SCK1

CT16B1_CAP0 / CT16B2_PWM1 / CT32B0_PWM1

P1.12

COM2 / SCK0

CT16B0_PWM0 / CT16B0_PWM2 / CT16B2_PWM2 / CT32B0_PWM3

P1.13

COM3 / URXD1 / SDA0 / MOSI1

CT16B0_PWM1 / CT32B1_PWM0 / CT32B2_CAP0

P1.14

SEG0 / UTXD1 / SCL0 / MISO0 / SEL1

CT16B1_PWM2 / CT32B0_PWM0 / CT32B0_PWM2

P1.15

SEG1 / URXD1 / MOSI0 / SCK1

CT16B1_PWM0 / CT32B0_PWM0 / CT32B2_PWM0

P2.0

AIN0 / I2SDIN / SEL0 / MOSI1

CT16B0_CAP0 / CT16B1_PWM0 / CT32B0_PWM2

P2.1

AIN1 / MISO0 / MISO1 / SEL1 / I2SWS

CT16B1_CAP0/ CT16B2_PWM1 / CT32B1_PWM1

P2.2

AIN2 / MOSI0 / SCK1 / I2SMCLK

CT16B2_CAP0 / CT16B0_PWM1 / CT32B0_PWM3

P2.3

AIN3 / SCK0

CT16B0_PWM0 / CT16B1_PWM2 / CT32B0_PWM0 / CT32B2_PWM3 / CT32B0_CAP0

P2.4

AIN4 / CT32B1_CAP0

CT16B0_PWM2 / CT16B1_PWM1 / CT16B2_PWM2 / CT32B0_PWM1 / CT32B1_PWM3

P2.5

AIN5 / I2SDIN

CT16B2_PWM0 / CT32B1_PWM2 / CT32B2_CAP0

P2.6

AIN6 / I2SMCLK

CT16B2_PWM1 / CT32B1_PWM0

P2.7

AIN7 / I2SWS

CT16B1_PWM2 / CT32B2_PWM1

P2.8

AIN8 / I2SDOUT

CT16B1_PWM1 / CT32B1_PWM1 / CT32B2_PWM3

P2.9

AIN9 / I2SWS

CT16B1_CAP0 / CT16B2_PWM0 / CT32B2_PWM3

P2.10

AIN10 / I2SBCLK

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 25 Version 2.0

SN32F760 Series

CT16B0_PWM2 / CT16B2_PWM2 / CT32B1_CAP0

P2.11

AIN11 / I2SBCLK

CT16B0_PWM1 / CT32B0_PWM2 / CT32B2_PWM0

P2.12

AIN12 / MISO0 / MISO1 / I2SDOUT

CT16B1_PWM0 / CT32B0_PWM3 / CT32B1_PWM2 / CT32B2_CAP0

P2.13

AIN13 / MOSI0 / SCK1

CT16B0_CAP0 / CT32B0_PWM1 / CT32B1_PWM3 / CT32B2_PWM1

P2.14

SCK0 / SEL1

CT16B2_CAP0 / CT32B0_PWM0 / CT32B1_PWM2 / CT32B2_PWM2

P2.15

SEL0 / MOSI1

CT16B0_PWM0 / CT32B1_PWM0 / CT32B2_PWM0 / CT32B2_PWM3 / CT32B0_CAP0

P3.0

SEG2 / URXD0 / I2SDIN / SCL1 / MISO1

CT16B0_CAP0 / CT16B2_PWM2 / CT32B2_PWM1

P3.1

SEG3 / I2SDOUT / UTXD0 / SEL0

CT16B2_PWM2 / CT16B2_PWM0 / CT32B2_PWM2 / CT32B0_CAP0

P3.2

SEG4 / UTXD0 / SDA1 / I2SMCLK / SCK0 / MOSI1

CT16B0_CAP0 / CT32B1_PWM0

P3.3

SEG5 / URXD0 / SCL1 / MISO0 / SCK1 / I2SBCLK

CT16B0_PWM0 / CT32B0_CAP0

P3.4

SEG6 / UTXD0 / SDA1 / MOSI0 / MISO1 / I2SWS

CT16B0_PWM1 / CT32B0_PWM3

P3.5

SEG7 / URXD0 / SDA1 / SEL0

CT16B1_CAP0 / CT16B2_PWM0 / CT16B2_PWM1 / CT32B1_PWM1

P3.6

SEG8 / URXD1 / SCL1 / SEL1 / SCK0 / I2SBCLK

CT16B2_CAP0 / CT16B0_PWM2

P3.7

SEG9 / SDA0 / SCK1 / I2SMCLK

CT16B1_PWM0 / CT32B0_PWM2 / CT32B2_PWM1 / CT32B2_CAP0

P3.8

SEG10 / UTXD1 / I2SDOUT / MOSI1

CT16B1_PWM2 / CT32B0_PWM1 / CT32B1_CAP0

P3.9

SEG11 / I2SDIN / MISO1 / SCL0

CT16B1_PWM1 / CT32B0_PWM0 / CT32B1_PWM3 / CT32B0_CAP0

P3.10

RESET / UTXD0 / UTXD1 / SEL0

CT16B0_CAP0 / CT16B2_PWM0 / CT32B1_PWM1 / CT32B2_PWM3

P3.11

CLKOUT / URXD0 / SCL0 / SCK0 / SEL1

CT16B0_PWM0 / CT16B2_PWM2 / CT32B1_PWM3

P3.12

HXTALIN / URXD1 / SDA1 / MISO1

CT16B0_PWM1 / CT16B2_CAP0 / CT32B1_PWM2

P3.13

HXTALOUT / UTXD1 / SCL1 / SDA0 / MOSI1

CT16B1_CAP0 / CT32B0_PWM2 / CT32B2_PWM2

P3.14

LXTALIN / URXD0 / SCL0 / MOSI0 / SCK1

CT16B1_PWM0 / CT32B0_PWM1 / CT32B2_CAP0

P3.15

LXTALOUT / UTXD0 / SDA0 / MISO0

CT16B0_PWM2 / CT16B2_PWM1 / CT32B1_PWM0 / CT32B2_PWM2

 Note:

1. VDD1/VLCD1 is the I/O and LCD driver power input pin for P1.6~P1.15 and P3.0~P3.9. This power input used for I/O power must be equal to VDD.

2. VDD12/VLCD12 is the double bonding pin with VDD1 and VDD2. This power input used for I/O power must be equal to VDD.

3. VDD2/VLCD2 is the I/O and LCD driver power input pin for P0.10~P0.15 and P1.0~P1.5. If VDD2 voltage is lower than VDD, user should manually force to set the I/O port P1.6 and P1.7 as input pull-down state in case of internal power collision.

4. VDD3/VLCD3 is the I/O and LCD driver power input pin for P0.0~P0.7. If VDD3 voltage is lower

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 26 Version 2.0

SN32F760 Series

than VDD, user should manually force to set the I/O port P1.6 and P1.7 as input pull-down state in case of internal power collision.

5. VDD1/VLCD1, VDD2/VLCD2, VDD3/VLCD3, and VDD12/VLCD12 power input shall not be floating.

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD Page 27 Version 2.0

SN32F760 Series

RPU

Output

Latch

GPIOn_CFG

I/O Input Bus

I/O Output Bus

GPIOPn_MODE

RPD

GPIOn_CFGGPIOPn_MODE

RPU

Output

Latch

GPIOn_CFG

I/O Input Bus

Output Bus

GPIOPn_MODE

RPD

GPIOn_CFG

GPIOPn_MODE

Specific Input Bus

Specific Input Function Control Bit

*. Specific Output

Function Control Bit

*. Some specific functions switch I/O direction directly, not through GPIOn_MODE register.

RPU

Output

Latch

GPIOn_CFG

I/O Input Bus

Output Bus

GPIOPn_MODE

RPD

GPIOn_CFG

GPIOPn_MODE

Specific Output Bus

Specific Input Function Control Bit

*. Specific Output

Function Control Bit

*. Some specific functions switch I/O direction directly, not through GPIOn_MODE register.

32-Bit Cortex-M0 Micro-Controller

1.6 PIN CIRCUIT DIAGRAMS

 Normal Bi-direction I/O Pin.

 Bi-direction I/O Pin Shared with Specific Digital Input Function, e.g. SPI, I2C…

 Bi-direction I/O Pin Shared with Specific Digital Output Function, e.g. SPI, I2C…

SONiX TECHNOLOGY CO., LTD Page 28 Version 2.0

SN32F760 Series

RPU

Output

Latch

GPIOn_CFG

I/O Input Bus

I/O Output Bus

GPIOPn_MODE

RPD

GPIOn_CFG

GPIOPn_MODE

*. Specific Output Function Control Bit

*. Some specific functions switch I/O direction directly, not through GPIOn_MODE register.

Analog IP Input Terminal

RPU

Output

Latch

GPIOn_CFG

I/O Input Bus

I/O Output Bus

GPIOPn_MODE

RPD

GPIOn_CFG

GPIOPn_MODE

*. Specific Output Function Control Bit

*. Some specific functions switch I/O direction directly, not through GPIOn_MODE register.

Analog IP Output Terminal

32-Bit Cortex-M0 Micro-Controller

 Bi-direction I/O Pin Shared with Specific Analog Input Function, e.g. XIN, ADC…

 Bi-direction I/O Pin Shared with Specific Analog Output Function, e.g. XOUT…

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2

0x0000 0000

64 KB on-chip FLASH

Reserved

8 KB SRAM

0x4000 0000

0x4008 0000

Peripheral

Reserved for Peripheral

0x6000 0000

Reserved for External

0xA000 0000

Reserved for External Device

0xE000 0000

Private Peripheral Bus

0xE010 0000

Reserved

0xFFFF FFFF

0x4000 0000

0x4000 2000

0x4000 4000

0x4000 6000

0x4000 8000

0x4001 0000

0x4001 2000

0x4001 4000

WDT

0x4001 6000

0x4001 8000

Reserved

0x4002 8000

0x4002 6000

Reserved

I2C0

0x4004 4000

0x4004 6000

0x4004 8000

GPIO 2

GPIO 3

GPIO 0

GPIO 1

Reserved

0x4008 0000

0xE000 0000

0xE010 0000

0xE000 ED00

0xE000 F000

Reserved

NVIC

Debug Control

0xE000 E000

Reserved

SSP 0

USART0

SYS0

SSP 1

USART 1

0x4006 0000

FMC

Reserved

CT16B0

CT16B1

CT16B2

CT32B0

RTC

ADC

PMU

0x4006 4000

0x4006 2000

0x4005 6000

0x4004 C000

0x4004 A000

0x4003 2000

0x4001 E000

Reserved

0x4001 A000

0x4003 4000

0x4005 8000

0x4005 A000

Reserved

0x1FFF 0000

0x2000 0000

0x2000 2000

SYS1

0x4005 E000

I2C 1

0x4005 C000

Reserved

PFPA

0x4004 2000

4 KB Boot ROM

0x1FFF 1000

Reserved

0x0001 0000

LCD

0x4003 6000

CT32B1

0x4000 A000

CT32B2

0x4000 C000

0x4001 C000

Reserved

32-Bit Cortex-M0 Micro-Controller

CENTRAL PROCESSOR UNIT (CPU)

2.1 MEMORY MAP

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SYSTICK_CALIB

SysTick interrupt

SYSTICK_LOAD

SYSTICK_VAL

24-bit down counter

CLKSOURCE

System Clock

Ref. clock

(Fix to 1)

1

0

SYSTICK_CTRL

clock

Load data

Private

Peripheral

Bus

ENABLE

COUNTFLAG TICKINT

 Note: When the processor is halted for debugging the counter does not decrease.

32-Bit Cortex-M0 Micro-Controller

2.2 SYSTEM TICK TIMER

The SysTick timer is an integral part of the Cortex-M0. The SysTick timer is intended to generate a fixed 10-ms interrupt for use by an operating system or other system management software.

Since the SysTick timer is a part of the Cortex-M0, it facilitates porting of software by providing a standard timer that is available on Cortex-M0 based devices.

Refer to the Cortex-M0 User Guide for details.

2.2.1 OPERATION

The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10-ms time interval between interrupts. The system tick timer is enabled through the

SysTick control register. The system tick timer clock is fixed to the frequency of the system clock. The block diagram of the SysTick timer:

When SysTick timer is enabled, the timer counts down from the current value (SYSTICK_VAL) to zero, reloads to the value in the SysTick Reload Value Register (SYSTICK_LOAD) on the next clock edge, then decrements on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set to 1. The COUNTFLAG bit clears on reads.

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Bit

Name

Description

Attribute

Reset

31:17

Reserved

R

0

16

COUNTFLAG

This flag is set when the System Tick counter counts down to 0, and is cleared by reading this register.

R/W

0

15:3

Reserved

R

0

2

CLKSOURCE

Selects the SysTick timer clock source. 0: reference clock. 1: system clock. (Fixed)

R

1

TICKINT

System Tick interrupt enable. 0: Disable the System Tick interrupt 1: Enable the System Tick interrupt, the interrupt is generated when the

System Tick counter counts down to 0.

R/W

0

ENABLE

System Tick counter enable. 0: Disable 1: Enable

R/W

0

Bit

Name

Description

Attribute

Reset

31:24

Reserved

R

0

23:0

RELOAD

Value to load into the SYSTICK_VAL when the counter is enabled and when it reaches 0.

R/W

0x5F7F9B

32-Bit Cortex-M0 Micro-Controller

2.2.2 SYSTICK USAGE HINTS AND TIPS

The interrupt controller clock updates the SysTick counter. Some implementations stop this clock signal for low power mode. If this happens, the SysTick counter stops.

Ensure SW uses word accesses to access the SysTick registers. The SysTick counter reload and current value are not initialized by HW. This means the correct initialization sequence

for the SysTick counter is:

1. Program the reload value in SYSTICK_LOAD register.

2. Clear the current value by writing any value to SYSTICK_VAL register.

3. Program the Control and Status (SYSTICK_CTRL) register.

2.2.3 SYSTICK REGISTERS

2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL)

Address: 0xE000 E010 (Refer to Cortex-M0 Spec)

2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD)

Address: 0xE000 E014 (Refer to Cortex-M0 Spec) The RELOAD register is set to the value that will be loaded into the SysTick timer whenever it counts down to zero.

This register is set by software as part of timer initialization. The SYSTICK_CALIB register may be read and used as the value for RELOAD if the CPU or external clock is running at the frequency intended for use with the SYSTICK_CALIB value. The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the system clock set to 50 MHz. The SysTick clock = system clock = 50 MHz RELOAD = (system tick clock frequency × 10 ms) −1 = (50 MHz × 10 ms) −1

= 0x0007A11F.

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Bit

Name

Description

Attribute

Reset

31:24

Reserved

R

0

23:0

CURRENT

Reading this register returns the current value of the System Tick counter. Writing any value clears the System Tick counter and the COUNTFLAG bit in SYSTICK_CTRL.

R/W

0x7E7F35

Bit

Name

Description

Attribute

Reset

31

NOREF

Indicates the reference clock to M0 is provided or not. 1: No reference clock provided.

R

1

30

SKEW

Indicates whether the TENMS value is exact, an inexact TENMS value can affect the suitability of SysTick as a software real time clock. 0: TENMS value is exact 1: TENMS value is inexact, or not given.

R

0

29:24

Reserved

R

0

23:0

TENMS

Reload value for 10ms timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known.

R/W

0xA71FF

32-Bit Cortex-M0 Micro-Controller

2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL)

Address: 0xE000 E018 (Refer to Cortex-M0 Spec)

2.2.3.4 System Tick Timer Calibration Value register (SYSTICK_CALIB)

Address: 0xE000 E01C (Refer to Cortex-M0 Spec)

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Execution

No.

Priority

Function

Description

Address Offset

0

-

Reserved

0x0000 0000

1

-3

Reset

0x0000 0004

2

-2

NMI_Handler

Non maskable interrupt.

0x0000 0008

3

-1

HardFault_Handler

All class of fault

0x0000 000C

4~10

Reserved

-

11

Settable

SVCCalll

0x0000 002C

12~13

Reserved

-

14

Settable

PendSV

0x0000 0038

15

Settable

SysTick

0x0000 003C

16

Settable

IRQ0/ 0x0000 0040

17

Settable

IRQ1/ 0x0000 0044

18

Settable

IRQ2/LCDIRQ

LCD

0x0000 0048

19

Settable

IRQ3/I2SIRQ

I2S

0x0000 004C

20

Settable

IRQ4/ 0x0000 0050

21

Settable

IRQ5/ 0x0000 0054

22

Settable

IRQ6/SSP0IRQ

SSP0

0x0000 0058

23

Settable

IRQ7/SSP1IRQ

SSP1

0x0000 005C

24

Settable

IRQ8/ 0x0000 0060

25

Settable

IRQ9/ 0x0000 0064

26

Settable

IRQ10/I2C0IRQ

I2C0

0x0000 0068

27

Settable

IRQ11/I2C1IRQ

I2C1

0x0000 006C

28

Settable

IRQ12/

0x0000 0070

29

Settable

IRQ13/USART0IRQ

USART0

0x0000 0074

30

Settable

IRQ14/USART1IRQ

USART1

0x0000 0078

32-Bit Cortex-M0 Micro-Controller

2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC)

All interrupts including the core exceptions are managed by the NVIC. NVIC has the following Features:

 The NVIC supports 32 vectored interrupts.  4 programmable interrupt priority levels with hardware priority level masking.  Low-latency exception and interrupt handling.  Efficient processing of late arriving interrupts.  Implementation of System Control Registers  Software interrupt generation.

2.3.1 INTERRUPT AND EXCEPTION VECTORS

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31

Settable

IRQ15/CT16B0IRQ

CT16B0

0x0000 007C

32

Settable

IRQ16/CT16B1IRQ

CT16B1

0x0000 0080

33

Settable

IRQ17/CT16B2IRQ

CT16B2

0x0000 0084

34

Settable

IRQ18/

0x0000 0088

35

Settable

IRQ19/CT32B0IRQ

CT32B0

0x0000 008C

36

Settable

IRQ20/CT32B1IRQ

CT32B1

0x0000 0090

37

Settable

IRQ21/CT32B2IRQ

CT32B2

0x0000 0094

38

Settable

IRQ22/

0x0000 0098

39

Settable

IRQ23/RTCIRQ

RTC

0x0000 009C

40

Settable

IRQ24/ADCIRQ

ADC

0x0000 00A0

41

Settable

IRQ25/WDTIRQ

WDT

0x0000 00A4

42

Settable

IRQ26/LVDIRQ

LVD

0x0000 00A8

43

Settable

IRQ27/

0x0000 00AC

44

Settable

IRQ28/P3IRQ

GPIO interrupt status of port 3

0x0000 00B0

45

Settable

IRQ29/P2IRQ

GPIO interrupt status of port 2

0x0000 00B4

46

Settable

IRQ30/P1IRQ

GPIO interrupt status of port 1

0x0000 00B8

47

Settable

IRQ31/P0IRQ

GPIO interrupt status of port 0

0x0000 00BC

Bit

Name

Description

Attribute

Reset

31:0

SETENA[31:0]

Interrupt set-enable bits. Write 0: No effect

1: Enable interrupt.

Read 0: Interrupt disabled

1: Interrupt enabled.

R/W

0

32-Bit Cortex-M0 Micro-Controller

2.3.2 NVIC REGISTERS

2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER)

Address: 0xE000 E100 (Refer to Cortex-M0 Spec.) The ISER enables interrupts, and shows the interrupts that are enabled.

2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER)

Address: 0xE000 E180 (Refer to Cortex-M0 Spec.) The ICER disables interrupts, and shows the interrupts that are enabled.

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Bit

Name

Description

Attribute

Reset

31:0

CLRENA[31:0]

Interrupt clear-enable bits. Write 0: No effect

1: Disable interrupt.

Read 0: Interrupt disabled

1: Interrupt enabled.

R/W

0

 Note: Writing 1 to the ISPR bit corresponding to

1. an interrupt that is pending has no effect

2. a disabled interrupt sets the state of that interrupt to pending.

Bit

Name

Description

Attribute

Reset

31:0

SETPEND[31:0]

Interrupt set-pending bits. Write 0: No effect

1: Change interrupt state to pending

Read 0: Interrupt is not pending

1: Interrupt is pending

R/W

0

 Note: Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt.

Bit

Name

Description

Attribute

Reset

31:0

CLRPEND[31:0]

Interrupt clear-pending bits. Write 0: No effect

1: Removes pending state of an interrupt

Read 0: Interrupt is not pending

1: Interrupt is pending

R/W

0

Bit

Name

Description

Attribute

Reset

31:24

PRI_(4*n+3)

Each priority field holds a priority value, 0-192. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[31:30] of each field, bits [29:24] read as zero and ignore writes. This means writing 255 to a priority register saves value 192 to the register.

R/W

0

23:16

PRI_(4*n+2)

Each priority field holds a priority value, 0-192. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[23:22] of each field, bits [21:16] read as zero and ignore writes. This

R/W

0

32-Bit Cortex-M0 Micro-Controller

2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR)

Address: 0xE000 E200 (Refer to Cortex-M0 Spec.) The ISPR forces interrupts into the pending state, and shows the interrupts that are pending.

2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR)

Address: 0xE000 E280 (Refer to Cortex-M0 Spec.) The ICPR removes the pending state from interrupts, and shows the interrupts that are pending.

2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7)

Address: 0xE000 E400 + 0x4 * n (Refer to Cortex-M0 Spec.) The interrupt priority registers provide an 8-bit priority field for each interrupt, and each register holds four priority fields.

This means the number of registers is implementation-defined, and corresponds to the number of implemented interrupts.

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means writing 255 to a priority register saves value 192 to the register.

15:8

PRI_(4*n+1)

Each priority field holds a priority value, 0-192. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[15:14] of each field, bits [13:8] read as zero and ignore writes. This means writing 255 to a priority register saves value 192 to the register.

R/W

0

7:0

PRI_4*n

Each priority field holds a priority value, 0-192. The lower the value, the greater the priority of the corresponding interrupt. The processor implements only bits[7:6] of each field, bits [5:0] read as zero and ignore writes. This means writing 255 to a priority register saves value 192 to the register.

R/W

0

 Note: To write to this register, user must write 0x05FA to the VECTKEY field at the same time, otherwise

the processor ignores the write.

Bit

Name

Description

Attribute

Reset

31:16

VECTKEY

Register key. Read as unknown. Write 0x05FA to VECTKEY, otherwise the write is ignored.

R/W

0

15

ENDIANESS

Data endianness implemented 0: Little-endian 1: Big-endian

R

0

14:3

Reserved

R

0

2

SYSRESETREQ

System reset request. This bit read as 0. 0: No effect 1: Requests a system level reset.

W

0

1

VECTCLRACTIVE

Reserved for debug use. This bit read as 0. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable.

W

0

Reserved

R

0

32-Bit Cortex-M0 Micro-Controller

2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC)

Address: 0xE000 ED0C (Refer to Cortex-M0 Spec) The entire MCU, including the core, can be reset by SW by setting the SYSRESREQ bit in the AIRC register in

Cortex-M0 spec.

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Bit

Name

Description

Attribute

Reset

31:16

Code Security[15:0]

Code Security 0xFFFF: CS0 0x5A5A: CS1 0xA5A5: CS2 0x55AA: CS3

R/W

0xFFFF

15:0

Reserved

R

All 1

32-Bit Cortex-M0 Micro-Controller

2.5 CODE OPTION TABLE

Address: 0x1FFF 2000

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Register

Description (Refer to Cortex-M0 Spec)

R0~R12

General-purpose registers for data operations.

SP (R13)

The Stack Pointer (SP). In Thread mode, the CONTROL register indicates the stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP) On reset, the processor loads the MSP with the value from address 0x00000000.

LR (R14)

The Link Register (LR). It stores the return information for subroutines, function calls, and exceptions.

PC (R15)

The Program Counter (PC). It contains the current program address. On reset, the processor loads the PC with the value of the reset vector, at address 0x00000004.

PSR

The Program Status Register (PSR) combines:

• Application Program Status Register (APSR)

• Interrupt Program Status Register (IPSR)

• Execution Program Status Register (EPSR).

These registers are mutually exclusive bit fields in the 32-bit PSR.

PRIMASK

The PRIMASK register prevents activation of all exceptions with configurable priority.

CONTROL

The CONTROL register controls the stack used when the processor is in Thread mode.

32-Bit Cortex-M0 Micro-Controller

2.6 CORE REGISTER OVERVIEW

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3

VDD VSS

Watchdog Normal Run Watchdog Stop

System Normal Run System Stop

LVD Detect Level

External Reset Low Detect

External Reset High Detect

Watchdog Overflow

Watchdog Reset Delay Time

External Reset Delay Time

Power On Delay Time

Power

External Reset

Watchdog Reset

System Status

32-Bit Cortex-M0 Micro-Controller

SYSTEM CONTROL

3.1 RESET

A system reset is generated when one of the following events occurs:

1. A low level on the RST pin (external reset).

2. Power-on reset (POR reset)

3. LVD reset

4. Watchdog Timer reset (WDT reset)

5. Software reset (SW reset)

6. DPDWAKEUP reset when exiting Deep power-down mode by DPDWAKEUP pin

The reset source can be identified by checking the reset flags in System Reset Status register (SYS0_RSTST). These sources act on the RST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x00000004 in the memory map. For more details, refer to Interrupt and Exception Vectors.

Finishing any reset sequence needs some time. The system provides complete procedures to make the power on reset successful. For different oscillator types, the reset time is different. That causes the VDD rise rate and start-up time of different oscillator is not fixed. RC type oscillator’s start-up time is very short, but the crystal type is longer. Under client terminal application, users have to take care of the power on reset time for the master terminal requirement. The reset timing diagram is as following.

3.1.1 POWER-ON RESET (POR)

The power on reset depends on LVD operation for most power-up situations. The power supplying to system is a rising curve and needs some time to achieve the normal voltage. Power on reset sequence is as following:

 Power-up: System detects the power voltage up and waits for power stable.  External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is

not high level, the system keeps reset status and waits external reset pin released.

 System initialization: All system registers is set as initial conditions and system is ready.  Oscillator warm up: Oscillator operation is successfully and supply to system clock.  Program executing: Power on sequence is finished and program executes from Boot loader.

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 Note: Please refer to the “WATCHDOG TIMER” about watchdog timer detail information.

VDD

VSS

V1

V2

V3

System Work

Well Area

System Work

Error Area

32-Bit Cortex-M0 Micro-Controller

3.1.2 WATCHDOG RESET (WDT RESET)

Watchdog reset is a system protection. In normal condition, system works well and clears watchdog timer by program.

Under error condition, system is in unknown situation and watchdog can’t be clear by program before watchdog timer

overflow. Watchdog timer overflow occurs and the system is reset. After watchdog reset, the system restarts and returns normal mode. Watchdog reset sequence is as following.

 Watchdog timer status: System checks watchdog timer overflow status. If watchdog timer overflow occurs, the

system is reset.

 System initialization: All system registers is set as initial conditions and system is ready.  Oscillator warm up: Oscillator operation is successfully and supply to system clock.  Program executing: Power on sequence is finished and program executes from 0x0.

Watchdog timer application note is as following.

 Before clearing watchdog timer, check I/O status and check RAM contents can improve system error.  Don’t clear watchdog timer in interrupt vector and interrupt service routine. That can improve main routine fail.  Clearing watchdog timer program is only at one part of the program. This way is the best structure to enhance the

watchdog timer function.

3.1.3 BROWN-OUT RESET

3.1.3.1 BROWN OUT DESCRIPTION

The brown-out reset is a power dropping condition. The power drops from normal voltage to low voltage by external factors (e.g. EFT interference or external loading changed). The brown out reset would make the system not work well or executing program error.

Brown-Out Reset Diagram

The power dropping might through the voltage range that’s the system dead-band. The dead-band means the power range can’t offer the system minimum operation power requirement. The above diagram is a typical brown out reset

diagram. There is a serious noise under the VDD, and VDD voltage drops very deep. There is a dotted line to separate the system working area. The above area is the system work well area. The below area is the system work error area called dead-band. V1 doesn’t touch the below area and not affect the system operation. But the V2 and V3 is under the below area and may induce the system error occurrence. Let system under dead-band includes some conditions.

DC application:

The power source of DC application is usually using battery. When low battery condition and MCU drive any loading,

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Vdd (V)

System Rate (Fcpu)

System Mini.

Operating Voltage.

System Reset

Voltage.

Dead-Band Area

Normal Operating

Area

Reset Area

 Note: The “Zener diode reset circuit”, “Voltage bias reset circuit” and “External reset IC” can completely

improve the brown out reset, DC low battery and AC slow power down conditions.

32-Bit Cortex-M0 Micro-Controller

the power drops and keeps in dead-band. Under the situation, the power won’t drop deeper and not touch the system reset voltage. That makes the system under dead-band.

AC application:

In AC power application, the DC power is regulated from AC power source. This kind of power usually couples with AC noise that makes the DC power dirty. Or the external loading is very heavy, e.g. driving motor. The loading operating induces noise and overlaps with the DC power. VDD drops by the noise, and the system works under unstable power situation.

The power on duration and power down duration are longer in AC application. The system power on sequence protects the power on successful, but the power down situation is like DC low battery condition. When turn off the AC power, the VDD drops slowly and through the dead-band for a while.

3.1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION

To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. Different system executing rates have different system minimum operating voltage. The electrical characteristic section shows the system voltage to executing rate relationship.

Normally the system operation voltage area is higher than the system reset voltage to VDD, and the reset voltage is decided by LVD detect level. The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. The dead-band definition is the system minimum operating voltage above the system reset voltage.

3.1.3.3 BROWN-OUT RESET IMPROVEMENT

How to improve the brown reset condition? There are some methods to improve brown out reset as following.

 LVD reset  Watchdog reset  Reduce the system executing rate  External reset circuit. (Zener diode reset circuit, Voltage bias reset circuit, External reset IC)

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VDD

VSS

System Normal Run

System Stop

LVD Detect Voltage

Power On Delay Time

Power

System Status

Power is below LVD Detect Voltage and System Reset.

32-Bit Cortex-M0 Micro-Controller

LVD reset:

The LVD (low voltage detector) is built-in SONiX 32-bit MCU to be brown out reset protection. When the VDD drops and is below LVD detect voltage, the LVD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, SW can monitor the signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of the chip. The LVD detect level is different by each MCU. The LVD voltage level is a point of voltage and not easy to cover all dead-band range. Using LVD to improve brown out reset is dependent on application requirement and environment. If the power variation is very deep, violent and trigger the LVD, the LVD can be the protection. If the

power variation can touch the LVD detect level and make system work error, the LVD can’t be the protection and need

to other reset methods. More detail LVD information is in the electrical characteristic section.

Watchdog reset:

The watchdog timer is a protection to make sure the system executes well. Normally the watchdog timer would be clear

at one point of program. Don’t clear the watchdog timer in several addresses. The system executes normally and the

watchdog won’t reset system. When the system is under dead-band and the execution error, the watchdog timer can’t

be clear by program. The watchdog is continuously counting until overflow occurrence. The overflow signal of watchdog timer triggers the system to reset and return to normal mode after reset sequence. This method also can improve brown out reset condition and make sure the system to return normal mode. If the system reset by watchdog and the power is still in dead-band, the system reset sequence won’t be successful and the system stays in reset status until the power return to normal range.

Reduce the system executing rate:

If the system rate is fast and the dead-band exists, to reduce the system executing rate can improve the dead-band. The lower system rate is with lower minimum operating voltage. Select the power voltage that’s no dead-band issue and find out the mapping system rate. Adjust the system rate to the value and the system exits the dead-band issue. This way needs to modify whole program timing to fit the application requirement.

External reset circuit: The external reset methods also can improve brown out reset and is the complete solution. There are three external

reset circuits to improve brown out reset including “Zener diode reset circuit”, “Voltage bias reset circuit” and “External

reset IC”. These three reset structures use external reset signal and control to make sure the MCU be reset under

power dropping and under dead-band. The external reset information is described in the next section.

3.1.4 EXTERNAL RESET

External reset function is controlled by External RESET pin control (SYS0_EXRSTCTRL) register. Default value is 1, which means external reset function is enabled. External reset pin is Schmitt Trigger structure and low level active. The system is running when reset pin is high level voltage input. The reset pin receives the low voltage and the system is reset. The external reset operation actives in power on and normal running mode. During system power-up, the external reset pin must be high level input, or the system keeps in reset status. External reset sequence is as following.

 External reset (only external reset pin enable): System checks external reset pin status. If external reset pin is  System initialization: All system registers is set as initial conditions and system is ready.

SONiX TECHNOLOGY CO., LTD Page 43 Version 2.0

not high level, the system keeps reset status and waits external reset pin released.

SN32F760 Series

MCU

VDD

VSS

VCC

GND

R

S

T

R1

47K ohm

C1

0.1uF

R2

100 ohm

 Note: The reset circuit is no any protection against unusual power or brown out reset.

MCU

VDD

VSS

VCC

GND

R

S

T

R1 47K ohm

C1

0.1uF

DIODE

R2

100 ohm

32-Bit Cortex-M0 Micro-Controller

 Oscillator warm up: Oscillator operation is successfully and supply to system clock.  Program executing: Power on sequence is finished and program executes from Boot loader.

The external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at unusual power condition, e.g. brown out reset in AC power application.

3.1.4.1 SIMPLY RC RESET CIRCUIT

This is the basic reset circuit, and only includes R1 and C1. The RC circuit operation makes a slow rising signal into reset pin as power up. The reset signal is slower than VDD power up timing, and system occurs a power on signal from the timing difference.

3.1.4.2 DIODE & RC RESET CIRCUIT

This is the better reset circuit. The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal. The reset circuit has a simply protection against unusual power. The diode offers a power positive path to conduct higher power to VDD. It is can make reset pin voltage level to synchronize with VDD voltage. The structure can

SONiX TECHNOLOGY CO., LTD Page 44 Version 2.0

SN32F760 Series

 Note: The R2 100 ohm resistor of “Simply reset circuit” and “Diode & RC reset circuit” is necessary to

limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge (ESD) or Electrical Over-stress (EOS).

MCU

VDD

VSS

VCC

GND

R

S

T

R1

33K ohm

R3

40K ohm

R2

10K ohm

Vz

Q1

E

C

B

MCU

VDD

VSS

VCC

GND

R

S

T

R1

47K ohm

R3

2K ohm

R2

10K ohm

Q1

E

C

B

32-Bit Cortex-M0 Micro-Controller

improve slight brown out reset condition.

3.1.4.3 ZENER DIODE RESET CIRCUIT

The Zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely. Use Zener voltage to be the active level. When VDD voltage level is above “Vz + 0.7V”, the C terminal of

the PNP transistor outputs high voltage and MCU operates normally. When VDD is below “Vz + 0.7V”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by Zener specification. Select the right Zener voltage to conform the application.

3.1.4.4 VOLTAGE BIAS RESET CIRCUIT

The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely. The operating voltage is not accurate as Zener diode reset circuit. Use R1, R2 bias voltage to be the active level. When

VDD voltage level is above or equal to “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs high

SONiX TECHNOLOGY CO., LTD Page 45 Version 2.0

SN32F760 Series

 Note: Under unstable power condition as brown out reset, “Zener diode reset circuit” and “Voltage bias

reset circuit” can protects system no any error occurrence as power dropping. When power drops

below the reset detect voltage, the system reset would be triggered, and then system executes reset sequence. That makes sure the system work well under unstable power situation.

MCU

VDD

VSS

VCC

GND

R

S

T

Reset

IC

VDD

VSS

RST

Bypass

Capacitor

0.1uF

32-Bit Cortex-M0 Micro-Controller

voltage and MCU operates normally. When VDD is below “0.7V x (R1 + R2) / R1”, the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode. Decide the reset detect voltage by R1, R2 resistances. Select the right R1, R2 value to conform the application. In the circuit diagram condition, the MCU’s reset pin level varies with VDD voltage variation, and the differential voltage is

0.7V. If the VDD drops and the voltage lower than reset pin detect level, the system would be reset. If want to make the reset active earlier, set the R2 > R1 and the cap between VDD and C terminal voltage is larger than 0.7V. The external reset circuit is with a stable current through R1 and R2. For power consumption issue application, e.g. DC power system, the current must be considered to whole system power consumption.

3.1.4.5 EXTERNAL RESET IC

The external reset circuit also uses external reset IC to enhance MCU reset performance. This is a high cost and good effect solution. By different application and system requirement to select suitable reset IC. The reset circuit can improve all power variation.

3.1.5 SOFTWARE RESET

The entire MCU, including the core, can be reset by software by setting the SYSRESREQ bit in the AIRC (Application

Interrupt and Reset Control) register in Cortex-M0 spec.

The software-initiated system reset sequence is as follows:

1. A software reset is initiated by setting the SYSRESREQ bit.

2. An internal reset is asserted.

3. The internal reset is deasserted and the MCU loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution.

SONiX TECHNOLOGY CO., LTD Page 46 Version 2.0

SN32F760 Series

 Note: The ILRC can ONLY be switched on and off by HW.

32-Bit Cortex-M0 Micro-Controller

3.2 SYSTEM CLOCK

Different clock sources can be used to drive the system clock (SYSCLK):

 12 MHz internal high speed RC (IHRC)  32 KHz internal low speed RC (ILRC)  PLL clock  High speed external (EHS) crystal clock  Low speed external (ELS) 32.768 KHz crystal

Each clock source can be switched on or off independently when it is not used, to optimize power consumption.

The micro-controller is a dual clock system. There are high-speed clock and low-speed clock. The high-speed clock is generated from the external oscillator & on-chip PLL circuit. The low-speed clock is generated from on-chip low-speed RC oscillator circuit (ILRC 16 KHz).

3.2.1 INTERNAL RC CLOCK SOURCE

3.2.1.1 Internal High-speed RC Oscillator (IHRC)

The internal high-speed oscillator is 12MHz RC type. The accuracy is ±2% under commercial condition. The IHRC can be switched on and off using the IHRCEN bit in Analog Block Control register (SYS0_ANBCTRL).

3.2.1.2 Internal Low-speed RC Oscillator (ILRC)

The system low clock source is the internal low-speed oscillator built in the micro-controller. The low-speed oscillator uses RC type oscillator circuit. The frequency is affected by the voltage and temperature of the system. In common condition, the frequency of the RC oscillator is about 32 KHz.

SONiX TECHNOLOGY CO., LTD Page 47 Version 2.0

SN32F760 Series

PFD LPF VCO

DIV

M

DIV

P

Fclkout

FvcoFclkin

DIV

F

32-Bit Cortex-M0 Micro-Controller

3.2.2 PLL

SONiX 32-bit MCU uses the PLL to create the clocks for the core and peripherals. The input frequency range is 10MHz to 25MHz. The input clock is divided down and fed to the Phase-Frequency Detector (PFD). This block compares the phase and frequency of its inputs, and generates a control signal when phase and/ or frequency do not match. The loop filter filters these control signals and drives the voltage controlled oscillator (VCO), which generates the main clock and optionally two additional phases. The VCO frequency range is 156MHz to 320MHz. These clocks are divided by P by the programmable post divider to create the output clock(s). The VCO output clock is then divided by M by the programmable feedback divider to generate the feedback clock. The output signal of the phase-frequency detector is also monitored by the lock detector, to signal when the PLL has locked on to the input clock.

The PLL settling time is 100 μs.

3.2.2.1 PLL Frequency selection

The PLL frequency equations:

F

VCO

F

CLKOUT

= F

CLKIN

= F

/ F * M

/ P

VCO

The PLL frequency is determined by the following parameters:

 F  F  F

: Frequency from the PLLCLKSEL multiplexer.

CLKIN

: Frequency of the Voltage Controlled Oscillator (VCO); 156 to 320 MHz.

VCO

: Frequency of PLL output.

CLKOUT

 P: System PLL post divider ratio, controlled by PSEL bits in PLL control register (SYS0_PLLCTRL).  F: System PLL front divider ratio, controlled by FSEL bits in PLL control register (SYS0_PLLCTRL).  M: System PLL feedback divider ratio, controlled by MSEL bits in PLL control register (SYS0_PLLCTRL).

To select the appropriate values for M, P, and F, it is recommended to follow these constraints:

1. 10MHz ≤ F

2. 150MHz ≤ F

3. 2 < M ≤31

4. F = 1, or 2

5. P = 6, 8, 10, 12, or 14 (duty 50% +/- 2.5%)

6. F

= 20MHz, 30MHz, 40MHz, 50MHz, 24MHz, 36MHz, 48MHz, 32MHz, 22MHz, 24MHz, 50MHz

CLKOUT

≤ 25MHz

CLKIN

≤ 330MHz

VCO

with jitter < ±500 ps

SONiX TECHNOLOGY CO., LTD Page 48 Version 2.0

SN32F760 Series

MCU

VCC

GND

C

20pF

XIN

X

O

U

T

VDD

VSS

C 20pF

CRYSTAL

 Note: Connect the Crystal/Ceramic and C as near as possible to the XIN/XOUT/VSS pins of MCU.

Oscillator Mode

XTALIN pin

XTALOUT pin

IHRC

GPIO

EHS X’TAL

Crystal/Ceramic

4MHz Ceramic

4MHz Crystal

32-Bit Cortex-M0 Micro-Controller

3.2.3 EXTERNAL CLOCK SOURCE

3.2.3.1 External High-speed (EHS) Clock

External high clock includes Crystal/Ceramic modules. The startup time of Crystal is longer. The oscillator start-up time decides reset time length.

3.2.3.2 CRYSTAL/CERAMIC

Crystal/Ceramic devices are driven by XIN, XOUT pins. For high/normal/low frequency, the driving currents are different.

 Structure: 1MHz~25MHz EHS external crystal/ceramic resonator  Main Purpose: System high clock source, RTC clock source, and PLL clock source.  Warm-up Time: 2048*F  XIN/XOUT Shared Pin Selection:

SONiX TECHNOLOGY CO., LTD Page 49 Version 2.0

EHS

SN32F760 Series

 Note: Connect the Crystal/Ceramic and C as near as possible to the LXIN/LXOUT/VSS pins of MCU. The

capacitor between LXIN/LXOUT and VSS must be 10pF.

Clock Source

H/W Configuration

Description

External clock source

(Bypass)

In Bypass mode, the external clock signal (square, sinus or triangle) with ~50% duty cycle must be provided to drive the XTALIN/ LXTALIN pin while the XTALOUT/ LXTALOUT pin should be the inverse of the input clock signal.

EHS X’tal can have a frequency of up to 25

MHz. Select this mode by setting EHSEN bit in Analog Block Control register

(SYS0_ANBCTRL).

MCU

VCC

GND

C

10pF

LXIN

L

XOU

T

VDD

VSS

C 10pF

32768Hz

32-Bit Cortex-M0 Micro-Controller

The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.

The EHS crystal is switched on and off using the EHSEN bit in Analog Block Control register (SYS0_ANBCTRL).

3.2.3.3 External Low-speed (ELS) Clock

The low-speed oscillator can use 32768 crystal oscillator circuit.

3.2.3.4 CRYSTAL

Crystal devices are driven by LXIN, LXOUT pins. The 32768 crystal and 10pF capacitor must be as near as possible to MCU. The ELS crystal is switched on and off using the ELSEN bit in Analog Block Control register (SYS0_ANBCTRL).

3.2.3.5 Bypass Mode

SONiX TECHNOLOGY CO., LTD Page 50 Version 2.0

SN32F760 Series

ELS X’TAL must have a frequency of 32.768

KHz. You select this mode by setting ELSEN bit in Analog Block Control register

(SYS0_ANBCTRL).

External X’TAL

(EHS/ELS X’TAL)

The 10 to 25 MHz EHS X’TAL has the advantage of producing a very accurate rate on the main clock

ELS X’TAL must have a frequency of 32.768

KHz.

32-Bit Cortex-M0 Micro-Controller

3.2.4 SYSTEM CLOCK (SYSCLK) SELECTION

After a system reset, the IHRC is selected as system clock. When a clock source is used directly or through the PLL as system clock, it is not possible to stop it.

A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source is ready.

Ready bits in SYS0_CSST register indicate which clock(s) is (are) ready and SYSCLKST bits in SYS0_CLKCFG register indicate which clock is currently used as system clock.

3.2.5 CLOCK-OUT CAPABITITY

The MCU clock output (CLKOUT) capability allows the clock to be output onto the external CLKOUT pin. The configuration registers of the corresponding GPIO port must be programmed in alternate function mode.

One of 6 clock signals can be selected as clock output:

1. HCLK

2. IHRC

3. ILRC

4. PLL clock output

5. ELS X’TAL

6. EHS X’TAL

The selection is controlled by the CLKOUTSEL bits in SYS1_AHBCLKEN register.

SONiX TECHNOLOGY CO., LTD Page 51 Version 2.0

SN32F760 Series

 Note: EHSEN / ELSEN / IHRCEN bit can NOT be cleared if the EHS X’tal / ELS X’tal / IHRC is selected as

system clock or is selected to become the system clock.

Bit

Name

Description

Attribute

Reset

31:6

Reserved

R

0

5

EHSFREQ

Frequency range (driving ability) of EHS X’TAL 0: <=12MHz 1: >12MHz

R/W

0 4 EHSEN

External high-speed clock enable

0: Disable EHS X’TAL. 1: Enable EHS X’TAL.

R/W

0

3

Reserved

R

0

2

ELSEN

External low-speed oscillator enable 0: Disable External 32.768 KHz oscillator 1: Enable External 32.768 KHz oscillator

R/W

0

1

Reserved

R

0

IHRCEN

Internal high-speed clock enable 0: Disable internal 12 MHz RC oscillator. 1: Enable internal 12 MHz RC oscillator.

R/W

1

 Note: PLLEN bit can NOT be cleared if the PLL is selected as system clock or is selected to become the

system clock.

Bit

Name

Description

Attribute

Reset

31:16

Reserved

R

0

15

PLLEN

PLL enable 0: Disable 1: Enable

R/W

0

14

Reserved

R

0

13:12

PLLCLKSEL[1:0]

System PLL clock source 00: IHRC 12 MHz oscillator 01: EHS X’TAL 10 MHz ~ 25 MHz Other: Reserved

R/W

0

11:9

Reserved

R

0

8

FSEL

Front divider value. The division value F is the programmed 2

FSEL

0: F = 1 1: F = 2

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.3 SYSTEM CONTROL REGISTERS 0

Base Address: 0x4006 0000

3.3.1 Analog Block Control register (SYS0_ANBCTRL)

Address Offset: 0x00 Reset value: 0x0000 0001

3.3.2 PLL control register (SYS0_PLLCTRL)

Address Offset: 0x04

SONiX TECHNOLOGY CO., LTD Page 52 Version 2.0

SN32F760 Series

7:5

PSEL[2:0]

Post divider value. P= PSEL[2:0]*2 000~010: Reserved 011: P = 6 100: P = 8 101: P = 10 110: P = 12 111: P = 14

R/W

011b

4:0

MSEL[4:0]

Feedback divider value. M: 3~31

R/W

0x3

Fclkout

Fclkin

V V V V

V V V

V V

V

44MHz

48MHz

16MHz

22MHz

16MHz

12MHz

20MHz

30MHz

40MHz

22MHz

24MHz

25MHz

10MHz

50MHz

24MHz

25MHz

32MHz

36MHz

F

CLKIN

(MHz)

FSEL

F=2

FEL

MSEL[4:0]=M

F

VCO

(MHz)

=F

CLKIN

/F*M

PSEL[2:0]

P= PSEL[2:0]*2

F

CLKOUT

(MHz)

10

0 1 20

200 5 10

20

10

0 1 22

220 5 10

22

10

0 1 18

180 3 6

30

10

0 1 24

240 3 6

40

10

0 1 30

300 3 6

50

12

0 1 16

192 4 8

24

12

0 1 18

216 3 6

36

12

0 1 24

288 3 6

48

12

0 1 25

300 3 6

50

16

0 1 16

256 4 8

32

16

0 1 18

288 3 6

48

20

1 2 30

300 3 6

50

22

0 1 12

264 3 6

44

24

0 1 12

288 3 6

48

25

0 1 12

300 3 6

50

Bit

Name

Description

Attribute

Reset

32-Bit Cortex-M0 Micro-Controller

To select the appropriate values for M, P, and F, it is recommended to follow these constraints:

1. 10MHz ≤ F

2. 150MHz ≤ F

3. 2 < M ≤31

4. F = 1, or 2

5. P = 6, 8, 10, 12, or 14 (duty 50% +/- 2.5%)

6. F

= 20MHz, 30MHz, 40MHz, 50MHz, 24MHz, 36MHz, 48MHz, 32MHz, 22MHz, 24MHz, 50MHz

CLKOUT

≤ 25MHz

CLKIN

≤ 330MHz

VCO

with jitter < ±500 ps

3.3.2.1 RECOMMEND FREQUENCY SETTING

F

VCO

F

CLKOUT

= F

CLKIN

= F

/ F * M

/ P

VCO

3.3.3 Clock Source Status register (SYS0_CSST)

Address Offset: 0x08

SONiX TECHNOLOGY CO., LTD Page 53 Version 2.0

SN32F760 Series

31:7

Reserved

R

0

6

PLLRDY

PLL clock ready flag 0: PLL unlocked 1: PLL locked

R

0

5

Reserved

R

0

4

EHSRDY

External high-speed clock ready flag 0: EHS oscillator not ready 1: EHS oscillator ready

R

0

3

Reserved

R

0

2

ELSRDY

External low-speed clock ready flag 0: ELS oscillator not ready 1: ELS oscillator ready

R

0

1

Reserved

R

0

IHRCRDY

IHRC ready flag 0: IHRC not ready 1: IHRC ready

R

1

Bit

Name

Description

Attribute

Reset

31:7

Reserved

R

0

6:4

SYSCLKST[2:0]

System clock switch status Set and cleared by HW to indicate which clock source is used as system clock. 000: IHRC is used as system clock 001: ILRC is used as system clock

010: EHS X’TAL is used as system clock 011: ELS X’TAL is used as system clock

100: PLL is used as system clock Other: Reserved

R

0

3

Reserved

R

0

2:0

SYSCLKSEL[2:0]

System clock switch Set and cleared by SW. 000: IHRC 001: ILRC

010: EHS X’TAL 011: ELS X’TAL

100: PLL output Other: Reserved

R/W

0

Bit

Name

Description

Attribute

Reset

31:4

Reserved

R

0

3:0

AHBPRE[3:0]

AHB clock source prescale value 0000: SYSCLK / 1 0001: SYSCLK / 2 0010: SYSCLK / 4 0011: SYSCLK / 8 0100: SYSCLK / 16 0101: SYSCLK / 32 0110: SYSCLK / 64 0111: SYSCLK / 128 1000: SYSCLK / 256

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.3.4 System Clock Configuration register (SYS0_CLKCFG)

Address Offset: 0x0C

3.3.5 AHB Clock Prescale register (SYS0_AHBCP)

Address Offset: 0x10

SONiX TECHNOLOGY CO., LTD Page 54 Version 2.0

SN32F760 Series

1001: SYSCLK / 512 Other: Reserved

Bit

Name

Description

Attribute

Reset

31:5

Reserved

R

0

4

PORRSTF

POR reset flag Set by HW when a POR reset occurs. 0: ReadNo POR reset occurred WriteClear this bit 1: POR reset occurred.

R/W

1

3

EXTRSTF

External reset flag Set by HW when a reset from the RESET pin occurs. 0: ReadNo reset from RESET pin occurred WriteClear this bit 1: Reset from RESET pin occurred.

R/W

0 2 LVDRSTF

LVD reset flag Set by HW when a LVD reset occurs. 0: ReadNo LVD reset occurred WriteClear this bit 1: LVD reset occurred.

R/W

0 1 WDTRSTF

WDT reset flag Set by HW when a WDT reset occurs. 0: ReadNo watchdog reset occurred WriteClear this bit 1: Watchdog reset occurred.

R/W

0 0 SWRSTF

Software reset flag Set by HW when a software reset occurs. 0: ReadNo software reset occurred WriteClear this bit 1: Software reset occurred.

R/W

1

Bit

Name

Description

Attribute

Reset

31:16

Reserved

R

0

15

LVDEN

LVD enable 0: Disable 1: Enable

R/W

0

14

LVDRSTEN

LVD Reset enable 0: Disable 1: Enable

R/W

0

13:7

Reserved

R

0

6:4

LVDINTLVL[2:0]

LVD interrupt level 000: 1.80V 001: 2.00V

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.3.6 System Reset Status register (SYS0_RSTST)

Address Offset: 0x14

This register contains the reset source except DPDWAKEUP reset, since the MODE bits in PMU_CTRL register had presented this case.

3.3.7 LVD Control register (SYS0_LVDCTRL)

Address Offset: 0x18 The LVD control register selects four separate threshold values for generating a LVD interrupt to the NVIC or LVD

reset.

SONiX TECHNOLOGY CO., LTD Page 55 Version 2.0

SN32F760 Series

010: 2.40V 011: 2.70V 100: 3.00V 101: 3.60V Other: Reserved

3

Reserved

R

0

2:0

LVDRSTLVL[2:0]

LVD reset level 000: 1.80V 001: 2.00V 010: 2.40V 011: 2.70V 100: 3.00V 101: 3.60V Other: Reserved

R/W

0

Bit

Name

Description

Attribute

Reset

31:1

Reserved

R

0

RESETDIS

External RESET pin disable bit. 0: Enable external RESET pin. (P3.10 acts as RESET pin) 1: Disable. (P3.10 acts as GPIO pin)

R/W

1

Bit

Name

Description

Attribute

Reset

31:1

Reserved

R

0

SWDDIS

SWD pin disable bit. 0: Enable SWD pin. (P0.9 acts as SWDIO pin, P0.8 acts as SWCLK pin) 1: Disable. (P0.8 and P0.9 act as GPIO pins)

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.3.8 External RESET Pin Control register (SYS0_EXRSTCTRL)

Address Offset: 0x1C

3.3.9 SWD Pin Control register (SYS0_SWDCTRL)

Address Offset: 0x20

SONiX TECHNOLOGY CO., LTD Page 56 Version 2.0

SN32F760 Series

 Note:

1. When the clock is disabled, the peripheral register values may not be readable by SW and the value returned is always 0x0.

2. HW will replace GPIO with CLKOUT function directly if CLKOUTSEL is Not 0.

Bit

Name

Description

Attribute

Reset

31

Reserved

R

0

30:28

CLKOUTSEL[2:0]

Clock output source 000: Disable 001: ILRC clock 010: ELS clock 100: HCLK 101: IHRC clock 110: EHS clock 111: PLL clock output

R/W

0

27:25

Reserved

R

0

24

WDTCLKEN

Enables clock for WDT. 0: Disable 1: Enable

R/W

1

23

RTCCLKEN

Enables clock for RTC. 0: Disable 1: Enable

R/W

0

22

I2SCLKEN

Enables clock for I2S. 0: Disable 1: Enable

R/W

0

21

I2C0CLKEN

Enables clock for I2C0. 0: Disable 1: Enable

R/W

0

20

I2C1CLKEN

Enables clock for I2C1. 0: Disable 1: Enable

R/W

0

19:18

Reserved

R

0

17

USART1CLKEN

Enables clock for USART1. 0: Disable 1: Enable

R/W

0

16

USART0CLKEN

Enables clock for USART0. 0: Disable 1: Enable

R/W

0

15:14

Reserved

R

0

13

SSP1CLKEN

Enables clock for SSP1. 0: Disable 1: Enable

R/W

0

12

SSP0CLKEN

Enables clock for SSP0. 0: Disable 1: Enable

R/W

0

11

ADCCLKEN

Enables clock for ADC. 0: Disable

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.4 SYSTEM CONTROL REGISTERS 1

Base Address: 0x4005 E000

3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN)

Address Offset: 0x00 The SYS_AHBCLKEN register enables the AHB clock to individual system and peripheral blocks.

SONiX TECHNOLOGY CO., LTD Page 57 Version 2.0

SN32F760 Series

1: Enable

10

CT32B2CLKEN

Enables clock for CT32B2. 0: Disable 1: Enable

R/W

0

9

CT32B1CLKEN

Enables clock for CT32B1. 0: Disable 1: Enable

R/W

0 8 CT32B0CLKEN

Enables clock for CT32B0. 0: Disable 1: Enable

R/W

0 7 CT16B2CLKEN

Enables clock for CT16B2. 0: Disable 1: Enable

R/W

0 6 CT16B1CLKEN

Enables clock for CT16B1. 0: Disable 1: Enable

R/W

0 5 CT16B0CLKEN

Enables clock for CT16B0. 0: Disable 1: Enable

R/W

0

4:3

Reserved

R

0

2

LCDCLKEN

Enables clock for LCD 0: Disable 1: Enable

R/W

0

1

Reserved

R

0

GPIOCLKEN

Enables clock for GPIO. 0: Disable 1: Enable

R/W

1

 Note: Must reset the corresponding peripheral with SYS1_PRST register after changing the prescale

value.

Bit

Name

Description

Attribute

Reset

31

Reserved

R 0

30:28

CT32B2PRE[2:0]

CT32B2 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

27

Reserved

R

0

26:24

SSP1PRE[2:0]

SSP1 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

23

Reserved

R 0

22:20

SSP0PRE[2:0]

SSP0 clock source prescaler 000: HCLK / 1 001: HCLK / 2

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.4.2 APB Clock Prescale register 0 (SYS1_APBCP0)

Address Offset: 0x04

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010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

19

Reserved

R

0

18:16

ADCPRE[2:0]

ADC clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

15

Reserved

R

0

14:12

CT32B1PRE[2:0]

CT32B1 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

11

Reserved

R

0

10:8

CT32B0PRE[2:0]

CT32B0 clock source prescaler. 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

7

Reserved

R

0

6:4

CT16B1PRE[2:0]

CT16B1 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

3

Reserved

R

0

2:0

CT16B0PRE[2:0]

CT16B0 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

 Note: Must reset the corresponding peripheral with SYS1_PRST register after changing the prescale

value.

Bit

Name

Description

Attribute

Reset

31

Reserved

R

0

32-Bit Cortex-M0 Micro-Controller

3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1)

Address Offset: 0x08

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30:28

CT16B2PRE[2:0]

CT16B2 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

27

Reserved

R

0

26:24

I2C1PRE[2:0]

I2C1 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

23

Reserved

R

0

22:20

WDTPRE[2:0]

WDT clock source prescaler 000: WDT_PCLK = WDT clock source / 1 001: WDT_PCLK = WDT clock source / 2 010: WDT_PCLK = WDT clock source / 4 011: WDT_PCLK = WDT clock source / 8 100: WDT_PCLK = WDT clock source / 16 101: WDT_PCLK = WDT clock source / 32 Other: Reserved

R/W

0

19:15

Reserved

R 0

14:12

I2SPRE[2:0]

I2S clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 111: HCLK / 3 Other: Reserved

R/W

0

11

Reserved

R

0

10:8

I2C0PRE[2:0]

I2C0 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

7

Reserved

R 0

6:4

USART1PRE[2:0]

USART1 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

3

Reserved

R 0

2:0

USART0PRE[2:0]

USART0 clock source prescaler 000: HCLK / 1 001: HCLK / 2 010: HCLK / 4 011: HCLK / 8 100: HCLK / 16 Other: Reserved

R/W

0

32-Bit Cortex-M0 Micro-Controller

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SN32F760 Series

Bit

Name

Description

Attribute

Reset

31:4

Reserved

R

0

3:0

CLKOUTPRE[3:0]

Clock-out source prescaler 0000: Clock-out source / 1 0001: Clock-out source / 2 0010: Clock-out source / 4 0011: Clock-out source / 8 0100: Clock-out source / 16 0101: Clock-out source / 32 0110: Clock-out source / 64 0111: Clock-out source / 128 1000: Clock-out source / 256 1001: Clock-out source / 512 Other: Reserved

R/W

0

Bit

Name

Description

Attribute

Reset

31:25

Reserved

R 0

24

WDTRST

WDT reset 0: No effect 1: Reset WDT

R/W

0

23

RTCRST

RTC reset 0: No effect 1: Reset RTC

R/W

0

22

I2SRST

I2S reset 0: No effect 1: Reset I2S

R/W

0

21

I2C0RST

I2C0 reset 0: No effect 1: Reset I2C0

R/W

0

20

I2C1RST

I2C1 reset 0: No effect 1: Reset I2C1

R/W

0

19:18

Reserved

R

0

17

USART1RST

USART1 reset 0: No effect 1: Reset USART1

R/W

0

16

USART0RST

USART0 reset 0: No effect 1: Reset USART0

R/W

0

15

LCDRST

LCD reset 0: No effect 1: Reset LCD

R/W

0

14

Reserved

R

0

13

SSP1RST

SSP1 reset 0: No effect 1: Reset SSP1

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.4.4 APB Clock Prescale register 2 (SYS1_APBCP2)

Address Offset: 0x0C

3.4.5 Peripheral Reset register (SYS1_PRST)

Address Offset: 0x10 All bits are cleared by HW automatically after setting as “1”.

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12

SSP0RST

SSP0 reset 0: No effect 1: Reset SSP0

R/W

0

11

ADCRST

ADC reset 0: No effect 1: Reset ADC

R/W

0

10

CT32B2RST

CT32B2 reset 0: No effect 1: Reset CT32B2

R/W

0 9 CT32B1RST

CT32B1 reset 0: No effect 1: Reset CT32B1

R/W

0 8 CT32B0RST

CT32B0 reset 0: No effect 1: Reset CT32B0

R/W

0

7

CT16B2RST

CT16B2 reset 0: No effect 1: Reset CT16B2

R/W

0

6

CT16B1RST

CT16B1 reset 0: No effect 1: Reset CT16B1

R/W

0

5

CT16B0RST

CT16B0 reset 0: No effect 1: Reset CT16B0

R/W

0

4

Reserved

R 0

3

GPIOP3RST

GPIO port 3 reset 0: No effect 1: Reset GPIO port 3

R/W

0 2 GPIOP2RST

GPIO port 2 reset 0: No effect 1: Reset GPIO port 2

R/W

0 1 GPIOP1RST

GPIO port 1 reset 0: No effect 1: Reset GPIO port 1

R/W

0

GPIOP0RST

GPIO port 0 reset 0: No effect 1: Reset GPIO port 0

R/W

0

32-Bit Cortex-M0 Micro-Controller

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Bit

Name

Description

Attribute

Reset

31:0

Dividend[31:0]

Unsigned integer Dividend

R/W

0

 Note: Quotient is 0xFFFFFFFF when Divisor is 0x0, instead of occurring Hard Fault, since FW shall be

able to handle this case.

Bit

Name

Description

Attribute

Reset

31:0

Divisor[31:0]

Unsigned integer Divisor

R/W

0

 Note: Quotient is 0xFFFFFFFF when Divisor is 0x0, instead of occurring Hard Fault, since FW shall be

able to handle this case.

Bit

Name

Description

Attribute

Reset

31:0

Quotient[31:0]

Unsigned integer Quotient

R/W

0

Bit

Name

Description

Attribute

Reset

31:0

Remainder[31:0]

Unsigned integer Remainder

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.4.6 Divider Dividend register (SYS1_DIVIDEND)

Address Offset: 0x20

3.4.7 Divider Divisor register (SYS1_DIVISOR)

Address Offset: 0x24

3.4.8 Divider Quotient register (SYS1_QUOTIENT)

Address Offset: 0x28

3.4.9 Divider Remainder register (SYS1_REMAINDER)

Address Offset: 0x2C

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Bit

Name

Description

Attribute

Reset

31:1

Reserved

R

0

DIVS

Divider start control bit. 0: Divider stops/finishes operation. 1: Start to execute Dividing. DIVS is cleared by HW automatically when

the operation of dividing finishes.

R/W

0

32-Bit Cortex-M0 Micro-Controller

3.4.10 Divider Control register (SYS1_DIVCTRL)

Address Offset: 0x30

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4

 Note:

1. The debug mode is not supported in Deep-sleep and Deep Power-down mode.

2. The pins which are not pin-out shall be set correctly to decrease power consumption in low-power modes. Strongly recommended to set these pins as input pull-up.

32-Bit Cortex-M0 Micro-Controller

SYSTEM OPERATION MODE

4.1 OVERVIEW

The chip builds in four operating mode for difference clock rate and power saving reason. These modes control oscillators, op-code operation and analog peripheral devices’ operation.

 Normal mode  Sleep mode  Deep sleep mode  Deep Power-down mode

4.2 NORMAL MODE

In Normal mode, the ARM Cortex-M0 core, memories, and peripherals are clocked by the system clock. The

SYS1_AHBCLKEN register controls which peripherals are running.

Selected peripherals have individual peripheral clocks with their own clock dividers in addition to the system clock. The peripheral clocks can be disabled respectively.

The power to various analog blocks (IHRC, EHS X’TAL, ELS X’TAL, PLL, Flash, LVD, ADC) can be controlled at any time individually through the enable bit of all blocks.

4.3 LOW-POWER MODES

There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down mode. The PMU_CTRL register controls which mode is desired.

The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or altering the system clock divider value. This allows a trade-off of power versus processing speed based on application requirements.

Run-time power control allows disable the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider for power control.

4.3.1 SLEEP MODE

In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped and execution of instructions is suspended. Peripheral functions, if selected to be clocked in SYS1_AHBCLKEN register, continue operation during Sleep mode

and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used

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 Note: User SHALL decide to power down low speed clock source (ELS X’TAL, ILRC oscillator) or not

if RTC or LCD is enabled.

32-Bit Cortex-M0 Micro-Controller

by the processor itself, memory systems and related controllers, and internal buses. The power state of the analog blocks (IHRC, EHS X’TAL, ELS X’TAL, PLL, Flash, LVD, ADC) is determined by the

enable bit of all blocks. The processor state and registers, peripheral registers, and internal SRAM values are maintained and the logic levels

of the pins remain static. Wake up the chip from Sleep mode by an interrupt occurs. The RESET pin has keep functionality in Sleep mode. The Sleep mode is entered by using the following steps:

1. Write 4 to PMU_CTRL register.

2. Execute ARM Cortex-M0 WFI instruction.

4.3.2 DEEP-SLEEP MODE

In Deep-sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of instructions is suspended.

The clock to the peripheral functions are stopped because the power state of oscillators are powered down, the clock source are stopped, except RTC or LCD low speed clock source (ELS X’TAL, ILRC) if used.

The processor state and registers, peripheral registers, and internal SRAM values are maintained and the logic levels of the pins remain static.

All GPIO pins are served as wakeup pins. The user must program the GPIO registers for each pin to set the appropriate edge polarity for the corresponding wakeup event, only edge sensitive is supported to wakeup MCU. The system will exit Deep-sleep mode when GPIO indicates a GPIO interrupt to the ARM core. Furthermore, the interrupts corresponding to each input must be enabled in the NVIC.

The RESET pin has keep functionality in Deep-sleep mode. The Deep-sleep mode is entered by using the following steps:

1. Write 2 to PMU_CTRL register.

2. Execute ARM WFI instruction. The advantage of the Deep-sleep mode is that can power down clock generating blocks such as oscillators and PLL,

thereby gaining far greater dynamic power savings over Sleep mode. In addition, the Flash can be powered down in Deep-sleep mode resulting in savings in static leakage power, however at the expense of longer wake-up times for the Flash memory.

4.3.3 DEEP POWER-DOWN (DPD) MODE

In Deep power-down mode, power (Turn off the on-chip voltage regulator) and clocks are shut off to the entire chip with the exception of the GPIO pins.

The processor state and registers, peripheral registers, and internal SRAM values are not retained. However, the chip can retain data in four BACKUP registers, and the status of all GPIO pins can also be latched.

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32-Bit Cortex-M0 Micro-Controller

All GPIO pins can be served as DPDWAKEUP pins. However, the DPDWAKEUP pins which are used to wake up MCU shall be set as input pull-up and keep in HIGH level before entering Deep power-down mode. The user must program the GPIO registers for each pin to set the appropriate GPIO status (input pull-up, input pull-down, input floating, output high, and output low, open-drain) and then program PMU_LATCHCTRL1 register to latch the status of all GPIO pins.

When any of the DPDWAKEUP pins is pulled LOW, MCU wakes up from Deep power-down mode. The on-chip voltage regulator will be turned on, and when the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the chip re-boots.

Once the chip has rebooted, the user can read PMU_CTRL register to verify that the reset was caused by a wake-up event from Deep power-down and was not a cold reset. If MCU wakes up from Deep power-down mode, the user must program GPIO registers with the same settings (input pull-up, input pull-down, input floating, output high, and output low) and then program PMU_LATCHCTRL2 register to release the status of all GPIO pins.

The RESET pin has no functionality in Deep power-down mode.

4.3.3.1 Entering Deep power-down mode

Follow these steps to enter Deep power-down mode from Normal mode:

1. Disable analog IP (ADC, LCD, HXTAL, LXTAL), External reset, SWD.

2. Setup the desired GPIO status of all GPIO pins. The DPDWAKEUP pins which are used to wake up MCU shall be set as input-pull up and keep in HIGH level. (Strongly recommended to set output high first, and then set as input pull-up to reduce pull-up time)

3. (Optional) Save data to be retained during Deep power-down to the DATA bits in Backup registers.

4. Write 0x5A5A0001 to PMU_LATCHCTRL1 register to latch the status of all GPIO pins.

5. Write 1 to PMU_CTRL register.

6. Time spent between step 1 and step 5 shall longer than 20 us.

7. Execute ARM Cortex-M0 WFI/WFE instruction.

After step 7, the PMU turns off the on-chip voltage regulator and waits for a wake-up signal from the DPDWAKEUP pins.

4.3.3.2 Exiting Deep power-down mode

Follow these steps to wake up the chip from Deep power-down mode:

1. Any of the DPDWAKEUP pins level is from HIGH to LOW.

– The PMU will turn on the on-chip voltage regulator. When the core voltage reaches the power-on-reset (POR)

Trigger point, a system reset will be triggered and the chip reboots.

– All registers will be reset, except the Backup registers and PMU_CTRL register.

2. Read the PMU_CTRL register to verify that the reset was caused by a wake-up event from Deep power-down and

was not a cold reset.

3. Clear PMU_CTRL register.

4. (Optional) Read the stored data in the backup registers.

5. Setup the same GPIO status of all GPIO pins as step 2 of 4.3.3.1.

6. Write 0x5A5A0001 to PMU_LATCHCTRL2 register to release the status of all GPIO pins.

7. Setup the PMU for the next Deep power-down cycle.

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 Note: Wakeup from Sleep mode spends NO wakeup time if the clock doesn’t stop.

32-Bit Cortex-M0 Micro-Controller

4.4 WAKEUP

4.4.1 OVERVIEW

Under low power mode, program doesn’t execute. The wakeup trigger can wake the system up to normal mode. The wakeup function builds in interrupt operation and trigger system executing interrupt service routine as system wakeup occurrence.

 The wakeup trigger sources of the Sleep mode are all interrupts and the RESET pin.  The wakeup trigger sources of the Deep-sleep mode are the GPIO interrupt, RTC interrupt, LCD interrupt, and the

RESET pin.

 The wakeup trigger sources of the Deep Power-down mode are DPDWAKEUP pins which are input pull-up and

latched before entering DPD mode.

4.4.2 WAKEUP TIME

When the system is in Sleep mode, the high clock is enabled or disabled by F/W. If the high clock stops and MCU is waken up from Sleep mode, MCU waits for 2048 external high-speed oscillator clocks and 32 internal high-speed oscillator clocks as the wakeup time to stable the oscillator circuit. After the wakeup time, the system goes into the normal mode.

When the system is in Deep-sleep mode, the high clock will stop. When MCU is waken up from Deep-sleep mode, MCU waits for 2T*ILRC and IHRC/EHS warm up time(32T*IHRC/2048T*EHS). After the wakeup time, the system goes into the normal mode.

The value of the external high clock oscillator wakeup time from Deep sleep mode is as the following.

The total Wakeup time of EHS X’tal = 2T*ILRC + 1/F

* 2048 (sec) + high clock start-up time

EHS

 Example: F

= 62.5us + 112.4 us + oscillator start-up time (F

The value of the IHRC wakeup time is as the following.

=20MHz, the wakeup time from Deep sleep mode is as the following.

EHS

The total Wakeup time = 2T*ILRC + 1/F

* 2048 + oscillator start-up time

EHS

The total Wakeup time of IHRC = 2T*ILRC + 1/F

* 32 (sec)

IHRC

 Example: F

The total Wakeup time = 2T*ILRC + 1/F

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=12MHz, the wakeup time is as the following.

IHRC

* 32 = 62.5us + 2.67 us (F

IHRC

= 12MHz)

IHRC

= 20MHz)

EHS

SN32F760 Series

 Note: The high clock start-up time is depended on the VDD and oscillator type of high clock.

Deep power-down

mode

Reset

Run

mode

Deep-sleep

mode

Sleep

mode

Wake-up condition

Interrupt

Wake-up condition

GPIO Wakeup RTC interrupt LCD interrupt

Wake-up condition

Pulling any of the DPDWAKEUP pins LOW

Reset condition

One of reset trigger sources actives

Reset condition

One of reset trigger sources actives

Enter mode condition

1. PMU_CTRL = 4

2. WFI instruction

Enter mode condition

1. Pull High DPDWAKEUP pins

2. DPDEN = 1

3. WFI instruction

Enter mode condition

1. PMU_CTRL = 2

2. WFI instruction

32-Bit Cortex-M0 Micro-Controller

4.5 STATE MACHINE OF PMU

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Operation

Mode

Normal Mode

Low-Power Mode

Sleep Mode

Deep-Sleep Mode

Deep Power-down Mode

IHRC

By IHRCEN

Disable

OFF

ILRC

ON

***

OFF

EHS X’TAL

By EHSEN

Disable

OFF

ELS X’TAL

By ELSEN

***

OFF

PLL

By PLLEN

Disable

OFF

Cortex-M0

Running

Stop

Flash ROM

Enable

Disable

OFF

RAM

Enable

Maintain

OFF

ADC

By ADENB

Disable

LVD

By LVDEN

Disable

OFF

LCD

By LCDENB

***

OFF

RTC

By RTCEN

OFF

Peripherals

By Enable bit of each peripherals

Disable HCLK

OFF

IO status

-

Maintained

Latched

Wakeup

Source

N/A

All interrupts,

RESET pin

GPIO interrupt,

RTC interrupt, LCD interrupt,

RESET pin

DPDWAKEUP pins

(which are input pull-up)

LCDENB

LCDCLK

RTCENB

RTC_CLKS

ILRC*

ELS*

0

--0

--- X X 1 0 (ILRC)

O X 1 (ELS)

X

O

1

0 (ILRC)

0

---

O

X

1 (ELS)

X

O

1

0 (ILRC)

1

0 (ILRC)

O

X

1 (ELS)

X

O

1

0 (ILRC)

1

1 (ELS)

O

1 (ELS)

0 (ILRC)

O

32-Bit Cortex-M0 Micro-Controller

4.6 OPERATION MODE COMPARSION TABLE

***

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 Note: Backup registers will be reset only when all power has been completely removed from the chip.

Bit

Name

Description

Attribute

Reset

31:8

Reserved

R

0

7:0

BACKUPDATA[7:0]

BACKUPDATA Data retained during Deep power-down mode.

R/W

0

 Note: 1. The PMU_CTRL register retains data through the Deep power-down mode when power is still

applied to the VDD pin, and will be reset only when all power has been completely removed from the chip.

2. The pins which are not pin-out shall be set correctly to decrease power consumption in low- power modes. Strongly recommended to set these pins as input pull-up.

Bit

Name

Description

Attribute

Reset

31:3

Reserved

R

0

2:0

MODE[2:0]

Low power mode selection 000: Disable. 001: WFI instruction will make MCU enter Deep-power down mode. 010: WFI instruction will make MCU enter Deep-sleep mode. 100: WFI instruction will make MCU enter Sleep mode. Other: Disable

R/W

0

32-Bit Cortex-M0 Micro-Controller

4.7 PMU REGISTERS

Base Address: 0x4003 2000

4.7.1 Backup registers 0~15 (PMU_BKP0~15)

Address Offset: 0x0, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0x24, 0x28, 0x2C, 0x30, 0x34, 0x38, 0x3C

The backup registers retain data through the Deep power-down mode when power is still applied to the VDD pin but the chip has entered Deep power-down mode.

4.7.2 Power Control register (PMU_CTRL)

Address Offset: 0x40 The power control register selects whether one of the ARM Cortex-M0 controlled power-down modes (Sleep mode or

Deep-sleep mode) or the Deep power-down mode is entered and provides the flags for Sleep or Deep-sleep modes and Deep power-down modes respectively.

4.7.3 I/O Latch Control register 1 (PMU_LATCHCTRL1)

Address Offset: 0x44

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Bit

Name

Description

Attribute

Reset

31:16

LATCHKEY

Latch register key. Read as 0. When writing to the register you must write 0x5A5A to LATCHKEY, otherwise behaviour of writing to the register is ignored.

W

0

15:1

Reserved

R

0

LATCHEN

Latch enable bit 0: No effect 1: Enable GPIO latch function

R/W

0

Bit

Name

Description

Attribute

Reset

31:16

LATCHKEY

Latch register key. Read as 0. When writing to the register you must write 0x5A5A to LATCHKEY, otherwise behaviour of writing to the register is ignored.

W

0

15:1

Reserved

R

0

LATCHDIS

Latch disable bit 0: No effect 1: Disable GPIO latch function

R/W

0

Bit

Name

Description

Attribute

Reset

31:1

Reserved

R

0

LATCH

Latch status bit 0: Not Latch yet 1: GPIO status is Latched.

R

0

32-Bit Cortex-M0 Micro-Controller

4.7.4 I/O Latch Control register 2 (PMU_LATCHCTRL2)

Address Offset: 0x48

4.7.5 I/O Latch Status register (PMU_LATCHST)

Address Offset: 0x4C

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5

32-Bit Cortex-M0 Micro-Controller

GENERAL PURPOSE I/O PORT (GPIO)

5.1 OVERVIEW

Digital ports can be configured input/output by SW

 Each individual port pin can serve as external interrupt input pin.  Interrupts can be configured on single falling or rising edges and on both edges.  The I/O configuration registers control the electrical characteristics of the pads.  Internal pull-up/pull-down resistor.  Most of the I/O pins are mixed with analog pins and special function pins.

5.2 GPIO MODE

All GPIO pins are inputs and floating by default. The MODE bits in the GPIOn_CFG (n=0,1,2,3) register allow the selection of on-chip pull-up or pull-down resistors for each pin or select the repeater mode.

The repeater mode enables the pull-up resistor if the pin is logic HIGH and enables the pull-down resistor if the pin is logic LOW. This causes the pin to retain its last known state if it is configured as an input and is not driven externally. The state retention is not applicable to the Deep power-down mode.

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SN32F760 Series

Bit

Name

Description

Attribute

Reset

31:16

Reserved

R

0

15:0

DATA[15:0]

Input data (read) or output data (write) for Pn.0 to Pn.15

R/W

0

 Note: HW will switch I/O Mode directly when Specific function (Peripheral, ADC) is enabled, not through

GPIOn_MODE register.

Bit

Name

Description

Attribute

Reset

31:16

CURRENT[15:0]

Driving/Sinking current selection (x = 0 to 15) 0: Typical 10mA 1: Typical 20mA

R/W

0

15:0

MODE[15:0]

Selects pin x as input or output (x = 0 to 15) 0: Pn.x is configured as input 1: Pn.x is configured as output.

R/W

0

 Note: HW will switch I/O Mode directly when Specific function (Peripheral, ADC) is enabled, not through

GPIOn_MODE register.

Bit

Name

Description

Attribute

Reset

31:30

CFG15[1:0]

Configuration of Pn.15 00: Pull-up resistor enabled. 01: Pull-down resistor enabled. 10: Inactive (no pull-down/pull-up resistor enabled). 11: Repeater mode.

R/W

10b

29:28

CFG14[1:0]

Configuration of Pn.14 00: Pull-up resistor enabled. 01: Pull-down resistor enabled. 10: Inactive (no pull-down/pull-up resistor enabled).

R/W

10b

32-Bit Cortex-M0 Micro-Controller

5.3 GPIO REGISTERS

Base Address: 0x4004 4000 (GPIO 0)

0x4004 6000 (GPIO 1) 0x4004 8000 (GPIO 2) 0x4004 A000 (GPIO 3)

5.3.1 GPIO Port n Data register (GPIOn_DATA) (n=0,1,2,3)

Address offset: 0x00

5.3.2 GPIO Port n Mode register (GPIOn_MODE) (n=0,1,2,3)

Address offset: 0x04

5.3.3 GPIO Port n Configuration register (GPIOn_CFG) (n=0,1,2,3)

Address offset: 0x08 Reset value: 0xAAAAAAAA

SONiX TECHNOLOGY CO., LTD Page 74 Version 2.0

SN32F760 Series

11: Repeater mode.