SONIX SN32F107, SN32F108, SN32F109 User Manual
SN32F100 Series
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32-Bit Cortex-M0 Micro-Controller
SN32F100 Series
USER’S MANUAL
SN32F107
SN32F108
SN32F109
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.
SONiX TECHNOLOGY CO., LTD Page 1 Version 1.9
SN32F100 Series
Version
Date
Description
1.0
2013/03/18
First version released.
1.1
2013/03/29
1. Update Codec Spec.
2. Update DAC Setting 3 Register.
3. Update Sigma-delta DAC Power-Up Sequence.
1.2
2013/04/02
1. Update Codec Spec.
2. Update ADC Setting 23 Register.
3. Update DAC Setting 1 Register and DAC Setting 2 Register.
1.3
2013/06/04
1. Add SN32F100 Start Kit V1.1 description.
2. Add Comparator Output Debounce Time.
3. Update supply current.
4. Add Operation Mode Comparison Table.
5. Update System Block Diagram.
6. Update System Tick Timer description.
7. Update LQFP 64 Pin Package Information.
8. Update Comparator description.
9. Modify ADC’s SEL_MIC definition.
1.4
2013/07/16
1. Update I2S’s Status register default value.
2. Update ADC’s SEL_MIC register default value.
3. Update Code Security diagram.
4. Update Code Option Table.
5. Update High-level and Low-level input voltage Spec.
6. Update P0.14/DPDWAKEUP pin description.
1.5
2014/02/27
1. Update Electrical characteristics.
2. Update Code Security table in Code Security section.
3. Add Note for I/O open-drain function.
4. Add descriptions of I2C events which trigger I2C interrupt for I2Cn_STAT register.
5. Update SN-LINK description in Chap 17. Development Tool.
6. Add Notice for BOOT pin in Chap 16. SWD.
7. Add WAKEUP sections.
8. Fix typing error.
1.6
2014/06/04
1. Update SN-LINK-V2 photos.
2. Fix typing errors.
1.7
2015/05/29
1. Update UART baud rate sample.
1.8
2016/07/22
1. Fix typing errors.
2. Add Notice: HCLK MUST be equal or less than 24MHz during Flash program and erase
operations.
3. Add SSPn Data Fetch (SSPn_DF) register.
4. Update LQFP48 package information.
1.9
2018/02/02
1. Fix typing errors.
2. Remove SYSTICKPRE[1:0]
3. Remove SYS0_ANTIEFT register.
4. Update WDTPRE[2:0] bits description in SYS1_APBCP1 register.
5. Update TO[15:0] bits description in I2Cn_TOCTRL register.
6. Add Note for setting the pins which are not pin-out.
32-Bit Cortex-M0 Micro-Controller
AMENDENT HISTORY
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Table of Content
AMENDENT HISTORY ................................................................................................................................ 2
PRODUCT OVERVIEW ....................................................................................................................... 13
1.1 FEATURES ...................................................................................................................................... 13
1.2 SYSTEM BLOCK DIAGRAM ........................................................................................................ 15
1.3 CLOCK GENERATION BLOCK DIAGRAM ................................................................................ 16
1.4 PIN ASSIGNMENT ......................................................................................................................... 17
1.5 PIN DESCRIPTIONS ....................................................................................................................... 20
1.6 PIN CIRCUIT DIAGRAMS ............................................................................................................. 25
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 27
2.1 MEMORY MAP ............................................................................................................................... 27
2.2 SYSTEM TICK TIMER ................................................................................................................... 28
2.2.1 OPERATION ............................................................................................................................ 28
2.2.2 SYSTICK USAGE HINTS AND TIPS ....................................................................................... 29
2.2.3 SYSTICK REGISTERS .............................................................................................................. 29
2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL) ................................... 29
2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD) ........................................... 29
2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL) ............................................ 30
2.2.3.4 System Tick Timer Calibration Value register (SYST_CALIB) ......................................... 30
2.3 NESTED VECTORED INTERRUPT CONTROLLER (NVIC) ..................................................... 31
2.3.1 INTERRUPT AND EXCEPTION VECTORS ........................................................................... 31
2.3.2 NVIC REGISTERS .................................................................................................................... 31
2.3.2.1 IRQ0~31 Interrupt Set-Enable Register (NVIC_ISER) ....................................................... 32
2.3.2.2 IRQ0~31 Interrupt Clear-Enable Register (NVIC_ICER) ................................................... 32
2.3.2.3 IRQ0~31 Interrupt Set-Pending Register (NVIC_ISPR) ..................................................... 32
2.3.2.4 IRQ0~31 Interrupt Clear-Pending Register (NVIC_ICPR) ................................................. 32
2.3.2.5 IRQ0~31 Interrupt Priority Register (NVIC_IPRn) (n=0~7) ............................................... 33
2.4 APPLICATION INTERRUPT AND RESET CONTROL (AIRC) .................................................. 33
2.5 CODE OPTION TABLE .................................................................................................................. 35
2.6 CORE REGISTER OVERVIEW ..................................................................................................... 36
SYSTEM CONTROL............................................................................................................................. 37
3.1 RESET .............................................................................................................................................. 37
3.1.1 POWER-ON RESET (POR) ...................................................................................................... 37
3.1.2 WATCHDOG RESET (WDT RESET) ....................................................................................... 38
3.1.3 BROWN-OUT RESET............................................................................................................... 38
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3.1.3.1 BROWN OUT DESCRIPTION ........................................................................................... 38
3.1.3.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION ............................................... 39
3.1.3.3 BROWN-OUT RESET IMPROVEMENT .......................................................................... 39
3.1.4 EXTERNAL RESET .................................................................................................................. 40
3.1.4.1 SIMPLY RC RESET CIRCUIT ........................................................................................... 41
3.1.4.2 DIODE & RC RESET CIRCUIT ......................................................................................... 41
3.1.4.3 ZENER DIODE RESET CIRCUIT ...................................................................................... 42
3.1.4.4 VOLTAGE BIAS RESET CIRCUIT ................................................................................... 42
3.1.4.5 EXTERNAL RESET IC ....................................................................................................... 43
3.1.5 SOFTWARE RESET ................................................................................................................. 43
3.2 SYSTEM CLOCK ............................................................................................................................ 44
3.2.1 INTERNAL RC CLOCK SOURCE ........................................................................................... 44
3.2.1.1 Internal High-speed RC Oscillator (IHRC) .......................................................................... 44
3.2.1.2 Internal Low-speed RC Oscillator (ILRC) ........................................................................... 44
3.2.2 PLL ........................................................................................................................................... 45
3.2.2.1 PLL Frequency selection ...................................................................................................... 45
3.2.3 EXTERNAL CLOCK SOURCE ................................................................................................ 46
3.2.3.1 External High-speed (EHS) Clock ....................................................................................... 46
3.2.3.2 CRYSTAL/CERAMIC ......................................................................................................... 46
3.2.3.3 Audio External High-speed (AUEHS) Clock ....................................................................... 47
3.2.3.4 External Low-speed (ELS) Clock......................................................................................... 47
3.2.3.5 CRYSTAL ............................................................................................................................ 47
3.2.3.6 Bypass Mode ........................................................................................................................ 48
3.2.4 SYSTEM CLOCK (SYSCLK) SELECTION............................................................................... 49
3.2.5 CLOCK-OUT CAPABITITY ..................................................................................................... 49
3.3 SYSTEM CONTROL REGISTERS 0 .............................................................................................. 50
3.3.1 Analog Block Control register (SYS0_ANBCTRL) ................................................................... 50
3.3.2 PLL control register (SYS0_PLLCTRL) ................................................................................... 50
3.3.2.1 RECOMMEND FREQUENCY SETTING.......................................................................... 51
3.3.3 Clock Source Status register (SYS0_CSST) .............................................................................. 52
3.3.4 System Clock Configuration register (SYS0_CLKCFG) .......................................................... 52
3.3.5 AHB Clock Prescale register (SYS0_AHBCP) ......................................................................... 52
3.3.6 System Reset Status register (SYS0_RSTST) ............................................................................ 53
3.3.7 LVD Control register (SYS0_LVDCTRL) ................................................................................. 53
3.3.8 External RESET Pin Control register (SYS0_EXRSTCTRL) ................................................... 55
3.3.9 SWD Pin Control register (SYS0_SWDCTRL) ......................................................................... 55
3.4 SYSTEM CONTROL REGISTERS 1 .............................................................................................. 56
3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN) .................................................................... 56
3.4.2 APB Clock Prescale register 0 (SYS1_APBCP0) ..................................................................... 57
3.4.3 APB Clock Prescale register 1 (SYS1_APBCP1) ..................................................................... 58
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3.4.4 Peripheral Reset register (SYS1_PRST) ................................................................................... 59
SYSTEM OPERATION MODE ........................................................................................................... 61
4.1 OVERVIEW ..................................................................................................................................... 61
4.2 NORMAL MODE ............................................................................................................................ 61
4.3 LOW-POWER MODES ................................................................................................................... 61
4.3.1 SLEEP MODE .......................................................................................................................... 61
4.3.2 DEEP-SLEEP MODE............................................................................................................... 62
4.3.3 DEEP POWER-DOWN (DPD) MODE .................................................................................... 62
4.3.3.1 Entering Deep power-down mode ........................................................................................ 63
4.3.3.2 Exiting Deep power-down mode .......................................................................................... 63
4.4 WAKEUP INTERRUPT .................................................................................................................. 63
4.5 WAKEUP ......................................................................................................................................... 63
4.5.1 OVERVIEW .............................................................................................................................. 63
4.5.2 WAKEUP TIME ........................................................................................................................ 63
4.6 STATE MACHINE OF PMU ........................................................................................................... 64
4.7 OPERATION MODE COMPARSION TABLE .............................................................................. 65
4.8 PMU REGISTERS ........................................................................................................................... 66
4.8.1 Backup registers 0 to 15 (PMU_BKP0~15) ............................................................................. 66
4.8.2 Power control register (PMU_CTRL) ...................................................................................... 66
GENERAL PURPOSE I/O PORT (GPIO) .......................................................................................... 67
5.1 OVERVIEW ..................................................................................................................................... 67
5.2 GPIO MODE .................................................................................................................................... 67
5.3 GPIO REGISTERS ........................................................................................................................... 68
5.3.1 GPIO Port n Data register (GPIOn_DATA) (n=0,1,2,3)......................................................... 68
5.3.2 GPIO Port n Mode register (GPIOn_MODE) (n=0,1,2,3) ...................................................... 68
5.3.3 GPIO Port n Configuration register (GPIOn_CFG) (n=0,1,2,3) ............................................ 68
5.3.4 GPIO Port n Interrupt Sense register (GPIOn_IS) (n=0,1,2,3) ............................................... 70
5.3.5 GPIO Port n Interrupt Both-edge Sense register (GPIOn_IBS) (n=0,1,2,3) ........................... 70
5.3.6 GPIO Port n Interrupt Event register (GPIOn_IEV) (n=0,1,2,3) ............................................ 70
5.3.7 GPIO Port n Interrupt Enable register (GPIOn_IE) (n=0,1,2,3) ............................................ 70
5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3) ................................... 71
5.3.9 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3) .............................................. 71
5.3.10 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3) .................................... 71
5.3.11 GPIO Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3) ............................... 71
5.3.12 GPIO Port n Open-Drain Control register (GPIOn_ODCTRL) (n=0,1,2,3) .......................... 71
16-BIT TIMER WITH CAPTURE FUNCTION ................................................................................ 74
6.1 OVERVIEW ..................................................................................................................................... 74
6.2 FEATURES ...................................................................................................................................... 74
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6.3 PIN DESCRIPTION ......................................................................................................................... 74
6.4 BLOCK DIAGRAM ......................................................................................................................... 75
6.5 TIMER OPERATION ...................................................................................................................... 76
6.6 PWM ................................................................................................................................................. 77
6.7 CT16BN REGISTERS ...................................................................................................................... 78
6.7.1 CT16Bn Timer Control register (CT16Bn_TMRCTRL) (n=0,1) ............................................. 78
6.7.2 CT16Bn Timer Counter register (CT16Bn_TC) (n=0,1) ......................................................... 78
6.7.3 CT16Bn Prescale register (CT16Bn_PRE) (n=0,1) ................................................................. 78
6.7.4 CT16Bn Prescale Counter register (CT16Bn_PC) (n=0,1) ..................................................... 78
6.7.5 CT16Bn Count Control register (CT16Bn_CNTCTRL) (n=0,1) .............................................. 79
6.7.6 CT16Bn Match Control register (CT16Bn_MCTRL) (n=0,1) ................................................. 79
6.7.7 CT16Bn Match register 0~3 (CT16Bn_MR0~3) (n=0,1) ......................................................... 80
6.7.8 CT16Bn Capture Control register (CT16Bn_CAPCTRL) (n=0,1) .......................................... 80
6.7.9 CT16Bn Capture 0 register (CT16Bn_CAP0) (n=0,1) ............................................................ 81
6.7.10 CT16Bn External Match register (CT16Bn_EM) (n=0,1) .................................................... 81
6.7.11 CT16Bn PWM Control register (CT16Bn_PWMCTRL) (n=0,1) ............................................. 81
6.7.12 CT16Bn Timer Raw Interrupt Status register (CT16Bn_RIS) (n=0,1) .................................... 82
6.7.13 CT16Bn Timer Interrupt Clear register (CT16Bn_IC) (n=0,1) ............................................... 82
32-BIT TIMER WITH CAPTURE FUNCTION ................................................................................ 83
7.1 OVERVIEW ..................................................................................................................................... 83
7.2 FEATURES ...................................................................................................................................... 83
7.3 PIN DESCRIPTION ......................................................................................................................... 83
7.4 BLOCK DIAGRAM ......................................................................................................................... 84
7.5 TIMER OPERATION ...................................................................................................................... 85
7.6 PWM ................................................................................................................................................. 86
7.7 CT32BN REGISTERS ...................................................................................................................... 87
7.7.1 CT32Bn Timer Control register (CT32Bn_TMRCTRL) (n=0,1) ............................................. 87
7.7.2 CT32Bn Timer Counter register (CT32Bn_TC) (n=0,1) ......................................................... 87
7.7.3 CT32Bn Prescale register (CT32Bn_PRE) (n=0,1) ................................................................. 87
7.7.4 CT32Bn Prescale Counter register (CT32Bn_PC) (n=0,1) ..................................................... 87
7.7.5 CT32Bn Count Control register (CT32Bn_CNTCTRL) (n=0,1) .............................................. 88
7.7.6 CT32Bn Match Control register (CT32Bn_MCTRL) (n=0,1) ................................................. 88
7.7.7 CT32Bn Match register 0~3 (CT32Bn_MR0~3) (n=0,1) ......................................................... 89
7.7.8 CT32Bn Capture Control register (CT32Bn_CAPCTRL) (n=0,1) .......................................... 89
7.7.9 CT32Bn Capture 0 register (CT32Bn_CAP0) (n=0,1) ............................................................ 90
7.7.10 CT32Bn External Match register (CT32Bn_EM) (n=0,1) ....................................................... 90
7.7.11 CT32Bn PWM Control register (CT32Bn_PWMCTRL) (n=0,1) ............................................. 90
7.7.12 CT32Bn Timer Raw Interrupt Status register (CT32Bn_RIS) (n=0,1) .................................... 91
7.7.13 CT32Bn Timer Interrupt Clear register (CT32Bn_IC) (n=0,1) ............................................... 91
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WATCHDOG TIMER (WDT) .............................................................................................................. 92
8.1 OVERVIEW ..................................................................................................................................... 92
8.2 BLOCK DIAGRAM ......................................................................................................................... 93
8.3 WDT REGISTERS ........................................................................................................................... 94
8.3.1 Watchdog Configuration register (WDT_CFG) ....................................................................... 94
8.3.2 Watchdog Clock Source register (WDT_CLKSOURCE) ......................................................... 94
8.3.3 Watchdog Timer Constant register (WDT_TC)........................................................................ 94
8.3.4 Watchdog Feed register (WDT_FEED) ................................................................................... 95
REAL-TIME CLOCK (RTC) ............................................................................................................... 96
9.1 OVERVIEW ..................................................................................................................................... 96
9.2 FEATURES ...................................................................................................................................... 96
9.3 FUNCTIONAL DESCRIPTION ...................................................................................................... 96
9.3.1 INTRODUCTION ..................................................................................................................... 96
9.3.2 RESET RTC REGISTERS ......................................................................................................... 96
9.3.3 RTC FLAG ASSERTION .......................................................................................................... 96
9.3.4 RTC OPERATION .................................................................................................................... 97
9.4 BLOCK DIAGRAM ......................................................................................................................... 98
9.5 RTC REGISTERS ............................................................................................................................ 99
9.5.1 RTC Control register (RTC_CTRL) ......................................................................................... 99
9.5.2 RTC Clock Source Select register (RTC_CLKS) ...................................................................... 99
9.5.3 RTC Interrupt Enable register (RTC_IE) ................................................................................. 99
9.5.4 RTC Raw Interrupt Status register (RTC_RIS) ........................................................................ 99
9.5.5 RTC Interrupt Clear register (RTC_IC) ................................................................................. 100
9.5.6 RTC Second Counter Reload Value register (RTC_SECCNTV) ............................................ 100
9.5.7 RTC Second Count register (RTC_SECCNT) ........................................................................ 100
9.5.8 RTC Alarm Counter Reload Value register (RTC_ALMCNTV) ............................................. 100
9.5.9 RTC Alarm Count register (RTC_ALMCNT) ......................................................................... 101
SPI/SSP .............................................................................................................................................. 102
10.1 OVERVIEW ................................................................................................................................... 102
10.2 FEATURES .................................................................................................................................... 102
10.3 PIN DESCRIPTION ....................................................................................................................... 103
10.4 INTERFACE DESCRIPTION ....................................................................................................... 104
10.4.1 SPI .......................................................................................................................................... 104
10.4.2 SSI ........................................................................................................................................... 105
10.4.3 COMMUNICATION FLOW ................................................................................................... 105
10.4.3.1 SINGLE-FRAME ........................................................................................................... 105
10.4.3.2 MULTI-FRAME ............................................................................................................ 106
10.5 AUTO-SEL (AUTO-CS) ................................................................................................................... 106
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10.6 SSP REGISTERS ........................................................................................................................... 107
10.6.1 SSP n Control register 0 (SSPn_CTRL0) (n=0, 1) ................................................................. 107
10.6.2 SSP n Control register 1 (SSPn_CTRL1) (n=0, 1) ................................................................. 108
10.6.3 SSP n Clock Divider register (SSPn_CLKDIV) (n=0, 1) ....................................................... 108
10.6.4 SSP n Status register (SSPn_STAT) (n=0, 1) ......................................................................... 108
10.6.5 SSP n Interrupt Enable register (SSPn_IE) (n=0, 1) ............................................................. 109
10.6.6 SSP n Raw Interrupt Status register (SSPn_RIS) (n=0, 1) ..................................................... 109
10.6.7 SSP n Interrupt Clear register (SSPn_IC) (n=0, 1) ............................................................... 109
10.6.8 SSP n Data register (SSPn_DATA) (n=0, 1) .......................................................................... 110
10.6.9 SSP n Data Fetch register (SSPn_DF) (n=0, 1) .................................................................... 110
I2C ...................................................................................................................................................... 111
11.1 OVERVIEW ................................................................................................................................... 111
11.2 FEATURES .................................................................................................................................... 111
11.3 PIN DESCRIPTION ....................................................................................................................... 112
11.4 WAVE CHARACTERISTICS ....................................................................................................... 112
11.5 I2C MASTER MODES .................................................................................................................. 113
11.5.1 MASTER TRANSMITTER MODE .......................................................................................... 113
11.5.2 MASTER RECEIVER MODE ................................................................................................. 113
11.5.3 ARBITRATION ....................................................................................................................... 113
11.6 I2C SLAVE MODES ...................................................................................................................... 114
11.6.1 SLAVE TRANSMITTER MODE ............................................................................................. 114
11.6.2 SLAVE RECEIVER MODE .................................................................................................... 114
11.7 MONITOR MODE ......................................................................................................................... 115
11.7.1 INTERRUPT ........................................................................................................................... 115
11.7.2 LOSS of ARBITRATION ......................................................................................................... 115
11.8 I2C REGISTERS ............................................................................................................................ 116
11.8.1 I2C n Control register (I2Cn_CTRL) (n=0,1) ........................................................................ 116
11.8.2 I2C n Status register (I2Cn_STAT) (n=0,1) ........................................................................... 117
11.8.3 I2C n TX Data register (I2Cn_TXDATA) (n=0,1) ................................................................. 118
11.8.4 I2C n RX Data register (I2Cn_RXDATA) (n=0,1) ................................................................. 118
11.8.5 I2C n Slave Address 0 register (I2Cn_SLVADDR0) (n=0,1) ................................................. 118
11.8.6 I2C n Slave Address 1~3 register (I2Cn_SLVADDR1~3) (n=0,1) ........................................ 118
11.8.7 I2C n SCL High Time register (I2Cn_SCLHT) (n=0,1) ......................................................... 118
11.8.8 I2C n SCL Low Time register (I2Cn_SCLLT) (n=0,1) ........................................................... 119
11.8.9 I2C n Timeout Control register (I2Cn_TOCTRL) (n=0,1) .................................................... 119
11.8.10 I2C n Monitor Mode Control register (I2Cn_MMCTRL) (n=0,1) ..................................... 119
UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER (UART) .................... 121
12.1 OVERVIEW ................................................................................................................................... 121
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12.2 FEATURES .................................................................................................................................... 121
12.3 PIN DESCRIPTION ....................................................................................................................... 121
12.4 BLOCK DIAGRAM ....................................................................................................................... 122
12.5 BAUD RATE CALCULATION .................................................................................................... 123
12.6 AUTO-BAUD FLOW .................................................................................................................... 124
12.6.1 AUTO-BAUD .......................................................................................................................... 124
12.6.2 AUTO-BAUD MODES ........................................................................................................... 125
12.7 UART REGISTERS ....................................................................................................................... 127
12.7.1 UART n Receiver Buffer register (UARTn_RB) (n=0, 1) ....................................................... 127
12.7.2 UART n Transmitter Holding register (UARTn_TH) (n=0, 1) ............................................... 127
12.7.3 UART n Divisor Latch LSB registers (UARTn_DLL) (n =0, 1) ............................................. 127
12.7.4 UART n Divisor Latch MSB register (UARTn_DLM) (n=0,1) .............................................. 127
12.7.5 UART n Interrupt Enable register (UARTn_IE) (n=0, 1) ...................................................... 128
12.7.6 UART n Interrupt Identification register (UARTn_II) (n=0,1) .............................................. 128
12.7.7 UART n FIFO Control register (UARTn_FIFOCTRL) (n=0,1)............................................. 130
12.7.8 UART n Line Control register (UARTn_LC) (n=0,1) ............................................................ 130
12.7.9 UART n Line Status register (UARTn_LS) (n=0,1) ................................................................ 130
12.7.10 UART n Scratch Pad register (UARTn_SP) (n=0, 1) ......................................................... 132
12.7.11 UART n Auto-baud Control register (UARTn_ABCTRL) (n=0, 1) .................................... 132
12.7.12 UART n Fractional Divider register (UARTn_FD) (n=0, 1) ............................................. 132
12.7.13 UART n Control register (UARTn_CTRL) (n=0, 1) ........................................................... 133
12.7.14 UART n Half-duplex Enable register (UARTn_HDEN) (n=0, 1) ...................................... 133
AUDIO (I2S/CODEC) ...................................................................................................................... 135
13.1 OVERVIEW ................................................................................................................................... 135
13.1.1 I2S Description ....................................................................................................................... 135
13.1.2 Codec Description .................................................................................................................. 135
13.2 FEATURES .................................................................................................................................... 135
13.2.1 I2S Features ............................................................................................................................ 135
13.2.2 Codec Features ....................................................................................................................... 135
13.3 PIN DESCRIPTION ....................................................................................................................... 136
13.3.1 I2S Pin Description ................................................................................................................ 136
13.3.2 Codec Pin Description............................................................................................................ 136
13.3.3 Audio Clock Pin Description .................................................................................................. 136
13.4 BLOCK DIAGRAM ....................................................................................................................... 137
13.4.1 I2S CLCOK CONTROL .......................................................................................................... 137
13.4.2 I2S BLOCK DIAGRAM .......................................................................................................... 137
13.4.3 16-Bit Sigma-Delta ADC BLOCK DIAGRAM ....................................................................... 138
13.4.4 16-Bit Sigma-Delta DAC BLOCK DIAGRAM ....................................................................... 139
13.5 FUNCTIONAL DESCRIPTION .................................................................................................... 140
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13.5.1 I2S OPERATION .................................................................................................................... 140
13.5.2 I2S FIFO OPERAION ............................................................................................................ 142
13.5.2.1 MONO ............................................................................................................................ 142
13.5.2.2 STEREO ......................................................................................................................... 142
13.6 I2S REGISTERS............................................................................................................................. 143
13.6.1 I2S Control register (I2S_CTRL) ........................................................................................... 143
13.6.2 I2S Clock register (I2S_CLK) ................................................................................................. 144
13.6.3 I2S Status register (I2S_STATUS) .......................................................................................... 144
13.6.4 I2S Interrupt Enable register (I2S_IE) ................................................................................... 145
13.6.5 I2S Raw Interrupt Status register (I2S_RIS) .......................................................................... 145
13.6.6 I2S Interrupt Clear register (I2S_IC) ..................................................................................... 146
13.6.7 I2S RX FIFO register (I2S_RXFIFO) .................................................................................... 146
13.6.8 I2S TX FIFO register (I2S_TXFIFO) ..................................................................................... 146
13.7 CODEC ADC REGISTERS ........................................................................................................... 146
13.7.1 ADC Setting 1 register (ADC_SET1) ..................................................................................... 146
13.7.2 ADC Setting 2 register (ADC_SET2) ..................................................................................... 147
13.7.3 ADC Setting 3 register (ADC_SET3) ..................................................................................... 147
13.7.4 ADC Setting 4 register (ADC_SET4) ..................................................................................... 147
13.7.5 ADC Setting 5 register (ADC_SET5) ..................................................................................... 147
13.7.6 ADC Setting 6 register (ADC_SET6) ..................................................................................... 147
13.7.7 ADC Setting 7 register (ADC_SET7) ..................................................................................... 147
13.7.8 ADC Setting 8 register (ADC_SET8) ..................................................................................... 148
13.7.9 ADC Setting 9 register (ADC_SET9) ..................................................................................... 148
13.7.10 ADC Setting 10 register (ADC_SET10) ............................................................................. 148
13.7.11 ADC Setting 11 register (ADC_SET11) ............................................................................. 148
13.7.12 ADC Setting 12 register (ADC_SET12) ............................................................................. 148
13.7.13 ADC Setting 13 register (ADC_SET13) ............................................................................. 149
13.7.14 ADC Setting 14 register (ADC_SET14) ............................................................................. 149
13.7.15 ADC Setting 15 register (ADC_SET15) ............................................................................. 149
13.7.16 ADC Setting 16 register (ADC_SET16) ............................................................................. 149
13.7.17 ADC Setting 18 register (ADC_SET18) ............................................................................. 150
13.7.18 ADC Setting 19 register (ADC_SET19) ............................................................................. 150
13.7.19 ADC Setting 20 register (ADC_SET20) ............................................................................. 151
13.7.20 ADC Setting 21 register (ADC_SET21) ............................................................................. 151
13.7.21 ADC Setting 22 register (ADC_SET22) ............................................................................. 151
13.7.22 ADC Setting 23 register (ADC_SET23) ............................................................................. 151
13.7.23 ADC Setting 24 register (ADC_SET24) ............................................................................. 152
13.8 CODEC DAC REGISTERS ........................................................................................................... 152
13.8.1 DAC Setting 1 register (DAC_SET1) ..................................................................................... 152
13.8.2 DAC Setting 2 register (DAC_SET2) ..................................................................................... 152
SONiX TECHNOLOGY CO., LTD Page 10 Version 1.9
SN32F100 Series
1
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4
4
4
1
1
1
5
5
5
32-Bit Cortex-M0 Micro-Controller
13.8.3 DAC Setting 3 register (DAC_SET3) ..................................................................................... 152
13.8.4 DAC Setting 4 register (DAC_SET4) ..................................................................................... 153
13.8.5 DAC Status register (DAC_STATUS)..................................................................................... 153
13.9 SIGMA-DELTA ADC CONTROL FLOW .............................................................................................. 153
13.9.1 Sigma-delta ADC Power-up Sequence ................................................................................... 153
13.9.2 Sigma-delta ADC Power-down Sequence .............................................................................. 153
13.9.3 Sigma-delta ADC Enable Sequence ....................................................................................... 154
13.10 SIGMA-DELTA DAC CONTROL FLOW .......................................................................................... 154
13.10.1 Sigma-delta DAC Power-up Sequence ............................................................................... 154
13.10.2 Sigma-delta DAC Power-down Sequence .......................................................................... 154
13.10.3 Sigma-delta DAC Enable Sequence ................................................................................... 154
24-CHANNEL COMPARATOR .................................................................................................... 155
14.1 OVERVIEW ................................................................................................................................... 155
14.2 COMPARATOR OPERATION ..................................................................................................... 156
14.3 COMPARATOR APPLICATION NOTICE .................................................................................. 157
14.4 COMPARATOR CONTROL REGISTERS ................................................................................... 157
14.4.1 Comparator Control register (CMPM) .................................................................................. 157
14.4.2 Comparator Interrupt Enable register (CMP_IE) ................................................................. 158
14.4.3 Comparator Interrupt Status register (CMP_RIS) ................................................................. 159
14.4.4 Comparator Interrupt Clear register (CMP_IC) ................................................................... 159
FLASH ............................................................................................................................................... 160
15.1 OVERVIEW ................................................................................................................................... 160
15.2 EMBEDDED FLASH MEMORY .................................................................................................. 160
15.3 FEATURES .................................................................................................................................... 160
15.4 ORGANIZATION .......................................................................................................................... 161
15.5 READ ............................................................................................................................................. 161
15.6 PROGRAM/ERASE ....................................................................................................................... 161
15.7 EMBEDDED BOOT LOADER ..................................................................................................... 161
15.8 FLASH MEMORY CONTROLLER (FMC) .................................................................................. 162
15.8.1 CODE SECURITY (CS) .......................................................................................................... 162
15.8.2 PROGRAM FLASH MEMORY ............................................................................................... 163
15.8.3 ERASE .................................................................................................................................... 163
15.8.3.1 PAGE ERASE ................................................................................................................ 163
15.8.3.2 MASS ERASE ................................................................................................................ 163
15.9 READ PROTECTION .................................................................................................................... 163
15.10 FMC REGISTERS ...................................................................................................................... 164
15.10.1 Flash Status register (FLASH_STATUS) ........................................................................... 164
15.10.2 Flash Control register (FLASH_CTRL) ............................................................................. 164
SONiX TECHNOLOGY CO., LTD Page 11 Version 1.9
SN32F100 Series
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6
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7
7
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1
1
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8
8
1
1
1
9
9
9
2
2
2
0
0
0
2
2
2
1
1
1
32-Bit Cortex-M0 Micro-Controller
15.10.3 Flash Data register (FLASH_DATA) ................................................................................. 164
15.10.4 Flash Address register (FLASH_ADDR) ........................................................................... 165
SERIAL-WIRE DEBUG (SWD) ..................................................................................................... 166
16.1 OVERVIEW ................................................................................................................................... 166
16.2 FEATURES .................................................................................................................................... 166
16.3 PIN DESCRIPTION ....................................................................................................................... 166
16.4 DEBUG NOTE ............................................................................................................................... 166
16.4.1 LIMITATIONS ........................................................................................................................ 166
16.4.2 DEBUG RECOVERY .............................................................................................................. 166
16.4.3 INTERNAL PULL-UP/DOWN RESISTORS on SWD PINS ................................................... 167
DEVELOPMENT TOOL ................................................................................................................ 168
17.1 SN-LINK-V2 .................................................................................................................................. 169
17.2 SN32F100 STARTER-KIT ............................................................................................................ 170
17.2.1 SN32F100 Start Kit V1.0 ........................................................................................................ 170
17.2.2 SN32F100 Start Kit V1.1/V1.2 ............................................................................................... 172
ELECTRICAL CHARACTERISTIC ............................................................................................ 174
18.1 ABSOLUTE MAXIMUM RATING .............................................................................................. 174
18.2 ELECTRICAL CHARACTERISTIC ............................................................................................. 174
18.3 CHARACTERISTIC GRAPHS ..................................................................................................... 176
FLASH ROM PROGRAMMING PIN ........................................................................................... 178
PACKAGE INFORMATION ......................................................................................................... 179
20.1 LQFP 48 PIN .................................................................................................................................. 179
20.2 LQFP 64 PIN .................................................................................................................................. 180
20.3 LQFP 80 PIN .................................................................................................................................. 181
MARKING DEFINITION ............................................................................................................... 182
21.1 INTRODUCTION .......................................................................................................................... 182
21.2 MARKING INDETIFICATION SYSTEM .................................................................................... 182
21.3 MARKING EXAMPLE ................................................................................................................. 183
21.4 DATECODE SYSTEM .................................................................................................................. 183
SONiX TECHNOLOGY CO., LTD Page 12 Version 1.9
SN32F100 Series
1
1
1
Memory configuration
Timer
64KB on-chip Flash programming memory.
Two 16-bit and two 32-bit general purpose timers with
8KB SRAM.
a total of four capture inputs, 6PWMs
4KB Boot ROM
DAC
Operation Frequency up to 50MHz
16-bit Sigma-delta DAC for Audio.
Can drive the L/R Channel Earphone.
Interrupt sources
SNR 90dB.
ARM Cortex-M0 built-in Nested Vectored Interrupt
THD+N -75dB.
Controller (NVIC).
ADC
I/O pin configuration
16-bit Sigma-delta ADC for Audio.
Up to 62 General Purpose I/O (GPIO) pins with
AGC function.
Configurable pull-up/pull-down resistors.
Differential Microphone input.
GPIO pins can be used as edge and level sensitive
Build-in Microphone Bias Voltage support.
interrupt sources.
SNR 94dB.
High-current source driver (20 mA)
THD+N -80dB.
Comparator input pin: CM0~CM23.
Comparator output pin: CMO.
24-channel Comparator.
Programmable Watchdog Timer (WDT)
Programmable watchdog frequency with watchdog
Interface
Clock source and divider.
-Two I2C controllers supporting I2C-bus specification
with multiple address recognition and monitor mode.
System tick timer
-Two UART controllers with fractional baud rate
24-bit timer.
generation.
The system tick timer clock is fixed to the frequency of
-Two SPI controllers with SSP features and multi-
the system clock.
protocol capabilities.
The SysTick timer is intended to generate a fixed 10-ms
-I2S Function with mono and stereo audio data
interrupt.
supported, MSB justified data format supported, and
can operate as either master or slave.
Real-Time Clock (RTC)
System clocks
LVD with separate thresholds
-External high clock: Crystal type 10MHz~25MHz
Reset: 1.65V for V
CORE
1.8V, 2.0/2.4/2.7V for VDD
-External Audio high clock: Crystal type 16.384MHz
Interrupt: 2.0/2.4/2.7/3.0V for VDD
-External low clock: Crystal type 32.768 KHz
-Internal high clock: RC type 12 MHz
Fcpu (Instruction cycle)
-Internal low clock: RC type 16 KHz
F
CPU
= F
HCLK
= F
SYSCLK
/1, F
SYSCLK
/2, F
SYSCLK
/4, …,
-PLL allows CPU operation up to the maximum CPU
F
SYSCLK
/512.
rate without the need for a high-frequency crystal.
May be run from the external high clock or the
Working voltage 1.8V ~ 3.6V
internal high RC oscillator.
-Clock output function which can reflect the internal
Operating modes
high/low RC oscillator, HCLK, PLL output, and
Normal, Sleep, Deep-sleep, and Deep power-down
external high/low clock.
Serial Wire Debug (SWD)
Package (Chip form support)
LQFP 80 pin
In-System Programming (ISP) supported
LQFP 64 pin
LQFP 48 pin
32-Bit Cortex-M0 Micro-Controller
PRODUCT OVERVIEW
1.1 FEATURES
SONiX TECHNOLOGY CO., LTD Page 13 Version 1.9
SN32F100 Series
Chip
ROM
RAM
Boot
Loader
F
CPU
.
(Max
MHz)
UART
SPI
I2C
I2S
TIMER
PWM
16-bit
Σ-δ
ADC
16-bit
Σ-δ
DAC
CMP
GPIO
with
Wakeup
Package
SN32F107F
64KB
8KB
4KB
50 1 1 2 -
16-bit x 2
32-bit x 2
4 1 1 8 32
LQFP48
SN32F108F
64KB
8KB
4KB
50 2 1 2 -
16-bit x 2
32-bit x 2
6 1 1
17
46
LQFP64
SN32F109F
64KB
8KB
4KB
50 2 2 2 1
16-bit x 2
32-bit x 2
6 1 1
24
62
LQFP80
32-Bit Cortex-M0 Micro-Controller
Features Selection Table
SONiX TECHNOLOGY CO., LTD Page 14 Version 1.9
SN32F100 Series
TEST/DEBUG
INTERFACE
GPIO ports
PIO0_0~15
PIO1_0~13
PIO2_0~15
PIO3_0~15
SWDIO
SWCLK
XTALOUT,
AUXTALOUT,
LXTALOUT
XTALIN,
AUXTALIN,
LXTALIN
CLKOUT
CT32B0_PWM[1:0]
CT32B0_CAP0
CT32B1_PWM[1:0]
CT32B1_CAP0
CT16B0_PWM[0]
CT16B0_CAP0
CT16B1_PWM[0]
CT16B1_CAP0
SCK0
SEL0
MISO0
MOSI0
SCL0
SDA0
SCK1
SEL1
MISO1
MOSI1
/RESET
ARM
CORTEX-M0
CLOCK GENERATION
FLASH ROM
64KB
SRAM
8KB
SYS
PMU
POWER CONTROL/
SYSTEM FUNCTIONS
SPI1
I2C0
UART 0
SPI0
UART 1
POWER
REGULATOR
ILRC
16KHz
IHRC
12MHz
LVD
Clocks
Controls
AHB-LITE BUS
AHB TO APB
BRIDGE
APB BUS
RTC
32-bit TIMER 0
with 2 PWM
32-bit TIMER 1
with 2 PWM
16-bit TIMER 0
with 1 PWM
16-bit TIMER 1
with 1 PWM
16-bit Sigma-delta ADC
GPIO
VCORE
VDD 1.8V~3.6V
WDT
I2C1
SCL1
SDA1
URXD1
UTXD1
I2S
I2SBCLK
I2SWS
I2SDIN
I2SDOUT
I2SMCLK
16-bit Sigma-delta DAC
Comparator
FLASH ROM
(BOOT LOADER)
4KB
CM0~CM23
CMO
VOUTP
VOUTN
VMID/VCOM
AVDD/AVSS
AVDD_DRV
AVSS_DRV
MIC_P/MIC_N
MIC_BIAS
VMID/AVDD/AVSS
URXD0
UTXD0
32-Bit Cortex-M0 Micro-Controller
1.2 SYSTEM BLOCK DIAGRAM
SONiX TECHNOLOGY CO., LTD Page 15 Version 1.9
SN32F100 Series
XTALOUT
XTALIN
External High
speed Crystal
oscillator
1MHz~25MHz
CLKOUT
PLL
1, 2, … , 32
IHRC
12MHz
ILRC
16KHz
PLLCLKSEL
IHRC
ILRC
PLLCLKout
SYSCLK
SYSCLKSEL
CLKOUTSEL
EHS
SSP0
Clock Prescaler
/1,2,4,8,16
WDTCLKSEL
WDT
Clock Prescaler
/1, 2, 4, 8, 16, 32
WDT_PCLK
SSP0_PCLK
HCLK
AHB clock for SSP0
SSP0CLKEN
WDT
register block
WDT
clock source
SSP0
register block
SSP0
clock source
AHB clock for WDT
AHB clock for AHB to APB bridge, to AHB
matrix, to Cortex-M0 FCLK, HCLK, and
System Timer ,to SYS, and to PMU
AHB clock for GPIO
GPIOCLKEN
LXTALOUT
LXTALIN
External Low
Speed Crystal
oscillator
32.768KHz
ELS
GPIO block
AHB
Prescaler
/1,2,4,…,512
PLLCLKout
RTCSEL
ILRC
ELS
/128
RTC_PCLK
RTC
register block
RTC
clock source
AHB clock for RTC
RTCCLKEN
SSP1
Clock Prescaler
/1,2,4,8,16
SSP1_PCLK
AHB clock for SSP1
SSP1CLKEN
SSP1
register block
SSP1
clock source
Comparator
Clock Prescaler
/1,2,4,8,16
CMP_PCLK
AHB clock for
Comparator
CMPCLKEN
Comparator
register block
Comparator
clock source
AHB clock for ADC
ADCCLKEN
ADC
register block
ADC
clock source
I2C0
Clock Prescaler
/1,2,4,8,16
I2C0_PCLK
AHB clock for ADC
I2C0CLKEN
I2C0
register block
I2C0
clock source
CT32B1
Clock Prescaler
/1,2,4,8,16
CT32B1_PCLK
AHB clock for CT32B1
CT32B1CLKEN
CT32B1
register block
CT32B1
clock source
CT32B0
Clock Prescaler
/1,2,4,8,16
CT32B0_PCLK
AHB clock for CT32B0
CT32B0CLKEN
CT32B0
register block
CT32B0
clock source
CT16B1
Clock Prescaler
/1,2,4,8,16
CT16B1_PCLK
AHB clock for CT16B1
CT16B1CLKEN
CT16B1
register block
CT16B1
clock source
CT16B0
Clock Prescaler
/1,2,4,8,16
CT16B0_PCLK
AHB clock for CT16B0
CT16B0CLKEN
CT16B0
register block
CT16B0
clock source
USART1
Clock Prescaler
/1,2,4,8,16
USART1_PCLK
AHB clock for USART1
USART1CLKEN
USART1
register block
USART1
clock source
USART0
Clock Prescaler
/1,2,4,8,16
USART0_PCLK
AHB clock for USART0
USART0CLKEN
USART0
register block
USART0
clock source
AHB clock for SRAM
SRAM block
AHB clock for FLASH
FLASH block
CLKOUT
Prescaler
/1,2,4,…,512
WDTCLKEN
I2C1
Clock Prescaler
/1,2,4,8,16
I2C1_PCLK
AHB clock for I2C1
I2C1CLKEN
I2C1
register block
I2C1
clock source
AHB clock for DAC
DACCLKEN
DAC
register block
DAC
clock source
I2S
Clock Prescaler
/1,2,4,8,16
I2S_PCLK
AHB clock for I2S
I2SCLKEN
I2S
register block
I2S
clock source
AUXTALOUT
AUXTALIN
External High
speed Crystal
oscillator
16.384MHz
Audio Clock
Prescaler
/1,2,4,8,16
MCLKSEL
MCLK
AUCLKout
AUCLKout
32-Bit Cortex-M0 Micro-Controller
1.3 CLOCK GENERATION BLOCK DIAGRAM
SONiX TECHNOLOGY CO., LTD Page 16 Version 1.9
SN32F100 Series
VDD
VSS
P3.15/SDA1/CT32B1_CAP0
P3.14/SCL1/CT32B0_CAP0
P3.9/CT16B0_PWM0
P3.8/CMO
P3.7/CM23/CT32B1_PWM1
P3.6/CM22/CT32B0_PWM1
P3.5/CM21/CT16B1_PWM0
P3.4/CM20
P3.3/CM19
P3.2/CM18
P3.1/CM17
P3.0/CM16
P2.15/CM15
P2.14/CM14
P2.13/CM13
P2.12/CM12
VSS
VDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P3.10/CT32B0_PWM0 1 ● 60 P2.11/CM11
P3.11/CT32B1_PWM0 2 59 P2.10/CM10
P3.12/URXD1/CT16B0_CAP0 3 58 P2.9/CM9
P3.13/UTXD1/CT16B1_CAP0 4 57 P2.8/CM8
P0.0/URXD0 5 56 P2.7/CM7
P0.1/UTXD0 6 55 P2.6/CM6
P0.2/SCL0 7 54 P2.5/CM5
P0.3/SDA0 8 53 P2.4/CM4
P0.4/SCK0/PGDCLK 9 52 P2.3/CM3
P0.5/SEL0/PGDIN 10 51 P2.2/CM2
P0.6/MISO0/OTPCLK 11 50 P2.1/CM1
P0.7/MOSI0/VR_DOUT 12 49 P2.0/CM0
P0.8/SCK1 13 48 P1.13/XTALOUT
P0.9/SEL1 14 47 P1.12/XTALIN
P0.10/MISO1 15 46 P1.1/AUXTALIN
P0.11/MOSI1 16 45 P1.0/AUXTALOUT
P0.12/SWCLK 17 44 P1.11/LXTALOUT
P0.13/SWDIO 18 43 P1.10/LXTALIN
P0.14/DPDWAKEUP 19 42 VSS
P0.15/RESET 20 41 VDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VMID_ADC
MIC_BIAS
AVDD_ADC
P1.8/MIC_N
P1.7/MIC_P
AVSS_ADC
AVDD_DRV
VOUTP
VOUTN
AVSS_DRV
AVDD_DAC
VMID_DAC
VCOM_DAC
AVSS_DAC
P1.2/I2SMCLK
P1.3/I2SDIN
P1.4/I2SDOUT
P1.5/I2SBCLK
P1.6/I2SWS
P1.9/CLKOUT
SN32F109F
32-Bit Cortex-M0 Micro-Controller
1.4 PIN ASSIGNMENT
SN32F109F (LQFP 80 pins)
SONiX TECHNOLOGY CO., LTD Page 17 Version 1.9
SN32F100 Series
VDD
VSS
P3.15/SDA1/CT32B1_CAP0
P3.14/SCL1/CT32B0_CAP0
P3.9/CT16B0_PWM0
P3.8/CMO
P3.7/CM23/CT32B1_PWM1
P3.6/CM22/CT32B0_PWM1
P3.5/CM21/CT16B1_PWM0
P3.4/CM20
P3.3/CM19
P3.2/CM18
P3.1/CM17
P3.0/CM16
VSS
VDD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
P3.10/CT32B0_PWM0 1 ● 48 P2.8/CM8
P3.11/CT32B1_PWM0 2 47 P2.7/CM7
P3.12/URXD1/CT16B0_CAP0 3 46 P2.6/CM6
P3.13/UTXD1/CT16B1_CAP0 4 45 P2.5/CM5
P0.0/URXD0 5 44 P2.4/CM4
P0.1/UTXD0 6 43 P2.3/CM3
P0.2/SCL0 7 42 P2.2/CM2
P0.3/SDA0 8 41 P2.1/CM1
P0.4/SCK0/PGDCLK 9 40 P2.0/CM0
P0.5/SEL0/PGDIN 10 39 P1.13/XTALOUT
P0.6/MISO0/OTPCLK 11 38 P1.12/XTALIN
P0.7/MOSI0/VR_DOUT 12 37 P1.1/AUXTALIN
P0.12/SWCLK 13 36 P1.0/AUXTALOUT
P0.13/SWDIO 14 35 P1.11/LXTALOUT
P0.14/DPDWAKEUP 15 34 P1.10/LXTALIN
P0.15/RESET 16 33 VSS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VMID_ADC
MIC_BIAS
AVDD_ADC
P1.8/MIC_N
P1.7/MIC_P
AVSS_ADC
AVDD_DRV
VOUTP
VOUTN
AVSS_DRV
AVDD_DAC
VMID_DAC
VCOM_DAC
AVSS_DAC
P1.9/CLKOUT
VDD
SN32F108F
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.
32-Bit Cortex-M0 Micro-Controller
SN32F108F (LQFP 64 pins)
SONiX TECHNOLOGY CO., LTD Page 18 Version 1.9
SN32F100 Series
VDD
VSS
P3.15/SDA1/CT32B1_CAP0
P3.14/SCL1/CT32B0_CAP0
P3.9/CT16B0_PWM0
P3.8/CMO
P3.7/CM23/CT32B1_PWM1
P3.6/CM22/CT32B0_PWM1
P3.5/CM21/CT16B1_PWM0
P3.4/CM20
P3.3/CM19
P3.2/CM18
48 47 46 45 44 43 42 41 40 39 38 37
P0.0/URXD0 1 ● 36 P2.1/CM1
P0.1/UTXD0 2 35 P2.0/CM0
P0.2/SCL0 3 34 P1.13/XTALOUT
P0.3/SDA0 4 33 P1.12/XTALIN
P0.4/SCK0/PGDCLK 5 32 P1.1/AUXTALIN
P0.5/SEL0/PGDIN 6 31 P1.0/AUXTALOUT
P0.6/MISO0/OTPCLK 7 30 P1.11/LXTALOUT
P0.7/MOSI0/VR_DOUT 8 29 P1.10/LXTALIN
P0.12/SWCLK 9 28 VSS
P0.13/SWDIO 10 27 VDD
P0.14/DPDWAKEUP 11 26 AVSS_DAC
P0.15/RESET 12 25 VCOM_DAC
13 14 15 16 17 18 19 20 21 22 23 24
VMID_ADC
MIC_BIAS
AVDD_ADC
P1.8/MIC_N
P1.7/MIC_P
AVSS_ADC
AVDD_DRV
VOUTP
VOUTN
AVSS_DRV
AVDD_DAC
VMID_DAC
SN32F107F
Note: The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.
32-Bit Cortex-M0 Micro-Controller
SN32F107F (LQFP 48 pins)
SONiX TECHNOLOGY CO., LTD Page 19 Version 1.9
SN32F100 Series
PIN NAME
TYP
E
DESCRIPTION
VDD, VSS
P
Power supply input pins for digital circuit.
AVDD_DAC,
AVSS_DAC
P
Power supply input pins for Sigma-delta DAC.
AVDD_ADC,
AVSS_ADC
P
Power supply input pins for Sigma-delta ADC.
AVDD_DRV,
AVSS_DRV
P
Power supply input pins for Sigma-delta DAC Driver.
VCOM_DAC
P
Sigma-delta DAC Common mode output.
VMID_DAC
P
Sigma-delta DAC VMID output.
VMID_ADC
P
Sigma-delta ADC VMID output.
MIC_BIAS
P
Sigma-delta ADC Microphone Bias Voltage output.
P0.0/URXD0
I/O
P0.0 — General purpose digital input/output pin with high-current sink driver.
URXD0 — Receiver input for UART0.
P0.1/UTXD0
I/O
P0.1 — General purpose digital input/output pin with high-current sink driver.
UTXD0 — Transmitter output for UART0.
P0.2/SCL0
I/O
P0.2 — General purpose digital input/output pin with high-current sink driver.
SCL0 — I2C clock input/output.
P0.3/SDA0
I/O
P0.3 — General purpose digital input/output pin with high-current sink driver.
SDA0 — I2C data input/output.
P0.4/SCK0
I/O
P0.4 — General purpose digital input/output pin.
SCK0— Serial clock for SSP0.
P0.5/SEL0
I/O
P0.5 — General purpose digital input/output pin.
SEL0 —Slave Select for SSP0.
P0.6/MISO0
I/O
P0.6 — General purpose digital input/output pin.
MISO0— Master In Slave Out for SSP0.
P0.7/MOSI0
I/O
P0.7 — General purpose digital input/output pin with high-current sink driver.
MOSI0 — Master Out Slave In for SSP0.
P0.8/SCK1
I/O
P0.8 — General purpose digital input/output pin.
SCK1 — Serial clock for SSP1.
32-Bit Cortex-M0 Micro-Controller
1.5 PIN DESCRIPTIONS
SONiX TECHNOLOGY CO., LTD Page 20 Version 1.9
SN32F100 Series
P0.9/SEL1
I/O
P0.9 — General purpose digital input/output pin.
SEL1 — Slave Select for SSP1.
P0.10/MISO1
I/O
P0.10 — General purpose digital input/output pin.
MISO1 — Master In Slave Out for SSP1.
P0.11/MOSI1
I/O
P0.11 — General purpose digital input/output pin.
MOSI1 — Master Out Slave In for SSP1.
P0.12/SWCLK
I/O
P0.12 — General purpose digital input/output pin.
SWCLK — Serial wire clock.
P0.13/SWDIO
I/O
P0.13 — General purpose digital input/output pin.
SWDIO — Serial wire debug input/output.
P0.14/DPDWAKEUP
I
P0.14 — General purpose digital input pin.
DPDWAKEUP — Deep power-down mode wake-up pin.
P0.15/RESET
I/O
P0.15 — General purpose digital input/output pin.
RESET — external Reset input.
P1.0/AUXTALOUT
I/O
P1.0 — General purpose digital input/output pin.
AUXTALOUT — External high-speed X’tal output pin for audio.
P1.1/AUXTALIN
I/O
P1.1 — General purpose digital input/output pin.
AUXTALIN — External high-speed X’tal input pin for audio.
P1.2/I2SMCLK
I/O
P1.2 — General purpose digital input/output pin.
I2SMCLK — MCLK for I2S.
P1.3/I2SDIN
I/O
P1.3 — General purpose digital input/output pin.
I2SDIN — Serial data in for I2S.
P1.4/I2SDOUT
I/O
P1.4 — General purpose digital input/output pin.
I2SDOUT — Serial data out for I2S.
P1.5/I2SBCLK
I/O
P1.5 — General purpose digital input/output pin.
I2SBCLK — BCLK for I2S.
P1.6/I2SWS
I/O
P1.6 — General purpose digital input/output pin.
I2SWS — WS for I2S.
P1.7/MIC_P
I/O
P1.7 — General purpose digital input/output pin.
MIC_P — Sigma-delta ADC MIC difference input (+).
P1.8/MIC_N
I/O
P1.8 — General purpose digital input/output pin.
MIC_N — Sigma-delta ADC MIC difference input (-).
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 21 Version 1.9
SN32F100 Series
VOUTP
O
VOUTP — Sigma-delta DAC output (+).
VOUTN
O
VOUTN — Sigma-delta DAC output (-).
P1.9/CLKOUT
I/O
P1.9 — General purpose digital input/output pin.
CLKOUT — Clockout pin.
P1.10/LXTALIN
I/O
P1.10 — General purpose digital input/output pin.
LXTALIN — External low-speed X’tal input pin.
P1.11/LXTALOUT
I/O
P1.11 — General purpose digital input/output pin.
LXTALOUT — External low-speed X’tal output pin.
P1.12/XTALIN
I/O
P1.12 — General purpose digital input/output pin.
XTALIN — External high-speed X’tal input pin.
P1.13/XTALOUT
I/O
P1.13 — General purpose digital input/output pin.
XTALOUT — External high-speed X’tal output pin.
P2.0/CMP
I/O
P2.0 — General purpose digital input/output pin.
CMP — Comparator channel 0.
P2.1/CM1
I/O
P2.1 — General purpose digital input/output pin.
CM1 — Comparator channel 1.
P2.2/CM2
I/O
P2.2 — General purpose digital input/output pin.
CM2 — Comparator channel 2.
P2.3/CM3
I/O
P2.3 — General purpose digital input/output pin.
CM3 — Comparator channel 3.
P2.4/CM4
I/O
P2.4 — General purpose digital input/output pin.
CM4 — Comparator channel 4.
P2.5/CM5
I/O
P2.5 — General purpose digital input/output pin.
CM5 — Comparator channel 5.
P2.6/CM6
I/O
P2.6 — General purpose digital input/output pin.
CM6 — Comparator channel 6.
P2.7/CM7
I/O
P2.7 — General purpose digital input/output pin.
CM7 — Comparator channel 7.
P2.8/CM8
I/O
P2.8 — General purpose digital input/output pin.
CM8 — Comparator channel 8.
P2.9/CM9
I/O
P2.9 — General purpose digital input/output pin.
CM9 — Comparator channel 9.
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 22 Version 1.9
SN32F100 Series
P2.10/CM10
I/O
P2.10 — General purpose digital input/output pin.
CM10 — Comparator channel 10.
P2.11/CM11
I/O
P2.11 — General purpose digital input/output pin.
CM11 — Comparator channel 11.
P2.12/CM12
I/O
P2.12 — General purpose digital input/output pin.
CM12 — Comparator channel 12.
P2.13/CM13
I/O
P2.13 — General purpose digital input/output pin.
CM13 — Comparator channel 13.
P2.14/CM14
I/O
P2.14 — General purpose digital input/output pin.
CM14 — Comparator channel 14.
P2.15/CM15
I/O
P2.15 — General purpose digital input/output pin.
CM15 — Comparator channel 15.
P3.0/CM16
I/O
P3.0 — General purpose digital input/output pin.
CM16 — Comparator channel 16.
P3.1/CM17
I/O
P3.1 — General purpose digital input/output pin.
CM17 — Comparator channel 17.
P3.2/CM18
I/O
P3.2 — General purpose digital input/output pin.
CM18 — Comparator channel 18.
P3.3/CM19
I/O
P3.3 — General purpose digital input/output pin.
CM19 — Comparator channel 19.
P3.4/CM20
I/O
P3.4 — General purpose digital input/output pin.
CM20 — Comparator channel 20.
P3.5/CM21/
CT16B1_PWM0
I/O
P3.5 — General purpose digital input/output pin.
CM21 — Comparator channel 21.
CT16B1_PWM0 — PWM output 0 for CT16B1.
P3.6/CM22/
CT32B0_PWM1
I/O
P3.6 — General purpose digital input/output pin.
CM22 — Comparator channel 22.
CT32B0_PWM1 — PWM output 1 for CT32B0.
P3.7/CM23/
CT32B1_PWM1
I/O
P3.7 — General purpose digital input/output pin.
CM23 — Comparator channel 23.
CT32B1_PWM1 — PWM output 1 for CT32B1.
P3.8/CMO
I/O
P3.8 — General purpose digital input/output pin.
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 23 Version 1.9
SN32F100 Series
CMO — Comparator output pin.
P3.9/CT16B0_PWM0
I/O
P3.9 — General purpose digital input/output pin.
CT16B0_PWM0 — PWM output 0 for CT16B0.
P3.10/CT32B0_PWM0
I/O
P3.10 — General purpose digital input/output pin.
CT32B0_PWM0 — PWM output 0 for CT32B0.
P3.11/CT32B1_PWM0
I/O
P3.11 — General purpose digital input/output pin.
CT32B1_PWM0 — PWM output 0 for CT32B1.
P3.12/URXD1/
CT16B0_CAP0
I/O
P3.12 — General purpose digital input/output pin with high-current sink driver.
URXD1 — Receiver data input for UART1.
CT16B0_CAP0 — Capture input 0 for CT16B0.
P3.13/UTXD1/
CT16B1_CAP0
I/O
P3.13 — General purpose digital input/output pin with high-current sink driver.
UTXD1 — Transmitter data output for UART1.
CT16B1_CAP0 — Capture input 0 for CT16B1.
P3.14/SCL1/
CT32B0_CAP0
I/O
P3.14 — General purpose digital input/output pin with high-current sink driver.
SCL1— I2C clock input/output.
CT32B0_CAP0 — Capture input 0 for CT32B0.
P3.15/SDA1/
CT32B1_CAP0
I/O
P3.15 — General purpose digital input/output pin with high-current sink driver.
SDA1 — I2C data input/output.
CT32B1_CAP0 — Capture input 0 for CT32B1.
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 24 Version 1.9
SN32F100 Series
RPU
Output
Latch
Pin
GPIOn_CFG
I/O Input Bus
I/O Output Bus
GPIOPn_MODE
RPD
GPIOn_CFGGPIOPn_MODE
RPU
Output
Latch
Pin
GPIOn_CFG
I/O Input Bus
Output Bus
GPIOPn_MODE
RPD
GPIOn_CFG
GPIOPn_MODE
Specific Input Bus
Specific Input Function Control Bit
*. Specific Output
Function Control Bit
*. Some specific functions switch I/O direction directly, not through GPIOn_MODE register.
RPU
Output
Latch
Pin
GPIOn_CFG
I/O Input Bus
Output Bus
GPIOPn_MODE
RPD
GPIOn_CFG
GPIOPn_MODE
Specific Output Bus
Specific Input Function Control Bit
*. Specific Output
Function Control Bit
*. Some specific functions switch I/O direction directly, not through GPIOn_MODE register.
32-Bit Cortex-M0 Micro-Controller
1.6 PIN CIRCUIT DIAGRAMS
Normal Bi-direction I/O Pin.
Bi-direction I/O Pin Shared with Specific Digital Input Function, e.g. SPI, I2C…
Bi-direction I/O Pin Shared with Specific Digital Output Function, e.g. SPI, I2C…
SONiX TECHNOLOGY CO., LTD Page 25 Version 1.9
SN32F100 Series
RPU
Output
Latch
Pin
GPIOn_CFG
I/O Input Bus
I/O Output Bus
GPIOPn_MODE
RPD
GPIOn_CFG
GPIOPn_MODE
*. Specific Output Function Control Bit
*. Some specific functions switch I/O direction directly, not through GPIOn_MODE register.
Analog IP Input Terminal
RPU
Output
Latch
Pin
GPIOn_CFG
I/O Input Bus
I/O Output Bus
GPIOPn_MODE
RPD
GPIOn_CFG
GPIOPn_MODE
*. Specific Output Function Control Bit
*. Some specific functions switch I/O direction directly, not through GPIOn_MODE register.
Analog IP Output Terminal
32-Bit Cortex-M0 Micro-Controller
Bi-direction I/O Pin Shared with Specific Analog Input Function, e.g. XIN, ADC…
Bi-direction I/O Pin Shared with Specific Analog Output Function, e.g. XOUT…
SONiX TECHNOLOGY CO., LTD Page 26 Version 1.9
SN32F100 Series
2
2
2
0x0000 0000
0x0001 0000
64 KB on-chip FLASH
0x1FFF 2000
Reserved
8 KB SRAM
Reserved
0x4000 0000
0x4008 0000
Peripheral
Reserved for Peripheral
0x6000 0000
Reserved for External
0xA000 0000
Reserved for External Device
0xE000 0000
Private Peripheral Bus
0xE010 0000
Reserved
0xFFFF FFFF
0x4000 0000
0x4000 2000
0x4000 4000
0x4000 6000
0x4000 8000
0x4001 0000
0x4001 2000
0x4001 4000
WDT
0x4001 6000
0x4001 8000
0x4001 C000
Reserved
Reserved
Reserved
Reserved
I2C0
0x4004 4000
0x4004 6000
0x4004 8000
GPIO2
GPIO3
GPIO0
GPIO1
Reserved
0x4008 0000
0xE000 0000
0xE010 0000
0xE000 ED00
0xE000 F000
Reserved
NVIC
Debug Control
0xE000 E000
Reserved
SSP0
UART0
SYS0
SSP1
UART1
0x4006 0000
FMC
Reserved
CT16B0
CT16B1
CT32B0
CT32B1
I2S
RTC
PMU
0x4006 4000
0x4006 2000
0x4005 6000
0x4004 C000
0x4004 A000
0x4003 2000
0x4001 E000
Reserved
0x4001 A000
0x4003 4000
0x4005 8000
0x4005 A000
0x1FFF 0000
0x1FFF 1000
0x2000 0000
0x2000 2000
4 KB Boot ROM
Reserved
0x1FFF 2800
SYS1
0x4005 E000
I2C1
0x4005 C000
Sigma-delta DAC
Comparator
Sigma-delta ADC
0x4006 5000
0x4006 6000
0x4006 8000
32-Bit Cortex-M0 Micro-Controller
CENTRAL PROCESSOR UNIT (CPU)
2.1 MEMORY MAP
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SN32F100 Series
SYSTICK_CALIB
SysTick interrupt
SYSTICK_LOAD
SYSTICK_VAL
24-bit down counter
CLKSOURCE
System clock
Ref. clock
(Fix to 1)
1
0
SYSTICK_CTRL
clock
Load data
Private
Peripheral
Bus
ENABLE
COUNTFLAG TICKINT
Note: When the processor is halted for debugging the counter does not decrease.
32-Bit Cortex-M0 Micro-Controller
2.2 SYSTEM TICK TIMER
The SysTick timer is an integral part of the Cortex-M0. The SysTick timer is intended to generate a fixed 10-ms
interrupt for use by an operating system or other system management software.
Since the SysTick timer is a part of the Cortex-M0, it facilitates porting of software by providing a standard timer that is
available on Cortex-M0 based devices.
Refer to the Cortex-M0 User Guide for details.
2.2.1 OPERATION
The SysTick timer is a 24-bit timer that counts down to zero and generates an interrupt.
The intent is to provide a fixed 10-ms time interval between interrupts. The system tick timer is enabled through the
SysTick control register. The system tick timer clock is fixed to the frequency of the system clock.
The block diagram of the SysTick timer:
When SysTick timer is enabled, the timer counts down from the current value (SYST_VAL) to zero, reloads to the value
in the SysTick Reload Value Register (SYST_LOAD) on the next clock edge, then decrements on subsequent clocks.
When the counter transitions to zero, the COUNTFLAG status bit is set to 1. The COUNTFLAG bit clears on reads.
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SN32F100 Series
Bit
Name
Description
Attribute
Reset
31:17
Reserved
R
0
16
COUNTFLAG
This flag is set when the System Tick counter counts down to 0, and is
cleared by reading this register.
R/W
0
15:3
Reserved
R
0
2
CLKSOURCE
Selects the SysTick timer clock source.
0: reference clock.
1: system clock. (Fixed)
R
1
1
TICKINT
System Tick interrupt enable.
0: Disable the System Tick interrupt
1: Enable the System Tick interrupt, the interrupt is generated when the
System Tick counter counts down to 0.
R/W
0
0
ENABLE
System Tick counter enable.
0: Disable
1: Enable
R/W
0
Bit
Name
Description
Attribute
Reset
31:24
Reserved
R
0
23:0
RELOAD
Value to load into the SYST_CVR when the counter is enabled and when
it reaches 0.
R/W
0x5F7F9B
32-Bit Cortex-M0 Micro-Controller
2.2.2 SYSTICK USAGE HINTS AND TIPS
The interrupt controller clock updates the SysTick counter. Some implementations stop this clock signal for low power
mode. If this happens, the SysTick counter stops.
Ensure SW uses word accesses to access the SysTick registers.
The SysTick counter reload and current value are not initialized by HW. This means the correct initialization sequence
for the SysTick counter is:
1. Program the reload value in SYSTICK_LOAD register.
2. Clear the current value by writing any value to SYSTICK_VAL register.
3. Program the Control and Status (SYSTICK_CTRL) register.
2.2.3 SYSTICK REGISTERS
2.2.3.1 System Tick Timer Control and Status register (SYSTICK_CTRL)
Address: 0xE000 E010 (Refer to Cortex-M0 Spec)
2.2.3.2 System Tick Timer Reload value register (SYSTICK_LOAD)
Address: 0xE000 E014 (Refer to Cortex-M0 Spec)
The RELOAD register is set to the value that will be loaded into the SysTick timer whenever it counts down to zero.
This register is set by software as part of timer initialization. The SYST_CALIB register may be read and used as the
value for RELOAD if the CPU or external clock is running at the frequency intended for use with the SYST_CALIB
value.
The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the
system clock set to 50 MHz.
The SysTick clock = system clock = 50 MHz
RELOAD = (system tick clock frequency × 10 ms) −1 = (50 MHz × 10 ms) −1
= 0x0007A11F.
SONiX TECHNOLOGY CO., LTD Page 29 Version 1.9
SN32F100 Series
Bit
Name
Description
Attribute
Reset
31:24
Reserved
R
0
23:0
CURRENT
Reading this register returns the current value of the System Tick counter.
Writing any value clears the System Tick counter and the COUNTFLAG
bit in SYST_CSR.
R/W
0x7E7F35
Bit
Name
Description
Attribute
Reset
31
NOREF
Indicates the reference clock to M0 is provided or not.
1: No reference clock provided.
R
1
30
SKEW
Indicates whether the TENMS value is exact, an inexact TENMS value
can affect the suitability of SysTick as a software real time clock.
0: TENMS value is exact
1: TENMS value is inexact, or not given.
R
0
29:24
Reserved
R
0
23:0
TENMS
Reload value for 10ms timing, subject to system clock skew errors. If the
value reads as zero, the calibration value is not known.
R/W
0xA71FF
32-Bit Cortex-M0 Micro-Controller
2.2.3.3 System Tick Timer Current Value register (SYSTICK_VAL)
Address: 0xE000 E018 (Refer to Cortex-M0 Spec)
2.2.3.4 System Tick Timer Calibration Value register (SYST_CALIB)
Address: 0xE000 E01C (Refer to Cortex-M0 Spec)
SONiX TECHNOLOGY CO., LTD Page 30 Version 1.9
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