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CompactPCI® CPV5370 Single Board

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Computer and CPTM04 Transition

Module

Installation and Reference

Guide

CPV5370A/IH1

May 25, 2001 Edition

© Copyright 2001 Motorola, Inc.

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All Rights Reserved

Printed in the United States of America

Motorola

Intel
Pentium

®

and the Motorola symbol are registered trademarks of Motorola, Inc.

®

and the Intel logo are registered trademarks of Intel Corporation.

®

is a registered trademark of Intel Corporation.

MMX™ and the MMX logo are trademarks of Intel Corporation.
Windows NT

CompactPCI
Phoenix

®

is a registered trademark of Microsoft in the US and other countries

®

is a register ed t rademark of PCI Indu st rial Computer Manufa ctu re rs Group.

®

is a registered trademark of Phoenix Technologies Ltd.

All other products ment io ned i n this document are tradema rks or re gi stered trademarks of
their respective holders.

Notice

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While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. a ssumes n o lia bility r esulti ng from any omissio ns in this docu ment, or from
the use of the information obtained there in. Motorola reserves the righ t to revise this
document and to ma ke c hanges from time to ti me in the content hereof without obligation
of Motorola to notify any person of such revision or changes.

Electronic versions of this material may be read online, downloaded for personal use, or
referenced in another document as a URL to the Motorola Computer Group website. The
text itself may not b e published commerci ally in print o r electronic for m, edited, transla ted,
or otherwise altered withou t the permission of Motorola, Inc.

It is possible that this pu blicati on ma y cont ain r eferenc e to, or i nformat ion a bout Mot oro la
products (machines and pr ograms), progra mming, or services that are not av ailable in your
country. Such references or information must not be construed to mean that Motorola
intends to announce such Motorola products, programming, or services in your country.

Limited and Restricted Rights Legend

If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice applies unless otherwise agreed to in writing by
Motorola, Inc.

Use, duplication, or disclosure by the Government is subject to restrictions as set forth in
subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013v
(Nov. 1995) and of the Rights in Noncommercial Comput er Software and Documentation
clause at DFARS 252.227-7014 (Jun. 1995)

Motorola, Inc.

Computer Group

2900 South Diablo Way

Tempe, Arizona 85282

Safety Summary

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The following general safety precautions must be observed during all phases of operation, service, and repair of this
equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result
in personal injury or damage to the equipment.

The safety precaut ions listed be low represent warnings of ce rtain danger s of which Mot orola is awar e. You, as the
user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of
the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the
equipment is su pplied wi th a three-c onductor A C power ca ble, the po wer cable m ust be plug ged into an a pproved
three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable must meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive stmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other
qualified service personnel may remove equipment covers for internal subassembly or component replacement or any
internal adjust ment. Service pe rsonnel should n ot replace compon ents with power c able connected. Under certain
conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel
should always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling the CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent
CRT implosion, do not handl e the CRT and avoid rough handling o r jarring of t he equipment . Handling o f a CRT
should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that safety features are maintained.

Observe Warnings in Manual.

W arn ings , such as th e exa mple be low, preced e pote ntia lly da nger ous pro cedu res th rough out th is manual . In struc tion s
contained in the warnings m ust be follow ed. You should also employ all ot her safety precautions w hich you dee m
necessary for the operation of the equipment in your operat in g environment.

To prevent serious injury or death from dangerous voltages,
use extreme caution when hand ling, testing, and adj usting this

Warning

equipment and its components.

Flammability

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All Motorola PWBs (printed w iring boards) are manufactured with a flammability rating
of 94V-0 by UL-recognized manufacturers.

EMI Caution

This equipment generates, uses, and can radiate electro-

!

CAUTION

magnetic energy. It may cause or be susceptible to electro­magnetic interference (EMI) if not installed and used with
adequate EMI protection.

CE Notice (European Community)

This is a Class A product. In a domestic environment, this

!

WARNING

Motorola Compute r Group pro ducts wi th the CE mar king co mply with the EMC Dir ective
(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:

product may cause radio interference, in which case the user
may be required to take adequate measures.

EN55022 “Limits and Methods of Measurement of Radio Interference
Characteristics of Information Technology Equipment”; this product
tested to Equipment Class A

EN50082-1:1997 “Electromagnet i c Compati bil it y- -Generic Immunity
Standard, Part 1, Residential, Commercial and Light Industry”.

System products al so fulf ill EN60950 ( product saf ety) which i s essenti ally the r equirement
for the Low Voltage Directive (73/23/EEC).

Board products are tested in a representative system to show compliance with the above
mentioned requirements. A proper installation in a CE-marked system will maintain the
required EMC /safety performance.

In accordance with European Community directives, a “Declaration of Conformity” has
been made and is on file within the European Union. The “Declaration of Conformity” is
available on request. Please contact your sales representative.

Lithium Battery Caution

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Caution

This product contains a lithium battery to power the clock and calendar circuitry.

Danger of explosion if battery is replaced i ncorrectly. Replace

!

CAUTION

!

Attention

!

Vorsicht

battery only with the same or equivalent type recommended
by the equipment manufacturer. Dispose of used batteries

according to the manufacturer’s instructions.

Il y a danger d’ex plosion s’i l y a remplace ment incorr ect de la
batterie. Remplacer uniquement avec une batterie du même
type ou d’un type éq uivalent re commandé par le construct eur .
Mettre au rebut les batteries usagées conformément aux
instructions du fabricant.

Explosionsgefahr bei unsachgemäßem Austausch der
Batterie. Ersatz nur durch denselben oder einen vom
Hersteller empfohlenen Typ. Entsorgung gebrauchter
Batterien nach Angaben des Herstellers.

Table of Contents

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CHAPTER 1 Hardware Preparation and Installation

Introduction ................................................................................................................1-1

Additional Features.............................................................................................1-2

Input/Output Interfaces.......................................................................................1-3

Special Functions................................................................................................1-5

On-Board and Front Panel Components on the CPV5370 Single

Board Computer.............................................................................................1-6

On-Board and Rear Panel Components on the CPTM04

Transition Module........................................................................................1-10

Equipment Required.........................................................................................1-13

Overview of Startup Procedures.......................................................................1-13

Unpacking Instructions.....................................................................................1-14

Before Installing the CPV5370..................................................................1-14

Antistatic Precautions.......................................................................................1-14

Mounting Memory Mezzanine Cards...............................................................1-15

Mounting PCI Mezzanine Cards.......................................................................1-16

Mounting the Slim Line EIDE Hard Drive.......................................................1-17

Hardware Configuration...................................................................................1-17

Connecting to Board Connectors......................................................................1-18

Installing the CPV5370 Sing le Board Computer and CPTM04

Transition Module...............................................................................................1-19

Replacing Lithium Batteries .................................................... ................................1-21

CHAPTER 2 Starting Up the CPV5370 Single Board Computer

Introduction................................................................................................................2-1

Applying Power to the System ..................................................................................2-1

Switches and Indicators .............................................................................................2-2

CHAPTER 3 Functional Description

Introduction................................................................................................................3-1

PhoenixBIOS Description................................ ...................................................3-1

Soft Reset.................................................. ...................................................3-1

Headless Operation......................................................................................3-2

Remote Setup...............................................................................................3-2

vii

Network Boot..............................................................................................3-2

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Peripheral Component Interconnect (PCI) Local Bus Interface................................3-3

CompactPCI Bus Interface........................................................................................3-3

Peripheral Hot Swap Function ...........................................................................3-3

Watchdog Timer........................................................................................................3-3

Memory Address Mapping.............................. ...... ..... ...... ........................................ .3-4

I/O Address Map .......................................................................................................3-5

Field Programmable Gate Array Registers................................................................3-6

FPGA Register Descriptions..............................................................................3-7

Status Register.............................................................................................3-8

Watchdog Timer Register.........................................................................3-10

Interrupt Selection Register.......................................................................3-13

SCI Enable Register..................................................................................3-15

NMI Enable Register.................................................................................3-16

IRQ Enable Register .................................................................................3-17

Alarm Enable Register....................................... ...... ..... ...... ...... ................3-18

Latch Enable Register...............................................................................3-19

Power-On Status Register.........................................................................3-21

LAN A Control Register...........................................................................3-22

LAN B Control Register ...........................................................................3-23

Flash BIOS Control Register ....................................................................3-24

Jump to User Code in Alternate Flash Bank...........................................................3-25

CHAPTER 4 Connector Pin Assignments

Ethernet Connectors...........................................................................................4-1

Serial Port Connectors........................................................................................4-3

Video Connector for the CPV5370 (J17) and CPTM04 (J20) Modules.............4-6

Keyboard/Mouse P/S2 Connector for the CPV5370 and CPTM04 Modules....4-7

Keyboard/Mouse/Power LED Connector for the CPTM04

Transition Module .........................................................................................4-8

USB Connector for the CPTM04 Transition Module ........................................4-8

Parallel Connector on the CPTM04 Transition Module ....................................4-9

EIDE Connector for the CPTM04 Transition Module ....................................4-10

CompactFlash Connector for the CPTM04 Transition Module ......................4-11

Floppy Connector for the CPTM04 Transition Module ..................................4-13

Indicator LED/Miscellaneous Connector on the CPTM04

Transition Module ......................................................................................4-15

IPMI System Management Bus Connector on the CPTM04

Transition Module (J1)................................................................................4-16

viii

CompactFlash Master/Slave Connector on the CPTM04

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Transition Module (J16) ..............................................................................4-16

CPV5370 Single Board Computer, CompactPCI Bus

Connectors (J1 and J2).................................................................................4-17

CPV5370 Single Board Computer, CompactPCI Rear I/O

Connectors (J3, J4, and J5)..........................................................................4-19

CPTM04 Transition Module, Rear I/O Connectors (J3, J4, and J5).................4-26

APPENDIX A Specifications

APPENDIX B Thermal Analysis

Measuring Local Air Temperature.....................................................................B-7

APPENDIX C Related Documentation

Motorola Computer Group Documents....................................................................C-1

URLs.........................................................................................................................C-1

ix

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List of Figures

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Figure 1-1. Block Diagram of the CPV5370 Single Board Computer ......................1-4

Figure 1-2. CPV5370 Single Board Computer Front Panel ......................................1-7

Figure 1-3. Location of CPV5370 Single Board Computer

On-Board Components.........................................................................................1-9

Figure 1-4. On-Board Components and Rear Panel Connectors on the

CPTM04 Transition Module...............................................................................1-12

Figure 1-5. Installing the CPV537 0 Single Board Computer and CPTM04

Transition Module in Your Computer Chassis....................................................1-20

Figure B-1. Location of Thermally Significant Components on the CPV5370

Single Board Computer - Primary Side ..............................................................B-3

Figure B-2. Location of Thermally Significant Components on the CPV5370

Single Board Computer - Secondary Side .......................................................... B-4

Figure B-3. Mounting a Thermocouple Under a Heatsink ......................................B-6

Figure B-4. Measuring Local Air Temperature .......................................................B-7

xi

xii

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List of T ables

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Table 1-1. Input/Output Interfaces on the CPV5370 Single Board Computer

and the CPTM04 Transition Module.....................................................................1-3

Table 1-2. Front Panel Connectors, Board Connectors, and Components on the

CPV5370 Single Board Computer........................................................................1-8

Table 1-3. Rear Panel and On-Board Connectors, and Components on the

CPTM04 Transition Module...............................................................................1-10

T ab le 1-4. Startup Overview......................................... ........................................ ...1-13

Table 3-1. Memory Addresses and Descriptions.......................................................3-4

Table 3-2. I/O Addresses and Descriptions................................................................3-5

Table 3-3. System Management Modes.....................................................................3-7

Table 3-4. Index and data register address and function............................................3-7

Table 3-5. Map of the FPGA register set...................................................................3-8

Table 3-6. Bit descriptions for the STAT register ......................................................3-8

Table 3-7. Bit descriptions for the Watchdog Timer register...................................3-10

Table 3-8. Bit values for selecting watchdog timeout time......................................3-11

Table 3-9. Bit values defining watchdog timeout and disabling ..............................3-11

Table 3-10. SOFT_RST bit 5 settings......................................................................3-12

Table 3-11. Bit descriptions for the INTUM register...............................................3-13

Table 3-12. Bit values for determining driven IRQ lines.........................................3-14

Table 3-13. Bit descriptions for the SCIEN register................................................3-15

Table 3-14. Bit descriptions for the NMIEN register...............................................3-16

Table 3-15. Bit descriptions for the IRQEN register ...............................................3-17

Table 3-16. Bit descriptions for the ALEN register.................................................3-18

Table 3-17. Bit descriptions for the LEN register....................................................3-19

Table 3-18. Bit descriptions for the Power-On Status register.................................3-21

T ab le 3-19. Bit descriptions for the LAN A register............................ ....................3-22

T ab le 3-20. Bit descriptions for the LAN B register................................................3-23

Table 3-21. Bit descriptions for the Flash BIOS Control register............................3-24

Table 3-22. Bit selections for the Flash BIOS Device Bank Control ......................3-24

Table 4-1. Ethernet Connector Pin Assignments for the CPV5370 Single

Board Computer and CPTM04 Transition Module...............................................4-1

Table 4-2. Serial Port Connector Pin Assignments for the CPV5370

Single Board Computer (J19)...............................................................................4-3

xiii

Table 4-3. Serial Port Connect or Pin Assignments for the CPTM04

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Transition Module (COM2) (J28) ........................................................................4-4

Table 4-4. Serial Port Connect or Pin Assignments for the CPTM04

Transition Module (COM1)..................................................................................4-5

T a b le 4-5. Video Connector Pin Assignm ent s for th e CPV5370 (J17) and

CPTM04 (J20) Modules.......................................................................................4-6

Table 4-6. Keyboard/Mouse P/S2 Connector Pin Assignments for the CPV5370

(J7) and CPTM04 (J24) Modules .........................................................................4-7

Table 4-7. Keyboard/Mouse/Power LED Connector Pin Assignments for the

CPTM04 Transition Module.................................................................................4-8

Table 4-8. USB Connector Pin Assignments for the CPTM04

Transition Module ................................................................................................4-8

Table 4-9. Parallel Connector Pin Assignments on the CPTM04

Transition Module ................................................................................................4-9

Table 4-10. EIDE Connector Pin Assignments for the CPTM04

Transition Module ..............................................................................................4-10

Table 4-11. CompactFlash Connector Pin Assignments for the CPTM04

Transition Module ..............................................................................................4-11

Table 4-12. Floppy Connector Pin Assignments for the CPTM04

Transition Module ..............................................................................................4-13

Table 4-13. Indicator LED/Miscellaneous Connector Pin Assignments on the

CPTM04 Transition Module (J2)........................................................................4-15

Table 4-14. IPMI System Management Bus Connector Pin Assignments on the

CPTM04 Transition Module (J1)........................................................................4-16

Table 4-15. CompactFlash Master/Slave Connector on the CPTM04

Transition Module (J16) 1 ..................................................................................4-16

Table 4-16. CPV5370 Backplane Connector Pin Assignments (J1) .......................4-17

Table 4-17. CPV5370 Backplane Connector Pin Assignments (J2) .......................4-18

Table 4-18. CPV5370 Single Board Computer, Rear I/O Connector Pin

Assignments (J3)................................................................................................4-19

Table 4-19. Signal Descriptions for the CPV 5370 Single Board Computer

Backplane Connector (J3) ..................................................................................4-20

Table 4-20. CPV5370 Rear I/O Pin Assignments (J4)............................................ 4-21

Table 4-21. CPV5370 Rear I/O Pin Assignments (J5)............................................ 4-22

Table 4-22. Signal Descriptions for the CPV 5370 Single Board Computer

Backplane Connector (J5) ..................................................................................4-23

Table 4-23. CPTM04 Transition Module, Rear I/O Connector Pin

Assignments (J3)................................................................................................4-26

xiv

Table 4-24. Signal Description s for the CPTM04 Transition Module,

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Backplane Connector (J3)...................................................................................4-27

Table 4-25. CPTM04 Transition Module, Rear I/O Connector Pin

Assignments (J5).................................................................................................4-28

Table A-1. Power Requirements for the CPV5370 Single Board Computer and

Transition Module ...............................................................................................A-1

Table A-2. Physical Characteristics of the CPV5370 Single Board Computer ....... A-1

Table A-3. Lithium Battery Specifications ..............................................................A-2

Table A-4. Environmental Specifications 1 .............................................................A-2

Table B-1. Thermally Significant Compon ents on the CPV5370 Single

Board Computer ..................................................................................................B-2

Table C-1. Motorola Computer Group Documents .................................................C-1

xv

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About This Manual

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This CompactPCI® CPV5370 Single Board Computer (SBC) and
CPTM04 Transition Module (TM) Installation and Reference Guide
describes the installa tion, components, and configurations of the CPV5370
SBC and TM. Use this guide for general and technical information about
the CPV5370 CompactPCI System CPU. These tables give you
descriptions of CPV5370 SBC, CPTM04 TM and CPMEZZ Memory
Mezzanine M odels.

CPV5370 Single Board Computer Models

CompactPCI
Single Board

Computer Model

Numbers

CPV5370-700-01 CompactPCI SBC with 700MHz processor, 256MB

SDRAM, one PMC site, CompactFlash

CPV5370-700-02 CompactPCI SBC with 700MHz processor, 256MB

SDRAM, one PMC site, hard drive

CPV5370-700-03 CompactPCI SBC with 700MHz processor, 512MB

SDRAM, one PMC site, CompactFlash

CPV5370-700-04 CompactPCI SBC with 700MHz processor, 512MB

SDRAM, one PMC site, hard drive

CPV5370-700-05 CompactPCI SBC with 700MHz processor, 1G

SDRAM, one PMC site, CompactFlash

CPV5370-700-06 CompactPCI SBC with 700MHz processor, 1G

SDRAM, one PMC site, hard drive

Description

™ connector

™ connector

™ connector

xvii

CPTM04 Transition Module Model

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The CPV5370 uses an optional transition module for peripheral and
network connections required at the rear of the chassis.

CPTM04

T ransition Module

Model Number

CPTM04 Transition Module with front panel

keyboard/mouse, dual Ethernet, video, COM2, and
optional PIM module knockout

1

Refer to Additional Features on page 1-2 and Input/Output

Interfaces

on page 1-3 for more information about CPTM04 features.

CPMEZZ Memory Module Models

CPMEZZ

Memory Module

Model Number

CPMEZZ-256B 256MB Memory Mezzanine, bottom installation
CPMEZZ-256B-F 256MB Memory Mezzanine, bottom installation by

factory
CPMEZZ-256T 256MB Memory Mezzanine, top installation
CPMEZZ-256T-F 256MB Memory Mezzanine, top installation by

factory

Description

Description

1

xviii

Overview of Contents

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This section cont ains a short descrip tion of the content of ea ch chapter a nd

appendix in this manual.

This Chapter or Appendix: Gives you:

Chapter 1, Hardware Preparation

and Installation

Chapter 2,

Starting Up the
CPV5370 Single Board
Computer

Chapter 3,

Functional
Descripti on

Chapter 4, Connector Pin

Assignments

Appendix A, Specifications board specifications.
Appendix B, Thermal Analysis the information necessary to conduct thermal

Appendix C, Related

Documentation

a product description, input/output interfaces and
special functions and a block diagram.

information about ESD, board installation and
power up, replacement of lithium batteries, locations
of connectors and indicators.

a functional description including information about
the PCI Bus, the watchdog timer, memory address
mapping, the I/O address map and the FPGA
registers.

pin assignments for the SBC and transition module.

evaluations of your board in specific system
configurations.

information about related Motorola Computer
Group documents, other related documents and
URLs for access to more information.

xix

Who Should Use This Guide

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The information in this guide is written for system installers, original

equipment manufacturers (OEM) and technicians. The procedures assume
familiarity with the safety practices and regulatory compliance required for
using and modifying electronic equipment. Personnel who install
CompactPCI systems shoul d be trained and experienced with th e installation
of computers and computer equipment.

Comments and Suggestions

We welcome and appreciate your comments on our documentation. We
want to know what you think about our manuals and how we can make
them better. Mail comments to:

Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282

You can also submit comments to the following e-mail address:

[e-mail]

In all your correspondenc e, pleas e list your name, pos itio n, and company.
Be sure to include the title and par t number of the manual and tell how you
used it. Then tell us your feelings about its strengths and weaknesses and
any recommendations for improvements.

xx

1Hardware Preparation and

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This chapter gives you information about:

❏ features and functions of the CPV5370 Single Board Computer

❏ basic preparation and installation
❏ ESD precautions
❏ replacing lithium batteries

Note This document treats the CPV5370 SBC as a component of a

Introduction

Installation

(SBC) and CPTM04 Transition Module (TM)

system, and assumes that you install it in a CompactPCI

backplane that is PCI I ndustrial Computer Manu facturer’s Group
(PICMG) compliant.

1

The CPV5370 Single Board Computer (SBC) is a hot swap, single-slot,
CompactPCI

computer. It is powe re d by a Pentium
It can serve either as a standard CompactPCI peripheral CPU or as a
system controller.

The Pentium
board Frame AGP graphics contr oller, dual on- board Ethernet con trollers,
and standard PC I/O plus a PMC site for expansion.

An optional CPTM04 Transition Module (TM) gives you backplane I/O
for PCI Mezzanine Card (PMC) sites and on-board devices.

The CPV5370 meets the needs of embedded application developers.
Typical applications include broadband data or intelligent network
switching, CTI server, industrial control and automation, military and
aerospace, and medical, scientific, or imaging products.

®

(Compact Peripheral Communica tion Inter face) complia nt

®

III processor gives you, two USB ports, PCI EIDE, on-

®

III processor and 440GX chip set.

1-1

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Hardware Preparation and Installation

Additional Features

The CPV5370 gives you these features:

❏ Pentium III processor Low Power module for high end embedded

applications

❏ Up to 1GB on-board DRAM memory (256MB or 512MB on

baseboard, up to two 256MB mezzanine boards)

❏ Accelerated 2D graphics with 4MB video memory
❏ Dual Fast Ethernet controllers for monitoring and telecom

applications

❏ Hot Swap comp atibility allowing insertion or removal of the

CPV5370 and other per ipheral CPU slot boards while the chassis is
powered up

❏ An array of on-board I/O available from the front panel of the

CPV5370 and/or the rear panel via t he CPTM0 4 Trans ition Module

The CPTM04 Transition Module gives you these features:

❏ rear panel connections for:

– PS/2 keyboard/mouse
–video
– COM2 (serial port 2)
– Ethernet 1 and 2
–PIM 1

❏ on-board connectors for:

– PS/2 keyboard/mouse
–floppy
– USB0 and USB1
– secondary IDE
– COM1 (serial port 1)
– parallel port

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Input/Output Interfaces

Refer to Table 1-1 for brief descriptions of the input/output interfaces on
the CPV5370 Single Board Computer and CPTM04 Transition Module.
Do not use the rear panel connectors and internal connectors at the same
time.

Note When the identical fun ct ion is available through the CPV5370’s

front panel and the r ear t ransiti on mod ule, yo u can us e eit her th e
front or the rear, not both.

T able 1- 1. Input/Out put Interfa ces on the CP V5370 Single Boar d Computer and

the CPTM04 Transition Module

Function CPV5370 CPTM04 Transition Module

Front Panel On-board Rear Panel On-board

Ethernet 1 RJ-45 - RJ-45 ­Ethernet 2 RJ-45 - RJ-45 ­COM1 (Serial Port 1) 9-pin D-sub - - 10-pin shrouded
COM2 (Serial Port 2) - - 9-pin D-sub ­PMC Panel PMC 1 Device - PMC 1 Device ­PMC Panel - - - ­Keyboard/Mouse 6-pin mini-DIN - 6-pin mini-DIN 12-pin connector
Floppy - - - 34-pin connector
Parallel - - - 26-pin shrouded
USB 0 and USB 1 - - - 2-stacked 4-pin
Video 15-pin D-sub - 15-pin D-sub ­Primary IDE
Secondary IDE - - - 40-pin connector
CompactFlash

1

Primary IDE available on CPV5370-700-02, -04, and -06

2

CompactFlash available on CPV5370-700-01, -03, and -05

1

2

- 40-pin connector - -

- 50-pin connector - 50-pin connector

1

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Hardware Preparation and Installation

Refer to Figure 1-1 for a block diagram of the CPV5370 Single

Clock

Generator

Debug

Connector

VideoPMC 1 I/O

Processor

Board Computer.

PMC

100MHz Processor

PCI Bridge

and

Memory

Controller

(North
Bridge)

Intel

440GX

Soldered-on memory: to 512MBx8

Memory mezzanine: to 512MBx8

Bus

AGP Video

(Optional)

AGP

KBD

Front Panel

EthernetEthernet

COM 1

Mouse

Ethernet 1

Ethernet 2

Ethernet 1

Intel 82559

Ethernet 2

Intel 82559

Ultra I/O

COM 1

COM 2

33MHz 64-bit PCI

ISA Bridge

Intel PIIX4E

FPGA

Flash

BIOS

System
Monitor

On-Card

Hard Drive

(Optional)

KBD

Mouse

Printer

Floppy

IDE Flash

USB 1

USB 0

(Optional)

User I/O J5 & J3

Local Bus

(South Bridge)

ISA

Primary IDE

Secondary IDE

PMC I/O

PCI to PCI

BRIDGE

Intel 21154

Video

CPCI J1/J2

HA

Bus

J4

33MHz 64-bit CPCI Bus

2942 0501

Figure 1-1. Block Diagram of the CPV5370 Single Board Computer

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The CPV5370 uses these funct ions designed for cert ain applications. Refer
to Chapter 3, Functional Description for programmer’s reference

information.

❏ Watchdog Timer

The watchdog timer can operate in four modes:
– Disabled
– Sets the timeout fl ag in the Watchdog Strobe /St at us port in ISA

– Sets the timeout fl ag in the Watchdog Strobe /St at us port in ISA

– Sets the timeout fl ag in the Watchdog Strobe /St at us port in ISA

You can program the watchdog timer via registers in the ISA I/O
memory map. The watchdog timer is protected from being
accidentally enabled. The timer supports a range of count down
time-outs up to eight minutes.

Introduction

1

I/O memory map

I/O memory map + Assert a selectable interrupt (ISA IRQ)

I/O memory map + Assert NMI followed by a system Reset or
Soft Reset

❏ Advanced System Monitoring

The CPV5370 monitors the following system events:
– On-card temperature
– BGA2 thermal fault
– On-card voltages +5V, +3.3V, +12V, and the processor core

voltages
– System Management Bus (SMBUS) alert signal
– Chassis power supply loss of regulation

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Hardware Preparation and Installation

On-Board and Front Panel Components on the CPV5370 Single Board Computer

The CPV5370’s front panel has connectors and switches for:

❏ Ethernet 1 and 2 (RJ-45 connectors with indicator lights)
❏ COM1 asynchronous serial port (9-pin connector)
❏ one PMC panel (keyed for 5.0V PCI)
❏ video port (15-pin high density D-sub connector)
❏ keyboard/mouse (circular mini-DIN connector)
❏ board reset (push button switch)

LED indicator lights on the front panel display of the CPV5370 include:

❏ left LED - Pow er (green)/Ala rm (red)
❏ right LED - Hard Disk Drive (green)

1-6 Computer Group Literature Center Web Site

Refer to Figure 1-2 for the location of the CPV5370 front panel

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components.

ETHERNET

ETHERNET

COM 1

PMC site

Introduction

1

Figure 1-2. CPV5370 Single Board Computer Front Panel

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Video
Connector

Keyboard/Mouse
Connector

Reset
LED for Power (green)/Alarm (red)

LED for Hard Disk Drive (green)

2931 0401

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Hardware Preparation and Installation

The CPV5370 carries components on both sides. Table 1-2 lists the
connectors availa ble to s upport devi ces. Ref er to Fi gure 1-3 . Also refer to
Chapter 4, Connector Pin Assignments.

Table 1-2. Front Panel Connectors, Board Connectors, and

Components on the CPV5370 Single Board Computer

Connector Description

J1 CompactPCI Bus Connector
J2 CompactPCI Bus Connector
J3 Rear I/O CompactPCI Connector
J4 Rear I/O CompactPCI Connector
J5 Rear I/O CompactPCI Connector
J7 Keyboard/mouse

J9 Ethernet 2 connector
J10 Ethernet 1 connector
J11 PMC bus signal connector
J12 PMC I/O connector
J13 PMC bus signal connector
J14 PCI64 bit PCI extension on PMC2 connector
J16 Memory Mezzanine
J17 Video connector
J18 Primary IDE connector
J19 COM1 (asynchronous serial port)
J21 Debug port
J23 Primary IDE CompactFlash

Refer to Figure 1-3 for the location of CPV5370 Single Board Computer
on-board components. There are no on-board configuration jumpers.

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Mezzanine
Modules

Introduction

1

Slim Line

Drive

J19

J9

J10

J8

J15

J20

J23

J17

J7

J18

J11

J13

J6

J21

J22

J16

J1

J12

J14

J2

J3

J4

J5

2926 0301

Figure 1-3. Location of CPV5370 Single Board Computer On-Board

Components

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Hardware Preparation and Installation

On-Board and Rear Panel Components on the CPTM04 Transition Module

The CPTM04 Transition Module (Figure 1-4) has connectors on the rear
panel for:

❏ keyboard/mouse (PS/2)
❏ Ethernet 1 and Ethernet 2 (RJ45)
❏ COM2 (serial port) (9-pin D-sub)
❏ video (15 pin high density D-sub)

Table 1-3 lists the connect ors available to supp ort devices on the CPTM04

Transition Module.

Table 1-3. Rear Panel and On-Boar d Connectors, and Components on

the CPTM04 Transit ion Module

Connector Description

J1 IPMI System Management Bus Connector

J3 Rear I/O CompactPCI Connector

J4 Rear I/O CompactPCI Connector

J5 Rear I/O CompactPCI Connector
J10 PIM (64-pin PMC I/O connector - power)
J14 PIM (64-pin PMC I/O connector - signals)
J15 USB (8-pin connector)
J16 CompactFlash (master/slave jumper)
J17 Power On LED, EIDE Activity LED, Push

button reset (12-pin header)
J18 Ethernet 2 connector
J19 Ethernet 1 connector
J20 Video (15-pin high d ensity D-sub)
J21 Floppy connector (34-pin connector)
J22 COM2 (serial port 2 - 9-pin D-sub)
J23 COM1 (serial port 1 - 10-pin shrouded)

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Table 1-3. Rear Panel and On-Boar d Connectors, and Components on

the CPTM04 Transition Module (Continued)

Connector Description

J24 Keyboard/Mouse connector (external, 6-pin

PS/2 female)
J25 Parallel connector (26-pin shrouded)
J26 Secondary EIDE (40-pin shrouded)
J27 CompactFlash (50-pin)

1

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Hardware Preparation and Installation

Refer to Figure 1-4 for on-board components a nd rear pane l connectors o n
the CPTM04 Transition Module.

J16

J5 J4 J3

J27

J21

J25

J26

J23 J15

J17

J20J22J24

J19J18

Keyboard/
Mouse

COM 2

VIDEO

ETHERNET 2

ETHERNET 1

PIM 1

J14J10

J1

Figure 1-4. On-Board Components and Rear Panel Connectors on the

CPTM04 Transition Module

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A CPV5370 system requires this equipment:

❏ CompactPCI system enclosure
❏ system console terminal
❏ operating system
❏ disk drives
❏ Transition Module (CPTM04) and connecting cables.

Overview of Startup Procedures

Table 1-4 shows the things you need to do before you can use this board.

It also tells you where to find the information you need to perform each
step.

Table 1-4. Startup Overview

Introduction

1

For information about: Go to:

Unpacking the hardware
Mounting memory mezzanine

cards
Mounting PCI Mezzanine Cards

(PMC)
Hard drive mounting

Hardware Configuration
Installing the CPV537 0 SBC and

CP TM04 TM

Powering-up the system

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Unpacking Instructions on page 1-14
Mounting Memory Mezzanine Cards on

page 1-15

Mounting PCI Mezzanine Cards on page

1-16

Mounting the Slim Line EIDE Hard

on page 1-17

Drive
Hardware Configuration on page 1-17
Installing the CPV5370 Sin gle Board

Computer and CPTM04 Transition
Module

on page 1-19

Applying Power to the System on page 2-1

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Hardware Preparation and Installation

Unpacking Instructions

Note If the shipping carton is damaged upon receipt, request that the

carrier’s agent be present duri ng the unpacking and inspect ion of
the equipment.

Unpack the equipment from the shipping carton. Refer to the packing list
and verify that al l items are present . Sa ve t h e pac king material for s tor ing
and reshipping of equipment.

Avoid touching areas of integrated circui tr y. Static discharge can damage
circuits.

Caution

Before Installing the CPV5370

After removing the CPV5370 from its packaging:

❏ Check for obvious physical damage.
❏ Verify that th e coin cell battery is in its holder and inserted

correctly.

Make sure that you disconnect the chassis from the main power supply
before you continue.

Antistatic Precautions

Use ESD

Wrist Strap

1-14 Computer Group Literature Center Web Site

Motorola strongly recommends tha t you use an anti static wris t strap and a
conductive foam pad when installing or upgrading a system. Electronic
components, such as d isk dr ives, c omputer boards , and memor y modules ,
can be extremely sensitive to electrostatic discharge (ESD). After
removing the component from its protective wrapper or from the system,
place the componen t flat on a grounded, static -free surface (an d, in the case
of a board, component side up). Do not slide the component over any
surface.

If an ESD station is not available, you can avoid damage resulting from

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ESD by wearing an antistatic wrist strap (available at electronics stores)
that is attached to an active electrical ground. Note that a system chassis
may not be grounded if it is unplugged.

Dangerous voltages, capable of causing death, are present in this
equipment. Use extreme caution when handling, testing, and adjusting.

Warning

Avoid touching areas of integrated circui tr y. Static discharge can damage
these circuits.

Caution

Mounting Memory Mezzanine Cards

You can mount one or two 256MB Memory Mezzanine Modules on the
CPV5370 Single Board Co mputer. Refer to Antistatic Precaut ions on page

1-14 before beginning installation. Refer to Figure 1-3.

Introduction

1

1. Attach three stando ffs t o the CP V5370 bo ard and s ecure wi th th ree
nuts on the secondary side of the board.

2. Place one Memory Mez zanine M odule o n top of the t hree st andoffs
and press onto the J16 connector on the CPV5370.

3. Secure with three screws.
If mounting a second Me mory Mezz anine Module use a second se t

of three standoffs instead of three screws.

4. Place the second Memory Mezzanine Module on top of the three
standoffs and press onto the connector on the first Memory
Mezzanine Module.

5. Secure with three screws.

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Hardware Preparation and Installation

Mounting PCI Mezzanine Cards

You can mount one 32 bit, 5.0V PCI Mezzanin e Card (PMC) on the PMC

site. The PMC expansi on runs at 3 3MHz. I t’s I /O signal s are rout ed to the
rear transition module. Refer to Anti static Precau tions on page 1-14 before
beginning installation. The PMC site is keyed for 5.0V PCI bus interface.

Note You cannot install PMCs that are only compatible wit h 3.3V PCI.
The PMC module I/O connects to J3.

1. Attach an ESD strap to your wri st. Att ach the o ther en d of the ESD
strap to the chassis as a ground. Keep the ESD secured throughout
this procedure.

2. Shut down the operating system.

Dangerous voltages, capable of causing death, are present in this
equipment. Use extreme caution when handling, testing, and adjusting.

Warning

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Mounting the Slim Line EIDE Hard Drive

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You can mount a Slim Line EIDE hard drive on the CPV5370. Refer to

Figure 1-3. No configurat ion is require d. The drive is conf igured as master

with no jumpers installed.

Slim Line Hard Drive (rear view)

1. Connect the Slim Line EIDE drive cable to the CPV5370, J18
connector.

2. Position the drive on the CPV5370.

Introduction

1

2846 1100

3. Connect the drive cable to the drive.

4. Secure the drive to the CPV5370 using three screws.

Hardware Configuration

To produce the necessary hardware configuration and to make sure the
CPV5370 operates properly , you may need to mak e cert ain modif icat ions
by setting bits in control registers after installing the module in a system.

We describe the CPV5370 control registers in Chapter 3, Functional

Description.

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Hardware Preparation and Installation

Connecting to Board Connectors

The CPV5370 Single Board Computer (SBC) and CPTM04 Transition
Module (TM) give you board connectors for attaching peri pheral devic es.
Before installing t he SBC or TM, you may want to connect you r peripheral
cables to the connectors. Refer to Chapter 4, Connector Pin Assignments.

Notes When the identical function is available through the SBC (front

panel) and TM (rear panel), you can use either the front or the
rear, not both.

Always remove power from the system before connecting peripherals to

!

Warning

!

Caution

the SBC or TM. To reduce the ri sk of personal injury, disc onnect the power
cord from the power source. Only qualified, experienced electronics
personnel should access the interior of a chassis.

The components of the SBC and TM are sensitive to static discharge.
While out of the unit, place the modules on a static-dissipative surface or
into a static-shielding bag.

Current revisions of the CPV5370 do not support PMC (PCI Mezzanine

!

Caution

1-18 Computer Group Literature Center Web Site

Card) Interface Modules (PIMs) requiring +12.0V. Plugging a PIM that
requires +12.0V into the CPTM04 with a CPV5370 could damage the
PIM. Please see your PIM documentation for the voltage requirements of
your module.

Installing the CPV5370 Single Board Computer and CPTM04 Transition Module

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Installing the CPV5370 Single Bo ard Computer
and CPTM04 Transition Module

Refer to Figure 1-5. To install the CPV5370 into your computer chassis:

1. Follow the instructions in your chassis user manual to remove any
outer cover.

2. Locate the desired peripheral slot.

3. Remove any filler panel (or existing board) that might fill that slot.

4. Install the top and botto m edge of the CPV5370 in the gui des of th e
chassis.

1

Step 2Step 1 Step 3 Step 4

5. Make sure that the lever s of the two inje ctor/ejectors are in the
outward position.

6. Slide the CPV5370 into the chassis until resistance is felt.

7. Simultaneously move the injector/ejector levers in an inward
direction.

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Hardware Preparation and Installation

8. Verify that the CPV5370 is properly seated and secure it to the
chassis using the two screws located adjacent to the injector/ejector
levers.

9. Connect the appropriate cables to the CPV5370

10. Repeat steps 3 through 9 for installing the transition module.

Transition Module

Single Board Computer

Figure 1-5. Installing the CPV5370 Single Board Computer and CPTM04

Transition Module in Your Computer Chassis

1-20 Computer Group Literature Center Web Site

2165 9803

Replacing Lithium Batteries

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Follow these safety rules for proper battery operation and to reduce
equipment and personal injury hazards when handling lithium batteries.
Use the battery for its intended application only.

Note Do not recharge, open, puncture or crush, incinerate, expose to

high temperatures or dispose of in your general trash collection.

To replace the lithium batter y, observe the following guideli nes and follow
the steps below.

Note When replacing the battery, you must apply power to the board

to prevent data loss.

To prevent serious injury or death from dangerous voltages, use extreme
caution when handling, testing, and adjusting this equipment and its
components.

Replacing Lithium Batteries

1

Lithium batteries incorporate flammable materials such as lithium and

!

Warning

organic solvents. If lithium batteries are short-circuited or exposed to high
temperature or pressure , they may burst open and ignite, possibly resulting
in injury and/or fire. When dealing with lithium batteries, carefully follow
the precautions listed below to prevent accidents.

❏ Do not short-circuit.
❏ Do not disassemble, deform or apply excessive pressure.
❏ Do not heat or incinerate.
❏ Do not apply solder directly.
❏ Do not use different models, or new and old batteries together.
❏ Do not charge.
❏ Always check proper polarity.

To replace the on-board backup battery, follow the steps below.

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Hardware Preparation and Installation

Danger of explosion if battery is replaced incorrectly.

!

Caution

Caution

Replace only with the same or equivalent type recommended by the
equipment manufacturer. Dispose of used batteries according to the

manufacturer’s instructions.

Avoid touching areas of integrated circuitry; static discharge can damage
circuits.

Use ESD

Wrist Strap

Attach an ESD strap to your wrist. Attach the other end of the ESD strap
to an electrical gr ound. (Note tha t the system chass is may not be gr ounded
if it is unplugged.) Secure the ESD strap to your wrist and to ground
throughout the procedure.

1. To remove the battery from the module, carefully pull the battery
from the socket.

2. Before installing a new battery, make sure that the battery pins are
clean.

3. Note the battery polarity and press the new battery into the socket.

Note No soldering is required when the battery is in the socket.

4. Recycle or dispose of the old batte ry accord ing to loca l regu lati ons
and manufacturer’s instructions.

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2Starting Up the CPV5370 Single

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Board Computer

Introduction

This chapter gives you information about:

❏ the power-up procedure
❏ switches and indicators

Note This document treats the CPV5370 SBC as a component of a

system, and assumes that you install it in a CompactPCI
backplane that is PICMG compliant.

Applying Power to the System

Before applying power to the system you need to verify that:

❏ you completed all necessary hardware preparation

2

❏ you made all connections correctly
❏ the voltage se tting for the chass is power supply matc hes the voltage

present in the coun tr y of use (if the power suppl y in your system is
not auto-sensing).

When you apply power, the CPV5370 displays the PhoenixBIOS banner
and then runs a memory test.

2-1

Starting Up the CPV5370 Single Board Computer

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2

Switches and Indicators

You can access a push button reset switch through the CPV5370 Single
Board Computer (SBC) front panel. This switch is not programmable.

There are two LED indicators on the CPV5370 SBC front panel:

❏ left - Power (g reen)/Alarm (red)
❏ right - Hard Disk Drive (green) indicates hard drive activity on the

primary IDE channel.

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Introduction

This chapter gives you information about:

❏ the PhoenixBIOS
❏ the Peripheral Component Interconnect (PCI) Bus
❏ the watchdog timer
❏ memory address mapping
❏ the I/O address map
❏ Field Programmable Gate Array (FPGA) registers

The CPV5370 BIOS is similar to the CPV5350 BIOS. Refer to “Related

Documentation”, Table C-1 for information about how to access the

CPV5350 CompactPCI BIOS and Programmer’s Reference Guide
(Motorola part number CPV5350A/PGx). Refer to Jump to User Code in

Alternate Flash Bank at the end of this chapter fo r more informa tion about

the CPV5370 BIOS.

3

PhoenixBIOS Description

The CPV5370 uses the PhoenixBIOS to provide initial hardware
configuration for local devices and local operating system boot.

Soft Reset

You can generate a “soft reset” from your keyboard and the watchdog
timer. The BIOS preserves as much of the system memory state as
possible.

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A CPV5370 circuit monitors system power and provides the PWROK
signal to the PIIX4E. Th e PIIX4E distributes the reset to the rest of the
board by generating the CPU, PCI, and IDE resets. You can also r ese t the
board using the front panel reset switch and the FPGA watchdog timer.
You can program the Watchdog Timer to generate a soft reset. Refer to

Field Programmable Gate Array Registers on page 3-6 for programming

3

information.

Headless Operation

The BIOS can operate with no keyboa rd or display. You do, however, need
a keyboard and displa y to ch ange se tup opt ion s unles s you use the remot e
setup feature.

Remote Setup

You can change setup options remotely through the BIOS Setup ­Advanced Menu using a COM port. The defa ult settings for a terminal are :

❏ 19200 baud (bps)
❏ 1 stop bit
❏ no parity
❏ no flow control

Network Boot

We include the Intel PXE (Pre-boot E xecution Envi ronment) 82559 BI OS
extension module to provide operating system boot via one of the 82559
ports. This module is built into the BIOS. You can enable the PXE for
either port through the BIOS Setup-Advanced-PCI Configuration Menu.

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Peripheral Component Interconnect (PCI)
Local Bus Interface

The PCI local bus is a high-performance, 32-bit bus with multiplexed
address and data lines. Use it as an interconnect mechanism between
highly-integrated peripheral controller components, peripheral add-in
boards and processor/memory systems.

The CPV5370 supports a 32-bit l ocal PCI bus inte rface. On-boar d devices
connect directly to the local PCI bus.

CompactPCI Bus Interface

The CPV5370 supports a single 64-bi t CompactPCI bus interface. You can
insert the phy sical connec t or into a 64-bit High Availability CompactPCI
backplane and make connection to off card CompactPCI peripherals
through the PCI-PCI bridge.

3

Peripheral Hot Swap Function

The CPV5370 complies with the CompactPCI Hot Swap Specification in
peripheral mode. You must, however, use a compliant backplane with
proper pin staging.

W atchdo g Timer

The Field Programmable Gate Array (FPGA) includes a watchdog timer.
The watchdog timer has four modes of operation:

1. disabled

2. sets the timeout flag in the W atchd og Strob e/Stat us por t in ISA I /O
memory map

3. item 2 + assert a selectable interrupt (ISA IRQ)

4. item 2 + assert NMI followed by a sy stem reset or soft reset

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You can program the watchdog timer via registers in the ISA I/O memory
map. The watchdog ti mer is protected f rom being accidental ly enabled and
can support a range of count down time-outs up to eight minutes.

Memory Address Mapping

3

Refer to Table 3-1 for memory address information.

Table 3-1. Memory Addresses and Descriptions

Address Size Description

0xFFF80000 - 0xFFFFFFFF 512KB High BIOS Area
0xFEE01000 - 0xFFF7FFFF 17.5MB Available for PCI
0xFEE00000 - 0xFEE00FFF 4KB Local APIC Configuration Space
0xFEC10000 - 0xFEDFFFF 1.94MB Available for PCI
0xFEC00000 - 0xFEC0FFFF 64KB I/O APIC Configuration Space
0x00100000 - 0xFEDFFFFF 3.98GB Available for PCI when not used

for system memory
0x000F0000 - 0x000FFFFF 64K System BIOS Area
0x000E0000 - 0x000EFFFF 64KB Extended BIOS Area
0x000C0000 - 0x000DFFFF 128KB Expansion ROM Area
0x000A0000 - 0x000BFFFF 128K B Video Buffer Area
0x00000000 - 0x0009FFFF 640KB DOS Applications/Compatibility

Region

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Table 3-2 shows I/O addressing. You can use BIOS Setup or special

utilities to enable or relocate these features from their default values.

Table 3-2. I/O Addresses and Descriptions

I/O Address Map

Address (hex) Size Description

0000 - 000F 16 bytes PIIX4E DMA, channels 0 - 3
0020 - 0021 2 bytes PIIX4E Interrupt Controller 1
0040 - 0043 4 bytes PIIX4E - Timer 1
005B 2 bytes FPGA Watchdog Strobe/Status Register
005D 2 bytes FPGA Index Register
005F 2 bytes FPGA Data Register
0060 1 byte Keyboard Controller
0061 1 byte PIIX4E - NMI, Speaker Control
0064 1 byte Keyboard Controller
0070 - 7 1 bit PIIX4E NMI Enable
0070-6:0 7 bits PIIX4E RTC
0071 1 byte PIIX4E RTC
0072-0073 2 bytes PIIX4E RTC (extended registers)
0080 - 008F 16 bytes PIIX4E DMA Page Register
0092 1 byte PIIX4E Port 92 Register
00A0 - 00A1 2 bytes PIIX4E Interrupt Controller 2
00B2 - 00B3 2 bytes APM reserved
00C0 - 00DE 31 bytes PIIX4E DMA, channels 4 - 7
00EA 1 byte Ultra I/O General Purpose I/O Index Regist er
00EB 1 byte Ultra I/O General Purpose I/O Data Register
00F0 1 byte Reset Numeric Error
0170 - 0177 8 bytes Secondary IDE Channel
01F0 - 01F7 8 bytes Primary IDE Channel
02F8 - 02FF 8 bytes COM2
0376 1 byte Secondary IDE Channel Command Port

3

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Table 3-2. I/O Addresses and Descriptions (Continued)

Address (hex) Size Description

0377 1 byte Secondary IDE Channel Status Port
0378 - 037F 8 bytes LPT1
03F0 - 03F5 6 bytes Floppy

3

03F6 1 byte Primary IDE Channel Command Port
03F7-7 1 bit Floppy Disk Change Channel 1
03F7-6:0 7 bits Primary IDE Channel Status Port
03F7 (write) 1 byte Floppy Channel 1 Command
03F8 - 03FF 8 bytes COM 1
04D0 - 04D1 2 bytes Interrupt Controller Edge/Level Register
0CF8 - 0CFB 4 bytes PCI CONFADD (DWORD Access Only)
0CFC - 0CFF 4 bytes PCI CONFDATA
0CF9 1 byte PIIX4E Reset Control Register
FF00 - FF07 8 bytes IDE Bus Master Register
FFA0 - FFA7 8 bytes Primary Bus Master IDE Registers
FFA8 - FFAF 8 bytes Secondary Bus Master IDE Registers
FF80 - FF9F 32 bytes USB

Field Programmable Gate Array Registers

The Field Programmable Gate Array (FPGA) is used for add-on features
and control, and connect s to the i nte rnal I SA bus. It cons ists of a gro up of
I/O registers for control of features such as a Watchdog Timer, I/O
switching control, and system management functions.

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When a system management event occurs, the input causing the event
latches and remains latched until cleared by the system software. The
system management hardware notifies the system of the event depending
on the mode selected by the user. Refer to Table 3-3.

Table 3-3. System Management Modes

In: an:

IRQ Mode ISA interrupt generates - You can set the

interrupt by writing to the IRQ select
register.

SCI Mode SCI generates - The FPGA’s SCI output

connects to the PIIX4 Therm input GPI8.
NMI Mode NMI generates
ALARM Mode ALARM generates

FPGA Register Descriptions

This section describes how to access the various FPGA register sets. The
bit description tables below show bits 0 through 7 on the top line and bit
functions on the second line.

You can access the FPGA re gisters by a n index regi ster at offset 0 5h from
the base address of the FPGA (0 x5Dh). The data register is loc ated at offset
07h (0x5Fh). Refer to Table 3-4 . To acce ss an FPGA r egister , write to th e
index register first and the n read/write fr om the data register. The BIOS
sets the default FPGA Base address to 58h.

Table 3-4. Index and data register address and function

3

Port Offset address Function

Index 05h Register Index Port - selects the device register
Data 07h Data Port - read/write data to selected register
W atchdog

Strobe/Status

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03h Watchdog Strobe and Status register

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Refer to Table 3-5 for a map of the FPGA register set.

Table 3-5. Map of the FPGA register set

DEVICE 00h

SYSTEM

3

00 Status

03 Watchdog

04 INT Sel

05 SCI Mask

06 NMI Mask

07 IRQ Mask

08 Alm Mask

09 FLT Latch
0B Power On
0F DEV SEL

DEVICE 10h

LAN A Ctrl

01 LAN A 01 LAN B 01 FLASH

0F DEV SEL 0F DEV SEL 0F DEV SEL

DEVICE 11h

LAN B Ctrl

DEVICE 14h

FLASH Ctrl

Status Register

The Status Register (STAT) is a read only register. Reads of the unused
bits produce indeterminate values. Writes have no effect. The Temp
Alarm, SMB Alert, Alarm B, and Alarm A ar e all latched when active. You
must initiate a writ e to the LEN regi ster to clea r th e latc hed sign als . Refer
to Table 3-6.

Table 3-6. Bit descriptions for the STAT register

7 (most
significant
bit)

ALARM FAL- DEG- ENUM- LM81

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654 3 2 1 0 (least

ALARM A
(NMI)

LM81
ALARM B
(SMI)

SMB
ALERT

significant
bit)

CPU
TEMP
ALARM

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CPU TEMP ALARM (Bit 0)

This signal connects to the CPU thermal monitor chip alert (MAX1617)
output. The input is lat ched when a ctive and clea red vi a the LEN re giste r.
A read of this bit returns the latched status of the input.

SMB ALERT (Bit 1)

This bit reflects the level of the SMBus Alert signal.

LM81 ALARM A (Bit 3) and LM81 ALARM B (Bit 2)

The LM81 output functions feed these signals. The input is latched when
active and cleared via the LEN register. A read of these bits returns the
latched status of the input.

ENUM (Bit 4)

ENUM comes from the CPCI bus and signals the insertion of a new device.
The input is latched when active (low) and cl eared via th e LEN register. A
read of this bit returns the latched status of the input.

3

DEG (Bit 5)

DEG comes from the CPCI bus and signals a power supply deregulation
condition. A read of this bit returns the current state of the input.

FAL (Bit 6)

This signal comes from the CPCI bus and signals a power failure
condition. A read of this bit returns the current state of the input.

ALARM (Bit 7)

This signal comes from Device 0 Index Register 08h Alarm Enable.

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Watchdog Timer Re gister

Refer to Table 3-7 for Watchdog Timer Register (WDCFG) bit
descriptions.

Table 3-7. Bit descriptions for the Watchdog Timer register

3

7 (most
significant bit)

CLR_STATUS ALARM_EN SOFT

6 543210 (least

RST

significant
bit)

WD1 WD0 SEL2 SEL1 SEL0

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SEL0 (Bit 0), SEL1 (Bit 1) and SEL2 (Bit 2)

Use SEL0, SEL1 and SEL2 to select the watchdog timeout time. Writing
to these bits does not cl ear or rese t the watchdo g timer. Ref er to Table 3-8.

Table 3-8. Bit values for selecting watchdog timeout time

Period SEL2 SEL1 SEL0

.46 seconds 0 0 0
.93 seconds 0 0 1

3.73seconds 0 1 0

14.91seconds 0 1 1

29.82 seconds 1 0 0

1.98 minutes 1 0 1

3.97 minutes 1 1 0

7.95 minutes 1 1 1

WD0 (Bit 3) and WD1 (Bit 4)

Use these bits to define the eve nt that occurs on a watchdog timeo ut and to
disable the watchdog timer. Reading these bits returns the last value
written. Refer to Table 3-9.

Table 3-9. Bit values defining watchdog timeout and disabling

WD1 WD0 Description

3

0 0 DISABLED - Resets watchdog
0 1 POLLED
1 0 FPGA IRQX
1 1 NMI followed by reset or soft reset (7.2 8ms delay

before SBC Reset)

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SOFTRST (Bit 5)

Use this bit to cha nge the Watchdog Reset funct ion to Soft reset. Refer to

Table 3-10. This bit clears on power-up reset.

Table 3-10. SOFT_RST bit 5 settings

3

Set bit to: For:

0 (default) hard reset
1soft reset

ALARM_EN (Bit 6)

This bit controls whether an FPGA alarm generates on a watchdog timeo ut
event.

❏ Write a logic 1 to cause an alarm signal to become active on a

watchdog timeout event.

❏ Write a logic 0 to cause the alarm signal not to become active on a

watchdog timeout event.

❏ Read this bit to return the last written value.

CLR_STATUS (Bit 7)

Use this bit to reset the watchdog timer output latch.

❏ Write a logic 1 to hold the watchdog timer output latch in a reset

state.

❏ Write a logic 0 to permit a watchdog timer event to be latched.

Reading thi s bit returns the last written val ue.

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Use the Interrupt Selection Register (INTUM) to select the desired IRQ
line. Refer to Table 3-11. This IRQ can then be generated by a watchdog
Timeout or ENUM-.

Field Programmable Gate Array Registers

Table 3-11. Bit descriptions for the INTUM register

7 (most
significant
bit)

RES RES RES RES IRQSL3 IRQSL2 IRQSL1 IRQSL0

6543210 (least

significant
bit)

3

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IRQSL0 (Bit 0), IRQSL1 (Bit 1), IRQSL2 (Bit 2) and IRQSL3 (Bit 3)

These bits determine which IRQ is driven when an IRQ event triggers.
Refer to Table 3-12.

Table 3-12. Bit values for determining driven IRQ lines

3

Interrupt Line IRQSEL3 IRQSEL2 IRQSEL1 IRQSEL0

No IRQ Selected0000
No IRQ Selected0001
No IRQ Selected0010
No IRQ Selected0011
No IRQ Selected0100
Select IRQ50101
No IRQ Selected0110
Select IRQ70111
No IRQ Selected1000
Select IRQ91001
Select IRQ101010
Select IRQ111011
No IRQ Selected1100
No IRQ Selected1101
No IRQ Selected1110
No IRQ Selected1111

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The SCI Ena ble Register (SCIEN) defin es the type of events that can
generate an SCI. Refer to Table 3-13.

Table 3-13. Bit descriptions for the SCIEN register

Field Programmable Gate Array Registers

7 (most
significant
bit)

654 3 2 1 0 (least

significant
bit)

ENABLE RES RES ENUM- ALARM_A- ALARM_B- TEMP- SMB-

SMB (Bit 0)

❏ Set to a logic 1 to allow generation of an SCI when SMB Alert is

active. SMB ALERT is active when logic 0.

❏ Write a logic 0 to this bit to disable an SCI for this event.

TEMP (Bit 1)

❏ Set to a logic 1 to a llow ge nerat ion of an SCI when TE MP is act ive.
❏ Write a logic 0 to this bit to disable an SCI for this event.

ALARM_A (Bit 3) and ALARM_B (Bit 2)

❏ Set to a logic 1 to allow the generation of an SCI when the

ALARM_A or ALARM_B go active.

❏ Write a logic 0 to these bits to disable an SCI for this event.

ENUM (Bit 4)

3

❏ Set to a logic 1 to allow generation of an SCI when the ENUM event

occurs.

❏ Write a logic 0 to this bit to disable an SCI for this event.

ENABLE (Bit 7)

❏ Set to a logic 1 to allow generation of an SCI by one of the events

above.

❏ Write a logic 0 to prevent the events from generating an SCI.

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NMI Enable Register

The NMI Enab le Register (NMIEN) defines the events that c an generate
an NMI. Refer to Table 3-14.

Table 3-14. Bit descriptions for the NMIEN register

3

7 (most
significant
bit)

654 3 2 1 0 (least

significant
bit)

ENABLE RES RES ENUM ALARM_A ALARM_B TEMP SMB

SMB_ALERT (Bit 0)

❏ Set to a logic 1 to allow the generation of an NMI when the SMB

Alert is active.

❏ Write a logic 0 to this bit to disable an NMI fo r this event.

TEMP (Bit 1)

❏ Set to a logic 1 to allow the generation of an NMI when TEMP is

active.

❏ Write a logic 0 to this bit to disable an NMI fo r this event.

ALARM_A (Bit 3) and ALARM_B (Bit 2)

❏ Set to a logic 1 to allow the generation of an NMI when the

ALARM_A or ALARM_B go active.

❏ Write a logic 0 to this bit to disable an NMI fo r this event.

ENUM (Bit 4)

❏ Set to a logic 1 to allow the generation of an NMI when the ENUM

event occurs.

❏ Write a logic 0 to this bit to disable an NMI fo r this event.

ENABLE (Bit 7)

❏ Set to a logic 1 to allow the listed events to generate an NMI.
❏ Write a logic 0 to prevent the events from generating an NMI.

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The IRQ Enable Register (I RQEN) defines the event s that can gen erate an
IRQ. The IRQ generated is set by I RQ Select Register (IRQNUM). Refer
to Table 3-15.

Field Programmable Gate Array Registers

Table 3-15. Bit descriptions for the IRQEN register

7 (most
significant
bit)

ENABLE RES RES ENUM ALARM_A ALARM_B TEMP SMB

654 3 2 1 0 (least

significant
bit)

SMB (Bit 0)

❏ Set to a logic 1 to allow the generation of an IRQ when the SMB

Alert is active.

❏ Write a logic 0 to this bit to disable an IRQ fo r this event.

TEMP (Bit 1)

❏ Set to a logic 1 to allow the generation of an IRQ when TEMP is

active.

❏ Write a logic 0 to this bit to disable an IRQ fo r this event.

ALARM_A (Bit 3) and ALARM_B (Bit 2)

❏ Set to a logic 1 to allow the generation of an IRQ when the

ALARM_A or ALARM_B go active.

❏ Write a logic 0 to this bit to disable an IRQ fo r this event.

3

ENUM (Bit 4)

❏ Set to a logic 1 to allow the generation of an IRQ when the ENUM

event occurs.

❏ Write a logic 0 to this bit to disable an IRQ fo r this event.

ENABLE (Bit 7)

❏ Set to a logic 1 to allow the listed events to generate an IRQ.
❏ Write a logic 0 to prevent the events from generating an IRQ.

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Alarm Enable Register

The Alarm E nable Register (ALEN) def ines the even ts that genera te an
alarm output. Refer to Table 3-16.

Table 3-16. Bit descriptions for the ALEN register

3

7 (most
significant
bit)

654 3 2 1 0 (least

significant
bit)

ENABLE RES RES ENUM ALARM_A ALARM_B TEMP SMB

SMB (Bit 0)

❏ Set to a logic 1 to all ow t he generation of an Alarm wh en t he SMB

Alert is active.

❏ Write a logic 0 to this bit to disable an Alarm for this event

TEMP (Bit 1)

❏ Set to a logic 1 to all ow t he generation of an Alarm wh en TEMP i s

active.

❏ Write a logic 0 to this bit to disable an Alarm for this event.

ALARM_A (Bit 3) and ALARM_B (Bit 2)

❏ Set to a logic 1 to allow the generation of an Alarm when the

ALARM_A or ALARM_B go active.

❏ Write a logic 0 to this bit to disable an Alarm for this event.

ENUM (Bit 4)

❏ Set to a logic 1 to al low the generation of an Alarm when the ENUM

event occurs.

❏ Write a logic 0 to this bit to disable an Alarm for this event.

ENABLE (Bit 7)

❏ Set to a logic 1 to allow the listed events to generate an Alarm.
❏ Write a logic 0 to prevent the events from generating an Alarm.

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The Latch Enable Register ( LEN) resets latches in the Fie ld Programmable
Gate Array (FPGA) for the FAN, TEMP, ALARM_B, ALARM_B and
ENUM alarms. Refer to Table 3-17. This register is write only. Write a
logic 1 to cl ear the latc h for that b it position. Writing a logi c 0 has no effect
on the latch.

Table 3-17. Bit descriptions for the LEN register

Field Programmable Gate Array Registers

3

7 (most
significant
bit)

RES RES RES ENUM ALARM_A ALARM_B TEMP SMB_

6543 2 10

ALERT

SMB_ALERT (Bit 0) - SMB Alert Signal
This bit is set automatically when a SMB_ALERT event is signaled by an

SM bus device.

❏ Write a logic 1 to clear the SMB_ALERT input latch
❏ Writing a logic 0 has no effect

TEMP (Bit 1) - CPU Temperature Signal
This bit is s et automati cally whe n a TEMP even t is signa led by an o ff-card

thermostat device.

❏ Write a logic 1 to clear the TEMP input latch
❏ Writing a logic 0 has no effect

ALARM_B (Bit 2) - LM81 Alarm B Signal
This bit is set automati cal ly when an ALARM_B event is signaled by the

on-card LM81.

❏ Write a logic 1 to clear any latched ALARM_B events
❏ Writing a logic 0 has no effect

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ALARM_A (Bit 3) - LM81 Alarm A Signal
This bit is set aut omat ica ll y whe n an ALARM_A event is signal ed by th e

on-card LM81

❏ Write a logic 1 to clear any latched ALARM_A events

3

❏ Writing a logic 0 has no effect

ENUM (Bit 4) - Bus Enumeration Signal
This bit is s et automatically when an EN UM event oc curs.

❏ Write a logic 1 to clear any ENUM latched ev ents
❏ Writing a logic 0 has no effect

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The Power-On Status Regist er (POS) checks f or power-on condit ion. You
can also read back written bits. Refe r to Table 3-18.

Table 3-18. Bit descriptions for hte Power-On Status register

Field Programmable Gate Array Registers

7 (most
significant
bit)

PBSOFT RES RES RES FLAG1 FLAG0 PWRON1

6543 2 1 0

PWRON0 (Bit 0) and PWRON1 (Bit 1)

The BIOS uses this bit to determine if it is booting from a power-up
condition. It clears at power-on only. The BIOS may set it (write a 1) to
flag subsequent resets.

FLAG0 (Bit 2) and FLAG1 (Bit 3)

Applications use thes e bits to flag boot state s to the BIOS on the next reset.
These bits clear at power-on and are not affected by reset. Software may
set these bits by writing 1s to them.

PBSOFT (Bit 7)

Use this bit to program the function of the reset pushbutton switch. By
default the front pa nel pushbutton swit ch causes a hard res et. Set this bit to
a 1 to cause a so ft re set. Cl ea r the bit t o 0 to pr ogram th e sw itch to caus e a
hard reset. The default state is 0.

3

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LAN A Control Register

Use the LAN A Control Register (LNACTRL) to control t he on-card LAN
A controller. Bits written can also read back. Refer to Table 3-19.

Table 3-19. Bit descriptions for the LAN A register

3

7 (most
significant
bit)

ENABLE FRONT RES RES RES RES RES RES

6543210 (least

significant
bit)

FRONT (Bit 6)

The BIOS uses this bit to route LAN A signals to either the front or the re ar
connectors.

❏ Write a logic 0 to this bit to route LAN A signals to the front

connector.

❏ Write a logic 1 to this bit to route LAN A signals to the rear

connector.

The BIOS sets this bit according to CMOS setup.

ENABLE (Bit 7)

The BIOS uses this bit to enable LAN A.

❏ Write a logic 1 to this bit t o disable LAN A.
❏ Write a logic 0 to enable LAN A so that the operating system and

applicaiton code can use it.

The BIOS sets this bit according to CMOS setup.

3-22 Computer Group Literature Center Web Site

LAN B Control Register

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Use the LAN B Control Regist er (LNBCTRL) to control the on -card LAN
B controller. Bits written can also read back. Refer to Table 3-20.

Table 3-20. Bit descriptions for the LAN B register

Field Programmable Gate Array Registers

7 (most
significant
bit)

ENABLE FRONT RES RES RES RES RES RES

6543210 (least

significant
bit)

LAN B ENABLE (Bit 7)

The BIOS uses this bit to enable LAN B.

❏ Write a logic 1 to this bit t o disable LAN B.
❏ Write a logic 0 to this bit to enable LAN B so the operating system

and application code can us it.

The BIOS sets this bit according to CMOS setup.

FRONT (Bit 6)

The BIOS uses this bit to route the LAN B signals to either the front or the
rear connetors.

❏ Write a logic 1 to this bit to route LAN B signals to the rear

connector.

3

❏ Write a logic 0 to this bit t o route LAN B signals to the front

connector.

The BIOS sets this bit according to CMOS setup.

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Flash BIOS Control Register

Use the Flash BIOS Control Register (FLBCTRL) to control which bank
on the BIOS flash memory part is to be acces sed. Bits written can also read
back. Refer to Table 3-21.

Table 3-21. Bit descriptions for the Flash BIOS Control register

3

7 (most
significant
bit)

RES RES RES RES RES BC2 BC1 BC0

6543 2 10

BC0 (Bit 0), BC1 (Bit 1) and BC2 (Bit 2)

Use the Bank Control bits to control the Flash BIOS device. Reset selects
Bank 0 as the default. Refer to Table 3-22 for Bank Control bit settings.

Table 3-22. Bit selections for the Flash BIOS Device Bank Control

512K

BANK

Bank 0* 000000h FFF80000h 0 0 0

Bank 1 080000h FFF80000h 0 0 1
Bank 2
Bank 3 180000h FFF80000h 0 1 1
Bank 4 200000h FFF80000h 1 0 0
Bank 5
Bank 6 300000h FFF80000h 1 1 0
Bank 7

*Default Reset state

Flash

Offset

100000h FFF80000h 0 1 0

280000h FFF80000h 1 0 1

380000h FFF80000h 1 1 1

Window BC2 BC1 BC0

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Jump to User Code in Alternate Flash Bank

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Jump to User Code in Alternate Flash Bank

The flash device for the BIOS is a 4MB part consisting of eight 512K
banks. The BIOS occupies bank 0 only.

From the boot screen in t he BI OS setup, you can select an al ter nate 512K
flash bank to l oad and e xecute instea d of boot ing from standard devic es in
the boot menu. If you select one of the alternate banks (banks 1 - 7), the

BIOS looks for the five character signature “_MOT_” in the l ast five bytes
of the selected 512K bank. If found, the BIOS disables interrupts, timers,
and the watchdog. Then it reads the top 64K of the selected bank into
segment 0F000h and jumps to 0F000:FFF 0h. If the signatur e is not foun d,
the BIOS proceeds normally and attempts to boot from standard floppy
and hard drive devices.

Note When the bank switch and jump occurs, it happens very late in

POST after all hardware is initialized.

3

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3

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4Connector Pin Assignments

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This chapter gives you connector pin assignments for CPV5370 Single
Board Computer (SBC) and CPTM04 Transition Module (TM)
connectors.

Current revisions of the CPV5370 do not support PMC (PCI Mezzanine

!

Caution

Ethernet Connectors

Card) Interface Modules (PIMs) requiring +12.0V. Plugging a PIM that
requires +12.0V into the CPTM04 with a CPV5370 could damage the
PIM. Please see your PIM documentation for the voltage requirements of
your module.

Refer to Table 4-1 for Ethernet connector pin assignments for the:

❏ CPV5370 Single Board Computer

– Ethernet A (J10)
– Ethernet B (J9)

4

❏ CPTM04 Transition Module

– Ethernet 2 (J18)
– Ethernet 1 (J19)

T able 4-1. Ethernet Connector Pin Assignments for the CPV5370 Single

Board Computer and CPTM04 Transition Module

Pin

Number

1 TX+ Dif ferential transmit lines
2 TX- Differential transmit lines
3 RX+ Differential receive lines
4- -

Signal

Mnemonic

Signal Description

4-1

Connector Pin Assignments

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T able 4-1. Ethernet Connector Pin Assignments for the CPV537 0 Single

Board Computer and CPTM04 Transition Module (Continued)

Pin

Number

5- ­6 RX- Differential receive lines
7- -

4

8- -

Signal

Mnemonic

Signal Description

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Serial Port Connectors

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Refer to Table 4-2 for serial port connector pin assignments for the:

❏ CPV5370 Single Board Computer

– COM 1 (Serial Port 1) (J 19)

Refer to Table 4-3 and Table 4-4 for pin assignments for the:

❏ CPTM04 Transition Module

– COM 2 (Serial Port 2) (J 28)
– COM 1 (Serial Port 1) (J 21)

Table 4-2. Serial Port Connector Pin Assignments for the CPV5370

Single Board Computer (J19)

4

Pin

Number

1 DCD- Data set has detected the data carrier
2 RX Receives serial data input from

3 TX Sends serial output to

4 DTR- Indicates that a data set is ready to

5 GND Ground
6 DSR- Indicates that a data set is ready to

7 RTS- Indicates to data set that UART is

8 CTS- Indicates that data set is ready to

9 RI- Indicates that a modem has received

Single

Mnemonic

Signal Description

communications link

communications link

establish a communications like

establish a communications like

ready to exchange data

exchange data

a telephone ringing signal

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Table 4-3. Serial Port Connector Pin Assignments for the CPTM04

Tran sition Module (COM2) (J28)

Pin

Number

1 DCD Data set has detected the data carrier
2 RX Receives serial data input from

4

3 TX Sends serial output to

4 DTR Indicates that a data set is ready to

5 GND Ground
6 DSR Indicates that a data set is ready to

7 RTS Indicates to data set that UART is

8 CTS Indicates that a data set is ready to

9 RI Indicates that a modem has received

Single

Mnemonic

Signal Description

communication link

communication link

establish a communication link

establish a communication link

ready to exchange data

exchange data

a telephone ringing signal

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Table 4-4. Serial Port Connector Pin Assignments for the CPTM04

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Transition Module (COM1)

Pin

Number

1 DCD Data set has detected

3 RX Receives serial data

5 TX Sends serial data to

7 DTR D ata set is ready to

8 GND Ground 10 GND Ground

Signal

Mnemonic

Signal Description Pin

Number

the data carrier

input from
communication link

communication link

establish a
communication link

Signal

Mnemonic

2 DSR Data set is ready to

4 RTS UART is ready to

6 CTS Data set is ready to

8RI Modem has

Signal

Description

establish a
communications
link

exchange data

exchange data

received a
telephone ringing
signal

4

http://www.motorola.com/computer/literature 4-5

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Video Connector for the CPV5370 (J17) and CPTM04 (J20) Modules

Table 4-5. Video Connector Pin Assignments for the CPV5370 (J17) and

CPTM04 (J20) Modules

Pin

Number

1 RED Red signal

4

2 GREEN Green signal
3 BLUE Blue signal
4 NC no connection
5 DACVSS Video return
6 DACVSS Video return
7 DACVSS Video return
8 DACVSS Video return

9 NC no connection
10 DACVSS Video return
11 NC no connection
12 DDCDAT Display Data Channel data signal for DDC2 support
13 HSYNC Horizontal synchronization
14 VSYNC Vertical synchronization
15 DDCCLK Display Data Channel clock signal for DDC2 support

Signal

Mnemonic

Signal Description

4-6 Computer Group Literature Center Web Site

Keyboard/Mouse P/S2 Connector for the CPV5370 and

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CPTM04 Modules

Table 4-6. Keyboard/Mouse P/S2 Connector Pin Assignments for the

CPV5370 (J7) and CPTM04 (J24) Modules

Pin

Number

1 KBDDAT Data line for keyboard
2MDAT

3 GND Keyboard Ground
4 KBDVCC Keyboard Power
5 KBDCLK Clock for keyboard
6MCLK

7 CGND Common Ground

1

AUXDAT is Data line for mouse for the CPTM 04

2

AUXCLK is Clock for mouse for the CPTM04

Signal

Mnemonic

(AUXDAT)

(AUXCLK)

Signal Description

Data line for mouse

1

Clock for mouse

2

4

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Keyboard/Mouse/Power LED Connector for the CPTM04 Transition Module

T able 4- 7. Keyboard/Mouse/ Power LED Connector Pin Assignments for the

CPTM04 Transition Module

Pin

Number

1 PWRLED Power LED

4

3 GND Ground 4 KBDDAT Data line for

5 GND Ground 6 AUXDAT Data line for

7 - - 8 GND Ground
9 GND Ground 10 KBDVCC Keyboard power

11 - - 12 AUXCLK Clock for mouse

Signal

Mnemonic

Signal

Description

Indicator

Pin

Number

2KBDCLKClock for

Signal

Mnemonic

keyboard

keyboard

mouse

Signal

Description

USB Connector for the CPTM04 Transition Module

Table 4-8. USB Connector Pin Assignments for the CPTM04 Transition

Module

Pin

Number

1 +5V +5V dc power

3DATA1- USB serial

5DATA1+ USB serial

7 GND USB port common 8 GND USB port common

Signal

Mnemonic

Signal

Description

(current limited to

1.0A)

communication
differential pair

communication
differential pair

Pin

Number

2 +5V +5V dc power

4DATA0- USB serial

6DATA0+ USB serial

Signal

Mnemonic

Description

(current limited to

1.0A)

communication
differential pair

communication
differential pair

Signal

4-8 Computer Group Literature Center Web Site

Parallel Connector on the CPTM04 Transition Module

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Table 4-9. Parallel Connector Pin Assignments on the CPTM04 Transition

Module

Pin

Number

1 STROBE- Indicates data at

3 D0 Parallel data lines 4 ERR- Set low when an

5 D1 Parallel data lines 6 INIT- Initializes the

7 D2 Parallel data lines 8 SLIN- Selects the printer

9 D3 Parallel data lines 10 GND Ground
11 D4 Parallel data lines 12 GND Ground
13 D5 Parallel data lines 14 GND Ground
15 D6 Parallel data lines 16 GND Ground
17 D7 Parallel data lines 18 GND Ground
19 ACK- Input is pulsed by

21 BUSY Printer cannot

23 PE Printer is out of

25 SELECT Set high when

Signal

Mnemonic

Signal

Description

parallel port is
valid

the peripheral to
acknowledge data
retrieval

accept any more
data

paper

selected

Pin

Number

2 AFD- Causes printer to

20 GND Ground

22 GND Ground

24 GND Ground

26 - -

Signal

Mnemonic

Signal

Description

add a line feed

error is detected

printer

4

http://www.motorola.com/computer/literature 4-9

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EIDE Connector for the CPTM04 Transition Module

Table 4-10. EIDE Connector Pin Assignments for the CPTM04 Transition Module

Pin

Number

1 RESET- Reset signal to drive 2 GND Ground
3 DD7 Drive data line 4 DD8 Drive data line
5 DD6 Drive data line 6 DD9 Drive data line

4

7 DD5 Drive data line 8 DD10 Drive data line
9 DD4 Drive data line 10 DD11 Drive data line

11 DD3 Drive data line 12 DD12 Drive data line
13 DD2 D rive data line 14 DD13 Drive data line
15 DD1 D rive data line 16 DD14 Drive data line
17 DD0 D rive data line 18 DD15 Drive data line
19 GND Drive data line 20 - ­21 DMARQ Drive DMA request 22 GND Ground
23 IOW- Drive I/O write 24 GND Ground
25 IOR- Drive I/O read 26 GND Ground
27 IORDY Drive is ready for I/O

29 DMACK- Drive DMA acknowledge 30 GND Ground
31 INTRQ Drive interrupt request 32 IOCS16- Indicates a 16 bit

33 DA1 Drive register and data

35 DA0 Drive register and data

37 CS1- Chip select drive 0, also

39 DASP- Drive active/slave present 40 GND Ground

Signal

Mnemonic

Signal Description Pin

cycle(s)

port address line

port address line

command register block
select

Signal

Number

28 CSEL- Cable select

34 PDIAG- Output from drive 1

36 DA2 Drive register and data

38 CS3- Chip select drive 1,

Mnemonic

Signal Description

register is decoded

and monitored by
drive 0

port address line

also command register
block select

4-10 Computer Group Literature Center Web Site

CompactFlash Connector for the CPTM04 Transition Module

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Table 4-11. CompactFlash Connector Pin Assignments for the CPTM04

Transition Module

Pin

Number

1 GND Ground 26 - ­2 DD3 Drive data line 27 DD11 Drive data line
3 DD4 Drive data line 28 DD12 Drive data line
4 DD5 Drive data line 29 DD13 Drive data line
5 DD6 Drive data line 30 DD14 Drive data line
6 DD7 Drive data line 31 DD15 Drive data line
7 CS1- Chip select drive 0,

8 GND Ground 33 - -

9 GND Ground 34 IOR- Drive I/O read
10 GND Ground 35 IOW- Drive I/O write
11 GND Ground 36 VCC +5 Volts
12 GND Ground 37 INTRQ Drive interrupt request
13 VCC +5 Volts 38 VCC +5 Volts
14 GND Ground 39 CSE:L-

15 G ND Ground 40 - ­16 GND Ground 41 RESET- Reset signal to drive
17 GND Ground 42 IORDY Drive is ready for I/O

18 DA2 Drive register and data

19 DA1 Drive register and data

20 DA0 Drive register and data

Signal

Mnemonic

Signal Description Pin

Number

also command register
block select

port address lines

port address lines

port address lines

Signal

Mnemonic

32 CS3- Chip select drive 1,

DD3

43 - -

44 VCC +5 Volts

45 DASP- Drive active/slave

Signal Description

also command register
block select

Cable select

cycle(s)

present

4

http://www.motorola.com/computer/literature 4-11

Connector Pin Assignments

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Table 4-11. CompactFlash Connector Pin Assignments for the CPTM04

Transition Module (Continued)

Pin

Number

21 DD0 Drive data line 46 PDIAG- Output from drive 1

22 DD1 D ri ve data line 47 DD8 Drive data line

4

23 DD2 D ri ve data line 48 DD9 Drive data line
24 - - 49 DD10 Drive data line
25 - - 50 GND Ground

Signal

Mnemonic

Signal Description Pin

Number

Signal

Mnemonic

Signal Description

and monitored by
drive 0

4-12 Computer Group Literature Center Web Site

Floppy Connector for the CPTM04 Transition Module

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Table 4-12. Floppy Connector Pin Assignments for the CPTM04 Transition

Module

Pin

Number

1 GND Ground 2 DRVDENS0 Disk density select

3 GND Ground 4 N/C not connected

5 GND Ground 6 DRVDENS1 Disk density select

7 GND Ground 8 INDEX- Indicates the

9 GND Ground 10 MTR0- Motor enable outputs
11 GND Ground 12 DS1- Drive select 1
13 GND Ground 14 DS0- Drive select 0
15 GND Ground 16 MTR1- Motor enable outputs
17 GND Ground 18 DIR- Controls the direction

19 GND Ground 20 STEP- Supplies step pul ses to

21 GND Ground 22 WDATA- Writes serial data to

23 GND Ground 24 WGATE- Enables head of disk

25 GND Ground 26 TR0- Indicates that head of

Signal

Mnemonic

Signal

Description

Pin

Number

Signal

Mnemonic

Signal Description

communication

communication

beginning of a track

of the FDD head
during seek operations

move head during
seek operations

disk drive

drive to write to disk

FDD is at track 0

4

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Connector Pin Assignments

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Table 4-12. Floppy Connector Pin Assignments for the CPTM04 Transition

Module (Continued)

Pin

Number

27 GND Ground 28 WPROT- Indicates a disk is

29 GND Ground 30 RDATA- Raw read data from

4

31 GND Ground 32 HDSEL- Determines side of the

33 GND Ground 34 DSKCHG- Notifies the disk drive

Signal

Mnemonic

Signal

Description

Pin

Number

Signal

Mnemonic

Signal Description

write protected

disk drive

floppy disk being
accessed

controller that the
drive door is ope n

4-14 Computer Group Literature Center Web Site

Indicator LED/Miscellaneous Connector on the CPTM04

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Transition Module

Table 4-13. Indicator LED/Miscellaneous Connector Pin Assignments on the

CPTM04 Transi tion Module (J2)

Pin

Number

1 IDE_LED EIDE primary

3 PWR_LED Power ON

5 PBRESET Push button

7 N/C not connected 8 N/C not connected

9 SPKR Speaker 10 +5V +5V DC power

Signal

Mnemonic

Signal

Description

channel activity
LED. Connect
LED between pins
5 and 6

indicator.

system reset.
Connect switch
between pins 5 and
6

Pin

Number

2 +5V +5V DC power

4 GND Ground

6 GND Ground

Signal

Mnemonic

Signal Description

4

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IPMI System Management Bus Connector on the CPTM04 Transition Module (J1)

Table 4-14. IPMI System Management Bus Connector Pin

Assignments on the CPTM04 Transition Module (J1)

Pin

Number

1 SMBCLK System Management Bus Clock

4

2 GND Ground
3 SMBDAT S ystem Management Bus Data
4 +5V +5V dc power
5 N/C not connected

Signal

Mnemonic

Signal Description

CompactFlash Master/Slave Connector on the CPTM04 Transition Module (J16)

Table 4-15. CompactFlash Master/Slave Connector on the CPTM04

Transi tion Module (J16)

Pin

Number

1GND 2M_S_JMP

1

Jumper installed defines CompactFlash as master

device on EIDE primary channel

Signal Pin

Number

1

Signal

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Connectors (J1 and J2)

The CPV5370 Single Board Comput er provides a 64 bit CompactPCI interfac e
on connectors J1 and J2. Refer to Table 4-16 for J1 and Table 4-17 for J2 pin
designations.

Table 4-16. CPV5370 Backplane Connector Pin Assignments (J1)

Pin

Number

25 GND VCC VCC3 ENUM# REQ64# VCC GND
24 GND ACK64# AD[0] VIO_LP VCC AD[1] GND
23 GND AD[2] VCC_LP AD[3] AD[4] VCC3 GND
22 GND AD[5] AD[6] VCC3_LP GND AD[7] GND
21 GND C/BE[0]# GND AD[8] AD[9] VCC3 GND
20 GND AD[10] AD[11] VIO GND AD[12] GND
19 GND AD[13] GND AD[14] AD[15] VCC3 GND
18 GND C/BE[1]# PAR VCC3 GND SERR# GND
17 GND PERR# GND RSV RSV VCC3 GND
16 GND LOCK# STOP# VIO GND DEVSEL# GND
15 GND TRDY# BD_SEL# IRDY# FRAME# VCC3 GND

KEY

11 GND C/BE[2#] GND AD[16] AD[17] AD[18] GND
10 GND AD[19] AD[20] VCC3_LP GND AD[21] GND

9 GND AD[22] GND AD[23] IRSV C/BE[3]# GND
8 GND AD[24] AD[25] VIO GND AD[26] GND
7 GND AD[27] GND AD[28] AD[29] AD[30] GND
6 GND AD[31] CLK7 VCC3 GND REQ7# GND
5 GND GNT7# GND RST# BRSVP1B5 BRSVP1A5 GND
4 GND INTS INTP VIO_LP HLTY BRSVP1A4 GND
3 GND INTD# VCC_LP INTC# INTB# INT A# GND
2 GND RSV RSV RSV VCC RSV GND
1 GND VCC +12V RSV -12V VCC GND

FE D C B A Z

4

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Table 4-17. CPV5370 Backplane Connector Pin Assignments (J2)

Pin

Number

22 GND RSV RSV RSV RSV RSV GND
21 GND RSV RSV RSV GND CLK6 GND
20 GND RSV GND RSV GND CLK5 GND
19 GND RSV RSV RSV GND GND GND

4

18 GND BRSVP2E18 GND BRSVP2C18 BRSVP2B18 BRSVP2A18 GND
17 GND GNT6# REQ6# PRST# GND BRSVP2A17 GND
16 GND BRSVP2E16 GND DEG# BRSVP2B16 BRSVP2A16 GND
15 GND GNT5# REQ5# FAL# GND BRSVP2A15 GND
14 GND AD[32] GND AD[33] AD[34] AD[35] GND
13 GND AD[36] AD[37] VIO GND AD[38] GND
12 GND AD[39] GND AD[40] AD[41] AD[42] GND

11 GND AD[43] AD[44] VIO GND AD[45] GND

10 GND AD[46] GND AD[47] AD[48] AD[49] GND

9 GND AD[50] AD[51] VIO GND AD[52] GND
8 GND AD[53] GND AD[54] AD[55] AD[56] GND
7 GND AD[57] AD[58] VIO GND AD[59] GND
6 GND AD[60] GND AD[61] AD[62] AD[63] GND
5 GND PAR64 C/BE[4]# VIO GND C/BE[5]# GND
4 GND C/BE[6]# GND C/BE[7]# BRSVP2B4 VIO GND
3 GND GNT4# REQ4# GNT3# GND CLK4 GND
2 GND REQ3# GNT2# SYSEN# CLK3 CLK2 GND
1 GND REQ2# GNT1# REQ1# GND CLK1 GND

FE D C B A Z

4-18 Computer Group Literature Center Web Site

CPV5370 Single Board Computer, CompactPCI Rear I/O

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Connectors (J3, J4, and J5)

Table 4-18. CPV5370 Single Board Computer, Rear I/O Connector Pin

Assignments (J3)

Pin

Number

19 GND VDDCCLK VDDCDAT V_BLU V_GRN V_RED GND
18 GND GND V_VSYN V_HSYN GND HS_REQ GND
17 GND LANB RD- LANB TD- LANB TD+ GND HS_GNT GND
16 GND LANB RD+ LANA RD- LANA RD+ GND HS_FLT GND
15 GND VCC-12 LANA TD- LANA TD+ GND HS_EJ GND
14 GND VCC VCC VCC3 VCC3 VCC3 GND
13 GND PMC1 PMC2 PMC3 PMC4 PMC5 GND
12 GND PMC6 PMC7 PMC8 PMC9 PMC10 GND
11 GND PMC11 PMC12 PMC13 PMC14 PMC15 GND
10 GND PMC16 PMC17 PMC18 PMC19 PMC20 GND

9 GND PMC21 PMC22 PMC23 PMC24 PMC25 GND
8 GND PMC26 PMC27 PMC28 PMC29 PMC30 GND
7 GND PMC31 PMC32 PMC33 PMC34 PMC35 GND
6 GND PMC36 PMC37 PMC38 PMC39 PMC40 GND
5 GND PMC41 PMC42 PMC43 PMC44 PMC45 GND
4 GND PMC46 PMC47 PMC48 PMC49 PMC50 GND
3 GND PMC51 PMC52 PMC53 PMC54 PMC55 GND
2 GND PMC56 PMC57 PMC58 PMC59 PMC60 GND
1 GND PMC61 PMC62 PMC63 PMC64 VCC3 GND

FE D C B AZ

4

http://www.motorola.com/computer/literature 4-19

Connector Pin Assignments

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Table 4-19. Signal Descriptions for the CPV5370 Single Board Computer

Backplane Connector (J3)

Signal Signal

Mnemonic

Ethernet RD+, RD- Differential receive lines

TD+, TD- Differential transmit lines

Video Signal

4

Definitions

General GND Ground plane

Hot Swap Control

Signals

PMC2 I/O PMC [1 to 64] PMC I/O signals 1 through 64

V_RED Red signal
V_GREEN Green signal
V_BLU Blue signal
V_HSYNC Horizontal synchronization
V_VSYNC Vertical synchronization
VDDCCLK Display Data Channel clock signal for DDC2

support

VDDCDAT Display Data Channel data signal for DDC2 support

VCC-12 -12Vdc power
VCC5 5Vdc power
VCC3.3 3.3Vdc power
HS_REQ Hot Swap Request
HS_GNT Hot Swap Grant
HS_FLT Hot Swap Float
HS_EJ Hot Swap Eject

Signal Description

4-20 Computer Group Literature Center Web Site

Connector J4 contains floppy, printer por t and miscella neous functions. J4

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is an optionally installed connector. Refer to Table 4-20 and Table 4-21.

Table 4-20. CPV5370 Rear I/O Pin Assignments (J4)

Pin

Number

25 GND AD[32] AD[33] AD[34] AD[35] AD[36] GND
24 GND AD[37] GND AD[38] AD[39] AD[40] GND
23 GND AD[41] AD[42] AD[43] AD[44] AD[45] GND
22 GND AD[46] AD[47] AD[48] VCC3 AD[49] GND
21 GND AD[50] GND AD[51] AD[52] AD[53] GND
20 GND AD[54] AD[55] AD[56] VCC3 AD[57] GND
19 GND AD[58] GND AD[59] AD[60] AD[61] GND
18 GND AD[62] AD[63] PAR64 VCC3 C/BE[4]# GND
17 GND C/BE[5]# GND C/BE[6]# C/BE[7]# REQ64# GND
16 GND ACK64# AD[0] AD[1] VCC3 AD[2] GND
15 GND AD[3] GND AD[4] AD[5] AD[6] GND

Key

11 GND AD[7] GND C/BE[0]# AD[8] AD[9] GND
10 GND AD[10] AD[11] AD[12] VCC AD[13] GND

9 GND AD[14] GND AD[15] C/BE[1]# P AR GND
8 GND SERR# PERR# LOCK# VCC STOP# GND
7 GND DEVSEL# GND TRDY# IRDY# FRAME# GND
6 GND C/BE[2]# AD[16] AD[17] VCC AD[18] GND
5 GND AD[19] GND AD[20] CLK AD[21] GND
4 GND AD[22] AD[23] RSV VCC C/BE[3]# GND
3 GND AD[24] AD[25] AD[26] AD[27] AD[28] GND
2 GND AD[29] AD[30] AD[31] REQ# GNT# GND
1 GND RST# INTD# INTC# INTB# INTA# GND

FE D C B AZ

4

http://www.motorola.com/computer/literature 4-21

Connector Pin Assignments

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Table 4-21. CPV5370 Rear I/O Pin Assignments (J5)

Pin

FE D C B AZ

Number

22 GND SPKR- VCC ALARM- GND PBRESET- GND
21 GND MCLK MDAT VCC
20 GND SMBLART GND

1

19 GND UDATA0- UDATA0+ VCC

4

18 GND VCC

1

GND

1

1

SMBCLK SMBDATA VCC

1

UDATA1- UDATA1+ AFD- GND

KBDCLK KBDDAT GND

GND

1

1

STB- GND

GND

17 GND PD0 ERR- PD1 INIT- PD2 GND
16 GND SLIN- PD3 PD4 PD5 PD6 GND
15 GND PD7 ACK- BUSY PE SLCT GND
14 GND DTR(1) GND RI(1) CTS1 RTS(1) GND
13 GND TXD(1) DSR1 RXD(1) VCC DCD(1) GND
12 GND DTR(2) VCC RI(2) CTS2 RTS(2) GND
11 GND TXD(2) DSR(2) RXD(2) GND DCD(2) GND
10 GND DSKCHG- HDSEL- RDATA- WPROT- TR0- GND

9 GND WGATE- WDATA- STEP- DIR- MTR1- GND
8 GND DS0- DS1- MTR0- INDEX- DRATE GND
7 GND RPM_LC +12.0V DA1 CS3- CS1- GND
6 GND DA2 DA0 RESERVED GND RESERVED GND
5 GND DIOR- DMACK- DIOW IORDY DMARQ GND
4 GND INTRQ DD15 GND DD0 DD14 GND
3 GND DD1 DD13 DD2 DD12 DD3 GND
2 GND DD11 DD4 DD10 DD5 DD9 GND
1 GND DD6 DD8 DD7 DRESET- RESET- GND

1

These lines may be current limited and/or EMI filtered for direct cabling

4-22 Computer Group Literature Center Web Site

Table 4-22. Signal Descriptions for the CPV5370 Single Board Computer

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Backplane Connector (J5)

Signal Signal

Mnemonic

General VCC 5V power supply

GND Digital signal ground plane

Keyboard/Mouse

Device, TTL Levels

Miscellaneous

Signals

SM Bus Signals SMBDATA System Management Bus signals

EIDE (ATA-2),

Secondary Channel,

TTL levels

MCLK Clock for PS/2 mouse
MDAT Serial data line for PS/2 mouse
KBDCLK Clock for PC/AT or PS/2 keyboard
KBDDAT Serial data line for PC/AT or PS/2 keyboard
SPKR PC/AT speaker output, open collector
DIAG Diagno stic/alarm output, open collector
PBRESET Pushbutton system rese t input (pulled up, filtered,

and debounced on host car d)

RESET System reset output, TTL totem-pole

SMBCLK
SMBALRT
IOCS16- Indicates a 16 bit register is decoded
DMARQ Drive DMA request
DMACK- Drive DMA acknowledge
DIOR- Drive I/O read
DIOW- Drive I/O write
DASP- Drive active/slave present
IORDY Indicates drive is ready for I/O cycle(s)
DD[15:0] Drive data lines, bits 15--0
DRESET- Reset signal to drive
CS1- Chip select drive 0, also command register block

select

CS3- Chip select drive 1, also command register block

select
DA[2:0] Drive register and data port address lines
INTRQ Drive interrupt request
PDIAG- Output from drive 1 and monitored by drive 0

Signal Description

4

http://www.motorola.com/computer/literature 4-23

Connector Pin Assignments

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Table 4-22. Signal Descriptions for the CPV5370 Single Board Computer

Backplane Connector (J5) (Continued)

Signal Signal

Mnemonic

Parallel LPT Port,

TTL levels

4

Serial COM Ports

(1 and 2), RS232

levels

ACK- Pulsed by peripheral to acknowledge data sent

1

BUSY Indicates that the printer cannot accept more data
ERR- Peripheral detected an error
PD[7:0] Parallel data lines, bits 7--0
PE Paper end, indicates the printer is out of paper
AFD- Auto feed, causes printer to line feed
INIT- Initializes the printer
SLIN- Select in, selects the printer
STB- Data strobe, indicates data is valid
SLCT Select, peripheral indicates it is selected
CTS Clear to send
DCD Data carrier detected
DSR Data set ready
DTR Data terminal ready
RI Ring indic ator
RTS Request to send
RXD Serial receive data
TXD Serial transm it data

Signal Description

4-24 Computer Group Literature Center Web Site

Table 4-22. Signal Descriptions for the CPV5370 Single Board Computer

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Backplane Connector (J5) (Continued)

Signal Signal

Mnemonic

Floppy Disk Drive,

TTL levels

Universal Serial

Bus (USB) (0 and

1), USB levels

1

Some signals are redefined when used in EPP/ECP modes

DSKCHG- Indicates the drive door is open
DIR- Controls direction of the head during s t ep op erat i on s
DRVDENS[1:0] Disk density select communication
DS[1:0]- Drive selects
HDSEL- Selects top or bottom side head
INDEX- Indicates the beginning of a track
MTR[1:0] Motor enables
RDATA- Data read
STEP- Step, pulses move head in or out
TR0- Indicates that head is positioned above track 00
WDATA- Write data to drive
WGATE- Enables head write circuitry of drive
WPROT- Indicates disk is write-protected
UDATAn+ (+) Signal of differential data pair for USB channel
UDATAn- (-) Signal of differential data pair for USB channel

Signal Description

4

http://www.motorola.com/computer/literature 4-25

Connector Pin Assignments

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CPTM04 T ransition Module, Rear I/O Connectors (J3 and J5)

Table 4-23 through Table 4-25 show J3 and J5 connector pinouts and

signal description s.

Table 4-23. CPTM04 Transition Module, Rear I/O Connector Pin

Assignments (J3)

4

Pin

Number

19 GND V_DDCCLK V_DDCDAT V_BLU V_GRN V_RED
18 N/C GND V_VSYNC V_HSYNC GND HS_REQ
17 GND LANB RD- LANB TD- LANB TD+ GND HS_GNT
16 N/C LANB RD+ LANA RD- LANA RD+ GND HS_FLT
15 GND VCC-12 LANA TD- LANA TD+ GND HS_EJ
14 N/C VCC5 VCC5 VCC3.3 VCC3.3 VCC3.3
13 GND PMC1 PMC2 PMC3 PMC4 PMC 5
12 N/C PMC6 PMC7 PMC8 PMC9 PMC10

11 GND PMC11 PMC12 PMC13 PMC14 PMC15

10 N/C PMC16 PMC17 PMC18 PMC19 PMC20

9 GND PMC21 PMC22 PMC23 PMC24 PMC25
8 N/C PMC26 PMC27 PMC28 PMC29 PMC30
7 GND PMC31 PMC32 PMC33 PMC34 PMC35
6 N/C PMC36 PMC37 PMC38 PMC39 PMC40
5 GND PMC41 PMC42 PMC43 PMC44 PMC45
4 N/C PMC46 PMC47 PMC48 PMC49 PMC50
3 GND PMC51 PMC52 PMC53 PMC54 PMC55
2 N/C PMC56 PMC57 PMC58 PMC59 PMC60
1 GND PMC61 PMC62 PMC63 PMC64 VCC3.3

FE D C BA

4-26 Computer Group Literature Center Web Site

Table 4-24. Signal Descriptions for the CPTM04 Transition Module,

Solution Systems Technologies Inc.

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Backplane Connector (J3)

Signal Signal

Mnemonic

Ethernet (1 and 2) LANn_RD+,

LANn_RD­LANn_TD+,

LANn_TD-

Video Signal

Definitions

General GND Ground

PMC I/O PMCIO [1 to 64] PMC channel 1 I/O signals 1 through 64

High Availability

Hot Swap

V_RED Red signal
V_GRN Green signal
V_BLU Blue signal
V_HSYNC Horizontal synchronization
V_VSYNC Vertical synchronization
V_DDCCLK Display Data Channel, clock signal for DDC2

V_DDCDAT Display Data Channel, data signal for DDC2 support

+5V +5 Volts dc power
+3.3V +3.3 Volts dc power
N/C Not connected

-12V - 12 Volts dc power

HS_REQ Hot Swap Request
HS_GNT How Swap Grant
HS_FLT Hot Swap Float
HS_EJ Hot Swap Eject

Differential receive lines

Differential transmit lines

support

Signal Description

4

http://www.motorola.com/computer/literature 4-27

Connector Pin Assignments

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Table 4-25. CPTM04 Transition Module, Rear I/O Connector Pin

Assignments (J5)

Pin

Number

22 N/C SPKR +5V N/C GND PBRESET
21 GND MCLK MDAT +5V KBDCLK KBDDAT
20 N/C SMBALRT GND SMBCLK SMBDAT +5V

4

19 GND USB0- USB0+ +5V GND STB­18 N/C +5V GND USB1- USB1+ AFD­17 GND PD0 ERR- PD1 INIT- PD2
16 N/C SLIN- PD3 PD4 PD5 PD6
15 GND PD7 ACK- BUSY PE SLCT
14 N/C DTR1 GND RI1 CTS1 RTS1
13 GND TXD1 DSR1 RXD1 +5V DCD1
12 N/C DTR2 +5V RI2 CTS2 RTS2

11 GND TXD2 DSR2 RXD2 GND DCD2

10 N/C DSKCHG- HDSEL- RDATA- WPROT- TR0-

9 GND WGATE- WDATA- STEP- DIR- MTR1­8 N/C DS0- DS1- MTR0- INDEX- DRVDENS1­7 GND DRVDENS0- +12.0V DA1 CS3- CS1­6 N/C DA2 DA0 ATA66- GND RSRVD, N/C
5 GND DIOR- DMACK- DIOW- IORDY DMRQ
4 N/C IRQ DD15 GND DD0 DD14
3 GND DD1 DD13 DD2 DD12 DD3
2 N/C DD11 DD4 DD10 DD5 DD9
1 GND DD6 DD8 DD7 IDERST- GND

FE D C B A

4-28 Computer Group Literature Center Web Site

A Specifications

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Refer to thes e tables for:

❏ input power requirements (Table A-1)
❏ physical characteristics (Table A-2)
❏ lithium battery specifications (Table A-3 )
❏ environmental specifications (Table A-4)

Table A-1. Power Requirements for the CPV5370 Single Board

Computer and Transition Module

Input power Clock speed

+5V @ 2.9A 700MHz with 256 or 512MB
+3.3V @ 2.0A
+12V @ <25mA typical,

<25mA maximum

-12V @ .05A typical, .05A
maximum

SDRAM

A

Table A-2. Physical Characteristics of the CPV5370 Single Board

Computer

Parameter Description

Form Factor CompactPCI Standard 6U (233mm x

160mm x 20mm)
Conforms to PICMG 2.0, CompactPCI

(rev. 2.1) and PCI SIG 2.1 specifications

Dimensions 4 HP (.8 inches) wide

A-1